Low-power-consumption delay-locked loop with built-in automatic locking detection and control
Through the built-in automatic lock detection and control of low-power delayed phase-locking loop, the problem of continuous power consumption and jitter performance degradation in the locked state is solved, and a multi-phase clock signal output with low power consumption and low jitter is achieved.
Patent Information
- Application Number
- CN202510307626.5
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-03-17
- Publication Date
- 2025-07-18
AI Technical Summary
The existing delayed phase-locked loops continuously consume dynamic power consumption in the locked state, and the charge pump mismatch and noise introduction lead to degradation of jitter performance.
A low-power delayed phase lock loop with built-in automatic lock detection and control is designed. Through the voltage-controlled delay chain, phase detector, charge pump and lock detection and control circuit, the automatic lock detection and control of the delayed phase lock loop is realized. The automatic feedback mechanism corrects the filter capacitance voltage to reduce power consumption and jitter.
It effectively reduces the dynamic power consumption and jitter performance of the delayed phase-locked loop, and realizes low-power consumption and low-jitter multi-phase clock signal output.
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Figure CN120342389A_ABST
Abstract
Description
Technical Field
[0001] Embodiments of the present application relate to the field of time-domain analog integrated circuits, and particularly to a low-power delay locked loop and an electronic device with built-in automatic lock detection and control. Background Art
[0002] As the feature size of complementary metal oxide semiconductor (CMOS) technology shrinks, the power supply voltage of integrated circuits also decreases, resulting in a smaller voltage space for analog circuits and posing challenges to the design of analog circuits such as high-precision data converters. However, the reduction in process size reduces the parasitic capacitance of transistors, thereby reducing their delay, and signal processing in the time domain has obvious advantages. As a time-domain circuit capable of generating low-jitter multi-phase clocks, the delay locked loop can provide an accurate delay reference and has been widely used in time-domain analog circuits such as time-to-digital converters (TDCs).
[0003] In the prior art, there are the following two problems in the delay locked loop structure: in the locked state, the circuit still continuously injects clocks, resulting in continuous dynamic power consumption; in the loop closed state, charge pump mismatch and noise introduce voltage ripple, significantly affecting the stability of the control voltage and increasing the output jitter. Alternatively, the current and noise caused by the charge pump mismatch still affect the capacitors in the loop filter, resulting in the degradation of the jitter performance of the delay locked loop. Summary of the Invention
[0004] In view of this, embodiments of the present application propose a low-power delay locked loop and an electronic device with built-in automatic lock detection and control, aiming to reduce the dynamic power consumption and jitter of the delay locked loop.
[0005] To achieve the above object, an embodiment of the present application provides a low-power delay-locked loop with built-in automatic lock detection and control, including: a voltage-controlled delay chain, a phase detector, a charge pump, a lock detection and control circuit, a loop filter, and a lock detection and control circuit; the input end of the voltage-controlled delay chain is connected to a clock signal source, and the output ends of the first and last delay units are respectively connected to two input ends of the lock detection and control circuit and two input ends of the phase detector; both input ends of the phase detector are connected to a first controlled switch, the first controlled switch is connected to the output end of the lock detection and control circuit, and the two output ends of the phase detector are respectively connected to two input ends of the charge pump; the two input ends of the charge pump are respectively connected to the two output ends of the phase detector, and the output end is connected to the common input end of each delay unit of the voltage-controlled delay chain and the input end of the loop filter, and the output end of the charge pump has a second controlled switch, and the second controlled switch is connected to the output end of the lock detection and control circuit; wherein, the voltage-controlled delay chain is used for performing phase splitting processing on the input clock signal; the phase detector is used for receiving the first and last phase signals output by the voltage-controlled delay chain and outputting a phase difference; the charge pump is used for charging and discharging the loop filter according to the phase difference signal to generate a voltage signal for controlling the delay of the voltage-controlled delay chain; the lock detection and control circuit is used for detecting whether the phase difference between the first and last voltage-controlled units is less than the dead time of the phase detector and outputting a lock control signal. When the phase difference between the first and last voltage-controlled units is less than the dead time, the lock control signal controls the voltage-controlled delay chain to stop injecting the clock into the phase detector and controls the charge pump to disconnect the charge and discharge loop; when the phase difference between the first and last voltage-controlled units exceeds the dead time, the lock control signal restores the operation of the phase detector and the charge pump.
[0006] Optionally, the lock detection and control circuit includes a lock detection circuit, and the lock detection circuit includes: two multi-stage inverter chains, two D flip-flops, a NAND gate, a tri-state gate, and a NOT gate; the input ends of the two multi-stage inverter chains are respectively connected to the first and last delay units, and the output ends are respectively connected to two input ends of the corresponding two D flip-flops; the output ends of the two D flip-flops are connected to the input end of the NAND gate; the output end of the NAND gate is connected to the input end of the tri-state gate; the input end of the NOT gate is connected to the output end of the tri-state gate; wherein, the two multi-stage inverter chains are used for respectively delaying the first and last delay units to obtain delayed phase signals, and the delay amount of the delayed phase signals is equal to the dead time of the phase detector; the two D flip-flops are used for sampling the delayed phase signals to obtain sampling signals; the NAND gate and the tri-state gate are used for generating a Lock_B signal based on the sampling signals. When the Lock_B signal is at a low level, it indicates that the delay-locked loop is in a locked state, and the Lock_B signal is the lock control signal; the NOT gate is used for performing a NOT operation on the Lock_B signal to obtain a Lock signal.
[0007] Optionally, the charge pump includes a first transistor switch group, a charge pump output node, and a second transistor switch group connected in series; the first transistor switch group includes two PMOS transistors, and the two PMOS transistors are connected in series between VDD and the charge pump output node, and the gates of the two PMOS transistors are controlled by the Lock_B signal; the second transistor switch group includes two NMOS transistors, and the two NMOS transistors are connected in series between the charge pump output node and GND, and the gates of the two NMOS transistors are controlled by the Lock signal; in the locked state, the voltage of the Lock_B signal rises to a high level, the gate voltages of the two PMOS transistors are at a high level, the voltage of the Lock signal is at a low level, and the gate voltage of the NMOS transistor drops to a low level, making the charge pump have no current.
[0008] Optionally, the delay cells at all levels of the voltage-controlled delay chain 101 are current-starved delay cells.
[0009] Optionally, the lock detection and control circuit includes a state controller, and the operating states of the state controller include a startup stage, a sleep stage, and a calibration stage: when the lock detection and control circuit is in the startup stage, the lock control signal is at a high level, and the phase detector and the charge pump continue to operate; when the lock detection and control circuit is in the sleep stage, the phase difference between the first and last delay cells is less than the dead time, the lock control signal turns to a low level and is maintained for a preset time, and the phase detector and the charge pump continue to operate; when the lock detection and control circuit is in the calibration stage, the lock control signal is maintained for a time exceeding the preset time, the lock control signal turns to a high level, and the lock detection circuit starts to perform phase calibration on the voltage-controlled delay chain 101.
[0010] Optionally, the loop filter is a second-order passive RC network, and the loop filter includes a first branch and a second branch connected in parallel. The first ends of the first branch and the second branch are both connected to the output terminal of the charge pump, and the second ends are both grounded: the first branch includes a first capacitor and a resistor connected in series; the second branch includes a second capacitor; wherein, the capacitance value of the second capacitor is greater than a preset multiple of the first capacitor to achieve low-frequency ripple suppression.
[0011] Optionally, the phase detector has a clock injection circuit, and the clock injection circuit includes a first NAND gate and a second NAND gate; wherein, the two input terminals of the first NAND gate are respectively connected to the output terminal of the first delay cell of the voltage-controlled delay and the input terminal of the Lock_B signal, and the output terminal is connected; the two input terminals of the second NAND gate are respectively connected to the output terminal at the end of the voltage-controlled delay chain and the input terminal of the Lock_B signal.
[0012] Optionally, the total power consumption of the circuit in the locked state satisfies:
[0013]
[0014] Among them, C total represents the total capacitance driven by the clock signal, and V dD represents the power supply voltage; f clk represents the clock frequency; I static represents the static current of the delay locked loop, and ε represents the dynamic power consumption correction factor, whose value range is 0.1 ≤ ε ≤ 0.4.
[0015] To achieve the above object, an embodiment of the present application further provides an electronic device, including the above-mentioned delay locked loop circuit.
[0016] Optionally, the electronic device is a memory interface chip, a high-speed SerDes module or a millimeter-wave radar signal processor.
[0017] A low-power delay locked loop and an electronic device with built-in automatic lock detection and control proposed by an embodiment of the present application use a voltage-controlled delay chain 101 to perform phase splitting processing on an input clock signal; a phase detector is used to receive the first and last phase signals output by the voltage-controlled delay chain and output a phase difference; a charge pump is used to charge and discharge a loop filter according to the phase difference signal to generate a voltage signal for controlling the delay of the voltage-controlled delay chain; a lock detection and control circuit is used to detect whether the phase difference between the first and last voltage-controlled units is less than the dead zone time of the phase detector and output a lock control signal. When the phase difference between the first and last voltage-controlled units is less than the dead zone time, the lock control signal controls the voltage-controlled delay chain to stop injecting the clock into the phase detector and controls the charge pump to disconnect the charge and discharge loop; when the phase difference between the first and last voltage-controlled units exceeds the dead zone time, the lock control signal resumes the operation of the phase detector and the charge pump, realizing automatic detection of the locked state of the delay locked loop, correcting the capacitance voltage of the filter through an automatic feedback mechanism, and simultaneously achieving low-power and low-jitter performance. Description of the Drawings
[0018] Figure 1 is a structural block diagram of a low-power delay locked loop with built-in automatic lock detection and control provided in an embodiment of the present application;
[0019] Figure 2 is a lock detection and control circuit of a low-power delay locked loop with built-in automatic lock detection and control provided in an embodiment of the present application;
[0020] Figure 3 is a schematic diagram of the state transition of a timing controller of a low-power delay locked loop with built-in automatic lock detection and control provided in an embodiment of the present application;
[0021] Figure 4 is a charge pump circuit structure of a low-power delay locked loop with built-in automatic lock detection and control provided in an embodiment of the present application;
[0022] FIG. 5(a) is a schematic diagram of a voltage-controlled delay chain of a low-power delay-locked loop with built-in automatic lock detection and control provided by another embodiment of the present application;
[0023] FIG. 5(b) is a bias circuit of a voltage-controlled delay chain of a low-power delay-locked loop with built-in automatic lock detection and control provided by another embodiment of the present application;
[0024] FIG. 5(c) is a current-starved delay cell of a voltage-controlled delay chain of a low-power delay-locked loop with built-in automatic lock detection and control provided by another embodiment of the present application;
[0025] Figure 6 is a comparison of the power consumption of the delay-locked loop of the low-power delay-locked loop with built-in automatic lock detection and control provided in an embodiment of the present application with other structures;
[0026] Figure 7 is a comparison of the power consumption of the delay-locked loop of the low-power delay-locked loop with built-in automatic lock detection and control provided in an embodiment of the present application with other structures. Detailed implementation manners
[0027] To make the objectives, technical solutions, and advantages of the embodiments of the present application clearer, the embodiments of the present application will be described in detail below with reference to the accompanying drawings. However, those of ordinary skill in the art can understand that in the embodiments of the present application, many technical details are provided to enable readers to better understand the present application. However, even without these technical details and various changes and modifications based on the following embodiments, the technical solutions claimed in the present application can still be implemented. The following division of each embodiment is for convenience of description and should not constitute any limitation to the specific implementation manner of the present application. Each embodiment can be combined and cross-referenced with each other on the premise of not being contradictory.
[0028] An embodiment of the present application proposes a low-power delay-locked loop with built-in automatic lock detection and control. The implementation details of the low-power delay-locked loop with built-in automatic lock detection and control proposed in this embodiment will be specifically described below. The following content is only implementation details provided for convenient understanding and is not necessary for implementing this solution.
[0029] Reference Figure 1, the low-power delay-locked loop with built-in automatic lock detection and control proposed in this embodiment includes: a voltage-controlled delay chain 101, a phase detector 102, a charge pump 104, a loop filter 105, and a lock detection and control circuit 103; the input end of the voltage-controlled delay chain 101 is connected to a clock signal, and the output ends of the first and last delay units are respectively connected to the two input ends of the lock detection and control circuit 103 and the two input ends of the phase detector 102; both input ends of the phase detector 102 are connected to a first controlled switch, the first controlled switch is connected to the output end of the lock detection and control circuit 103, and the two output ends of the phase detector 102 are respectively connected to the two input ends of the charge pump 104; the two input ends of the charge pump 104 are respectively connected to the two output ends of the phase detector 102, the output end is connected to the common input end of each delay unit of the voltage-controlled delay chain 101 and the input end of the loop filter 105, and the output end of the charge pump 104 has a second controlled switch, and the second controlled switch is connected to the output end of the lock detection and control circuit 103; wherein, the voltage-controlled delay chain 101 is used for performing phase splitting processing on the input clock signal; the phase detector 102 is used for receiving the first and last phase signals output by the voltage-controlled delay chain 101 and outputting a phase difference; the charge pump 104 is used for charging and discharging the loop filter 105 according to the phase difference signal to generate a voltage signal for controlling the delay of the voltage-controlled delay chain 101; the lock detection and control circuit 103 is used for detecting whether the phase difference between the first and last voltage-controlled units is less than the dead time of the phase detector 102 and outputting a lock control signal. When the phase difference between the first and last voltage-controlled units is less than the dead time, the lock control signal controls the voltage-controlled delay chain 101 to stop injecting the clock into the phase detector 102 and controls the charge pump 104 to disconnect the charge and discharge loop; when the phase difference between the first and last voltage-controlled units exceeds the dead time, the lock control signal resumes the operation of the phase detector 102 and the charge pump 104.
[0030] Reference Figure 2 , in an embodiment of the present application, the lock detection and control circuit 103 includes a state controller, and the working states of the state controller include a startup stage, a sleep stage, and a calibration stage: when the lock detection and control circuit 103 is in the startup stage, the lock control signal is at a high level, and the phase detector 102 and the charge pump 104 keep working; when the lock detection and control circuit 103 is in the sleep stage, the phase difference between the first and last delay units is less than the dead time, the lock control signal turns to a low level and maintains for a preset time, and the phase detector 102 and the charge pump 104 keep working; when the lock detection and control circuit 103 is in the calibration stage, the maintaining time of the lock control signal exceeds the preset time, the lock control signal turns to a high level, and the lock detection circuit starts to perform phase calibration on the voltage-controlled delay chain 101.
[0031] The structural block diagram of the low-power delay-locked loop with built-in automatic lock detection and control proposed by the present invention is as Figure 2As shown in the figure, a lock detection and control circuit is added to the delay-locked loop structure of the literature. The basic working principle of this circuit is as follows: The input clock Clk_in passes through a voltage-controlled delay line 101 containing (n + 1) delay units, generating (n + 1) multi-phase clocks PH0, PH1, ..., PHn with equal delay intervals. When in phase lock, the delay interval of the clock signal passing through n delay units is exactly one clock cycle, so the delay time τ of a single delay unit is
[0032]
[0033] where T clk is the period of the input clock. To avoid the influence of parasitic parameters, PH1 and PHn are used as the inputs of the phase detector 102, and PH0 and PHn - 1 are used as the inputs of the lock detection and control circuit 103. Different from the existing delay-locked loops, three control switches S1, S2, and S3 are added at the input of the phase detector 102 and the input of the filter respectively. Among them, the controlled switches S1 and S2 are the first controlled switches, and S3 is the second controlled switch, which are used for the dynamic control of the input signals of the two modules. The three switches are controlled by the lock state signal Lock_B generated by the lock detection and control circuit. When Lock_B is at a high level, the switches are closed; otherwise, the switches are open. The design idea of the lock detection and control circuit 103 is as follows: After the phase-locked loop is normally locked, the phases of PH0 and PHn - 1 are compared. When the phases of the two signals are the same, it proves that the delay-locked loop is locked, Lock_B is at a low level, the three switches are open, and the circuit enters the sleep state; if the phases of the two signals are inconsistent, it indicates that the delay-locked loop is not locked, Lock_B is at a high level, the three switches are closed, and it enters the phase-lock correction working state. The working states of the lock detection and control circuit 103 are shown in Table 1.
[0034] Table 1 Working states of the lock detection and control circuit 103
[0035]
[0036] Reference Figure 3 , after adding automatic lock detection, the control process of the low-power delay-locked loop with built-in automatic lock detection and control proposed by the present invention is also different from the existing working process. The state description of the timing controller is as follows:
[0037] State 1: Startup phase: This phase operates in the same manner as a traditional delay-locked loop. During initialization, the timing control circuit sets the lock state signal Lock_B to high level to ensure that the three switches are closed in the initial state. Subsequently, the timing control circuit invokes the phase detector 102, charge pump 104, filter, and voltage-controlled delay chain 101 loop to complete the phase adjustment of the input clocks Clk_A and Clk_B until the two clock signals are in a phase-locked state, and then sets Lock_B to low level. Enter State 2.
[0038] State 2: Sleep phase: Lock_B is set to low level, and the three switches are opened. At this time, PH1 and PHn stop being injected into the phase detector 102, and the charge pump 104 also does not charge or discharge the capacitor in the filter. The timing controller continuously monitors the output signal of the phase-locked detection circuit. When the phase difference between PH0 and PHn-1 is within the dead zone of the phase-locked detection circuit, the delay-locked loop will be completely in an inactive state.
[0039] State 3: Phase-locked correction phase: When the control voltage on the filter gradually decreases and the phase difference between PH0 and PHn-1 gradually increases, exceeding the dead zone of the lock detection and control circuit 103, it causes a state change in the lock detection and control circuit 103, setting Lock_B to high level and closing the three switches. At this time, the delay-locked loop invokes the phase detector 102, charge pump 104, filter, and voltage-controlled delay chain 101 loop to complete the phase adjustment of the input clocks Clk_A and Clk_B until the two clock signals are in a phase-locked state, and then sets Lock_B to low level. Enter State 2.
[0040] The key point of the present invention lies in adding an automatic lock detection and control circuit 103 to the traditional delay-locked loop and redefining the timing controller of the delay-locked loop. A highly sensitive phase-locked detection circuit is adopted to quickly detect the phase-locked state of the circuit, thereby generating corresponding control signals. Through a negative feedback mechanism, the operation of the delay-locked loop is ultimately clamped between the sleep phase and the phase-locked correction phase, minimizing the signal jumps in the phase-locked loop circuit to achieve the purpose of reducing circuit power consumption and clock jitter. Compared with the existing ones, the present invention significantly reduces the unnecessary dynamic power consumption of the circuit and reduces the ripple on the control voltage to optimize the jitter performance by adding the lock detection and control circuit 103 to disconnect the loop after locking. Compared with the prior art, the present invention also adopts the method of stopping clock injection after locking to reduce dynamic power consumption, but solves the problems that the existing technology structure cannot automatically detect whether clock injection is required and the influence of the charge pump 104 on the capacitor in the loop filter 105 after stopping injection.
[0041] Continue to refer to Figure 2, in an embodiment of the present application, the lock detection and control circuit 103 has a lock detection circuit, and the lock detection circuit includes: two multi-stage inverter chains, two D flip-flops, a NAND gate, a tri-state gate, and a NOT gate; two input terminals of each of the two multi-stage inverter chains are respectively connected to the first and last delay units, and two output terminals of each are respectively connected to two input terminals of the corresponding two D flip-flops; output terminals of the two D flip-flops are connected to input terminals of the NAND gate; an output terminal of the NAND gate is connected to an input terminal of the tri-state gate; an input terminal of the NOT gate is connected to an output terminal of the tri-state gate; wherein, the two multi-stage inverter chains are used to respectively perform delay processing on the first and last delay units to obtain delay phase signals, and a delay amount of the delay phase signals is equal to a dead time of the phase detector 102; the two D flip-flops are used to sample the delay phase signals to obtain sampling signals; the NAND gate and the tri-state gate are used to generate a Lock_B signal based on the sampling signals, and when the Lock_B signal is at a low level, it indicates that the delay locked loop is in a locked state, and the Lock_B signal is a lock control signal; the NOT gate is used to perform a NOT operation on the Lock_B signal to obtain a Lock signal.
[0042] The schematic diagram of the lock detection and control circuit 103 is as Figure 2 shown. The main circuit modules of the lock detection circuit include two multi-stage inverter chains, two D flip-flops, a NAND gate, and a tri-state gate. The outputs of the circuit are the Lock_B and Lock signals. The purpose of the multi-stage inverter is to add a delay equal to the dead time of the phase detector 102 between the two inputs. When the phase difference between PH0 and PHn-1 is less than the dead time, the Lock_B output is at a low level, and the lock detection result is that the locked clock stops injecting into the phase detector 102, and the charge pump 104 stops working; if the phase difference between the two exceeds the dead time of the phase detector 102, the Lock_B output is at a high level. At this time, the lock detection result is unlocked, the switch in the phase detector 102 closes, the clock signal enters the delay locked loop, and the charge pump 104 resumes operation.
[0043] The lock detection and control circuit 103 further includes a timing controller, and the state transition schematic diagram of the timing controller is as Figure 3 shown. It is mainly divided into three states. In the startup stage, lock_B remains at a high level, which is the same as the working mode of the traditional delay locked loop. When the circuit is locked, it enters the sleep stage. At this time, lock_B is at a low level, and the circuit stops working. When the control voltage gradually decreases to get out of the locked state, the circuit enters the phase lock correction stage, lock_B is at a high level, and the delay locked loop enters the working state to correct the input phase.
[0044] Refer to Figure 4, in an embodiment of the present application, the charge pump 104 includes a first transistor switch group connected in series, an output node of the charge pump 104, and a second transistor switch group; the first transistor switch group includes two PMOS transistors, and the two PMOS transistors are connected in series between VDD and the output node of the charge pump 104, and the gates of the two PMOS transistors are controlled by the Lock_B signal; the second transistor switch group includes two NMOS transistors, and the two NMOS transistors are connected in series between the output node of the charge pump 104 and GND, and the gates of the two NMOS transistors are controlled by the Lock signal; in the locked state, the voltage of the Lock_B signal rises to a high level, the gate voltages of the two PMOS transistors are at a high level, the voltage of the Lock signal is at a low level, and the gate voltages of the NMOS transistors drop to a low level, so that there is no current in the charge pump 104.
[0045] Specifically, the schematic diagram of the charge pump 104 is as Figure 4 shown. Adopting a scheme different from but functionally equivalent to the prior art, this circuit is responsible for charging and discharging the subsequent loop filter 105 according to the widths of the UP and DN clock signals output by the phase detector 102, and generating a control voltage for controlling the voltage-controlled delay chain 101. Lock_B and Lock are used as signals to control the switch of the charge pump 104. When not locked, it works the same as the traditional structure. When the delay locked loop is locked, the Lock_B signal becomes low level, M28 is turned on, and the gate voltages of M15 and M16 become VDD; the Lock signal becomes high level, M9 is turned on, and the gate voltages of M11 and M13 become GND. At this time, there is no current in the charge pump 104 and the loop is disconnected. When the Lock_B signal is at a high level, the charge pump 104 works normally, generates charging and discharging current to realize the adjustment of the control voltage, realizes the non-ideal effect of not introducing switches, reduces the influence of charge injection and clock feedthrough on Vc, and further greatly reduces the influence of the charge pump 104 on the jitter of the delay locked loop.
[0046] Referring to FIG. 5, in an embodiment of the present application, the delay units at all levels of the voltage-controlled delay chain 101 are current-starved delay units.
[0047] Among them, the schematic diagram of the voltage-controlled delay chain 101 of the circuit is shown in FIG. 5(a). This circuit consists of n + 1 delay units whose delay time can be controlled by voltage. By changing the control voltage, a specific delay can be generated for the input clock signal, and finally the function of dividing the clock signal into n phases is realized. The present invention adopts the structure of current-starved delay units, and the schematic diagrams of its bias control circuit and delay units are respectively as Figure 5(b) and 5(c) shown.
[0048] Referring to Figure 1, in an embodiment of the present application, the loop filter 105 is a second-order passive RC network. The loop filter 105 includes a first branch and a second branch connected in parallel. The first ends of the first branch and the second branch are both connected to the output end of the charge pump 104, and the second ends are both grounded: the first branch includes a first capacitor and a resistor connected in series; the second branch includes a second capacitor; wherein, the capacitance value of the second capacitor is greater than a preset multiple of the first capacitor to achieve low-frequency ripple suppression.
[0049] Continue to refer to Figure 2 , in an embodiment of the present application, the phase detector 102 has a clock injection circuit. The clock injection circuit includes a first NAND gate and a second NAND gate; wherein, the two input ends of the first NAND gate are respectively connected to the PH0 signal input end and the Lock_B signal input end, and the output end is connected to the first input end of the phase detector; the two input ends of the second NAND gate are respectively connected to the PH n-1 signal input end and the Lock_B signal input end, and the output end is connected to the second input of the phase detector.
[0050] In an embodiment of the present application, the total power consumption of the circuit in the locked state satisfies:
[0051]
[0052] wherein, C total represents the total capacitance driven by the clock signal, V DD represents the power supply voltage; f clk represents the clock frequency; I static represents the static current of the delay locked loop, and ε represents the dynamic power consumption correction factor, and its value range is 0.1 ≤ ε ≤ 0.4.
[0053] For the delay locked loop in the related prior art 1, it continuously operates during the operation process, and its total power consumption is
[0054]
[0055] wherein, C total is the total capacitance driven by the clock signal; V DD is the power supply voltage; f clk is the clock frequency; I static is the static current of the delay locked loop. For the low-power delay locked loops of the related prior art 2 and the present invention, their total power consumption is
[0056]
[0057] Among them, ε is the dynamic power consumption correction factor, indicating the proportion of the duration of the phase-locked adjustment stage in the entire working stage when the low-power delay-locked loop of the present invention is working. It can be found that since the present invention proposes to add the lock detection and control circuit 103 to the control loop, and stop the clock injection and disconnect the voltage regulation after locking, the unnecessary signal transition activities of the delay-locked loop are minimized on the basis of not affecting the circuit performance.
[0058] The phase-locked loop designed using the 180-nanometer process is as Figure 1 shown, and the power consumption comparison is as Figure 6 shown. In terms of power consumption, the total power consumption of the delay-locked loop of the present invention is 5.35 mW, and the dynamic power consumption of the added lock detection and control circuit 103 is 0.36 mW, which has little impact on the overall power consumption performance of the delay-locked loop; using the same process, the total power consumption of the delay-locked loop designed with the architecture in the related prior art 1 reaches 17.6 mW; the total power consumption of the delay-locked loop implemented with the technology of the related prior art 2 is 7.46 mW. The present invention can further reduce the power consumption of the delay-locked loop, and the total power consumption is 30.4% and 71.7% of the architectures in the related prior art 1 and the related prior art 2 respectively.
[0059] In terms of the jitter performance of the delay-locked loop, the peak-to-peak jitter indexes of the three architectures are compared as Figure 7 shown, which are 78.05 ps, 64.48 ps, and 42.16 ps respectively. In the architecture of the related prior art 1, since the path from the charge pump 104 to the capacitor in the loop filter 105 remains closed, the stability of the output control voltage is the worst, so its jitter performance is the worst. Although the clock injection is stopped after locking in the related prior art 2, the loop still remains closed, so the influence of the charge pump 104 on the control voltage still exists, and thus the improvement of the jitter performance is limited. However, the present invention automatically performs lock detection and disconnects the loop after locking, avoiding the influence of charge pump 104 mismatch, noise, etc. on the control voltage, so the jitter performance is the best among the three architectures.
[0060] In summary, the delay-locked loop proposed by the present invention can greatly reduce the power consumption of the traditional delay-locked loop circuit on the basis of ensuring a stable multi-phase clock. At the same time, the delay-locked loop can generate a low-jitter delay clock signal in the sleep stage. After careful delay matching, as well as area and power consumption optimization, excellent low-power and low-jitter performance can be achieved on a small area.
[0061] Based on the above embodiments, the present application also proposes an electronic device, including the aforementioned delay-locked loop circuit.
[0062] In an embodiment of the present application, the electronic device is a memory interface chip, a high-speed SerDes module, or a millimeter-wave radar signal processor.
[0063] Those of ordinary skill in the art can understand that the above embodiments are specific embodiments for implementing the present application, and in actual applications, various changes can be made to them in form and details without departing from the spirit and scope of the present application.
Claims
1. A low-power delay-locked loop with built-in automatic lock detection and control, characterized in that Comprising: A voltage-controlled delay chain, a phase detector, a charge pump, a loop filter, and a lock detection and control circuit; The input end of the voltage-controlled delay chain is connected to a clock signal source, and the output ends of the first and last delay units of the voltage-controlled delay chain are respectively connected to two input ends of the lock detection and control circuit and two input ends of the phase detector; Both input ends of the phase detector are connected to a first controlled switch, the first controlled switch is connected to the output end of the lock detection and control circuit, and the two output ends of the phase detector are respectively connected to two input ends of the charge pump; The two input ends of the charge pump are respectively connected to the two output ends of the phase detector, the output end is connected to the common input end of each delay unit of the voltage-controlled delay chain and the input end of the loop filter, and the output end of the charge pump is connected to the output end of the lock detection and control circuit through the second controlled switch; Wherein, the voltage-controlled delay chain is used for performing phase splitting processing on the input clock signal; The phase detector is used for receiving the first and last phase signals output by the voltage-controlled delay chain and outputting a phase difference; The charge pump is used for charging and discharging the loop filter according to the phase difference signal and generating a voltage signal for controlling the delay of the voltage-controlled delay chain; The lock detection and control circuit is used for detecting whether the phase difference between the first and last voltage-controlled units is less than the dead zone time of the phase detector and outputting a lock control signal. When the phase difference between the first and last voltage-controlled units is less than the dead zone time, the lock control signal controls the voltage-controlled delay chain to stop injecting the clock into the phase detector and controls the charge pump to disconnect the charge and discharge loop; when the phase difference between the first and last voltage-controlled units exceeds the dead zone time, the lock control signal resumes the operation of the phase detector and the charge pump.
2. The low-power delay-locked loop with built-in automatic lock detection and control according to claim 1, wherein The lock detection and control circuit includes a lock control circuit, and the lock control circuit includes: two multi-stage inverter chains, two D flip-flops, a NAND gate, a tri-state gate, and a NOT gate; The input ends of the two multi-stage inverter chains are respectively connected to the first and last delay units, and the two output ends of each are respectively connected to two input ends of the corresponding two D flip-flops; The output ends of the two D flip-flops are connected to the input end of the NAND gate; The output end of the NAND gate is connected to the input end of the tri-state gate; The input end of the NOT gate is connected to the output end of the tri-state gate, and the output end outputs the Loc signal; Wherein, the two multi-stage inverter chains are used for respectively delaying the first and last delay units to obtain delayed phase signals, and the delay amount of the delayed phase signals is equal to the dead zone time of the phase detector; The two D flip-flops are used for sampling the delayed phase signals to obtain sampling signals; The NAND gate and the tri-state gate are used for generating the Lock_B signal based on the sampling signals. When the Lock_B signal is at a low level, it indicates that the delay lock phase loop is in a locked state, and the Lock_B signal is the lock control signal; The NOT gate is used for performing a NOT operation on the Lock_B signal to obtain the Lock signal.
3. The low-power delay-locked loop with built-in automatic lock detection and control according to claim 2, characterized in that The charge pump includes a series-connected first transistor switch group, a charge pump output node, and a second transistor switch group; The first transistor switch group includes two PMOS transistors, the two PMOS transistors are connected in series between VDD and the charge pump output node, and the gates of the two PMOS transistors are controlled by the Lock_B signal; The second transistor switch group includes two NMOS transistors, and the two NMOS transistors are connected in series between the charge pump output node and GND, and the gates of the two NMOS transistors are controlled by the Lock signal; In the locked state, the voltage of the Lock_B signal rises to a high level, the gate voltages of the two PMOS transistors are at a high level, the voltage of the Lock signal is at a low level, and the gate voltage of the NMOS transistor drops to a low level, so that there is no current in the charge pump.
4. The low-power delay locked loop with built-in automatic lock detection and control according to claim 1, characterized in that The delay units at all levels of the voltage-controlled delay chain are current-starved delay units.
5. The low-power delay locked loop with built-in automatic lock detection and control according to claim 1, characterized in that The lock detection and control circuit includes a state controller, and the working states of the state controller include a startup stage, a sleep stage, and a calibration stage; When the lock detection and control circuit is in the startup stage, the lock control signal is at a high level, and the phase detector and the charge pump keep working; When the lock detection and control circuit is in the sleep stage, the phase difference between the first and last delay units is less than the dead time, the lock control signal turns to a low level and maintains for a preset time, and the phase detector and the charge pump keep working; When the lock detection and control circuit is in the calibration stage, the maintaining time of the lock control signal exceeds the preset time, the lock control signal turns to a high level, and the lock detection circuit starts to perform phase calibration on the voltage-controlled delay chain.
6. The low-power delay-locked loop with built-in automatic lock detection and control according to claim 1, wherein The loop filter is a second-order passive RC network. The loop filter includes a first branch and a second branch connected in parallel. The first ends of the first branch and the second branch are both connected to the output end of the charge pump, and the second ends are both grounded: The first branch includes a first capacitor and a resistor connected in series; The second branch includes a second capacitor; Wherein, the capacitance value of the second capacitor is greater than a preset multiple of the first capacitor to achieve low-frequency ripple suppression.
7. The low-power delay-locked loop with built-in automatic lock detection and control according to claim 1, characterized in that The phase detector is connected to a clock injection circuit, and the clock injection circuit includes a first NAND gate and a second NAND gate; Wherein, the two input terminals of the first NAND gate are respectively connected to the output terminal of the first delay unit of the voltage-controlled delay and the input terminal of the Lock_B signal, and the output terminal is connected to the first input terminal of the phase detector; The two input terminals of the second NAND gate are respectively connected to the output terminal at the end of the voltage-controlled delay chain and the input terminal of the Lock_B signal, and the output terminal is connected to the second input terminal of the phase detector.
8. The low-power delay-locked loop with built-in automatic lock detection and control according to any one of claims 1-7, characterized in that The total power consumption of the circuit in the locked state satisfies: Among them, C total represents the total capacitance driven by the clock signal, V DD represents the power supply voltage; f clk represents the clock frequency; I static represents the static current of the delay locked loop, and ε represents the dynamic power consumption correction factor, whose value range is 0.1 ≤ ε ≤ 0.
4.
9. An electronic device, comprising the low-power delay-locked loop with built-in automatic lock detection and control according to any one of claims 1-7.
10. The electronic device according to claim 9, wherein, The electronic device includes: A memory interface chip, a high-speed SerDes module, and a millimeter-wave radar signal processor.