High-speed sampler circuit

Abstract

The invention provides a high-speed sampler circuit, and the circuit comprises a sampler which carries out the sampling of a differential input signal at a rising edge of a clock signal, and outputs a sampling result; when the clock signal is in a low level, the sampler is in a reset state; the threshold adjustment and sampler offset voltage calibration module is used for generating a control signal according to the sampling result; and the current generation module is used for generating a current signal according to the control signal, and filling the current signal into a differential output port of the sampler when the clock signal is at a high level, so as to adjust the threshold value of the sampler and offset the offset voltage of the sampler. According to the invention, the parasitic capacitance introduced by the output node can be reduced, and the working speed of the sampler is effectively improved.

Description

Technical Field

[0001] The present invention relates to the field of integrated circuit technology, and particularly to a high-speed sampler circuit. Background Art

[0002] In applications such as communication, radar, and data transmission, serdes is applied at the interface, which can reduce the input / output pins (PINs) and interconnections. With the rapid development of multimedia sharing, cloud computing, and virtual reality technologies in recent years, the data rate of serial links has been continuously increasing, and the unit interval (UI) of serdes circuits has become smaller and smaller. Due to the relatively large aperture delay of traditional samplers, the recovered clock offset and the jitter tolerance are reduced due to the decrease in signal-to-noise ratios (SNRs), resulting in an increase in the threshold drift and offset voltage of the sampler, and an increase in bit error rate (BER); at the same time, the sampling signal input to the high-speed sampler is used as the input for clock adjustment of the clock recovery circuit (CDR), so it is important to eliminate the input offset voltage (Vos) of the sampler.

[0003] In traditional receivers, an input offset voltage cancellation signal and a threshold adjustment signal are respectively added at the output end of the sampler, resulting in a large parasitic capacitance being introduced at the output node, reducing the performance of the sampler. Summary of the Invention

[0004] In view of the problems existing in the above prior art, the present invention proposes a high-speed sampler circuit, which mainly solves the problem that the parasitic capacitance at the output node of the existing sampler is relatively large, affecting the performance of the device.

[0005] To achieve the above and other purposes, the technical solution adopted by the present invention is as follows.

[0006] The present application provides a high-speed sampler circuit, including:

[0007] A sampler that samples the differential input signal and outputs a sampling result at the rising edge of the clock signal; when the clock signal is at a low level, the sampler is in a reset state;

[0008] A threshold adjustment and sampler offset voltage calibration module that generates a control signal according to the sampling result;

[0009] A current generation module that generates a current signal according to the control signal and, when the clock signal is at a high level, injects the current signal into the differential output port of the sampler to adjust the threshold of the sampler and cancel the offset voltage of the sampler.

[0010] In an embodiment of the present application, the sampler includes a zero-th NMOS transistor, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor;

[0011] The gates of the first NMOS transistor and the second NMOS transistor are respectively the differential input ports of the sampler; the sources of the first NMOS transistor and the second NMOS transistor are connected and connected to the drain of the zero-th NMOS transistor; the source of the zero-th NMOS transistor is grounded, and the gate is connected to the clock signal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor as the first output terminal, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor as the second output terminal. Among them, the first output terminal and the second output terminal form the differential output port; the gates of the first PMOS transistor and the second PMOS transistor are connected to the clock signal, and the sources of the first PMOS transistor and the second PMOS transistor are connected and connected to the power supply voltage.

[0012] In an embodiment of the present application, the current generation module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a third PMOS transistor, and a digital-to-analog converter;

[0013] The sources of the third NMOS transistor, the sixth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are grounded; the drain of the third NMOS transistor is respectively connected to the source of the fourth NMOS transistor and the source of the fifth NMOS transistor; the gate of the fourth NMOS transistor is connected to the clock signal, and the gate of the fifth NMOS transistor is connected to the inverted clock signal; the drain of the fourth NMOS transistor is connected to the first output terminal; the drain of the fifth NMOS transistor is respectively connected to the drain of the third PMOS transistor and the drain of the eighth NMOS transistor; the gate and the drain of the third PMOS transistor are connected, and the source is connected to the power supply voltage; the gate of the eighth NMOS transistor is connected to the inverted clock signal, and the source is respectively connected to the drain of the sixth NMOS transistor and the source of the seventh NMOS transistor; the gate of the seventh NMOS transistor is connected to the clock signal, and the drain is connected to the second output terminal; the gate of the third NMOS transistor is connected to the gate of the ninth NMOS transistor; the gate and the drain of the ninth NMOS transistor are connected and then connected to the positive output current terminal of the digital-to-analog converter; the gate of the sixth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the gate and the drain of the tenth NMOS transistor are connected and then connected to the negative output current terminal of the digital-to-analog converter.

[0014] In an embodiment of the present application, the current generation module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a third NMOS transistor, and a digital-to-analog converter;

[0015] The drains of the third PMOS transistor, the sixth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are connected to the power supply voltage; the source of the third PMOS transistor is respectively connected to the drains of the fourth PMOS transistor and the fifth PMOS transistor; the gate of the fourth PMOS transistor is connected to the inverted signal of the clock signal, and the gate of the fifth PMOS transistor is connected to the clock signal; the source of the fourth PMOS transistor is connected to the first output terminal; the source of the fifth PMOS transistor is respectively connected to the drain of the third NMOS transistor and the source of the eighth PMOS transistor; the gate and the drain of the third NMOS transistor are connected, and the source is grounded; the gate of the eighth PMOS transistor is connected to the clock signal, and the drain is respectively connected to the source of the sixth PMOS transistor and the drain of the seventh PMOS transistor; the gate of the seventh PMOS transistor is connected to the inverted signal of the clock signal, and the source is connected to the second output terminal; the gate of the third PMOS transistor is connected to the gate of the ninth PMOS transistor; the gate and the source of the ninth PMOS transistor are connected and then connected to the positive output current terminal of the digital-to-analog converter; the gate of the sixth PMOS transistor is connected to the gate of the tenth PMOS transistor, and the gate and the source of the tenth PMOS transistor are connected and then connected to the negative output current terminal of the digital-to-analog converter.

[0016] In an embodiment of the present application, the sizes of the fourth NMOS transistor, the fifth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all smaller than the sizes of the third NMOS transistor and the sixth NMOS transistor.

[0017] In an embodiment of the present application, the sizes of the fourth PMOS transistor, the fifth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are all smaller than the sizes of the third PMOS transistor and the sixth PMOS transistor.

[0018] In an embodiment of the present application, the current generation module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, and a digital-to-analog converter;

[0019] The drain of the fourth NMOS transistor is connected to the first output terminal, and the drain of the fifth NMOS transistor is connected to the second output terminal; the sources of the fourth NMOS transistor and the fifth NMOS transistor are connected and then connected to the drain of the third NMOS transistor; the gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to the control signal, and the on / off states of the fourth NMOS transistor and the fifth NMOS transistor are determined by the control signal; the gate of the third NMOS transistor is connected to the clock signal, and the source is respectively connected to the drain of the sixth NMOS transistor and the source of the seventh NMOS transistor; the gate of the seventh NMOS transistor is connected to the inverted clock signal, and the drain is connected to the gate and drain of the third PMOS transistor; the source of the third PMOS transistor is connected to the power supply voltage; the sources of the sixth NMOS transistor and the eighth NMOS transistor are grounded; the gate of the sixth NMOS transistor is respectively connected to the gate and drain of the eighth NMOS transistor; the drain of the eighth NMOS transistor is connected to one of the single-sided output current terminals of the digital-to-analog converter.

[0020] In an embodiment of the present application, the current generation module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, and a digital-to-analog converter;

[0021] The source of the fourth PMOS transistor is connected to the first output terminal, and the source of the fifth PMOS transistor is connected to the second output terminal; the drains of the fourth PMOS transistor and the fifth PMOS transistor are connected and then connected to the source of the third PMOS transistor; the gates of the fourth PMOS transistor and the fifth PMOS transistor are connected to the control signal, and the on / off states of the fourth PMOS transistor and the fifth PMOS transistor are determined by the control signal; the gate of the third PMOS transistor is connected to the inverted clock signal, and the drain is respectively connected to the source of the sixth PMOS transistor and the drain of the seventh PMOS transistor; the gate of the seventh PMOS transistor is connected to the clock signal, and the source is connected to the gate and drain of the third NMOS transistor; the source of the third NMOS transistor is grounded; the drains of the sixth PMOS transistor and the eighth PMOS transistor are connected to the power supply voltage; the gate of the sixth PMOS transistor is respectively connected to the gate and source of the eighth PMOS transistor; the source of the eighth PMOS transistor is connected to one of the single-sided output current terminals of the digital-to-analog converter.

[0022] In an embodiment of the present application, the sizes of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor are all smaller than the size of the sixth NMOS transistor.

[0023] In an embodiment of the present application, the sizes of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the seventh PMOS transistor are all smaller than the size of the sixth PMOS transistor.

[0024] As described above, a high-speed sampler circuit proposed by the present application has the following beneficial effects.

[0025] The current signal is poured into the sampler output port only when the clock signal is at a high level, which can reduce the parasitic capacitance introduced by the output node, and thus effectively improve the working speed of the sampler. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 FIG. is a schematic diagram of the circuit architecture of a sampler in the prior art.

[0027] Figure 2 FIG. is a schematic diagram of the circuit architecture of another sampler in the prior art.

[0028] Figure 3 FIG. is a schematic diagram of the circuit architecture of the high-speed sampler circuit in an embodiment of the present application.

[0029] Figure 4 FIG. is a schematic diagram of the principle of the high-speed sampler circuit in another embodiment of the present application.

[0030] Figure 5 FIG. is a schematic diagram of the principle of the high-speed sampling circuit in another embodiment of the present application.

[0031] Figure 6 FIG. is a schematic diagram of the principle of the high-speed sampler circuit in another embodiment of the present application.

[0032] Figure 7 FIG. is a schematic diagram of the principle of the high-speed sampler circuit in another embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0033] The following specific examples illustrate the embodiments of the present invention. Those skilled in the art can easily understand the other advantages and effects of the present invention from the content disclosed in this specification. The present invention can also be implemented or applied through other different specific embodiments. Various details in this specification can also be modified or changed based on different viewpoints and applications without departing from the spirit of the present invention. It should be noted that, without conflict, the following embodiments and the features in the embodiments can be combined with each other.

[0034] It should be noted that the diagrams provided in the following embodiments only illustrate the basic concept of the present invention in a schematic manner. Therefore, only the components related to the present invention are shown in the diagrams, rather than being drawn according to the number, shape, and size of the components in actual implementation. The type, quantity, and ratio of each component in actual implementation can be arbitrarily changed, and the component layout type may also be more complex.

[0035] The inventors have found through research that:

[0036] As Figure 1 and Figure 2 shown, the existing sampler controls differential pair transistors by outputting voltages from a DAC (Digital-to-Analog Converter), and adds an input offset voltage cancellation signal and a threshold adjustment signal at the output end. Since the differential pair transistors are directly and always connected to the output node, parasitic capacitance is still introduced at the output node. As UI becomes smaller and smaller, the impact of this parasitic capacitance cannot be ignored.

[0037] Based on the deficiencies of the existing sampler, an embodiment of the present application proposes a high-speed sampler circuit. The technical solution of the present application will be elaborated in detail below in combination with specific embodiments.

[0038] Please refer to Figure 3 , Figure 3 , which is a schematic diagram of the architecture of the high-speed sampler circuit in an embodiment of the present application. The circuit includes: a sampler that samples a differential input signal and outputs a sampling result at the rising edge of a clock signal; when the clock signal is at a low level, the sampler is in a reset state; a threshold adjustment and sampler offset voltage calibration module that generates a control signal according to the sampling result; a current generation module that generates a current signal according to the control signal and injects the current signal into the differential output port of the sampler when the clock signal is at a high level to adjust the threshold of the sampler and cancel the offset voltage of the sampler. The threshold adjustment and sampler offset voltage calibration module in the embodiment of the present application may include: a DFE threshold adjustment unit, an offset voltage calibration unit, and an adder, and its structure has been given in the existing solution shown in Figure 1 and will not be elaborated here.

[0039] In one embodiment, the sampler may include a zero-th NMOS transistor, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; the gates of the first NMOS transistor and the second NMOS transistor are respectively the differential input ports of the sampler; the sources of the first NMOS transistor and the second NMOS transistor are connected and connected to the drain of the zero-th NMOS transistor; the source of the zero-th NMOS transistor is grounded, and the gate is connected to the clock signal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor as a first output end, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor as a second output end, wherein the first output end and the second output end form the differential output port; the gates of the first PMOS transistor and the second PMOS transistor are connected to the clock signal, and the sources of the first PMOS transistor and the second PMOS transistor are connected and connected to the power supply voltage.

[0040] Please refer to Figure 4 , Figure 4 which is the schematic diagram of the high-speed sampler circuit in another embodiment of the present application. The current generation module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a third PMOS transistor, and a digital-to-analog converter; the sources of the third NMOS transistor, the sixth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are grounded; the drain of the third NMOS transistor is connected to the sources of the fourth NMOS transistor and the fifth NMOS transistor respectively; the gate of the fourth NMOS transistor is connected to the clock signal, and the gate of the fifth NMOS transistor is connected to the inverted clock signal; the drain of the fourth NMOS transistor is connected to the first output terminal; the drain of the fifth NMOS transistor is connected to the drains of the third PMOS transistor and the eighth NMOS transistor respectively; the gate and drain of the third PMOS transistor are connected, and the source is connected to the power supply voltage; the gate of the eighth NMOS transistor is connected to the inverted clock signal, and the source is connected to the drains of the sixth NMOS transistor and the seventh NMOS transistor respectively; the gate of the seventh NMOS transistor is connected to the clock signal, and the drain is connected to the second output terminal; the gate of the third NMOS transistor is connected to the gate of the ninth NMOS transistor; the gate and drain of the ninth NMOS transistor are connected and then connected to the positive output current terminal of the digital-to-analog converter; the gate of the sixth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the gate and drain of the tenth NMOS transistor are connected and then connected to the negative output current terminal of the digital-to-analog converter. Its working principle: when the CLK is at a low level, transistors P1 and P2 are turned on, pulling the output terminals VOP / VON to a high level respectively; transistors N4 and N7 are turned off, transistors N5 and N8 are turned on, and the current is introduced into the dummy transistor P3. When transistors N4, N5, N7, and N8 are switched, the static voltages of each node of the current generation module are relatively stable, reducing the setup time; transistor N0 is turned off, so even if the differential signals VIN / VIP change, the pull-down currents of transistors N1 and N2 cannot change, and the entire sampler is in a reset state. When the rising edge of CLK arrives, transistors P1 and P2 are turned off, transistor N0 is turned on, the differential signals VIN / VIP are sampled through transistors N1 and N2, and the results are output to the output terminals VOP / VON; at this time, transistors N5 and N8 are turned off, transistors N4 and N7 are turned on, and the currents of VOP / VON are pulled down through lines Ip / In to adjust the threshold of the sampler and cancel the offset voltage of the sampler. Since transistors N4, N5, N7, and N8 are of small size, isolating the large-size transistors N3 and N6, the parasitic capacitance on the output nodes VOP / VON is reduced, and the working speed of the sampler is improved.

[0041] Please refer to Figure 5 , Figure 5 which is the schematic diagram of the high-speed sampling circuit in another embodiment of the present application. The current generation module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a third NMOS transistor, and a digital-to-analog converter; the drains of the third PMOS transistor, the sixth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are connected to the power supply voltage; the source of the third PMOS transistor is respectively connected to the drains of the fourth PMOS transistor and the fifth PMOS transistor; the gate of the fourth PMOS transistor is connected to the inverted signal of the clock signal, and the gate of the fifth PMOS transistor is connected to the clock signal; the source of the fourth PMOS transistor is connected to the first output terminal; the source of the fifth PMOS transistor is respectively connected to the drain of the third NMOS transistor and the source of the eighth PMOS transistor; the gate and the drain of the third NMOS transistor are connected, and the source is grounded; the gate of the eighth PMOS transistor is connected to the clock signal, and the drain is respectively connected to the source of the sixth PMOS transistor and the drain of the seventh PMOS transistor; the gate of the seventh PMOS transistor is connected to the inverted signal of the clock signal, and the source is connected to the second output terminal; the gate of the third PMOS transistor is connected to the gate of the ninth PMOS transistor; the gate and the source of the ninth PMOS transistor are connected and then connected to the positive output current terminal of the digital-to-analog converter; the gate of the sixth PMOS transistor is connected to the gate of the tenth PMOS transistor, and the gate and the source of the tenth PMOS transistor are connected and then connected to the negative output current terminal of the digital-to-analog converter. Its working principle: when the CLK is at a low level, the transistors P1 and P2 are turned on, pulling the output terminals VOP / VON to a high level respectively; the transistors P4 and P7 are turned off, and the transistors P5 and P8 are turned on, leading the current into the dummy transistor N3. When the transistors P4, P5, P7, and P8 are switched, the static voltages of the various nodes of the current generation module are relatively stable, reducing the setup time; the transistor N0 is turned off, so even if the differential signals VIN / VIP change, the pull-down currents of the transistors N1 and N2 cannot change, and the entire sampler is in a reset state. When the rising edge of the CLK arrives, the transistors P1 and P2 are turned off, and the transistor N0 is turned on, sampling the differential signals VIN / VIP through the transistors N1 and N2 and outputting the results to the output terminals VOP / VON; at this time, the transistors P5 and P8 are turned off, and the transistors P4 and P7 are turned on, and the current is poured into VOP / VON through the lines Ip / In to adjust the threshold of the sampler and cancel the offset voltage of the sampler. Since the transistors P4, P5, P7, and P8 use small sizes and isolate the large-size transistors P3 and P6, the parasitic capacitance on the output nodes VOP / VON is reduced, improving the working speed of the sampler.

[0042] Please refer toFigure 6 , Figure 6 is the schematic diagram of the high-speed sampler circuit in another embodiment of the present application. The current generation module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, and a digital-to-analog converter; the drain of the fourth NMOS transistor is connected to the first output terminal, and the drain of the fifth NMOS transistor is connected to the second output terminal; the sources of the fourth NMOS transistor and the fifth NMOS transistor are connected and then connected to the drain of the third NMOS transistor; the gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to the control signal, and the on / off states of the fourth NMOS transistor and the fifth NMOS transistor are determined by the control signal; the gate of the third NMOS transistor is connected to the clock signal, and the source is respectively connected to the drain of the sixth NMOS transistor and the source of the seventh NMOS transistor; the gate of the seventh NMOS transistor is connected to the inverted clock signal, and the drain is connected to the gate and the drain of the third PMOS transistor; the source of the third PMOS transistor is connected to the power supply voltage; the sources of the sixth NMOS transistor and the eighth NMOS transistor are grounded; the gate of the sixth NMOS transistor is respectively connected to the gate and the drain of the eighth NMOS transistor; the drain of the eighth NMOS transistor is connected to one of the unilateral output current terminals of the digital-to-analog converter. Figure 6 and Figure 4 and Figure 5The main difference is that the DAC output current can also be single-endedly sunk. Its working principle is as follows: When the CLK is at a low level, transistors P1 and P2 are turned on, pulling the output terminals VOP / VON to a high level respectively; transistor N3 is turned off, and transistor N7 is turned on, leading the current into the dummy transistor P3. When transistors N3 and N7 switch, the static voltages of each node of the current generation module are relatively stable, reducing the setup time; transistors N4 and N5 are determined to turn on N4 or N5 by a digital module composed of DFE threshold adjustment and sampler offset voltage calibration according to the sampling results of the previous sampler. If N4 is turned on and N5 is turned off, the current passes through N4 and is introduced into VOP from line Ip to adjust the DFE threshold and the sampler offset voltage. Conversely, if N4 is turned off and N5 is turned on, the current passes through N5 and is introduced into VON from line In to adjust the DFE threshold and the sampler offset voltage; transistor N0 is turned off, so that even if the differential signals VIN / VIP change, the pull-down currents of transistors N1 and N2 cannot change, and the entire sampler is in a reset state. When the rising edge of CLK arrives, transistors P1 and P2 are turned off, and transistor N0 is turned on to sample the differential signals VIN / VIP through transistors N1 and N2 and output the results to the output terminals VOP / VON; at this time, transistor N7 is turned off, and transistor N3 is turned on, introducing the current that pulls down VOP or VON from line Ip or In through transistor N4 or N5 to adjust the threshold of the sampler and cancel the offset voltage of the sampler. Since transistors N3, N4, N5, and N7 are of small size, isolating the large-size transistor N6, the parasitic capacitance on the output nodes VOP / VON is reduced, improving the operating speed of the sampler.

[0043] Please refer to Figure 7 , Figure 7Schematic diagram of the high-speed sampler circuit in another embodiment of the present application. The current generation module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, and a digital-to-analog converter; the source of the fourth PMOS transistor is connected to the first output terminal, and the source of the fifth PMOS transistor is connected to the second output terminal; the drains of the fourth PMOS transistor and the fifth PMOS transistor are connected and then connected to the source of the third PMOS transistor; the gates of the fourth PMOS transistor and the fifth PMOS transistor are connected to the control signal, and the on-off states of the fourth PMOS transistor and the fifth PMOS transistor are determined by the control signal; the gate of the third PMOS transistor is connected to the inverted signal of the clock signal, and the drain is respectively connected to the source of the sixth PMOS transistor and the drain of the seventh PMOS transistor; the gate of the seventh PMOS transistor is connected to the clock signal, and the source is connected to the gate and the drain of the third NMOS transistor; the source of the third NMOS transistor is grounded; the drains of the sixth PMOS transistor and the eighth PMOS transistor are connected to the power supply voltage; the gate of the sixth PMOS transistor is respectively connected to the gate and the source of the eighth PMOS transistor; the source of the eighth PMOS transistor is connected to one of the unilateral output current terminals of the digital-to-analog converter. Figure 7 and Figure 4 as well as Figure 5The main difference is that the DAC output current can also be single-endedly sunk. Its working principle: When the CLK is at a low level, transistors P1 and P2 are turned on, pulling the output terminals VOP / VON to a high level respectively; transistor P3 is turned off, and transistor P7 is turned on, leading the current into the dummy transistor N3. When transistors P3 and P7 switch, the static voltages of each node of the current generation module are relatively stable, reducing the setup time; transistors P4 and P5 are determined to turn on P4 or P5 by a digital module composed of DFE threshold adjustment and sampler offset voltage calibration according to the previous sampling results of the sampler. If P4 is turned on and P5 is turned off, the current passes through P4 and is sunk into VOP from the line Ip to adjust the DFE threshold and the sampler offset voltage. Conversely, if P4 is turned off and P5 is turned on, the current passes through P5 and is sunk into VON from the line In to adjust the DFE threshold and the sampler offset voltage; transistor N0 is turned off, and even if the differential signals VIN / VIP change, it cannot cause the pull-down currents of transistors N1 and N2 to change, and the entire sampler is in a reset state. When the rising edge of the CLK arrives, transistors P1 and P2 are turned off, and transistor N0 is turned on. The differential signals VIN / VIP are sampled through transistors N1 and N2, and the results are output to the output terminals VOP / VON; at this time, transistor P7 is turned off, and transistor P3 is turned on. The current sunk into VOP or VON from the line Ip or In through transistor P4 or P5 adjusts the threshold of the sampler and cancels the offset voltage of the sampler. Since transistors P3, P4, P5, and P7 are of small size and isolate the large-size transistor P6, the parasitic capacitance on the output nodes VOP / VON is reduced, improving the working speed of the sampler.

[0044] The above embodiments are only illustrative of the principles and effects of the present invention, and are not used to limit the present invention. Any person familiar with this technology can modify or change the above embodiments without departing from the spirit and scope of the present invention. Therefore, all equivalent modifications or changes completed by those with ordinary knowledge in the technical field without departing from the spirit and technical idea disclosed by the present invention should still be covered by the claims of the present invention.

Claims

1. A high-speed sampler circuit, characterized in that, Including: A sampler that samples a differential input signal at the rising edge of a clock signal and outputs a sampling result; When the clock signal is at a low level, the sampler is in a reset state; A threshold adjustment and sampler offset voltage calibration module that generates a control signal according to the sampling result; A current generation module that generates a current signal according to the control signal and, when the clock signal is at a high level, injects the current signal into the differential output ports of the sampler to adjust the threshold of the sampler and cancel the offset voltage of the sampler.

2. The high-speed sampler circuit according to claim 1, wherein The sampler includes a zero-th NMOS transistor, a first NMOS transistor, a second NMOS transistor, a first PMOS transistor, and a second PMOS transistor; The gates of the first NMOS transistor and the second NMOS transistor are respectively the differential input ports of the sampler; the sources of the first NMOS transistor and the second NMOS transistor are connected and connected to the drain of the zero-th NMOS transistor; the source of the zero-th NMOS transistor is grounded and the gate is connected to the clock signal; the drain of the first NMOS transistor is connected to the drain of the first PMOS transistor as a first output terminal, and the drain of the second NMOS transistor is connected to the drain of the second PMOS transistor as a second output terminal, wherein the first output terminal and the second output terminal form the differential output ports; the gates of the first PMOS transistor and the second PMOS transistor are connected to the clock signal, and the sources of the first PMOS transistor and the second PMOS transistor are connected and connected to the power supply voltage.

3. The high-speed sampler circuit according to claim 2, wherein The current generation module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a ninth NMOS transistor, a tenth NMOS transistor, a third PMOS transistor, and a digital-to-analog converter; The sources of the third NMOS transistor, the sixth NMOS transistor, the ninth NMOS transistor, and the tenth NMOS transistor are grounded; the drain of the third NMOS transistor is connected to the sources of the fourth NMOS transistor and the fifth NMOS transistor respectively; the gate of the fourth NMOS transistor is connected to the clock signal, and the gate of the fifth NMOS transistor is connected to the inverted clock signal; the drain of the fourth NMOS transistor is connected to the first output terminal; the drain of the fifth NMOS transistor is connected to the drains of the third PMOS transistor and the eighth NMOS transistor respectively; the gate and the drain of the third PMOS transistor are connected, and the source is connected to the power supply voltage; the gate of the eighth NMOS transistor is connected to the inverted clock signal, and the source is connected to the drains of the sixth NMOS transistor and the seventh NMOS transistor respectively; the gate of the seventh NMOS transistor is connected to the clock signal, and the drain is connected to the second output terminal; the gate of the third NMOS transistor is connected to the gate of the ninth NMOS transistor; the gate and the drain of the ninth NMOS transistor are connected and then connected to the positive output current terminal of the digital-to-analog converter; the gate of the sixth NMOS transistor is connected to the gate of the tenth NMOS transistor, and the gate and the drain of the tenth NMOS transistor are connected and then connected to the negative output current terminal of the digital-to-analog converter.

4. The high-speed sampler circuit according to claim 2, wherein The current generation module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a ninth PMOS transistor, a tenth PMOS transistor, a third NMOS transistor, and a digital-to-analog converter; The drains of the third PMOS transistor, the sixth PMOS transistor, the ninth PMOS transistor, and the tenth PMOS transistor are connected to the power supply voltage; the source of the third PMOS transistor is connected to the drains of the fourth PMOS transistor and the fifth PMOS transistor respectively; the gate of the fourth PMOS transistor is connected to the inverted clock signal, and the gate of the fifth PMOS transistor is connected to the clock signal; the source of the fourth PMOS transistor is connected to the first output terminal; the source of the fifth PMOS transistor is connected to the drains of the third NMOS transistor and the eighth PMOS transistor respectively; the gate and the drain of the third NMOS transistor are connected, and the source is grounded; the gate of the eighth PMOS transistor is connected to the clock signal, and the drain is connected to the sources of the sixth PMOS transistor and the seventh PMOS transistor respectively; the gate of the seventh PMOS transistor is connected to the inverted clock signal, and the source is connected to the second output terminal; the gate of the third PMOS transistor is connected to the gate of the ninth PMOS transistor; the gate and the source of the ninth PMOS transistor are connected and then connected to the positive output current terminal of the digital-to-analog converter; the gate of the sixth PMOS transistor is connected to the gate of the tenth PMOS transistor, and the gate and the source of the tenth PMOS transistor are connected and then connected to the negative output current terminal of the digital-to-analog converter.

5. The high-speed sampler circuit according to claim 3, characterized in that The sizes of the fourth NMOS transistor, the fifth NMOS transistor, the seventh NMOS transistor, and the eighth NMOS transistor are all smaller than the sizes of the third NMOS transistor and the sixth NMOS transistor.

6. The high-speed sampler circuit according to claim 4, wherein The sizes of the fourth PMOS transistor, the fifth PMOS transistor, the seventh PMOS transistor, and the eighth PMOS transistor are all smaller than the sizes of the third PMOS transistor and the sixth PMOS transistor.

7. The high-speed sampler circuit according to claim 2, wherein The current generation module includes: a third NMOS transistor, a fourth NMOS transistor, a fifth NMOS transistor, a sixth NMOS transistor, a seventh NMOS transistor, an eighth NMOS transistor, a third PMOS transistor, and a digital-to-analog converter; The drain of the fourth NMOS transistor is connected to the first output terminal, and the drain of the fifth NMOS transistor is connected to the second output terminal; the sources of the fourth NMOS transistor and the fifth NMOS transistor are connected and then connected to the drain of the third NMOS transistor; the gates of the fourth NMOS transistor and the fifth NMOS transistor are connected to the control signal, and the on / off states of the fourth NMOS transistor and the fifth NMOS transistor are determined by the control signal; the gate of the third NMOS transistor is connected to the clock signal, and the source is respectively connected to the drain of the sixth NMOS transistor and the source of the seventh NMOS transistor; the gate of the seventh NMOS transistor is connected to the inverted clock signal, and the drain is connected to the gate and drain of the third PMOS transistor; the source of the third PMOS transistor is connected to the power supply voltage; the sources of the sixth NMOS transistor and the eighth NMOS transistor are grounded; the gate of the sixth NMOS transistor is connected to the gate and drain of the eighth NMOS transistor; the drain of the eighth NMOS transistor is connected to one of the single-sided output current terminals of the digital-to-analog converter.

8. The high-speed sampler circuit according to claim 2, wherein The current generation module includes: a third PMOS transistor, a fourth PMOS transistor, a fifth PMOS transistor, a sixth PMOS transistor, a seventh PMOS transistor, an eighth PMOS transistor, a third NMOS transistor, and a digital-to-analog converter; The source of the fourth PMOS transistor is connected to the first output terminal, and the source of the fifth PMOS transistor is connected to the second output terminal; the drains of the fourth PMOS transistor and the fifth PMOS transistor are connected and then connected to the source of the third PMOS transistor; the gates of the fourth PMOS transistor and the fifth PMOS transistor are connected to the control signal, and the on / off states of the fourth PMOS transistor and the fifth PMOS transistor are determined by the control signal; the gate of the third PMOS transistor is connected to the inverted clock signal, and the drain is respectively connected to the source of the sixth PMOS transistor and the drain of the seventh PMOS transistor; the gate of the seventh PMOS transistor is connected to the clock signal, and the source is connected to the gate and drain of the third NMOS transistor; the source of the third NMOS transistor is grounded; the drains of the sixth PMOS transistor and the eighth PMOS transistor are connected to the power supply voltage; the gate of the sixth PMOS transistor is connected to the gate and source of the eighth PMOS transistor; the source of the eighth PMOS transistor is connected to one of the single-sided output current terminals of the digital-to-analog converter.

9. The high-speed sampler circuit according to claim 7, wherein The sizes of the third NMOS transistor, the fourth NMOS transistor, the fifth NMOS transistor, and the seventh NMOS transistor are all smaller than the size of the sixth NMOS transistor.

10. The high-speed sampler circuit according to claim 8, wherein The sizes of the third PMOS transistor, the fourth PMOS transistor, the fifth PMOS transistor, and the seventh PMOS transistor are all smaller than the size of the sixth PMOS transistor.

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