Preparation method of semiconductor structure, semiconductor structure and electronic equipment

Abstract

The invention relates to a preparation method of a semiconductor structure, the semiconductor structure and electronic equipment. The preparation method of the semiconductor structure comprises the following steps: alternately forming a plurality of first sacrificial layers and a plurality of second sacrificial layers on a substrate; etching the plurality of first sacrificial layers and the plurality of second sacrificial layers to form a plurality of etching holes; the first sacrificial layers exposed out of the etching holes are etched in the first direction, a plurality of first containing grooves are formed, and the first containing grooves comprise top-layer first containing grooves and middle first containing grooves located between the top-layer first containing grooves and the substrate; forming a word line material layer which fills the middle first accommodating groove and covers the inner wall of the etching hole and the inner wall of the top first accommodating groove; etching to remove the bottom wall of the etching hole, the side wall of the etching hole in a second direction and the word line material layer in the top-layer first accommodating groove, wherein the second direction is parallel to the substrate and intersects with the first direction; a first conductive layer is formed in the top first accommodating groove. The manufacturing difficulty is reduced, and the integration density of the semiconductor structure is improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and particularly to a method for manufacturing a semiconductor structure, a semiconductor structure, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly. As a result, small differences in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, people hope to fabricate as many device units as possible on a limited substrate. Since Moore's Law came out, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] Based on this, a method for manufacturing a semiconductor structure, a semiconductor structure, and an electronic device are provided.

[0005] To achieve the above object, in a first aspect, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure, including:

[0006] Providing a substrate, and alternately forming a plurality of layers of first sacrificial layers and a plurality of layers of second sacrificial layers on the substrate along a direction perpendicular to the substrate;

[0007] Etching the plurality of layers of first sacrificial layers and the plurality of layers of second sacrificial layers along a direction perpendicular to the substrate to form a plurality of etched holes arranged at intervals in a first direction parallel to the substrate, and making a portion of the second sacrificial layer located between any two adjacent etched holes along the first direction constitute a virtual channel portion;

[0008] Etching each of the first sacrificial layers exposed by the etched holes along the first direction to form a plurality of first accommodation grooves, the first accommodation grooves communicating with adjacent etched holes, the first accommodation grooves including a top-layer first accommodation groove farthest from the substrate and an intermediate first accommodation groove located between the top-layer first accommodation groove and the substrate;

[0009] Forming a word line material layer filling the intermediate first accommodation groove and covering the inner walls of the etched holes and the inner walls of the top-layer first accommodation groove;

[0010] Etching and removing the word line material layer on the bottom wall of the etched holes, on the side walls of the etched holes opposite to each other in a second direction, and in the top-layer first accommodation groove, the word line material layer forming an initial word line, the second direction being parallel to the substrate and intersecting with the first direction;

[0011] Forming a first conductive layer in the top-layer first accommodation groove, the first conductive layer being connected to the initial word line to form a word line.

[0012] In this embodiment, the multi-layer first sacrificial layer and the multi-layer second sacrificial layer are etched. In the art, the sacrificial layer usually uses materials that are relatively easy to etch, and the process is relatively mature, which reduces the process difficulty and broadens the process window. The depth of the holes or trenches formed by etching the multi-layer first sacrificial layer and the multi-layer second sacrificial layer can meet the process requirements, which is beneficial to increasing the number of layers of the semiconductor structure and improving the integration density of the semiconductor structure. At the same time, after forming the word line by using the selective damascene process, the virtual channel part penetrates the word line, and the region where the virtual channel part is located is used to form the gate dielectric layer and the channel layer after forming the word line. Moreover, the thickness of the virtual channel part is the same as the thickness of the second sacrificial layer. Therefore, the total thickness of the gate dielectric layer and the channel layer can be controlled by controlling the thickness of the second sacrificial layer to improve the integration density of the semiconductor structure. In addition, in this embodiment, a conductive material is filled in the first accommodating groove of the first sacrificial layer, and the conductive material is deposited on the opposite sidewalls of the etched hole in the first direction to form the word line. The formation of the word line does not involve the pre-deposition and etching of the conductive material, and has a high preparation accuracy. A word line with uniform thickness can be prepared. On this basis, even if the thickness of the word line is reduced within a certain limit, the gate control ability of the transistor can be ensured. Therefore, it is beneficial to improve the integration density of the semiconductor structure.

[0013] In some of these embodiments, before forming the plurality of etched holes arranged at intervals in the first direction parallel to the substrate, the method for manufacturing the semiconductor structure further includes: etching the multi-layer first sacrificial layer and the multi-layer second sacrificial layer in a direction perpendicular to the substrate to form a plurality of defined hole groups arranged at intervals in the first direction. Any one of the defined hole groups includes a first defined hole and a second defined hole arranged at intervals in the second direction parallel to the substrate. The region between the first defined hole and the second defined hole in the same defined hole group is used to define the formation position of the etched hole; forming a third sacrificial layer to fill the first defined hole and the second defined hole; after forming the third sacrificial layer, etching the third sacrificial layer of the first defined hole and the second defined hole to obtain the etched hole;

[0014] The step of etching and removing the word line material layer on the bottom wall of the etched hole, on the opposite sidewalls of the etched hole in the second direction, and in the top-layer first accommodating groove includes: etching and removing the word line material layer on the bottom wall of the etched hole and in the top-layer first accommodating groove; forming a first isolation structure in the etched hole; etching and removing the third sacrificial layer and the word line material layer on the opposite sidewalls of the etched hole in the second direction to form the initial word line.

[0015] In some of these embodiments, the first sacrificial layer includes a silicon oxide layer, the second sacrificial layer includes a silicon nitride layer, and the third sacrificial layer includes an aluminum oxide layer.

[0016] In some embodiments, the method for preparing the semiconductor structure further includes: forming a fourth sacrificial layer filling the first definition hole and the second definition hole and covering the side wall of the first isolation structure, the portion of the second sacrificial layer located between any two adjacent first definition holes along the first direction constituting a virtual electrode portion; etching the multi-layer first sacrificial layer and the multi-layer second sacrificial layer along a direction perpendicular to the substrate to form an etched groove extending along the first direction, the etched groove being located on the side of the first definition hole away from the second definition hole and exposing the side wall of the fourth sacrificial layer in the first definition hole; etching away the virtual electrode portion and the virtual channel portion along the second direction to form a second receiving groove connected to the etched groove; forming a gate dielectric material layer on the inner walls of the second receiving groove and the etched groove, and covering the gate dielectric material layer. A fifth sacrificial layer covering the gate dielectric material layer; removing the fourth sacrificial layer in the first defined hole and forming a supporting structure in the first defined hole; etching and removing the gate dielectric material layer and the fifth sacrificial layer on the inner wall of the etched groove and in the removal area of the virtual electrode portion, and backfilling the sixth sacrificial layer in the removal area of the gate dielectric material layer and the fifth sacrificial layer, the sixth sacrificial layer and the fifth sacrificial layer having the same material; removing the fourth sacrificial layer in the second defined hole, etching and removing the retained second sacrificial layer along the second direction to form a third accommodating groove; based on the third accommodating groove, etching the gate dielectric material layer along the second direction until the fifth sacrificial layer is exposed to form a gate dielectric layer, the gate dielectric layer is annular in structure, and the surrounding axis of the gate dielectric layer extends along the second direction.

[0017] In some embodiments, the method for preparing the semiconductor structure further includes: removing the retained fifth sacrificial layer and the sixth sacrificial layer; forming a semiconductor layer filling the inner region of the gate dielectric layer ring and covering the inner wall of the third receiving groove, wherein the semiconductor layer in the inner region of the gate dielectric layer ring constitutes a channel layer of the transistor; forming a second conductive layer filling the third receiving groove and covering the semiconductor layer in the third receiving groove, wherein the semiconductor layer in the third receiving groove and the second conductive layer together constitute a bit line. The simultaneous preparation of the channel layer and the bit line in this embodiment can reduce the preparation time of the semiconductor structure, thereby improving the preparation efficiency of the semiconductor structure.

[0018] In some of these embodiments, the steps of forming the semiconductor layer that fills the region within the gate dielectric layer ring and covers the inner wall of the third receiving groove, and the second conductive layer that fills the third receiving groove and covers the semiconductor layer within the third receiving groove include: forming a semiconductor material layer that fills the region within the gate dielectric layer ring and covers the inner wall of the third receiving groove, the inner wall of the second defining hole, the inner wall of the second receiving groove, and the inner wall of the etching groove; forming a second conductive material layer that fills the third receiving groove, the second defining hole, the second receiving groove, and the etching groove and covers the semiconductor material layer within the third receiving groove, the second defining hole, the second receiving groove, and the etching groove; etching away the second conductive material layer and the semiconductor material layer within the second defining hole to form the bit line; etching away the second conductive material layer and the semiconductor material layer within the etching groove; etching away a target size of the second conductive material layer and the semiconductor material layer within the second receiving groove along the second direction, so that the remaining semiconductor material layer constitutes the channel layer, and the target size is smaller than the size of the virtual electrode portion in the second direction.

[0019] In some of these embodiments, the method for preparing the semiconductor structure further includes:

[0020] Before etching away the second conductive material layer and the semiconductor material layer within the etching groove: etching away a partial region of the support structure within the first defining hole that is close to the first isolation structure, and the size of the remaining portion of the support structure along the second direction is not greater than the target size; forming a second isolation structure in the removal region of the support structure and within the second defining hole;

[0021] After etching away a target size of the second conductive material layer and the semiconductor material layer within the second receiving groove along the second direction: forming a first electrode in the removal region of the second conductive material layer and the semiconductor material layer within the second receiving groove; removing the remaining support structure; removing the first sacrificial layer between adjacent first electrodes; forming a dielectric layer that coats the exposed surfaces of each first electrode; forming a second electrode that covers the surface of the dielectric layer facing away from the first electrode.

[0022] In some of these embodiments, before etching each of the first sacrificial layers exposed by the etching holes along the first direction to form a plurality of first accommodation grooves, the manufacturing method further includes: etching and removing the virtual channel portion exposed by the etching holes along the first direction; filling a seventh sacrificial layer in the removal area of the virtual channel portion and in the etching holes; the material of the seventh sacrificial layer is different from the material of the second sacrificial layer; removing the seventh sacrificial layer in the etching holes so that the remaining seventh sacrificial layer reconstitutes the virtual channel portion; after removing the fourth sacrificial layer in the second definition holes, the step of forming the third accommodation groove is: etching the second sacrificial layer and the seventh sacrificial layer in sequence along the second direction.

[0023] In a second aspect, embodiments of the present disclosure provide a semiconductor structure, including a substrate and a plurality of memory cells and a plurality of word lines disposed on the substrate; the word lines extend along a direction perpendicular to the substrate and have a plurality of accommodation holes spaced apart in the direction perpendicular to the substrate, and the axes of the accommodation holes are parallel to the substrate; the memory cells include transistors, and each transistor includes a gate dielectric layer covering the inner sidewall of the accommodation hole, and a semiconductor layer covering the surface of the gate dielectric layer facing away from the word line and filling the accommodation hole, and the semiconductor layer further extends to cover the sidewall of the gate dielectric layer in the direction perpendicular to the substrate.

[0024] In the above semiconductor structure, on the one hand, the transistor is a ring gate transistor, which is beneficial to further reducing the device size compared with a planar transistor; on the other hand, the semiconductor layer constitutes the channel layer of the transistor, and the word line constitutes the gate of the transistor. The semiconductor layer further extending to cover the sidewall of the gate dielectric layer in the direction perpendicular to the substrate increases the coverage area of the channel layer, which increases the control ability of the gate over the channel and improves the turn-off ability of the transistor.

[0025] In some of these embodiments, the size of the gate dielectric layer in the axial direction of the accommodation hole is the same as the size of the accommodation hole in the axial direction.

[0026] In some of these embodiments, the semiconductor structure further includes a plurality of bit lines, the bit lines extend along a direction parallel to the substrate and intersect with the axial direction of the accommodation holes, and each bit line includes two semiconductor extension portions that are opposite to each other in the direction perpendicular to the substrate and are integrally connected to the semiconductor layer, and a conductive portion located between the two semiconductor extension portions.

[0027] In some of these embodiments, the size of the bit line in the direction perpendicular to the substrate is equal to the size of the accommodation hole in the direction perpendicular to the substrate.

[0028] In some of these embodiments, the storage unit further includes a capacitor, which includes a first electrode electrically connected to an end of the semiconductor layer away from the bit line, a dielectric layer covering the first electrode, and a second electrode covering a surface of the dielectric layer away from the first electrode. A dimension of the first electrode in a direction perpendicular to the substrate is equal to a dimension of the accommodation hole in the direction perpendicular to the substrate.

[0029] In a third aspect, the present disclosure provides an electronic device, including the semiconductor structure described in the second aspect. Description of the Drawings

[0030] To more clearly illustrate the technical solutions in the embodiments of the present application or in the prior art, the following will briefly introduce the drawings required for use in the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0031] Figure 1 It is a process flow chart of a preparation method of a semiconductor structure provided in an embodiment;

[0032] Figure 2 It is a top view of a substrate in an embodiment;

[0033] Figure 3 It is a cross-sectional view along lines a-a', b-b', c-c', and d-d' after forming a stacked structure on a substrate in an embodiment;

[0034] Figure 4 It is a cross-sectional view along lines a-a', b-b', c-c', and d-d' after forming a first definition hole and a second definition hole in an embodiment;

[0035] Figure 5 It is a cross-sectional view along lines a-a', b-b', c-c', and d-d' after forming a third sacrificial layer in an embodiment;

[0036] Figure 6 It is a cross-sectional view along lines a-a', b-b', c-c', and d-d' after forming an etching hole in an embodiment;

[0037] Figure 7 It is a cross-sectional view along lines a-a', b-b', c-c', and d-d' after forming a first accommodation groove in an embodiment;

[0038] Figure 8 It is a cross-sectional view along lines a-a', b-b', c-c', and d-d' after forming a word line material layer and an insulating material layer in an embodiment;

[0039] Figure 9 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after etching the insulating material layer in an embodiment;

[0040] Figure 10 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after etching the word line material layer in an embodiment;

[0041] Figure 11 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after filling the etching holes and the top first accommodating grooves with insulating material in an embodiment;

[0042] Figure 12 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after removing the insulating material in the top first accommodating groove in an embodiment;

[0043] Figure 13 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the first conductive layer in an embodiment;

[0044] Figure 14 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the word line in an embodiment;

[0045] Figure 15 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the fourth sacrificial layer in an embodiment;

[0046] Figure 16 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the etching trenches in an embodiment;

[0047] Figure 17 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the second accommodating groove in an embodiment;

[0048] Figure 18 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the gate dielectric material layer and the fifth sacrificial layer in an embodiment;

[0049] Figure 19 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the support structure in an embodiment;

[0050] Figure 20Cross-sectional views along lines a-a', b-b', c-c', and d-d' after removing the fifth sacrificial layer on the inner wall of the etching trench in an embodiment;

[0051] Figure 21 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after backfilling the sixth sacrificial layer in an embodiment;

[0052] Figure 22 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after removing the fourth sacrificial layer in the second defined hole in an embodiment;

[0053] Figure 23 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the gate dielectric layer in an embodiment;

[0054] Figure 24 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after removing the remaining fifth and sixth sacrificial layers in an embodiment;

[0055] Figure 25 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the semiconductor material layer in an embodiment;

[0056] Figure 26 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the bit line in an embodiment;

[0057] Figure 27 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the second isolation structure in an embodiment;

[0058] Figure 28 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after etching and removing the second conductive material layer in the etching trench in an embodiment;

[0059] Figure 29 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the channel layer in an embodiment;

[0060] Figure 30 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after removing the remaining support structure in an embodiment;

[0061] Figure 31 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after removing the first sacrificial layer between longitudinally adjacent first electrodes in an embodiment;

[0062] Figure 32 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the dielectric layer and the second electrode in an embodiment;

[0063] Figure 33 Cross-sectional view of the semiconductor structure at the e-e' position in an embodiment;

[0064] Figure 34 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after removing the virtual channel portion exposed by the etching hole in an embodiment;

[0065] Figure 35 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the seventh sacrificial layer in an embodiment;

[0066] Figure 36 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after removing the seventh sacrificial layer in the etching hole in another embodiment;

[0067] Figure 37 Cross-sectional views along lines a-a', b-b', c-c', and d-d' after forming the second receiving groove in another embodiment;

[0068] Description of reference numerals:

[0069] 1 - Substrate; 2 - Word line material layer; 21 - First conductive layer; 22 - Word line; 3 - Gate dielectric material layer; 31 - Gate dielectric layer; 4 - Semiconductor material layer; 41 - Channel layer; 5 - Second conductive material layer; 51 - Second conductive layer; 6 - Bit line; 7 - First electrode; 8 - Dielectric layer; 9 - Second electrode;

[0070] A1 - First sacrificial layer; A2 - Second sacrificial layer; A21 - Virtual channel portion; A22 - Virtual electrode portion; A3 - Third sacrificial layer; A4 - Fourth sacrificial layer; A5 - Fifth sacrificial layer; A6 - Sixth sacrificial layer; A7 - Seventh sacrificial layer; A8 - Insulating material layer; B1 - Etching hole; B2 - Etching trench; C1 - First defining hole; C2 - Second defining hole; D1 - First isolation structure; D2 - Support structure; E1 - First receiving groove; E2 - Second receiving groove; E3 - Third receiving groove. Detailed implementation manners

[0071] To facilitate the understanding of this application, the following will provide a more comprehensive description of this application with reference to the relevant drawings. Embodiments of this application are shown in the drawings. However, this application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of this application more thorough and comprehensive.

[0072] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are for the purpose of describing exemplary embodiments only and are not intended to limit this application.

[0073] It should be understood that when an element or layer is referred to as "on", "adjacent to", or "connected to" another element or layer, it can be directly on, adjacent to, or connected to the other element or layer, or there may be intervening elements or layers. In contrast, when an element is referred to as "directly on", "directly adjacent to", "directly connected to", or "directly coupled to" another element or layer, there are no intervening elements or layers.

[0074] It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, and / or parts, these elements, components, regions, layers, and / or parts should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, or part from another element, component, region, layer, or part. Thus, without departing from the teachings of this disclosure, the first element, component, region, layer, doping type, or part discussed below may be represented as the second element, component, region, layer, or part.

[0075] Here, embodiments of the invention are described with reference to cross-sectional views that are schematic diagrams of ideal embodiments (and intermediate structures) of this disclosure, and thus variations in the shapes shown can be expected due to, for example, manufacturing techniques and / or tolerances. Therefore, the embodiments of this disclosure should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques.

[0076] See Figure 1 , an exemplary embodiment of this disclosure provides a method for preparing a semiconductor structure, including the following steps:

[0077] Step S10: Provide a substrate, and alternately form a plurality of layers of a first sacrificial layer and a plurality of layers of a second sacrificial layer on the substrate along a direction perpendicular to the substrate;

[0078] Step S20: Etch the multiple layers of the first sacrificial layer and the multiple layers of the second sacrificial layer along the direction perpendicular to the substrate to form multiple etched holes arranged at intervals in the first direction parallel to the substrate, and make the part of the second sacrificial layer located between any two adjacent etched holes along the first direction constitute the virtual channel part;

[0079] Step S30: Etch each of the first sacrificial layers exposed by the etched holes along the first direction to form multiple first accommodation grooves. The first accommodation grooves communicate with adjacent etched holes. The first accommodation grooves include a top-layer first accommodation groove farthest from the substrate and an intermediate first accommodation groove located between the top-layer first accommodation groove and the substrate;

[0080] Step S40: Form a word line material layer that fills the intermediate first accommodation groove and covers the inner walls of the etched holes and the inner walls of the top-layer first accommodation groove;

[0081] Step S50: Etch and remove the word line material layer on the bottom wall of the etched hole, on the opposite sidewalls of the etched hole in the second direction, and in the top-layer first accommodation groove. The word line material layer forms an initial word line. The second direction is parallel to the substrate and intersects with the first direction;

[0082] Step S60: Form a first conductive layer in the top-layer first accommodation groove. The first conductive layer is connected to the initial word line to form a word line.

[0083] In the embodiment, the multiple layers of the first sacrificial layer and the multiple layers of the second sacrificial layer are etched. In the art, the sacrificial layer usually uses a material that is relatively easy to etch, and the process is relatively mature. This reduces the process difficulty and broadens the process window. The depth of the holes or trenches formed by etching the multiple layers of the first sacrificial layer and the multiple layers of the second sacrificial layer can meet the process requirements, which is beneficial to increasing the number of layers of the semiconductor structure and improving the integration density of the semiconductor structure. At the same time, the selective damascene process is used. After the word line is formed, the virtual channel part penetrates the word line, and the area where the virtual channel part is located is used to form a gate dielectric layer and a channel layer after the word line is formed, and then a ring gate transistor is fabricated to improve the integration density of the semiconductor structure.

[0084] The word line prepared in this embodiment includes two parts. One part is filled in several first accommodation grooves, and one part is located on the opposite sidewalls of the etched hole in the first direction to surround the part located in the first accommodation groove. The dimension of the word line in the first direction is the thickness of the word line. In this embodiment, a conductive material is filled in the first accommodation groove of the first sacrificial layer and a conductive material is deposited on the opposite sidewalls of the etched hole in the first direction to form a word line. The formation of the word line does not involve the pre-deposition and etching of the conductive material, has a high preparation accuracy, and can prepare a word line with uniform thickness. On this basis, even if the thickness of the word line is reduced within a certain limit, the gate control ability of the transistor can be ensured. Therefore, it is beneficial to improve the integration density of the semiconductor structure.

[0085] The following will be combined with Figures 2 - 37The preparation method of the semiconductor structure of this embodiment will be described in detail.

[0086] In step S10, referring to Figures 2 - 3 , a substrate 1 is provided, and a plurality of layers of first sacrificial layer A1 and a plurality of layers of second sacrificial layer A2 are alternately formed on the substrate 1 in a direction perpendicular to the substrate 1. The plurality of layers of first sacrificial layer A1 and the plurality of layers of second sacrificial layer A2 form a stacked structure.

[0087] Specifically, the material of the substrate 1 can be a semiconductor material, and the semiconductor material can be at least one of silicon, silicon germanium, silicon germanium carbon, silicon carbide, gallium arsenide, indium arsenide, and indium phosphide.

[0088] The step of forming the above stacked structure can be: alternately depositing a first sacrificial material and a second sacrificial material by any one of a chemical vapor deposition process (Chemical Vapor Deposition, CVD), a physical vapor deposition process (Physical Vapor Deposition, PVD), an atomic layer deposition process (Atomic Layer Deposition, ALD), or a sputtering process (sputtering) to alternately form the first sacrificial layer A1 and the second sacrificial layer A2 on the surface of the substrate 1.

[0089] The first sacrificial material and the second sacrificial material have a high etching selectivity under the same etching conditions. Exemplarily, the first sacrificial material and the second sacrificial material can be selected from at least one of silicon oxide, silicon nitride, or silicon oxynitride, and the first sacrificial material and the second sacrificial material are different. In some embodiments, the first sacrificial material is silicon oxide and the second sacrificial material is silicon nitride.

[0090] In step S20, referring to Figure 6 , the plurality of layers of first sacrificial layer A1 and the plurality of layers of second sacrificial layer A2 are etched in a direction perpendicular to the substrate 1 to form a plurality of etching holes B1 arranged at intervals in a first direction parallel to the substrate 1. Each etching hole B1 longitudinally penetrates the stacked structure, and the portion of the second sacrificial layer A2 located between any two adjacent etching holes B1 in the first direction constitutes a virtual channel portion A21. Specifically, the process of etching the plurality of layers of first sacrificial layer A1 and the plurality of layers of second sacrificial layer A2 uses an etching process that combines dry and wet methods.

[0091] In some alternative embodiments, referring to Figures 4 - 6 , after step S10 and before step S20, that is, before forming a plurality of etching holes B1 arranged at intervals in a first direction parallel to the substrate 1, the preparation method of the semiconductor structure further includes:

[0092] Step S11, referring to Figure 4, etch the multiple layers of the first sacrificial layer A1 and the multiple layers of the second sacrificial layer A2 along the direction perpendicular to the substrate 1 to form a plurality of defined hole groups arranged at intervals in the first direction. Any defined hole group includes a first defined hole C1 and a second defined hole C2 arranged at intervals in the first direction parallel to the substrate 1. The region between the first defined hole C1 and the second defined hole C2 in the same defined hole group is used to define the formation position of the etch hole B1.

[0093] Step S12, refer to Figure 5 , form a third sacrificial layer A3 that fills the first defined hole C1 and the second defined hole C2. Refer to Figure 6 , after forming the third sacrificial layer A3, then perform step S20 to etch the stacked structure to obtain a plurality of etch holes B1. During the process of etching the stacked structure, the third sacrificial layer A3 can precisely limit the etching region between the first defined hole C1 and the second defined hole C2 as an etching barrier.

[0094] Specifically, the wet etching process is used to form the etch holes B1. The wet etching process has anisotropy. The third sacrificial layer A3 located in the first defined hole C1 and the second defined hole C2 can play a blocking role during the wet etching process to limit the etched region. This is beneficial for preparing self-aligned gate-all-around, reduces the process difficulty, and improves the stability of the semiconductor structure.

[0095] Specifically, the third sacrificial layer A3 has a high etching selectivity with respect to the first sacrificial layer A1 and the second sacrificial layer A2. The material of the third sacrificial layer A3 includes but is not limited to alumina, and the material of the third sacrificial layer A3 is different from that of the first sacrificial layer A1 and the second sacrificial layer A2.

[0096] In step S30, refer to Figure 7 , etch each of the first sacrificial layers A1 exposed by the etch holes B1 along the first direction to form a plurality of first accommodation grooves E1. The first accommodation grooves E1 communicate with adjacent etch holes B1. The first accommodation grooves E1 include a top-layer first accommodation groove farthest from the substrate 1 and an intermediate first accommodation groove located between the top-layer first accommodation groove and the substrate 1. Specifically, the wet etching process is selected for the process of etching the first sacrificial layer A1 to form the first accommodation grooves E1, and the specific etching solution can be selected according to the actual material of the first sacrificial layer A1.

[0097] In step S40, refer to Figure 8 , form a word line material layer 2 that fills the intermediate first accommodation groove and covers the inner walls of the etch holes B1 and the inner walls of the top-layer first accommodation grooves. Specifically, the process of forming the word line material layer 2 includes atomic layer deposition process, and the material of the word line material layer 2 is a conductive material, such as metal or indium tin oxide (ITO).

[0098] In step S50, refer toFigures 8 - 14 , etch away the word line material layer 2 on the bottom wall of the etching hole B1, on the side walls of the etching hole B1 opposite to each other in the second direction, and in the top-layer first accommodating groove. The word line material layer 2 forms an initial word line. The second direction is parallel to the substrate 1 and intersects with the first direction. The initial word line includes the word line material layer 2 located in the middle first accommodating groove and the word line material layer 2 on the side walls of the etching hole B1 opposite to each other in the first direction.

[0099] It should be noted that the inner wall of the top-layer first accommodating groove includes the bottom wall and the side walls of the top-layer first accommodating groove. Etching away the word line material layer 2 on the inner wall of the top-layer first accommodating groove can remove all the word line material layer 2 on the bottom and side walls of the accommodating groove E1, or only remove the word line material layer 2 on the bottom of the top-layer accommodating groove E1.

[0100] In addition, the etching sequence of the word line material layer 2 on the bottom wall of the etching hole B1, on the side walls of the etching hole B1 opposite to each other in the second direction, and on the inner wall of the top-layer first accommodating groove is not limited herein. The word line material layer 2 at the three positions can be etched sequentially, or the etching of one position can be carried out first and then the other two positions can be etched simultaneously, or the etching of two positions can be carried out first and then the etching of the other position can be carried out. For example, the word line material layer 2 on the bottom wall of the etching hole B1 and the bottom wall of the top-layer first accommodating groove can be etched simultaneously first, and then the word line material layer 2 on the side walls of the etching hole B1 opposite to each other in the second direction can be etched.

[0101] Exemplarily, the step of etching away the word line material layer 2 on the bottom wall of the etching hole B1, on the side walls of the etching hole B1 opposite to each other in the second direction, and in the top-layer first accommodating groove in step S50 includes:

[0102] Step S501, refer to Figure 10 , etch away the word line material layer 2 on the bottom wall of the etching hole B1 and in the top-layer first accommodating groove;

[0103] Step S502, refer to Figure 12 , form a first isolation structure D1 in the etching hole B1. The material of the first isolation structure D1 includes but is not limited to silicon oxide;

[0104] Step S503, refer to Figure 14 , etch away the third sacrificial layer A3 and the word line material layer 2 on the side walls of the etching hole B1 opposite to each other in the second direction to form an initial word line.

[0105] Specifically, refer to Figures 8 - 10 , the etching of the word line material layer 2 on the bottom wall of the etching hole B1 and the bottom wall of the top-layer first accommodating groove simultaneously can be carried out with reference to the following steps:

[0106] Continue to refer toFigure 8 Deposit an insulating material layer A8 on the surface of the word line material layer 2. Specifically, the material of the insulating material layer A8 can be the same as that of the first sacrificial layer A1, and the material of the insulating material layer A8 includes but is not limited to silicon oxide. The process of depositing the insulating material layer A8 includes but is not limited to atomic layer deposition process.

[0107] See Figure 9 Etch the insulating material layer A8 to remove the insulating material near the bottom wall of the etching hole B1 and the bottom wall of the top first accommodating groove; specifically, the process of etching the insulating material layer A8 selects a wet etching process or a dry etching process, and preferably a wet etching process.

[0108] See Figure 10 Use the etched insulating material layer A8 as a mask to etch the word line material layer 2 to remove the word line material layer 2 located at the bottom wall of the etching hole B1 and the bottom wall of the top first accommodating groove; specifically, the process of etching the insulating material layer A8 selects a wet etching process or a dry etching process, and preferably a wet etching process.

[0109] In step S60, see Figure 13 Form a first conductive layer 21 with a target thickness in the top first accommodating groove. The first conductive layer 21 is connected to the initial word line to form a word line 22. That is, the word line 22 includes the conductive material located in the accommodating groove E1 and the conductive material located on the side wall in the first direction of the etching hole B1. The material of the first conductive layer 21 can be the same as that of the word line material layer 2. The process of forming the first conductive layer 21 includes processes such as CVD, PVD, and ALD, and the specific process is selected according to the material of the first conductive layer 21.

[0110] It should be noted that step S60 can be executed after step S502 and before step S50. See Figures 12 - 14 After forming the first isolation structure D1, form a first conductive layer 21 in the top first accommodating groove, and then etch the third sacrificial layer A3 and the word line material layer 2 on the partial side wall of the etching hole B1.

[0111] In some embodiments, after forming the word line 22 in step S60, the method for preparing the semiconductor structure further includes:

[0112] Step S70: Form a gate dielectric layer 31 that penetrates the word line 22 along the second direction; forming the gate dielectric layer 31 may include the following steps:

[0113] Step S701: See Figure 15, forming a fourth sacrificial layer A4 filling the first definition hole C1 and the second definition hole C2 and covering the side wall of the first isolation structure D1, and the portion of the second sacrificial layer A2 located between any two adjacent first definition holes C1 along the first direction constitutes a virtual electrode portion A22. Specifically, the material of the fourth sacrificial layer A4 includes but is not limited to an organic glue material, and the material of the fourth sacrificial layer A4 is different from the first sacrificial layer A1 and the second sacrificial layer A2, and the fourth sacrificial layer A4 can be formed by a coating process.

[0114] Step S702, see Figure 16 , etching the multi-layer first sacrificial layer A1 and the multi-layer second sacrificial layer A2 in a direction perpendicular to the substrate 1, forming an etching groove B2 extending in the first direction, the etching groove B2 is located on the side of the first definition hole C1 away from the second definition hole C2, and exposes the side wall of the fourth sacrificial layer A4 in the first definition hole C1, and the etching groove B2 penetrates the stacked structure composed of the multi-layer first sacrificial layer A1 and the multi-layer second sacrificial layer A2. Specifically, the process of etching the stacked structure to form the etching groove B2 adopts a dry etching process.

[0115] Step S703, see Figure 17 , the virtual electrode portion A22 and the virtual channel portion A21 are etched away along the second direction to form a second receiving groove E2 connected to the etched groove B2. The etching process used at this time is a wet etching process.

[0116] Step S704, see Figure 18 , a gate dielectric material layer 3 and a fifth sacrificial layer A5 covering the gate dielectric material layer 3 are formed on the inner walls of the second receiving groove E2 and the etched groove B2. The process of forming the gate dielectric material layer 3 includes but is not limited to an atomic layer deposition process, the material of the gate dielectric material layer 3 is a high dielectric constant (High-K) material, such as aluminum oxide, and the material of the fifth sacrificial layer A5 can be the same as the material of the fourth sacrificial layer A4.

[0117] Step S705, see Figure 19 , remove the fourth sacrificial layer A4 in the first definition hole C1, and form a support structure D2 in the first definition hole C1. Specifically, a wet etching process is used to remove the fourth sacrificial layer A4; the material of the support structure D2 includes but is not limited to silicon carbide, and the process of forming the support structure D2 includes CVD, PVD, ALD and other processes.

[0118] Step S706, see Figures 20 - 21 , the gate dielectric material layer 3 and the fifth sacrificial layer A5 on the inner wall of the etching groove B2 and the removal area of the virtual electrode portion A22 are removed by etching, and the sixth sacrificial layer A6 is backfilled in the removal area of the gate dielectric material layer 3 and the fifth sacrificial layer A5, and the sixth sacrificial layer A6 and the fifth sacrificial layer A5 are made of the same material. Specifically, the fifth sacrificial layer A5 and the gate dielectric material layer 3 are removed by a wet etching process.

[0119] Step S707, refer to Figure 22 , and remove the fourth sacrificial layer A4 in the second defined hole C2; specifically, the fourth sacrificial layer A4 is removed by a wet etching process.

[0120] Step S708, refer to Figure 23 , etch and remove the remaining second sacrificial layer A2 along the second direction to form a third accommodation groove E3; based on the third accommodation groove E3, etch the gate dielectric material layer along the second direction until the fifth sacrificial layer A5 is exposed to form a gate dielectric layer 31. The gate dielectric layer 31 has an annular structure, and the axis around which the gate dielectric layer 31 is located extends along the second direction. The process of etching the second sacrificial layer A2 is a dry etching process or a wet etching process, which can be selected according to needs; the process of etching the gate dielectric material layer is a wet etching process.

[0121] In some embodiments, after the gate dielectric layer 31 is formed in step S70, the method for manufacturing a semiconductor structure further includes:

[0122] Step S80: form a channel layer 41 and a bit line 6; forming the gate dielectric layer 31 may include the following steps:

[0123] Step S801, refer to Figure 24 , and remove the remaining fifth sacrificial layer A5 and sixth sacrificial layer A6;

[0124] Step S802, refer to Figures 25 - 29 , sequentially form a semiconductor layer that fills the region inside the gate dielectric layer 31 ring and covers the inner wall of the third accommodation groove E3, and a second conductive layer 51 that fills the third accommodation groove E3 and covers the semiconductor layer inside the third accommodation groove E3. The semiconductor layer in the region inside the gate dielectric layer 31 ring constitutes the channel layer 41 of the transistor, and the semiconductor layer and the second conductive layer 51 inside the third accommodation groove E3 together constitute the bit line 6. In this embodiment, the synchronous preparation of the channel layer 41 and the bit line 6 can reduce the manufacturing time of the semiconductor structure, thereby improving the manufacturing efficiency of the semiconductor structure.

[0125] In one embodiment, the steps of forming the semiconductor layer and the second conductive layer 51 in step S802 include:

[0126] Step S802a, refer to Figure 25, a semiconductor material layer 4 is formed to fill the area inside the ring of the filling gate dielectric layer 31 and cover the inner walls of the third accommodation groove E3, the second definition hole C2, the second accommodation groove E2, and the etching groove B2. Specifically, the process of forming the semiconductor material layer 4 is an atomic layer deposition process, which can precisely control the deposition thickness of the semiconductor material layer 4 and is beneficial to controlling the volume of the semiconductor structure. The material of the semiconductor material layer 4 may include indium gallium zinc oxide. For example, the material of the semiconductor material layer 4 may include at least one of the following materials: tin zinc oxide, indium zinc oxide, indium tin oxide, tungsten-doped indium oxide, zinc oxide, indium oxide, tin oxide, titanium oxide, indium zinc oxide, zinc oxide nitride, magnesium zinc oxide, indium zinc oxide, indium gallium zinc oxide, zirconium indium zinc oxide, hafnium indium zinc oxide, tin indium zinc oxide, aluminum tin indium zinc oxide, silicon indium zinc oxide, tin zinc oxide, aluminum zinc tin oxide, gallium zinc tin oxide, zirconium zinc tin oxide, indium gallium silicon oxide.

[0127] Step S802b, continue to refer to Figure 25 , a second conductive material layer 5 is formed to fill the third accommodation groove E3, the second definition hole C2, the second accommodation groove E2, and the etching groove B2 and cover the semiconductor material layer 4 inside the third accommodation groove E3, the second definition hole C2, the second accommodation groove E2, and the etching groove B2. Specifically, the process of forming the semiconductor material layer 4 is an atomic layer deposition process.

[0128] Step S802c, refer to Figure 26 , the second conductive material layer 5 and the semiconductor material layer 4 inside the second definition hole C2 are etched away to form a bit line 6. Specifically, the second conductive material layer 5 and the semiconductor material layer 4 are etched using selective deep hole etching.

[0129] Step S802d, refer to Figure 28 , the second conductive material layer 5 inside the etching groove B2 is etched away. Specifically, the process of etching the second conductive material layer 5 is a dry etching process or a wet etching process, and the specific process can be selected according to actual needs.

[0130] Step S802e, refer to Figure 29 , the second conductive material layer 5 and the semiconductor material layer 4 with a target size inside the second accommodation groove E2 are etched away along the second direction so that the remaining semiconductor material layer 4 forms a channel layer 41. The target size of the transistor is formed to be smaller than the size of the virtual electrode portion A22 in the second direction to avoid damaging the transistor, and the channel layer 41 extends to cover the sidewalls of the gate dielectric layer 31 in the direction perpendicular to the substrate 1. Specifically, the process of etching the second conductive material layer 5 and the semiconductor material layer 4 is a wet etching process.

[0131] In some embodiments, before etching away the second conductive material layer 5 and the semiconductor material layer 4 inside the etching groove B2, the following steps are further included: refer to Figure 26, etch away the support structure D2 in a partial area near the first isolation structure D1 within the first defined hole C1, and the dimension of the remaining part of the support structure D2 along the second direction is not greater than the target dimension; see Figure 27 , form a second isolation structure in the removed area of the support structure D2 and within the second defined hole C2, and the material of the second isolation structure can be the same as that of the first sacrificial layer A1.

[0132] In some embodiments, the method for preparing a semiconductor structure further includes:

[0133] Step S90, after etching away a target dimension of the second conductive material layer 5 and the semiconductor material layer 4 within the second receiving groove E2 along the second direction to form a channel layer 41, form a capacitor; forming the gate dielectric layer 31 may include the following steps:

[0134] Step S901, see Figure 30 , after etching away a target dimension of the second conductive material layer 5 and the semiconductor material layer 4 within the second receiving groove E2 along the second direction, form a first electrode 7 in the removed area of the second conductive material layer 5 and the semiconductor material layer 4 within the second receiving groove E2. The process for forming the first electrode 7 includes an atomic layer deposition process.

[0135] Step S902, see Figure 31 , remove the remaining support structure D2. Specifically, the process for removing the support structure D2 includes a dry etching process or a wet etching process, which is selected according to actual needs.

[0136] Step S903, continue to see Figure 31 , remove the first sacrificial layer A1 between adjacent first electrodes 7. Specifically, use a wet etching process to remove the first sacrificial layer A1.

[0137] Step S904, see Figure 32 , form a dielectric layer 8 covering the exposed surfaces of each first electrode 7. Specifically, the process for forming the dielectric layer 8 includes but is not limited to an atomic layer deposition process.

[0138] Step S905, continue to see Figure 32 , form a second electrode 9 covering the surface of the dielectric layer 8 facing away from the first electrode 7. Specifically, the process for forming the second electrode 9 includes but is not limited to an atomic layer deposition process. The first electrode 7, the second electrode 9, and the dielectric layer 8 located therebetween form a capacitor. For the cross-sectional view of the semiconductor structure at the e-e' position, see Figure 33 , at this time, the semiconductor structure is a memory.

[0139] As an alternative embodiment, after forming the etching hole B1 and before etching the first sacrificial layer A1 to form a plurality of first accommodating grooves E1, that is, after performing step S20 and before performing step S30, the method for manufacturing a semiconductor structure further includes:

[0140] Step S21, referring to Figure 34 , etch and remove the virtual channel portion A21 exposed by the etching hole B1 along the first direction. Specifically, wet etching process is used for etching.

[0141] Step S22, referring to Figure 35 , fill the seventh sacrificial layer A7 in the removal area of the virtual channel portion A21 and the etching hole B1. The material of the seventh sacrificial layer A7 is different from that of the second sacrificial layer A2. The material of the seventh sacrificial layer A7 includes but is not limited to polysilicon. The process for forming the seventh sacrificial layer A7 includes but is not limited to atomic layer deposition process.

[0142] Step S23, referring to Figure 36 , remove the seventh sacrificial layer A7 in the etching hole B1, so that the remaining seventh sacrificial layer A7 reconstitutes the virtual channel portion A21.

[0143] Correspondingly, referring to Figure 37 , Figure 17 , after removing the fourth sacrificial layer A4 in the second definition hole C2, the step of forming the second accommodating groove E2 is: etching the second sacrificial layer A2 and the seventh sacrificial layer A7 in sequence along the second direction.

[0144] It should be noted that the steps for forming the word line 22, the gate dielectric layer 31, the channel layer 41, the bit line 6, the first electrode 7, the dielectric layer 8, and the second electrode 9 in this embodiment are the same as those in the previous embodiment, and will not be described herein again; the finally manufactured semiconductor structure is also the same.

[0145] To more clearly illustrate the method for manufacturing a semiconductor structure in the above-mentioned embodiments, the following combines Figures 2 - 37 to clearly and completely describe an exemplary method for manufacturing a semiconductor structure.

[0146] Referring to Figures 2 - 3 , provide a substrate 1, and alternately form a plurality of layers of the first sacrificial layer A1 and a plurality of layers of the second sacrificial layer A2 on the substrate 1 along the direction perpendicular to the substrate 1. The plurality of layers of the first sacrificial layer A1 and the plurality of layers of the second sacrificial layer A2 form a stacked structure.

[0147] Referring to Figure 4, etch the multiple layers of the first sacrificial layer A1 and the multiple layers of the second sacrificial layer A2 along the direction perpendicular to the substrate 1 to form a plurality of defined hole groups arranged at intervals in the first direction parallel to the substrate 1. Any defined hole group includes a first defined hole C1 and a second defined hole C2 arranged at intervals in the first direction parallel to the substrate 1, and the first direction intersects with the second direction.

[0148] See Figure 5 , form a third sacrificial layer A3 to fill the first defined hole C1 and the second defined hole C2.

[0149] See Figure 6 , etch the multiple layers of the first sacrificial layer A1 and the multiple layers of the second sacrificial layer A2 between the first defined hole C1 and the second defined hole C2 along the direction perpendicular to the substrate 1 to form a plurality of etched holes B1 arranged at intervals in the first direction parallel to the substrate 1. The etched holes B1 longitudinally penetrate the stacked structure, and the part of the second sacrificial layer A2 located between any two adjacent etched holes B1 along the first direction constitutes a virtual channel part A21. During the etching process of the stacked structure, the third sacrificial layer A3 can limit the etching area between the first defined hole C1 and the second defined hole C2, and the third sacrificial layer A3 is used to pre-define the formation position of the etched holes B1.

[0150] See Figure 7 , etch each first sacrificial layer A1 exposed by the etched holes B1 along the first direction to form a plurality of first accommodation grooves E1. The first accommodation grooves E1 communicate with adjacent etched holes B1. The first accommodation grooves E1 include a top first accommodation groove farthest from the substrate 1 and intermediate first accommodation grooves located between the top first accommodation groove and the substrate 1.

[0151] See Figure 8 , form a word line material layer 2 to fill the intermediate first accommodation grooves and cover the inner walls of the etched holes B1 and the inner walls of the top first accommodation grooves. The inner walls of the etched holes B1 include the bottom wall and the side walls of the etched holes B1, and the inner walls of the top first accommodation grooves include the bottom wall and the side walls of the top first accommodation grooves.

[0152] Continue to see Figure 8 , deposit an insulating material layer A8 on the word line material layer 2.

[0153] See Figure 9 , etch the insulating material layer A8 to remove the insulating material near the bottom wall of the etched holes B1 and the bottom wall of the top first accommodation grooves.

[0154] See Figure 10 , use the etched insulating material layer A8 as a mask to etch the word line material layer 2 to remove the word line material layer 2 on the bottom wall of the etched holes B1 and the bottom wall of the top first accommodation grooves.

[0155] See Figures 11 - 12, an insulating material is filled into the etching hole B1 and the top-layer first accommodating groove to form a first isolation structure D1 in the etching hole B1; the insulating material in the top-layer first accommodating groove is removed to expose the word line material.

[0156] See Figure 13 , a first conductive layer 21 with a target thickness is formed in the top-layer first accommodating groove, and the material of the first conductive layer 21 is the same as that of the word line material layer 2.

[0157] See Figure 14 , the third sacrificial layer A3 and the word line material layer 2 on the side walls of the etching hole B1 opposite to each other in the second direction are etched away, the word line material layer 2 forms an initial word line, and the first conductive layer 21 is connected to the initial word line to form the word line 22.

[0158] See Figure 15 , a fourth sacrificial layer A4 that fills the first defining hole C1 and the second defining hole C2 and covers the side wall of the first isolation structure D1 is formed, and the part of the second sacrificial layer A2 located between any two adjacent first defining holes C1 in the first direction constitutes a virtual electrode part A22.

[0159] See Figure 16 , the multi-layer first sacrificial layer A1 and the multi-layer second sacrificial layer A2 are etched along the direction perpendicular to the substrate 1 to form an etching trench B2 extending in the first direction. The etching trench B2 is located on the side of the first defining hole C1 away from the second defining hole C2 and exposes the side wall of the fourth sacrificial layer A4 in the first defining hole C1.

[0160] See Figure 17 , the virtual electrode part A22 and the virtual channel part A21 are etched away along the second direction to form a second accommodating groove E2 communicating with the etching trench B2. At this time, the etching process used is a wet etching process.

[0161] See Figure 18 , a gate dielectric material layer 3 is formed on the inner walls of the second accommodating groove E2 and the etching trench B2, and a fifth sacrificial layer A5 covering the gate dielectric material layer 3 is formed.

[0162] See Figure 19 , the fourth sacrificial layer A4 in the first defining hole C1 is removed, and a support structure D2 is formed in the first defining hole C1.

[0163] See Figures 20 - 21 , the gate dielectric material layer 3 and the fifth sacrificial layer A5 on the inner wall of the etching trench B2 and in the removal area of the virtual electrode part A22 are etched away, and the sixth sacrificial layer A6 is backfilled in the removal area of the gate dielectric material layer 3 and the fifth sacrificial layer A5. The material of the sixth sacrificial layer A6 is the same as that of the fifth sacrificial layer A5.

[0164] See Figure 22, remove the fourth sacrificial layer A4 in the second defined hole C2.

[0165] See Figure 23 , etch and remove the remaining second sacrificial layer A2 along the second direction to form a third accommodation groove E3; based on the third accommodation groove E3, etch the gate dielectric material layer along the second direction until the fifth sacrificial layer A5 is exposed, to form a gate dielectric layer 31, the gate dielectric layer 31 has an annular structure, and the circumferential axis of the gate dielectric layer 31 extends along the second direction.

[0166] See Figures 24 - 25 , remove the remaining fifth sacrificial layer A5 and sixth sacrificial layer A6; form a semiconductor material layer 4 that fills the area inside the gate dielectric layer 31 ring and covers the inner wall of the third accommodation groove E3, the inner wall of the second defined hole C2, the inner wall of the second accommodation groove E2, and the inner wall of the etching groove B2.

[0167] Continue to see Figure 25 , form a second conductive material layer 5 that fills the third accommodation groove E3, the second defined hole C2, the second accommodation groove E2, and the etching groove B2 and covers the semiconductor material layer 4 inside the third accommodation groove E3, the second defined hole C2, the second accommodation groove E2, and the etching groove B2;

[0168] See Figure 26 , etch and remove the second conductive material layer 5 and the semiconductor material layer 4 in the second defined hole C2, the semiconductor material layer 4 and the second conductive layer 51 in the third accommodation groove E3 together constitute a bit line 6;

[0169] Continue to see Figure 26 , etch and remove the support structure D2 in a partial area near the first isolation structure D1 in the first defined hole C1, and the remaining part of the support structure D2 has a dimension along the second direction not greater than the target dimension;

[0170] See Figure 27 , form a second isolation structure in the removed area of the support structure D2 and in the second defined hole C2, and the material of the second isolation structure is the same as the material of the first sacrificial layer A1.

[0171] See Figure 28 , etch and remove the second conductive material layer 5 in the etching groove B2;

[0172] See Figure 29 , etch and remove the second conductive material layer 5 and the semiconductor material layer 4 with a target dimension in the second accommodation groove E2 along the second direction, so as to at least retain the semiconductor material layer 4 in the area inside the gate dielectric layer 31 ring, and the semiconductor material layer 4 in the area inside the gate dielectric layer 31 ring constitutes the channel layer 41 of the transistor, and the target dimension is smaller than the dimension of the virtual electrode part A22 in the second direction.

[0173] See Figure 30, a first electrode 7 is formed in the removal area of the second conductive material layer 5 and the semiconductor material layer 4 in the second accommodation groove E2;

[0174] Refer to Figure 31 , remove the remaining support structure D2;

[0175] Continue to refer to Figure 31 , remove the first sacrificial layer A1 between the longitudinally adjacent first electrodes 7;

[0176] Refer to Figure 32 , form a dielectric layer 8 covering the exposed surface of each first electrode 7;

[0177] Continue to refer to Figure 32 , form a second electrode 9 covering the surface of the dielectric layer 8 facing away from the first electrode 7. The first electrode 7, the second electrode 9, and the dielectric layer 8 located therebetween form a capacitor. For the cross-sectional view of the semiconductor structure at the e-e' position, refer to Figure 33 , at this time, the semiconductor structure is a memory.

[0178] As an alternative embodiment, the method for preparing the semiconductor structure further includes: after forming the Figure 6 shown etch hole B1 and before etching the first sacrificial layer A1 to form a plurality of first accommodation grooves E1:

[0179] Refer to Figure 34 , etch and remove the virtual channel portion A21 exposed by the etch hole B1 along the first direction;

[0180] Refer to Figure 35 , fill the removal area of the virtual channel portion A21 and the etch hole B1 with a seventh sacrificial layer A7, and the material of the seventh sacrificial layer A7 is different from that of the second sacrificial layer A2.

[0181] Refer to Figure 36 , remove the seventh sacrificial layer A7 in the etch hole B1 so that the remaining seventh sacrificial layer A7 reconstitutes the virtual channel portion A21.

[0182] Correspondingly, refer to Figure 37 , Figure 17 , after removing the fourth sacrificial layer A4 in the second definition hole C2, the step of forming the second accommodation groove E2 is: sequentially etch the second sacrificial layer A2 and the seventh sacrificial layer A7 along the second direction.

[0183] It should be noted that the steps for forming the word line 22, the gate dielectric layer 31, the channel layer 41, the bit line 6, the first electrode 7, the dielectric layer 8, and the second electrode 9 in this embodiment are the same as those in the previous embodiment and will not be elaborated here; the finally prepared semiconductor structure is also the same.

[0184] It should be understood that although Figure 1Each step in the flowchart is shown in sequence according to the arrow's indication. However, these steps are not necessarily executed in the order indicated by the arrows. Unless otherwise explicitly stated in this document, there is no strict order restriction for the execution of these steps, and these steps can be executed in other orders. Moreover, Figure 1 At least some of the steps may include multiple steps or multiple stages. These steps or stages are not necessarily executed at the same time but can be executed at different times. The execution order of these steps or stages is not necessarily sequential either, but can be executed alternately or in rotation with at least some of the steps or stages in other steps or other steps.

[0185] Please continue to refer to Figures 35 - 36 This embodiment of the present disclosure also provides a semiconductor structure, including a substrate 1 and a plurality of memory cells and a plurality of word lines 22 disposed on the substrate 1. The word lines 22 extend in a direction perpendicular to the substrate 1 and have a plurality of receiving holes spaced apart in the direction perpendicular to the substrate 1. The axes of the receiving holes are parallel to the substrate 1. The memory cell includes a transistor, and the transistor includes a gate dielectric layer 31 covering the inner sidewall of the receiving hole, and a semiconductor layer covering the surface of the gate dielectric layer 31 facing away from the word line 22 and filling the receiving hole. The semiconductor layer also extends to cover the sidewall of the gate dielectric layer 31 in the direction perpendicular to the substrate 1. The semiconductor layer forms a channel layer 41, and the gate dielectric layer 31 isolates the semiconductor layer and the word line 22.

[0186] In the above semiconductor structure, the semiconductor layer forms the channel layer 41 of the transistor, and the word line 22 forms the gate of the transistor. The semiconductor layer also extends to cover the sidewall of the gate dielectric layer 31 in the direction perpendicular to the substrate 1, which increases the coverage area of the channel layer 41, enhances the control ability of the gate over the channel, and improves the turn-off ability of the transistor.

[0187] Specifically, a plurality of word lines 22 are arranged in sequence along a first direction parallel to the substrate 1, and an insulating material is filled between adjacent word lines 22; the axes of the receiving holes are parallel to a second direction of the substrate 1, and the second direction intersects the first direction.

[0188] In some embodiments, the dimension of the gate dielectric layer 31 along the axis direction of the receiving hole is substantially the same as the dimension of the receiving hole along its axis direction. Here, the two dimensions being substantially the same means that the two dimensions are exactly the same or the difference between the two dimensions is negligible compared to the dimension of the receiving hole along its axis direction.

[0189] In some of these embodiments, the semiconductor structure further includes a plurality of bit lines 6 arranged in the direction perpendicular to the substrate 1, and an insulating layer located between adjacent bit lines 6. The bit lines 6 extend in a direction parallel to the substrate 1 and intersect with the axial direction of the receiving holes. The bit line 6 includes two semiconductor extension parts that are opposite in the direction perpendicular to the substrate 1 and are integrally connected to the semiconductor layer, and a conductive part located between the two semiconductor extension parts. Specifically, the extension directions of the plurality of bit lines 6 are parallel to the first direction. The material of the insulating layer includes, but is not limited to, silicon oxide and silicon nitride. The material of the conductive part can be a metal material, and the material of the semiconductor extension part can be the same as that of the semiconductor layer.

[0190] In some of these embodiments, the dimension of the bit line 6 in the direction perpendicular to the substrate 1 is equal to the dimension of the receiving hole in the direction perpendicular to the substrate 1.

[0191] In some of these embodiments, the memory cell further includes a plurality of capacitors. The capacitor includes a first electrode 7 electrically connected to the end of the semiconductor layer facing away from the bit line 6, a dielectric layer 8 covering the first electrode 7, and a second electrode 9 covering the surface of the dielectric layer 8 facing away from the first electrode 7. The dimension of the first electrode 7 in the direction perpendicular to the substrate 1 is equal to the dimension of the receiving hole in the direction perpendicular to the substrate 1.

[0192] Furthermore, the dielectric layer 8 in the memory cell is a complete film layer that covers the first electrodes 7 of the plurality of capacitors. The second electrode 9 in the memory cell is also a complete film layer that covers the entire dielectric layer 8 in the memory cell. This memory cell is not only easy to fabricate, but also has a relatively high capacitor density, which is beneficial to improving the storage density of the semiconductor structure (such as a memory). At the same time, the film layer structure of the dielectric layer 8 can isolate the word line 22 and the second electrode 9.

[0193] It should be noted that the semiconductor structure provided in the second aspect of the embodiments of the present disclosure can be obtained by using the manufacturing method of the semiconductor structure provided in the first aspect. Therefore, the descriptions of the materials of the respective film layers of the semiconductor structure in the first aspect also apply to the semiconductor structure in the second aspect, and will not be elaborated here one by one.

[0194] The semiconductor structure provided in the embodiments of the present application can be used in integrated circuits, such as in chip fields such as memories, digital logic circuits, etc. In the field of memories, it can be used in, but is not limited to, DRAM, NAND, NOR Flash, etc. The above-mentioned semiconductor structure can be, but is not limited to, a three-dimensional stacked structure of transistors, or a three-dimensional stacked structure of memory cells, or a three-dimensional stacked structure of memory arrays, etc.

[0195] The embodiments of the present disclosure also provide an electronic device including the above-mentioned semiconductor structure. The electronic device includes data storage devices, photocopiers, network devices, household appliances, instruments, mobile phones, computers, and other devices with data storage functions.

[0196] In the description of this specification, the descriptions referring to terms such as "some embodiments", "other embodiments", "ideal embodiments", etc. mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In this specification, the schematic description of the above terms does not necessarily refer to the same embodiment or example.

[0197] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0198] The above embodiments only represent several implementation manners of the present application. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, multiple deformations and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A method for preparing a semiconductor structure, characterized in that, Including: Providing a substrate, and alternately forming a plurality of layers of a first sacrificial layer and a plurality of layers of a second sacrificial layer on the substrate along a direction perpendicular to the substrate; Etching the plurality of layers of the first sacrificial layer and the plurality of layers of the second sacrificial layer along a direction perpendicular to the substrate to form a plurality of etched holes arranged at intervals in a first direction parallel to the substrate, and making a portion of the second sacrificial layer located between any two adjacent etched holes along the first direction constitute a virtual channel portion; Etching each of the first sacrificial layers exposed by the etched holes along the first direction to form a plurality of first accommodating grooves, the first accommodating grooves communicating with adjacent etched holes, the first accommodating grooves including a top-layer first accommodating groove farthest from the substrate and an intermediate first accommodating groove located between the top-layer first accommodating groove and the substrate; Forming a word line material layer filling the intermediate first accommodating groove and covering the inner walls of the etched holes and the inner walls of the top-layer first accommodating grooves; Etching and removing the word line material layer on the bottom wall of the etched holes, on the side walls of the etched holes opposite to each other in a second direction, and in the top-layer first accommodating grooves, the word line material layer forming an initial word line, the second direction being parallel to the substrate and intersecting with the first direction; Forming a first conductive layer in the top-layer first accommodating groove, the first conductive layer being connected to the initial word line to form a word line.

2. The method for manufacturing a semiconductor structure according to claim 1, wherein Before forming the plurality of etched holes arranged at intervals in the first direction parallel to the substrate, the manufacturing method of the semiconductor structure further includes: Etching the plurality of layers of the first sacrificial layer and the plurality of layers of the second sacrificial layer along a direction perpendicular to the substrate to form a plurality of defined hole groups arranged at intervals in the first direction, any one of the defined hole groups including a first defined hole and a second defined hole arranged at intervals in a second direction parallel to the substrate, and the region between the first defined hole and the second defined hole in the same defined hole group being used to define the formation position of the etched holes; Forming a third sacrificial layer filling the first defined hole and the second defined hole; after forming the third sacrificial layer, etching the third sacrificial layer in the first defined hole and the second defined hole to obtain the etched holes; The step of etching and removing the word line material layer on the bottom wall of the etched holes, on the side walls of the etched holes opposite to each other in the second direction, and in the top-layer first accommodating grooves includes: Etching and removing the word line material layer on the bottom wall of the etched holes and in the top-layer first accommodating grooves; Forming a first isolation structure in the etched holes; Etching and removing the third sacrificial layer and the word line material layer on the side walls of the etched holes opposite to each other in the second direction to form the initial word line.

3. The method for manufacturing a semiconductor structure according to claim 2, wherein, The first sacrificial layer includes a silicon oxide layer, the second sacrificial layer includes a silicon nitride layer, and the third sacrificial layer includes an aluminum oxide layer.

4. The method for preparing a semiconductor structure according to claim 2, wherein, Further including: Forming a fourth sacrificial layer filling the first defined hole and the second defined hole and covering the side walls of the first isolation structure, a portion of the second sacrificial layer located between any two adjacent first defined holes along the first direction constituting a virtual electrode portion; Etch the multi-layer first sacrificial layer and the multi-layer second sacrificial layer along the direction perpendicular to the substrate to form an etch trench extending along the first direction, the etch trench being located on a side of the first defined hole away from the second defined hole and exposing the sidewall of the fourth sacrificial layer in the first defined hole; Etch and remove the dummy electrode portion and the dummy channel portion along the second direction to form a second accommodation groove communicating with the etch trench; Form a gate dielectric material layer on the inner walls of the second accommodation groove and the etch trench, and a fifth sacrificial layer covering the gate dielectric material layer; Remove the fourth sacrificial layer in the first defined hole and form a support structure in the first defined hole; Etch and remove the gate dielectric material layer and the fifth sacrificial layer on the inner wall of the etch trench and in the removal area of the dummy electrode portion, and backfill a sixth sacrificial layer in the removal area of the gate dielectric material layer and the fifth sacrificial layer, the sixth sacrificial layer and the fifth sacrificial layer being made of the same material; Remove the fourth sacrificial layer in the second defined hole, and etch and remove the remaining second sacrificial layer along the second direction to form a third accommodation groove; Based on the third accommodation groove, etch the gate dielectric material layer along the second direction until the fifth sacrificial layer is exposed to form a gate dielectric layer, the gate dielectric layer having an annular structure, and the axis of the gate dielectric layer extending along the second direction.

5. The manufacturing method of the semiconductor structure according to claim 4, wherein, Further comprising: Remove the remaining fifth sacrificial layer and sixth sacrificial layer; Form a semiconductor layer filling the region inside the gate dielectric layer ring and covering the inner wall of the third accommodation groove, and the semiconductor layer in the region inside the gate dielectric layer ring constitutes the channel layer of the transistor; Form a second conductive layer filling the third accommodation groove and covering the semiconductor layer in the third accommodation groove, and the semiconductor layer and the second conductive layer in the third accommodation groove together constitute a bit line.

6. The manufacturing method of the semiconductor structure according to claim 5, characterized in that, The steps of forming a semiconductor layer filling the region inside the gate dielectric layer ring and covering the inner wall of the third accommodation groove, and forming a second conductive layer filling the third accommodation groove and covering the semiconductor layer in the third accommodation groove include: Form a semiconductor material layer filling the region inside the gate dielectric layer ring and covering the inner walls of the third accommodation groove, the second defined hole, the second accommodation groove, and the etch trench; Form a second conductive material layer filling the third accommodation groove, the second defined hole, the second accommodation groove, and the etch trench and covering the semiconductor material layer in the third accommodation groove, the second defined hole, the second accommodation groove, and the etch trench; Etch and remove the second conductive material layer and the semiconductor material layer in the second defined hole to form the bit line; Etch and remove the second conductive material layer and the semiconductor material layer in the etch trench; Etch and remove the second conductive material layer and the semiconductor material layer with a target size in the second accommodation groove along the second direction so that the remaining semiconductor material layer constitutes the channel layer, the target size being smaller than the size of the dummy electrode portion in the second direction.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, Further comprising: Before etching away the second conductive material layer and the semiconductor material layer within the etching trench: Etch away the support structure in a partial region of the first defined hole near the first isolation structure, where the dimension of the remaining portion of the support structure along the second direction is not greater than the target dimension; Form a second isolation structure in the removal region of the support structure and within the second defined hole; After etching away the second conductive material layer and the semiconductor material layer of a target dimension within the second accommodation groove along the second direction: Form a first electrode in the removal region of the second conductive material layer and the semiconductor material layer within the second accommodation groove; Remove the remaining support structure; Remove the first sacrificial layer between adjacent ones of the first electrodes; Form a dielectric layer coating the exposed surfaces of each of the first electrodes; Form a second electrode covering the surface of the dielectric layer facing away from the first electrodes.

8. The method for preparing a semiconductor structure according to claim 4, wherein Before etching each of the first sacrificial layers exposed by the etching holes along the first direction to form a plurality of first accommodation grooves, the manufacturing method further includes: Etch away the exposed virtual channel portion of the etching holes along the first direction; Fill a seventh sacrificial layer in the removal region of the virtual channel portion and within the etching holes; the material of the seventh sacrificial layer is different from that of the second sacrificial layer; Remove the seventh sacrificial layer within the etching holes such that the remaining seventh sacrificial layer reconstitutes the virtual channel portion; After removing the fourth sacrificial layer within the second defined hole, the step of forming the third accommodation groove is: etching the second sacrificial layer and the seventh sacrificial layer in sequence along the second direction.

9. A semiconductor structure, characterized in that, Comprising: A substrate and a plurality of memory cells and a plurality of word lines disposed on the substrate; The word lines extend in a direction perpendicular to the substrate and have a plurality of accommodation holes spaced apart from each other in the direction perpendicular to the substrate, and the axes of the accommodation holes are parallel to the substrate; The memory cells include transistors, and the transistors include a gate dielectric layer covering the inner sidewalls of the accommodation holes, and a semiconductor layer covering the surface of the gate dielectric layer facing away from the word lines and filling the accommodation holes, and the semiconductor layer further extends to cover the sidewalls of the gate dielectric layer in the direction perpendicular to the substrate.

10. The semiconductor structure according to claim 9, wherein, The dimension of the gate dielectric layer along the axis direction of the accommodation holes is the same as the dimension of the accommodation holes along the axis direction.

11. The semiconductor structure according to claim 9, wherein, Further including a plurality of bit lines, the bit lines extend in a direction parallel to the substrate and intersect with the axis direction of the accommodation holes, and the bit lines include two semiconductor extension portions that face each other in the direction perpendicular to the substrate and are integrally connected to the semiconductor layer, and a conductive portion located between the two semiconductor extension portions.

12. The semiconductor structure according to claim 11, wherein, The dimension of the bit lines in the direction perpendicular to the substrate is equal to the dimension of the accommodation holes in the direction perpendicular to the substrate.

13. The semiconductor structure according to claim 9, wherein The memory cells further include capacitors, and the capacitors include a first electrode electrically connected to one end of the semiconductor layer facing away from the bit lines, a dielectric layer coating the first electrode, and a second electrode covering the surface of the dielectric layer facing away from the first electrode, and the dimension of the first electrode in the direction perpendicular to the substrate is equal to the dimension of the accommodation holes in the direction perpendicular to the substrate.

14. An electronic device, characterized in that, Comprising a semiconductor structure as described in any one of claims 9 to 13.

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