Semiconductor structure, preparation method thereof and electronic equipment

Abstract

The invention discloses a semiconductor structure, a preparation method thereof and electronic equipment, and relates to the technical field of semiconductors. The semiconductor structure comprises a substrate; the grid electrode extends along the direction vertical to the substrate; the channel layer at least partially surrounds the grid electrode and comprises a vertical part perpendicular to the substrate and an extending part extending from the vertical part in the direction away from the grid electrode; the two conductive layers are arranged at intervals in the direction away from the substrate, and the conductive layers are connected with the extending parts. The contact area between the channel layer and the conductive layer is increased, and the contact resistance between the channel layer and the conductive layer is reduced.

Description

Technical Field

[0001] Embodiments of the present disclosure relate to the field of semiconductor technology, and in particular, to a semiconductor structure, a method for manufacturing the same, and an electronic device. Background Art

[0002] With the development of integrated circuit technology, the critical dimensions of devices are increasingly reduced, and the types and quantities of devices included in a single chip increase accordingly. As a result, any minor difference in the process production may affect the device performance.

[0003] In order to reduce the cost of products as much as possible, it is desired to fabricate as many device units as possible on a limited substrate. Since Moore's law came into being, various semiconductor structure designs and process optimizations have been proposed in the industry to meet the requirements of current products. Summary of the Invention

[0004] Embodiments of the present disclosure provide a semiconductor structure, a method for manufacturing the same, and an electronic device, which can optimize the contact area between the channel layer and the conductive layer and reduce the contact resistance.

[0005] The present disclosure provides a semiconductor structure, including:

[0006] A substrate;

[0007] A gate extending in a direction perpendicular to the substrate;

[0008] A channel layer at least partially surrounding the gate, including a vertical portion perpendicular to the substrate and an extending portion extending from the vertical portion in a direction away from the gate;

[0009] Two conductive layers spaced apart in a direction away from the substrate, the conductive layer being connected to the extending portion.

[0010] In some embodiments, it further includes:

[0011] A contact layer connected to the conductive layer and the channel layer respectively.

[0012] In some embodiments, the material of the contact layer includes titanium nitride, ITO, and IAZO.

[0013] In some embodiments, it further includes:

[0014] A gate trench including a vertical hole in communication and two lateral grooves; the vertical hole is perpendicular to the substrate, and the two lateral grooves are located between the two conductive layers and the vertical hole and expose at least the ends of the conductive layer;

[0015] Wherein, the contact layer covers the inner walls of the lateral grooves.

[0016] In some embodiments, the contact layer is located on the inner wall of the lateral groove, the vertical portion is located on the side wall of the vertical hole, the protruding portion is located in the lateral groove, the protruding portion includes a bottom surface close to the substrate, a top surface away from the substrate, and a side surface connecting the bottom surface and the top surface, and the bottom surface, the top surface, and the side surface of the protruding portion are all in contact with the contact layer; the gate is at least located in the vertical hole and the lateral groove, and a gate insulating layer for isolating the channel layer and the gate is further provided in the lateral groove.

[0017] In some embodiments, it further includes:

[0018] A dielectric layer, the dielectric layer is located on the upper surface and the lower surface of each layer of the conductive layer, and the dielectric layer is a Low-K dielectric layer.

[0019] In some embodiments, it further includes:

[0020] A gate trench, the gate trench includes a first gate trench and a second gate trench communicating with the first gate trench; the first gate trench is perpendicular to the substrate; the second gate trench is located on the upper surface and the lower surface of the part of the conductive layer exposed on the periphery of the first gate trench;

[0021] The vertical portion is located on the side wall of the first gate trench, the protruding portion is located on the inner wall of the second gate trench, the gate is at least located in the first gate trench and the second gate trench, and a gate insulating layer for isolating the channel layer and the gate is further provided in the second gate trench.

[0022] In some embodiments, the two layers of conductive layers include a first conductive layer close to the substrate and a second conductive layer away from the substrate, and the semiconductor structure further includes:

[0023] A first insulating layer, located between the first conductive layer and the substrate, and in the direction perpendicular to the substrate, the first gate trench extends into the first insulating layer;

[0024] A second insulating layer, located between the first conductive layer and the second conductive layer;

[0025] A third insulating layer, located on the surface of the second conductive layer away from the substrate;

[0026] Wherein, the second gate trench includes a first gate sub-trench, a second gate sub-trench, and a third gate sub-trench. The first gate sub-trench extends from the first gate trench into the first insulating layer, and exposes a part of the lower surface of the first conductive layer close to the substrate. The second gate sub-trench extends from the first gate trench into the second insulating layer, and exposes a part of the upper surface of the first conductive layer far from the substrate and a part of the lower surface of the second conductive layer close to the substrate. The third gate sub-trench extends from the first gate trench into the third insulating layer, and exposes a part of the upper surface of the second conductive layer far from the substrate. The channel layer covers the exposed first conductive layer, the exposed second conductive layer, the exposed first insulating layer, the exposed second insulating layer, and the exposed third insulating layer.

[0027] The embodiment of the present application further includes a method for manufacturing a semiconductor structure, including:

[0028] Providing a substrate;

[0029] Forming a stacked structure on the upper surface of the substrate, the stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer arranged in sequence along a direction away from the substrate;

[0030] Forming a channel layer and a gate, the gate at least penetrates the first conductive layer and is perpendicular to the substrate; the channel layer at least partially surrounds the gate, the channel layer includes a vertical portion perpendicular to the substrate, and an extending portion extending from the vertical portion along a direction away from the gate, and the extending portion is connected to the first conductive layer and the second conductive layer.

[0031] In some embodiments, before forming the channel layer and the gate, it further includes a step of forming a contact layer; forming the contact layer, the channel layer, and the gate includes:

[0032] Forming a vertical hole in the stacked structure that at least penetrates the first conductive layer at the bottom of the stacked structure, the vertical hole is perpendicular to the substrate;

[0033] Transversely etching away a part of the first conductive layer and a part of the second conductive layer from the vertical hole to form a transverse groove communicating with the vertical hole;

[0034] Forming the contact layer on the inner wall of the transverse groove;

[0035] Forming the channel layer at least on the side wall of the vertical hole and the surface of the contact layer;

[0036] Forming a gate insulating layer and a gate at least in the vertical hole and the transverse groove.

[0037] In some embodiments, forming the contact layer on the inner wall of the transverse groove includes:

[0038] Forming a contact material layer on the upper surface of the stacked structure, the side walls of the vertical holes, the bottoms of the vertical holes, and the inner walls of the transverse grooves;

[0039] Forming a sacrificial layer in the vertical holes and the transverse grooves;

[0040] Removing the sacrificial layer located in the vertical holes to expose the contact material layer located on the side walls and the bottoms of the vertical holes;

[0041] Removing the exposed contact material layer to obtain the contact layer only located in the transverse grooves;

[0042] Removing the sacrificial layer located in the transverse grooves.

[0043] In some embodiments, the stacked structure further includes a dielectric layer, the dielectric layer is located on the upper surfaces of the first conductive layer and the second conductive layer away from the substrate and the lower surfaces of the first conductive layer and the second conductive layer close to the substrate, and extends to the vertical holes; after removing the sacrificial layer located in the transverse grooves, it further includes:

[0044] Removing the dielectric layer located between the first conductive layer and the vertical holes and between the second conductive layer and the vertical holes.

[0045] In some embodiments, forming a channel layer and a gate includes:

[0046] Forming a first gate trench that at least penetrates the bottom of the stacked structure of the first conductive layer, the first gate trench being perpendicular to the substrate;

[0047] Transversely etching the first insulating layer, the second insulating layer, and the third insulating layer based on the first gate trench to form a second gate trench, the second gate trench exposing the partial lower surfaces of the first conductive layer and the second conductive layer close to the substrate and the partial upper surfaces of the first conductive layer and the second conductive layer away from the substrate;

[0048] Forming the integrated channel layer at least on the inner walls of the second gate trench, the end faces of the first conductive layer exposed by the first gate trench, and the end faces of the second conductive layer exposed by the first gate trench;

[0049] Sequentially forming a gate insulating layer and the gate in the first gate trench and the second gate trench.

[0050] The present disclosure also provides an electronic device, including the semiconductor structure described in any one of the above. BRIEF DESCRIPTION OF THE DRAWINGS

[0051] In order to more clearly illustrate the technical solutions in the embodiments of the present disclosure or the related art, the following will briefly introduce the drawings required for the description of the embodiments or the related art. Obviously, the drawings in the following description are only some embodiments of the present disclosure. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0052] Figure 1 It is a schematic flowchart of a method for manufacturing a semiconductor structure in some embodiments;

[0053] Figure 2 It is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a stacked structure in some embodiments;

[0054] Figure 3 For Figure 2 It is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a vertical hole in corresponding some embodiments;

[0055] Figure 4 For Figure 3 It is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a lateral groove in corresponding some embodiments;

[0056] Figure 5 For Figure 4 It is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a contact material layer in corresponding some embodiments;

[0057] Figure 6 For Figure 5 It is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a sacrificial layer in corresponding some embodiments;

[0058] Figure 7 For Figure 6 It is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a contact layer in corresponding some embodiments;

[0059] Figure 8 For Figure 7 It is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after removing the sacrificial layer in corresponding some embodiments;

[0060] Figure 9 For Figure 8 It is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a gate in corresponding some embodiments;

[0061] Figure 10 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a stacked structure in some other embodiments;

[0062] Figure 11 is Figure 10 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a vertical hole in some corresponding embodiments;

[0063] Figure 12 is Figure 11 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a lateral groove in some corresponding embodiments;

[0064] Figure 13 is Figure 12 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a contact material layer in some corresponding embodiments;

[0065] Figure 14 is Figure 13 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a sacrificial layer in some corresponding embodiments;

[0066] Figure 15 is Figure 14 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a contact layer in some corresponding embodiments;

[0067] Figure 16 is Figure 15 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after removing the sacrificial layer in some corresponding embodiments;

[0068] Figure 17 is Figure 16 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a filled trench in some corresponding embodiments;

[0069] Figure 18 is Figure 17 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a gate in some corresponding embodiments;

[0070] Figure 19 is Figure 2 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a second gate trench in some other corresponding embodiments;

[0071] Figure 20 is Figure 19 Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming a gate in some corresponding embodiments.

[0072] Element number description:

[0073] 102. Substrate; 104. Stacked structure; 106. Contact layer; 108. Channel layer; 110. Gate; 201. First insulating layer; 202. Second insulating layer; 203. Third insulating layer; 204. First conductive layer; 205. Second conductive layer; 206. Contact material layer; 208. Dielectric layer; 210. Vertical portion; 212. Protruding portion; 302. Vertical hole; 304. Transverse groove; 306. Sacrificial layer; 308. Filling trench; 310. First gate trench; 312. Second gate trench; 314. Gate trench; 402. Hard mask layer; 404. Photoresist pattern layer; 406. Opening. Detailed implementation manners

[0074] For ease of understanding the embodiments of the present disclosure, the embodiments of the present disclosure will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the embodiments of the present disclosure are given in the drawings. However, the embodiments of the present disclosure can be implemented in many different forms and are not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the embodiments of the present disclosure more thorough and comprehensive.

[0075] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which the embodiments of the present disclosure belong. The terms used herein in the description of the embodiments of the present disclosure are only for the purpose of describing specific embodiments and are not intended to limit the embodiments of the present disclosure. The term "and / or" used herein includes any and all combinations of one or more of the related listed items.

[0076] In the description of the embodiments of the present disclosure, it should be understood that the orientation or positional relationships indicated by the terms "upper", "lower", "vertical", "horizontal", "inner", "outer", etc. are based on the methods or positional relationships shown in the drawings, and are only for the convenience of describing the embodiments of the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation to the embodiments of the present disclosure.

[0077] It can be understood that the terms "first", "second", etc. used in the present disclosure can be used herein to describe various elements, but these elements are not limited by these terms. These terms are only used to distinguish the first element from another element. For example, without departing from the scope of the present disclosure, the first client can be referred to as the second client, and similarly, the second client can be referred to as the first client. Both the first client and the second client are clients, but they are not the same client.

[0078] In addition, the terms "first" and "second" are used for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first" and "second" may explicitly or implicitly include at least one such feature. In the description of the present disclosure, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined. In the description of the present disclosure, "several" means at least one, such as one, two, etc., unless otherwise specifically defined.

[0079] As used herein, the term "substrate", "substrate" means and includes the substrate material or structure of the materials of the transistors introduced in the present disclosure. The substrate may be a semiconductor substrate, a base semiconductor layer on a support structure, a metal electrode, or a semiconductor substrate having one or more layers, structures, or regions formed thereon. The substrate may be a conventional silicon substrate or other bulk substrate including a layer of semiconductor material.

[0080] In the present disclosure, the upper surface of the substrate is the surface on which the substrate forms a stacked structure, the lower surface of the substrate is the surface opposite to the upper surface, and the upper and lower surfaces of other structures or layers are relative to the upper surface of the substrate. For a structure or layer located in the substrate, of the two surfaces parallel to the substrate surface, the one closer to the upper surface of the substrate is the upper surface / top surface / top / top face, and the one away from the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom face. For a structure or layer located on the substrate, conversely, of the two surfaces, the one closer to the upper surface of the substrate is the lower surface / bottom surface / bottom / bottom face, and the one away from the upper surface of the substrate is the upper surface / top surface / top / top face. For a structure, trench, hole, or layer formed in the semiconductor structure in a direction away from the substrate surface, the surface in the longitudinal direction is the sidewall of the structure, trench, hole, or layer, and the position where the trench or hole penetrates and stops is the bottom of the trench or hole.

[0081] Figure 1 is a schematic flow chart of a method for manufacturing a semiconductor structure in some embodiments. As Figure 1 shown, in this embodiment, a method for manufacturing a semiconductor structure is provided, including:

[0082] S102, providing a substrate.

[0083] Provide a substrate, the constituent materials of the substrate including but not limited to undoped single-crystalline silicon, doped single-crystalline silicon, silicon-on-insulator (SOI), stacked silicon-on-insulator (SSOI), stacked silicon-germanium-on-insulator (S-SiGeOI), silicon-germanium-on-insulator (SiGeOI), and germanium-on-insulator (GeOI), gallium arsenide (GaAs), gallium nitride (GaN), silicon carbide (SiC), or any combination thereof. As an example, in this embodiment, the constituent material of the substrate is selected as single-crystalline silicon. The substrate has a certain thickness and can serve as a structural support for the device structure (such as a stacked structure) formed thereon. In some embodiments, the substrate can be removed or thinned in some subsequent process steps.

[0084] S104, form a stacked structure on the upper surface of the substrate. The stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially arranged in a direction away from the substrate.

[0085] Form a stacked structure on the upper surface of the substrate. The stacked structure includes a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer sequentially arranged in a direction away from the upper surface of the substrate. The first insulating layer is located between the substrate and the first conductive layer, the second insulating layer is located between the first conductive layer and the second conductive layer, and the third insulating layer is located on the surface of the second conductive layer away from the substrate. It can be understood that the first conductive layer and the second conductive layer in the stacked structure together form a vertical transistor. One of the first conductive layer and the second conductive layer subsequently forms the source electrode of the vertical transistor, and the other conductive layer subsequently forms the drain electrode of the vertical transistor.

[0086] In some embodiments, the constituent materials of the first conductive layer and the second conductive layer in the stacked structure can be the same or different.

[0087] In some embodiments, the thicknesses of the first conductive layer and the second conductive layer in the stacked structure can be the same or completely different.

[0088] S106, form a channel layer and a gate.

[0089] A channel layer, a gate insulating layer, and a gate are formed in a stacked structure. The gate penetrates at least the first conductive layer and is perpendicular to the substrate, that is, the gate extends from the upper surface of the stacked structure away from the substrate to at least penetrate the first conductive layer located at the bottom layer of the stacked structure; the channel layer at least partially surrounds the gate, and at least partially surrounding includes completely surrounding, partially surrounding, and being disposed on one side of the gate parallel to the substrate. It can be understood that the channel layer is located between the gate and the stacked structure; the channel layer includes a vertical portion perpendicular to the substrate and an extending portion extending from the vertical portion in a direction away from the gate, and the extending portion is connected to the first conductive layer and the second conductive layer. Exemplarily, the vertical portion and the extending portion are integrally connected. It can be understood that the extending portion is correspondingly disposed with the conductive layers (the first conductive layer and the second conductive layer), that is, the extending portion extends into the stacked structure on one side of the vertical portion and is correspondingly disposed with the first conductive layer and the second conductive layer in the stacked structure. The channel layer serves as a conduction channel between the source and the drain of the vertical transistor, and the gate serves as the gate of the vertical transistor.

[0090] In the manufacturing method of the above semiconductor structure, the formed channel layer extends from the vertical portion in a direction away from the gate, increasing the contact area between the channel layer and the conductive layer, reducing the contact resistance between the channel layer and the conductive layer, and improving the performance of the semiconductor structure.

[0091] In the above embodiment, the extending portion is two parts corresponding to the source and the drain respectively. The gate extends laterally and has a side surface and an end surface. The channel layer is located between the conductive layer and the gate, and the channel layer wraps the end portion and the side surface of the gate.

[0092] The first conductive layer and the second conductive layer are annular, and the extending portion is also annular, and the extending portion and the vertical portion are an integral structure.

[0093] In some embodiments, before forming the channel layer and the gate, the step of forming a contact layer is further included. The contact layer is respectively located between the channel layer and the first conductive layer in step S102, and between the channel layer and the second conductive layer in step S102. In the longitudinal direction perpendicular to the substrate, the contact layer corresponding to the first conductive layer in step S102 and the contact layer corresponding to the second conductive layer in step S102 are spaced apart from each other to maintain insulation. At this time, the contact layer and the first conductive layer in step S102 (which can be regarded as the first main part) together serve as the new first conductive layer, and the contact layer and the second conductive layer in step S102 (which can be regarded as the second main part) together serve as the new second conductive layer. At this time, the first conductive layer includes the first main part and the contact layer, the second conductive layer includes the second main part and the contact layer, the contact layer is a work function adjustment layer. The contact layer between the first main part and the channel layer connects the first main part and the channel layer while adjusting the work function between the first main part and the channel layer. The contact layer between the second main part and the channel layer connects the second main part and the channel layer while adjusting the work function between the second main part and the channel layer. The adjusted work function of the contact layer is between the conductive work function of the first conductive layer and the channel work function of the channel layer, and between the conductive work function of the second conductive layer and the channel work function of the channel layer. By setting the contact layer, the contact resistance when the conductive layer (the first conductive layer, the second conductive layer) is in direct contact with the channel layer can be reduced.

[0094] Figure 2 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the stacked structure in some embodiments. Figure 3 is Figure 2 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the vertical hole in corresponding some embodiments. Figure 4 is Figure 3 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the lateral groove in corresponding some embodiments. Figure 5 is Figure 4 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the contact material layer in corresponding some embodiments. Figure 6 is Figure 5 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the sacrificial layer in corresponding some embodiments. Figure 7 is Figure 6 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the contact layer in corresponding some embodiments. Figure 8 is Figure 7 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after removing the sacrificial layer in corresponding some embodiments. Figure 9 is Figure 8Schematic cross-sectional view of the semiconductor structure in a direction perpendicular to the substrate after forming the gate in some corresponding embodiments. Exemplarily, the X direction can be Figure 2 the row direction in the plane parallel to the substrate 102 as shown, and the Y direction can be Figure 2 the longitudinal direction perpendicular to the substrate 102 (from the top surface of the substrate 102 to the bottom surface of the substrate 102) as shown, and the Z direction can be Figure 2 the column direction in the plane parallel to the substrate 102 as shown. As Figures 2 - 9 shown, in one of the embodiments, before forming the channel layer 108 and the gate 110, it further includes the step of forming the contact layer 106, and forming the contact layer 106, the channel layer 108 and the gate 110 includes step S202 - step S210.

[0095] S202, forming a vertical hole of the first conductive layer that at least penetrates the bottom of the stacked structure within the stacked structure, and the vertical hole is perpendicular to the substrate.

[0096] As Figures 2 - 3 shown, provide the substrate 102, and form a stacked structure 104 on the upper surface of the substrate 102. The stacked structure 104 includes a first insulating layer 201, a first conductive layer 204, a second insulating layer 202, a second conductive layer 205, and a third insulating layer 203 arranged in sequence along the direction away from the substrate 102. The bottom surface of the stacked structure 104 close to the substrate 102 is the first insulating layer 201, and the top surface facing away from the substrate 102 is the third insulating layer 203.

[0097] In some embodiments, the steps of forming the stacked structure 104 on the substrate 102 include: forming a first insulating layer 201 on the upper surface of the substrate 102; forming a first conductive layer 204 on the upper surface of the first insulating layer 201, and forming a second insulating layer 202 on the upper surface of the first conductive layer 204; Exemplarily, the first conductive layer 204 is replaced with the first conductive layer 204 and the second insulating layer 202 arranged in the row direction X, so as to lead out the device structure in the substrate 102 below the stacked structure 104 to a suitable position on the substrate 102 through the lead-out structure passing through the second insulating layer 202 on one side of the first conductive layer 204; forming a second conductive layer 205 on the upper surface of the second insulating layer 202; forming a third insulating layer 203 on the upper surface of the second conductive layer 205, Exemplarily, the second conductive layer 205 is replaced with the second conductive layer 205 (located on the second insulating layer 202 on one side of the first conductive layer 204 and the first conductive layer 204) and the third insulating layer 203 (located on the first conductive layer 204) arranged in the row direction X, so as to lead out the device structure (such as the source or drain of a vertical transistor) in the substrate 102 below the second conductive layer 205 or the first conductive layer 204 below the second conductive layer 205 to a suitable position on the substrate 102 through the lead-out structure passing through the third insulating layer 203 on one side of the second conductive layer 205; wherein, when there are multiple vertical transistors stacked in the semiconductor structure in a direction away from the substrate 102 from the upper surface of the substrate 102, the stacked structure 104 includes a repeating unit composed of the first conductive layer 204, the second insulating layer 202, the second conductive layer 205, and the third insulating layer 203 sequentially arranged in a direction away from the substrate 102 of the third insulating layer 203, and the number of layers of the repeating unit is the same as the number of stacked vertical transistors. In the drawings, an example is given with one vertical transistor formed on the substrate 102.

[0098] Form a hard mask layer 402 and a photoresist pattern layer 404 on the stacked structure 104. An opening 406 penetrating the photoresist pattern layer is formed in the photoresist pattern layer. The opening 406 defines the shape and position of the vertical hole 302. Using the photoresist pattern layer 404 as a mask, the stacked structure 104 is patterned, and the hard mask layer 402 exposed by the opening 406 and the part of the stacked structure 104 at least on the bottom first insulating layer 201 are etched away to form a vertical hole 302 in the stacked structure 104. The vertical hole 302 extends along the longitudinal direction Y. The side wall of the vertical hole 302 is surrounded by the stacked structure 104. The bottom of the vertical hole 302 exposes the first insulating layer 201, that is, in the longitudinal direction Y, the vertical hole 302 at least penetrates the first conductive layer 204 at the bottom of the stacked structure 104.

[0099] It can be understood that the method for preparing the semiconductor structure further includes the steps of removing the hard mask layer 402 and the photoresist pattern layer 404. The hard mask layer 402 and the photoresist pattern layer 404 can be removed during the formation of the vertical hole 302, or can be separately removed after the formation of the vertical hole 302.

[0100] In some embodiments, the vertical hole 302 extends along the longitudinal direction Y from the upper surface of the stacked structure 104 at least into the first insulating layer 201 below the first conductive layer 204 at the bottom layer of the stacked structure 104, so as to avoid the vertical hole 302 staying in the first conductive layer 204 at the bottom layer of the stacked structure 104 due to process deviation.

[0101] S204, laterally etch a distance D from the vertical hole 302 to remove part of the first conductive layer 204 and part of the second conductive layer 205 to form a lateral groove 304 communicating with the vertical hole, and the lateral groove is a connected ring shape.

[0102] As Figure 4 shown, based on the lateral etching (side etching) of the vertical hole 302, part of the conductive layers 204 of each layer are removed to form a plurality of lateral grooves 304 communicating with the vertical hole 302. Among them, the lateral grooves 304 correspond to the first conductive layer 204 and the second conductive layer 205 respectively, and surround the side wall of the vertical hole 302. The inner wall of the lateral groove 304 includes a first side wall and a second side wall extending and parallel to each other in a plane parallel to the substrate (the first plane where the row direction X and the column direction Z are located), and a third side wall extending in a plane perpendicular to the substrate 102 (the second plane where the longitudinal direction Y and the column direction Z are located), and the third side wall connects the first side wall and the second side wall.

[0103] In some embodiments, the lateral grooves 304 respectively expose the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 on both sides of the lateral groove 304, that is, in the longitudinal direction Y, the height of the lateral groove 304 corresponding to the first conductive layer 204 is equal to the thickness of the first conductive layer 204, and the height of the lateral groove 304 corresponding to the second conductive layer 205 is equal to the thickness of the second conductive layer 205.

[0104] In some embodiments, the ends of the first conductive layer 204 and the second conductive layer 205 are the third side walls (the side walls perpendicular to the substrate) of the lateral groove 304, for example, fully surrounded or partially surrounded.

[0105] S206, form a contact layer 106 on the inner wall of the lateral groove 304.

[0106] As Figures 5 - 7As shown, a contact layer 106 is formed on the inner wall (first side wall, second side wall, and third side wall) of the horizontal groove 304. In the longitudinal direction Y, adjacent contact layers 106 are isolated from each other. Among them, the work function of the contact layer 106 is between the work function of the first conductive layer 204 and the work function of the channel layer 108, and between the work function of the second conductive layer 205 and the work function of the channel layer 108. The contact layer 106 and the corresponding first conductive layer 204 serve as the new first conductive layer, and the contact layer 106 and the corresponding second conductive layer 205 serve as the new second conductive layer. The subsequent contact layer 106 serves as part of the source and drain of the vertical transistor, reducing the difference in work function between the source and the channel layer 108 and between the drain and the channel layer 108, thereby reducing the contact resistance. Moreover, with the thicknesses of the first conductive layer 204 and the second conductive layer 205 remaining unchanged, the contact layer 106 located on the inner wall of the horizontal groove 304 increases the contact area between the source and the channel layer 108 and between the drain and the channel layer 108, further reducing the contact resistance.

[0107] The described contact layer is a conductive layer, which can be a metal nitride or a metal oxide.

[0108] The contact layer between the first conductive layer and the second conductive layer needs to be disconnected in the direction perpendicular to the substrate 102 to ensure insulation.

[0109] The contact layer can be formed by ALD. The shape of the contact layer is adapted to the shape of the horizontal groove and contacts the first conductive layer or the second conductive layer on the third side wall.

[0110] S208: A channel layer 108 is formed on the side wall of the vertical hole 302 and the surface of each contact layer 106.

[0111] As Figure 9 As shown, the channel layer 108 is formed on the surface of the contact layer 106 by an atomic layer deposition process or a chemical vapor deposition process. The channel layer 108 extends along the first side wall, the second side wall, and the third side wall of the horizontal groove 304 and covers the side wall of the vertical hole 302. Among them, the channel layer 108 serves as the channel of the vertical transistor. In some embodiments, the channel layer 108 extends and covers to the bottom of the vertical hole 302. Further, the channel layer 108 extends along the side wall of the vertical hole 302 and covers the top surface of the stacked structure 104.

[0112] The shape of the channel layer in the horizontal groove is adapted to the shape of the contact layer. The channel layer includes a horizontal portion located on the first side wall and the second side wall and a vertical portion located on the third side wall, and the channel layer is annular.

[0113] S210: A gate 110 is formed at least in the vertical hole 302 and the horizontal groove 304.

[0114] AsFigure 9 As shown, a gate insulating layer (not shown in the figure) and a gate 110 are sequentially formed on the surface of the channel layer 108. The gate 110 fills the vertical holes 302 and the horizontal grooves 304, and the gate 110 serves as the gate of the vertical transistor. In some embodiments, the gate 110 fills the vertical holes 302 and the horizontal grooves 304.

[0115] As Figures 5 - 8 shown, in one embodiment, a contact layer 106 is formed on the inner wall of the horizontal groove 304, including steps S302 - step S310.

[0116] S302, a contact material layer 206 is formed on the upper surface of the stacked structure 104, the side walls of the vertical holes 302, the bottoms of the vertical holes 302, and the inner walls of the horizontal grooves 304.

[0117] As Figure 5 shown, by using a physical vapor deposition process, a contact material layer 206 is formed on the upper surface of the stacked structure 104 away from the substrate 102, the side walls of the vertical holes 302, the bottoms of the vertical holes 302, and the inner walls of the horizontal grooves 304.

[0118] S304, a sacrificial layer 306 is formed in the vertical holes 302 and the horizontal grooves 304.

[0119] As Figure 6 shown, a sacrificial layer 306 is formed on the surface of the contact material layer 206. The sacrificial layer 306 fills the vertical holes 302 and the horizontal grooves 304 and is located on the stacked structure 104; further, the sacrificial layer 306 fills the vertical holes 302 and the horizontal grooves 304.

[0120] S306, the sacrificial layer 306 located in the vertical holes 302 is removed to expose the contact material layer 206 located on the side walls and the bottoms of the vertical holes 302.

[0121] As Figure 6 、 Figure 7 shown, by using a dry etching process (plasma etching process), the sacrificial layer 306 in the vertical holes 302 is etched away to expose the contact material layer 206 located on the side walls and the bottoms of the vertical holes 302. At this time, the sacrificial layer 306 in the horizontal grooves 304 is retained, thereby protecting the contact material layer 206 on the inner wall of the horizontal grooves 304 and preventing the contact material layer 206 on the inner wall of the horizontal grooves 304 from being etched when the contact material layer 206 in the vertical holes 302 is removed subsequently.

[0122] S308, the exposed contact material layer 206 is removed to obtain the contact layer 106 only located in the horizontal grooves 304.

[0123] As Figure 7As shown, the sidewalls and the bottom of the vertical holes 302 are etched away to expose the contact material layer 206, resulting in the contact layer 106 formed by the remaining contact material layer 206. The contact layer 106 corresponds to the first conductive layer 204 and the second conductive layer 205 respectively. In the longitudinal direction Y, adjacent contact layers 106 are isolated by the second insulating layer 202.

[0124] It can be understood that when the etching rates of the contact material layer 206 and the sacrificial layer 306 are the same, the contact material layer 206 on the sidewalls of the vertical holes 302 and the sacrificial layer 306 in the vertical holes 302 are removed simultaneously. At this time, the contact material layer 206 at the bottom of the vertical holes 302 is retained as part of the contact layer 106.

[0125] S310, removing the sacrificial layer 306 located in the transverse grooves 304.

[0126] As Figure 8 shown, a wet etching process is used to remove the sacrificial layer 306 located in the transverse grooves 304 to expose the surface of the contact layer 106, facilitating the increase of the contact area between the channel layer and the contact layer 106 (including the new first conductive layer of the contact layer 106 and the new second conductive layer of the contact layer 106) when forming the channel layer in contact with the contact layer 106 later, and reducing the contact resistance.

[0127] In some embodiments, the constituent materials of the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 include, but are not limited to, one or more of silicon oxides (such as silicon dioxide), silicon nitrides (such as silicon oxynitride), and nitrides (such as silicon nitride). Exemplarily, the constituent materials of the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 are silicon dioxide.

[0128] In some embodiments, the constituent materials of the first conductive layer 204 and the second conductive layer 205 include, but are not limited to, one or more of conductive polysilicon, metals, conductive metal nitrides, conductive metal oxides, and metal silicides. Among them, the metal can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2); the metal silicide includes titanium silicide (TiSi). Exemplarily, the constituent materials of the first conductive layer 204 and the second conductive layer 205 are tungsten (W).

[0129] In some embodiments, the constituent materials of the contact layer 106 include conductive metals or conductive metal compounds, such as titanium and titanium nitride. Exemplarily, the constituent material of the contact layer 106 is titanium nitride.

[0130] In some embodiments, the material constituting the channel layer 106 may be a material such as silicon or polysilicon with a bandgap less than 2 eV, or may also be a wide-bandgap material, such as a metal oxide material with a bandgap greater than 2 eV.

[0131] For example, the material of the channel layer 106 may include metal oxides of at least one of the following metals: indium, gallium, zinc, tin, tungsten, magnesium, zirconium, aluminum, hafnium, etc. Of course, the metal oxide may also include compounds containing other elements, such as elements N, Si, etc.; and may also include other minor doping elements.

[0132] In some embodiments, the material of the channel layer 106 may include one or more of the following: indium gallium zinc oxide (InGaZnO), indium zinc oxide (InZnO), indium gallium oxide (InGaO), indium tin oxide (InSnO), indium gallium tin oxide (InGaSnO), indium gallium zinc tin oxide (InGaZnSnO), indium oxide (InO), tin oxide (SnO), zinc tin oxide (ZnSnO, ZTO), indium aluminum zinc gold oxide (InAlZnO), zinc oxide (ZnO), indium gallium silicon oxide (InGaSiO), indium tungsten oxide (InWO, IWO), titanium oxide (TiO), zinc oxide nitride (ZnON), magnesium zinc oxide (MgZnO), zirconium indium zinc oxide (ZrInZnO), hafnium indium zinc oxide (HfInZnO), tin indium zinc oxide (SnInZnO), aluminum tin indium zinc oxide (AlSnInZnO), silicon indium zinc oxide (SiInZnO), aluminum zinc tin oxide (AlZnSnO), gallium zinc tin oxide (GaZnSnO), zirconium zinc tin oxide (ZrZnSnO), etc. As long as the leakage current of the transistor can meet the requirements, it can be specifically adjusted according to the actual situation.

[0133] These materials have a wide bandgap and low leakage current. For example, when the channel layer 106 is IGZO, the leakage current of the transistor is small, thereby improving the operating performance of the dynamic memory.

[0134] The above materials of the channel layer 106 only emphasize the element types of the materials, not the atomic ratio in the materials and the film quality of the materials.

[0135] In some embodiments, the material constituting the sacrificial layer 306 includes but is not limited to one or more of undoped polysilicon, silicon oxide (such as silicon dioxide), silicon nitride (such as silicon oxynitride), nitride (such as silicon nitride), wherein the etching rate of the sacrificial layer 306 is greater than the etching rates of the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203. Preferably, the material constituting the sacrificial layer 306 is undoped polysilicon.

[0136] In some embodiments, the constituent material of the gate insulating layer may be silicon oxide (SiO2) or silicon oxynitride (SiNO). Since the feature size of the gate is very small, the gate insulating layer preferably uses a high dielectric constant (high-k) material to reduce the parasitic capacitance. High-k materials include hafnium oxide, hafnium silicon oxide, hafnium silicon oxynitride, lanthanum oxide, zirconium oxide, zirconium silicon oxide, titanium oxide, tantalum oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, aluminum oxide, etc. In an ideal embodiment, they are hafnium oxide, zirconium oxide, and aluminum oxide. The formation process of the gate dielectric layer can adopt any existing technology well-known to those skilled in the art, such as chemical vapor deposition.

[0137] In some embodiments, the constituent material of the gate includes, but is not limited to, one or more of conductive polysilicon, metal, conductive metal nitride, conductive metal oxide, and metal silicide. Among them, the metal can be tungsten (W), nickel (Ni), or titanium (Ti); the conductive metal nitride includes titanium nitride (TiN); the conductive metal oxide includes iridium oxide (IrO2), indium tin oxide (ITO); the metal silicide includes titanium silicide (TiSi). Preferably, the constituent material of the gate is indium tin oxide (ITO).

[0138] Figure 10 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a stacked structure in some other embodiments. Figure 11 is Figure 10 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a vertical hole in some corresponding embodiments. Figure 12 is Figure 11 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a lateral groove in some corresponding embodiments. Figure 13 is Figure 12 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a contact material layer in some corresponding embodiments. Figure 14 is Figure 13 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a sacrificial layer in some corresponding embodiments. Figure 15 is Figure 14 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming a contact layer in some corresponding embodiments. Figure 16 is Figure 15 FIG. is a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after removing the sacrificial layer in some corresponding embodiments, as shown in Figures 10 - 16As shown, in one embodiment, the stacked structure 104 further includes a dielectric layer 208. Exemplarily, the dielectric constant of the dielectric layer 208 is less than or equal to 3.9. The dielectric layer 208 is located on the upper surfaces of the first conductive layer 204 and the second conductive layer 205 away from the substrate 102 and on the lower surfaces of the first conductive layer 204 and the second conductive layer 205 close to the substrate 102. At this time, in the longitudinal direction Y, on the side of the first insulating layer 201 away from the substrate 102, the dielectric layer 208, the first conductive layer 204, and the dielectric layer 208 are sequentially arranged. On the side of the second insulating layer 202 away from the substrate 102, the dielectric layer 208, the second conductive layer 205, and the dielectric layer 208 are sequentially arranged. Through the dielectric layer 208 on the upper and lower surfaces of the first conductive layer 204 and on the upper and lower surfaces of the second conductive layer 205, the parasitic capacitance between the source and drain of the vertical transistor can be reduced, thereby reducing the delay during data transmission.

[0139] As Figure 10 , Figure 11 shown, a hard mask layer 402 and a photoresist pattern layer 404 are formed on the stacked structure 104. An opening 406 penetrating through the photoresist pattern layer is formed in the photoresist pattern layer. The opening 406 defines the shape and position of the vertical hole 302. Using the photoresist pattern layer 404 as a mask, the stacked structure 104 is patterned, and the part of the hard mask layer 402 and at least the part of the dielectric layer 208 on the bottom in the stacked structure 104 exposed by the opening 406 are etched away to form a vertical hole 302 in the stacked structure 104. The vertical hole 302 extends at least to the lower surface of the first conductive layer 204 close to the substrate 102 at the bottom layer of the stacked structure 104. At this time, the vertical hole 302 at least penetrates the dielectric layer 208 on the surface of the first conductive layer 204 away from the substrate 102 at the bottom layer of the stacked structure 104. It can be understood that when the vertical hole 302 extends to the lower surface of the first conductive layer 204 at the bottom layer of the stacked structure 104, the bottom of the vertical hole 302 exposes the dielectric layer 208 on the bottom surface of the stacked structure 104. When the vertical hole 302 penetrates the first conductive layer 204 at the bottom layer of the stacked structure 104 and the dielectric layer 208 on the lower surface of the first conductive layer 204, the sidewall of the vertical hole 302 exposes the dielectric layer 208, and the bottom of the vertical hole 302 exposes the first insulating layer 201. At this time, the dielectric layer 208 extends to the vertical hole 302. As Figure 12 shown, based on the lateral etching (side etching) of the vertical hole 302, part of the first conductive layer 204 and part of the second conductive layer 205 are removed to form two lateral grooves 304 communicating with the vertical hole 302. At this time, the first sidewall and the second sidewall of the lateral groove 304 expose part of the surface of the adjacent insulating layer.

[0140] As Figures 13 - 16As shown, a contact layer 106 is formed on the inner wall of the horizontal groove 304. Specifically, first, a contact material layer 206 is formed on the inner wall of the horizontal groove 304. The contact material layer 206 extends along the inner wall of the horizontal groove 304 and covers the side wall of the vertical hole 302, the bottom of the vertical hole 302, and the upper surface of the stacked structure 104. Second, a sacrificial layer 306 is formed in the vertical hole 302 and the horizontal groove 304. Third, the sacrificial layer 306 located in the vertical hole 302 is removed to expose the contact material layer 206 located on the side wall and the bottom of the vertical hole 302. Then, the exposed contact material layer 206 is removed to obtain the contact layer 106 located in the horizontal groove 304. Then, the sacrificial layer 306 located in the horizontal groove 304 is removed, which is convenient for increasing the contact area between the channel layer and the contact layer 106 and reducing the contact resistance when forming the channel layer in contact with the contact layer 106 later. The contact layer 106 is in contact with a part of the surface of the dielectric layer 208 (the surface of the dielectric layer 208 exposed by the horizontal groove 304), and the shape of the dielectric layer 208 is the same as that of the adjacent conductive layers (the first conductive layer 204 and the second conductive layer 205).

[0141] The dielectric layer is a Low-K material, such as a dielectric material with a dielectric constant less than 3.9, which can reduce the parasitic capacitance between adjacent conductive layers.

[0142] Figure 17 For Figure 16 a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the filling trench in some corresponding embodiments, Figure 18 For Figure 17 a schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the gate in some corresponding embodiments, as Figure 17 、 Figure 18 shown. In one embodiment, after removing the sacrificial layer 306 located in the horizontal groove 304, it further includes: laterally etching the vertical hole 302 to remove at least a part of the dielectric layer 208 in contact with the contact layer 106 to form a filling trench 308 that exposes the contact layer 106 and the corresponding insulating layers (the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203) and is communicated with the vertical hole 302. At this time, the side wall of the filling trench 308 extending in the plane perpendicular to the substrate 102 (the second plane where the longitudinal direction Y and the column direction Z are located) is located between the third side wall and the vertical hole 302 or aligned with the third side wall.

[0143] Specifically, through a wet etching process, at least a part of the dielectric layer 208 exposed by the horizontal etching of the vertical holes 302 is etched. It can be understood that when the bottom of the vertical holes 302 exposes the dielectric layer 208 in contact with the lower surface of the first conductive layer 204 at the bottom layer of the stacked structure 104, the dielectric layer 208 exposed at the bottom of the vertical holes 302 is etched both vertically and horizontally. The subsequently formed channel layer 108 covers the inner walls of the filled trenches 308. By horizontally etching the dielectric layer 208, the contact area between the channel layer 108 and the source and drain of the vertical transistor is further increased, resulting in a lower contact resistance.

[0144] As Figure 18 shown, a channel layer 108 is formed on each exposed surface of the contact layer 106. The channel layer 108 extends along the first sidewall and the second sidewall of the horizontal groove 304 to cover the inner walls of the filled trenches 308 and the sidewalls of the vertical holes 302. Among them, the channel layer 108 serves as the channel of the vertical transistor; a gate 110 is formed at least in the vertical holes 302 and the horizontal groove 304. In some embodiments, in the longitudinal direction Y, the thickness of the dielectric layer 208 is less than or equal to twice the thickness of the channel layer 108. At this time, the channel layer 108 fills the filled trenches 308.

[0145] In some embodiments, in the longitudinal direction Y, the thickness of the dielectric layer 208 is greater than twice the thickness of the channel layer 108. At this time, the gate 110 is also filled in the filled trenches 308 (as Figure 18 shown).

[0146] In one of the embodiments, after removing the sacrificial layer 306 located in the horizontal groove 304, it further includes: removing the dielectric layer 208 located between the conductive layer 204 and the vertical holes 302 to form a filled trench 308 that exposes the insulating layers (the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203) and the contact layer 106 and is communicated with the vertical holes 302, that is, removing the dielectric layer 208 between the third sidewall of the horizontal groove 304 and the vertical holes 302; at this time, the area of the contact layer 106 exposed by the filled trench 308 is the largest, and the contact resistance is reduced the most by horizontally etching the dielectric layer 208. Figure 19 For Figure 2 the schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the second gate trench in some corresponding embodiments, Figure 20 For Figure 19 the schematic cross-sectional view of the semiconductor structure in the direction perpendicular to the substrate after forming the gate in some corresponding embodiments, as Figure 19 、 Figure 20 shown, in this embodiment, forming the channel layer 108 and the gate 110 includes steps S402 - step S408.

[0147] S402. Form a first gate trench 310 that at least penetrates the bottom of the stacked structure 104 and reaches the first conductive layer 204. The first gate trench 310 is perpendicular to the substrate 102.

[0148] Form a first gate trench 310 within the stacked structure 104. The first gate trench 310 is perpendicular to the substrate 102. The definition of the first trench 310 is similar to the definition of the vertical hole 302 in the above embodiments, and will not be elaborated here.

[0149] In some embodiments, the first gate trench 310 extends from the upper surface of the stacked structure 104 into the first insulating layer 201. The thickness of the first insulating layer 201 between the first gate trench 310 and the upper surface of the substrate 102 is such that after forming the second gate trench 312, there is a first insulating layer 201 between the first gate trench 310, the second gate trench 312, and the upper surface of the substrate 102. Through this setting, a second gate trench 312 can be formed later to expose a part of the lower surface of the first conductive layer 204 at the bottom layer of the stacked structure 104, achieving the purpose of further increasing the contact area between the channel layer 108 and the source and drain of the vertical transistor, and making the contact resistance lower.

[0150] S404. Transversely etch the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 based on the first gate trench 310 to form a second gate trench 312. The second gate trench 312 is located on the periphery of the first gate trench 310.

[0151] Adopt a wet etching process to transversely etch the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 exposed on the sidewalls of the first gate trench 310 based on the first gate trench 310 to form a second gate trench 312. The second gate trench 312 is located on the periphery of the first gate trench 310. The second gate trench 312 exposes a part of the lower surface of the first conductive layer 204 and the second conductive layer 205 close to the substrate 102, and a part of the upper surface of the first conductive layer 204 and the second conductive layer 205 far from the substrate 102. Among them, the second gate trench 312 is connected to the first gate trench 310, and the second gate trench 312 surrounds the sidewalls of the first gate trench 310. By forming the second gate trench 312, the exposed area of the first conductive layer 204 and the second conductive layer 205 can be increased, thereby increasing the contact area between the channel layer 108 and the first conductive layer 204, the second conductive layer 205 (the source and drain of the vertical transistor), and making the contact resistance lower.

[0152] In some embodiments, the sidewalls of the second gate trench 312 extending in a plane parallel to the substrate 102 (the first plane where the row direction X and the column direction Z are located) are less than or equal to the areas of the first conductive layer 204 and the second conductive layer 205 in a plane parallel to the substrate (the first plane where the row direction X and the column direction Z are located), while reducing the contact resistance, the production cost is reduced.

[0153] S406, form an integral channel layer 108 at least on the end faces of the first conductive layer 204 exposed by the first gate trench 310 and the end faces of the second conductive layer 205 exposed by the first gate trench 310 on the inner wall of the second gate trench 312.

[0154] Adopt an atomic layer deposition process to form an integral channel layer 108 on the surfaces of the first insulating layer 201, the second insulating layer 202, and the third insulating layer 203 exposed by the second gate trench 312, and on the surfaces of the first conductive layer 204 and the second conductive layer 205 exposed by the first gate trench 310 and the second gate trench 312. Further, the channel layer 108 extends along the sidewalls of the second gate trench 312 and covers the top surface of the stacked structure 104 away from the substrate 102 and / or the bottom of the first gate trench 310.

[0155] S408, form a gate insulating layer and a gate 110 in the first gate trench 310 and the second gate trench 312.

[0156] Form a gate insulating layer and a gate 110 on the surface of the channel layer 108. The gate insulating layer and the gate 110 are filled in the first gate trench 310 and the second gate trench 312, and the gate insulating layer is located between the channel layer 108 and the gate 110. In some embodiments, the gate 110 fills the first gate trench 310 and the second gate trench 312.

[0157] It should be understood that although Figure 1 the steps in the flowchart of Figure 1 are shown in sequence according to the indication of the arrows, these steps are not necessarily executed in the order indicated by the arrows. Unless there is a clear indication in this article, the execution of these steps has no strict order restriction, and these steps can be executed in other orders. Moreover,

[0158] The present disclosure provides a semiconductor structure. The same or corresponding parts as those in the embodiments of the preparation method of the above semiconductor structure will not be elaborated below. As Figure 9 , Figure 18 , Figure 20 shown, the semiconductor structure provided in the present disclosure includes a substrate 102, two conductive layers (a first conductive layer 204 and a second conductive layer 205), a channel layer 108, and a gate 110; the gate 110 extends in a direction Y perpendicular to the substrate 102, and the channel layer 108 at least partially surrounds the gate 110, and at least partially surrounding includes completely surrounding, partially surrounding, and being disposed on one side of the gate 110 parallel to the substrate 102; the channel layer 108 includes a vertical portion perpendicular to the substrate 102 and an extending portion extending from the vertical portion in a direction away from the gate 110. Exemplarily, the vertical portion and the extending portion are integrally connected; the two conductive layers are arranged at intervals in a direction away from the substrate 102, and the conductive layers (the first conductive layer 204 and the second conductive layer 205) are connected to the extending portion.

[0159] In the above semiconductor structure, the channel layer 108 includes an extending portion extending from the vertical portion in a direction away from the gate 110, and the conductive layer is connected to the extending portion, which increases the contact area between the channel layer 108 and the conductive layers (the first conductive layer 204 and the second conductive layer 205), and reduces the contact resistance between the channel layer 108 and the conductive layers (the first conductive layer 204 and the second conductive layer 205).

[0160] As Figure 9As shown, in some embodiments, the semiconductor structure further includes a contact layer 106. The contact layer is located in the lateral groove and has two horizontal planes and a vertical plane between the horizontal planes. The contact layer 106 is respectively connected to the conductive layers (the first conductive layer 204 and the second conductive layer 205) and the channel layer 108, which can increase the contact area between the conductive layer and the channel layer. At this time, the contact layer 106 and the first conductive layer 204 (which can be regarded as the first main part) together serve as the new first conductive layer, and the contact layer 106 and the second conductive layer 205 (which can be regarded as the second main part) together serve as the new second conductive layer. At this time, the first conductive layer includes the first main part and the contact layer, and the second conductive layer includes the second main part and the contact layer. In the longitudinal direction Y, the contact layer 106 corresponding to the first conductive layer 204 (the first main part) and the contact layer 106 corresponding to the second conductive layer 206 (the second main part) are isolated from each other. The contact layer 106 is a work function adjustment layer. The contact layer between the first main part and the channel layer connects the first main part and the channel layer while adjusting the work function between the first main part and the channel layer. The contact layer between the second main part and the channel layer connects the second main part and the channel layer while adjusting the work function between the second main part and the channel layer 108. The work function of the contact layer 106 is between the work function of the first conductive layer 204 and the work function of the channel layer 108, and between the conductive work function of the second conductive layer 205 and the channel work function of the channel layer 108. The contact layer 106 serves as part of the source and drain of the vertical transistor, reducing the difference in work function between the source and the channel layer 108 and between the drain and the channel layer 108, thereby reducing the contact resistance.

[0161] In some embodiments, the material of the contact layer 106 includes conductive materials such as titanium nitride, ITO, and IAZO (InAlZnO).

[0162] As Figure 4 、 Figure 7 As shown, in one of the embodiments, the semiconductor structure further includes: a gate trench 314, and the gate trench 314 includes a connected vertical hole 302 and two lateral grooves 304; the vertical hole 302 is perpendicular to the substrate 102, and the lateral grooves 304 are located between the conductive layers (the first conductive layer 204 and the second conductive layer 205) and the vertical hole 302, and expose at least the ends of the conductive layers (the first conductive layer 204 and the second conductive layer 205); wherein, the contact layer 106 covers the inner wall of the lateral groove 304. Without changing the thickness of the first conductive layer 204 and the second conductive layer 205, the contact layer 106 located on the inner wall of the lateral groove 304 increases the contact area between the source and the channel layer 108 and between the drain and the channel layer 108, further reducing the contact resistance.

[0163] In one embodiment, the contact layer 106 is located on the inner wall of the lateral groove 304, the vertical portion 210 is located on the side wall of the vertical hole 302, and the protruding portion 212 is located in the lateral groove 304. The protruding portion includes a bottom surface close to the substrate 102, a top surface away from the substrate 102, and a side surface connecting the bottom surface and the top surface. The bottom surface, the top surface, and the side surface of the protruding portion are all in contact with the contact layer 106. The gate 110 is at least located in the vertical hole 302 and the lateral groove 304, and an isolation channel layer and a gate insulating layer of the gate are further provided in the lateral groove 304.

[0164] As Figures 10 - 18 shown, in one embodiment, the stacked structure 104 further includes a dielectric layer 208. The dielectric layer 208 is located on the upper surfaces of the respective conductive layers (the first conductive layer 204 and the second conductive layer 205) away from the substrate 102 and on the lower surfaces of the conductive layers (the first conductive layer 204 and the second conductive layer 205) close to the substrate 102. The channel layer 108 is in contact with the dielectric layer 208. By means of the dielectric layer 208, the parasitic capacitance between the source and drain (the first conductive layer 204 and the second conductive layer 205) of the vertical transistor can be reduced, thereby reducing the delay in the data transmission process.

[0165] As Figure 16 shown, in some embodiments, the dielectric layer 208 extends along the upper and lower surfaces of the conductive layers (the first conductive layer 204 and the second conductive layer 205) to at least a partial surface of the contact layer 106.

[0166] As Figure 17 shown, in some embodiments, the dielectric layer 208 only covers the upper surface of the first conductive layer 204, the upper surface of the second conductive layer 205, the lower surface of the first conductive layer 204, and the lower surface of the second conductive layer 205.

[0167] As Figure 19 、 Figure 20As shown, in some embodiments, the semiconductor structure further includes: a gate trench 314, which includes a first gate trench 310 and a second gate trench 312 communicating with the first gate trench 310; the first gate trench 310 is perpendicular to the substrate 102; the second gate trench 312 is located on the periphery of the first gate trench 310; the vertical portion 210 is located on the sidewall of the first gate trench 310, and the protruding portion is located on the inner wall of the second gate trench 312, and is in contact with the lower surface of the conductive layer (the first conductive layer 204 and the second conductive layer 205) close to the substrate 102 and the upper surface of the conductive layer (the first conductive layer 204 and the second conductive layer 205) away from the substrate 102. The gate 110 is at least located in the first gate trench 310 and the second gate trench 312. An isolation channel layer 108 and a gate insulating layer of the gate 110 are further provided in the second gate trench 312. In this setting, the second gate trench 312 exposes a partial surface of the conductive layer (the first conductive layer 204 and the second conductive layer 205), so as to further increase the contact area between the channel layer 108 and the source and drain of the vertical transistor, and achieve the purpose of lower contact resistance.

[0168] As Figures 19 - 20 shown, the two-layer conductive layer includes a first conductive layer 204 close to the substrate 102 and a second conductive layer 205 away from the substrate 102. The semiconductor structure further includes:

[0169] a first insulating layer 201, located between the first conductive layer 204 and the substrate 102. In the direction perpendicular to the substrate 102, the first gate trench 310 extends into the first insulating layer 201;

[0170] a second insulating layer 202, located between the first conductive layer 204 and the second conductive layer 205;

[0171] a third insulating layer 203, located on the surface of the second conductive layer 205 away from the substrate 102;

[0172] Among them, the second gate trench 312 includes a first gate sub-trench, a second gate sub-trench, and a third gate sub-trench. The first gate sub-trench extends from the first gate trench 310 into the first insulating layer 201 and exposes a part of the lower surface of the first conductive layer 204 close to the substrate 102. The second gate sub-trench extends from the first gate trench 310 into the second insulating layer 202 and exposes a part of the upper surface of the first conductive layer 204 far from the substrate 102 and a part of the lower surface of the second conductive layer 205 close to the substrate 102. The third gate sub-trench extends from the first gate trench 310 into the third insulating layer 203 and exposes a part of the upper surface of the second conductive layer 205 far from the substrate 102. The channel layer 108 covers the exposed first conductive layer 204, the exposed second conductive layer 205, the exposed first insulating layer 201, the exposed second insulating layer 202, and the exposed third insulating layer 203.

[0173] The present disclosure also provides an electronic device, including the semiconductor structure described in any one of the above. The electronic device may include a smart phone, a computer, a tablet computer, an artificial intelligence device, a wearable device, or a smart mobile terminal. The embodiments of the present application do not impose special restrictions on the specific form of the above electronic device.

[0174] The technical features of the above embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope recorded in this specification.

[0175] The above embodiments only represent several implementation manners of the embodiments of the present disclosure. The description is relatively specific and detailed, but it should not be construed as a limitation on the scope of the invention patent. It should be noted that for those of ordinary skill in the art, without departing from the concept of the embodiments of the present disclosure, several deformations and improvements can still be made, and these all belong to the protection scope of the embodiments of the present disclosure.

Claims

1. A semiconductor structure, characterized in that, Comprising: A substrate; A gate electrode extending in a direction perpendicular to the substrate; A channel layer at least partially surrounding the gate electrode, including a vertical portion perpendicular to the substrate and an extending portion extending away from the gate electrode from the vertical portion; Two conductive layers arranged at intervals in a direction away from the substrate, and the conductive layers are connected to the extending portion.

2. The semiconductor structure according to claim 1, wherein Further comprising: A contact layer connected to the conductive layer and the channel layer respectively.

3. The semiconductor structure according to claim 2, wherein The material of the contact layer includes titanium nitride, ITO, and IAZO.

4. The semiconductor structure according to claim 2, wherein Further comprising: A gate trench, the gate trench including a vertically connected hole and two lateral grooves; the vertically connected hole is perpendicular to the substrate, and the two lateral grooves are located between the two conductive layers and the vertically connected hole, and at least the ends of the conductive layers are exposed; Wherein, the contact layer covers the inner wall of the lateral groove.

5. The semiconductor structure according to claim 4, characterized in that, The contact layer is located on the inner wall of the lateral groove, the vertical portion is located on the side wall of the vertically connected hole, the extending portion is located in the lateral groove, the extending portion includes a bottom surface close to the substrate, a top surface away from the substrate, and a side surface connecting the bottom surface and the top surface, and the bottom surface, top surface and side surface of the extending portion are all in contact with the contact layer; the gate electrode is at least located in the vertically connected hole and the lateral groove, and a gate insulating layer for isolating the channel layer and the gate electrode is further provided in the lateral groove.

6. The semiconductor structure according to claim 1, characterized in that Further comprising: A dielectric layer, the dielectric layer is located on the upper surface and the lower surface of each conductive layer, and the dielectric layer is a Low-K dielectric layer.

7. The semiconductor structure according to claim 1, wherein Further comprising: A gate trench, the gate trench including a first gate trench and a second gate trench communicating with the first gate trench; The first gate trench is perpendicular to the substrate; The second gate trench is located on the upper surface and the lower surface of a part of the conductive layer exposed on the periphery of the first gate trench; The vertical portion is located on the side wall of the first gate trench, the extending portion is located on the inner wall of the second gate trench, the gate electrode is at least located in the first gate trench and the second gate trench, and a gate insulating layer for isolating the channel layer and the gate electrode is further provided in the second gate trench.

8. The semiconductor structure according to claim 7, wherein, The two conductive layers include a first conductive layer close to the substrate and a second conductive layer away from the substrate, and the semiconductor structure further comprises: A first insulating layer located between the first conductive layer and the substrate, and in a direction perpendicular to the substrate, the first gate trench extends into the first insulating layer; A second insulating layer located between the first conductive layer and the second conductive layer; A third insulating layer located on the surface of the second conductive layer away from the substrate; Among them, the second gate trench includes a first gate sub-trench, a second gate sub-trench, and a third gate sub-trench. The first gate sub-trench extends from the first gate trench into the first insulating layer and exposes a part of the lower surface of the first conductive layer close to the substrate. The second gate sub-trench extends from the first gate trench into the second insulating layer and exposes a part of the upper surface of the first conductive layer far from the substrate and a part of the lower surface of the second conductive layer close to the substrate. The third gate sub-trench extends from the first gate trench into the third insulating layer and exposes a part of the upper surface of the second conductive layer far from the substrate. The channel layer covers the exposed first conductive layer, the exposed second conductive layer, the exposed first insulating layer, the exposed second insulating layer, and the exposed third insulating layer.

9. A method for preparing a semiconductor structure, characterized in that, Comprising: Providing a substrate; Forming a stacked structure on the upper surface of the substrate, the stacked structure including a first insulating layer, a first conductive layer, a second insulating layer, a second conductive layer, and a third insulating layer arranged in sequence in a direction away from the substrate; Forming a channel layer and a gate, the gate at least penetrating the first conductive layer and being perpendicular to the substrate; the channel layer at least partially surrounds the gate, the channel layer including a vertical portion perpendicular to the substrate and an extending portion extending from the vertical portion in a direction away from the gate, and the extending portion is connected to the first conductive layer and the second conductive layer.

10. The method for manufacturing a semiconductor structure according to claim 9, wherein Before forming the channel layer and the gate, it further includes the step of forming a contact layer; forming the contact layer, the channel layer, and the gate includes: Forming a vertical hole in the stacked structure that at least penetrates the first conductive layer at the bottom of the stacked structure, the vertical hole being perpendicular to the substrate; Transversely etching away a part of the first conductive layer and a part of the second conductive layer from the vertical hole to form a transverse groove communicating with the vertical hole; Forming the contact layer on the inner wall of the transverse groove; Forming the channel layer at least on the side wall of the vertical hole and the surface of the contact layer; Forming a gate insulating layer and the gate at least in the vertical hole and the transverse groove.

11. The method for preparing a semiconductor structure according to claim 10, wherein The forming the contact layer on the inner wall of the transverse groove includes: Forming a contact material layer on the upper surface of the stacked structure, the side wall of the vertical hole, the bottom of the vertical hole, and the inner wall of the transverse groove; Forming a sacrificial layer in the vertical hole and the transverse groove; Removing the sacrificial layer in the vertical hole to expose the contact material layer on the side wall and the bottom of the vertical hole; Removing the exposed contact material layer to obtain the contact layer only located in the transverse groove; Removing the sacrificial layer in the transverse groove.

12. The method for manufacturing a semiconductor structure according to claim 11, wherein The stacked structure further includes a dielectric layer, the dielectric layer is located on the upper surface of the first conductive layer and the second conductive layer far from the substrate and the lower surface of the first conductive layer and the second conductive layer close to the substrate, and extends to the vertical hole; After removing the sacrificial layer in the transverse groove, it further includes: Remove the dielectric layer between the first conductive layer and the vertical hole, and between the second conductive layer and the vertical hole.

13. The method for manufacturing a semiconductor structure according to claim 9, wherein Form a channel layer and a gate, including: Form a first gate trench that at least penetrates the first conductive layer at the bottom of the stacked structure, and the first gate trench is perpendicular to the substrate; Transversely etch the first insulating layer, the second insulating layer, and the third insulating layer based on the first gate trench to form a second gate trench, and the second gate trench exposes the lower surfaces of the portions of the first conductive layer and the second conductive layer close to the substrate, and the upper surfaces of the portions of the first conductive layer and the second conductive layer far from the substrate; Form the integral channel layer at least on the inner walls of the second gate trench, the end faces of the first conductive layer exposed by the first gate trench, and the end faces of the second conductive layer exposed by the first gate trench; Successively form a gate insulating layer and the gate in the first gate trench and the second gate trench.

14. An electronic device, characterized in that, Comprise the semiconductor structure according to any one of claims 1-8.

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