Semiconductor structure, manufacturing method thereof and memory system

Abstract

The invention provides a semiconductor structure, a manufacturing method thereof and a memory system, and the manufacturing method of the semiconductor structure comprises the steps: providing a substrate structure; wherein the substrate structure comprises a plurality of active columns which are arranged in an array; each active column comprises a first end and a second end which are arranged along a third direction; forming a storage structure on the first side of the active column; the storage structure is connected with the first end; forming a plurality of first conductive structures arranged along the first direction on the second side of the active column; the first conductive structure extends along the second direction and is connected with the second end; the first side and the second side are two opposite sides of the active column along the third direction; forming a first conductive shielding structure between adjacent first conductive structures from the second side; the first conductive shielding structure extends along a second direction; and etching the first conductive structure from the second side of the active column to form a plurality of first conductive wires arranged along the second direction, and etching the first conductive shielding structure to form a plurality of first conductive shielding wires arranged along the second direction.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technology, for example, to a semiconductor structure, a manufacturing method thereof, and a memory system. Background Art

[0002] A semiconductor device is an electronic device with conductivity between that of a good conductor and an insulator, which utilizes the special electrical properties of semiconductor materials to perform specific functions. Semiconductor devices can be used to manufacture storage devices, which have the characteristics of high integration, fast read / write speed, and low cost, and are widely used in various consumer electronic products, such as computers, mobile phones, and set-top boxes.

[0003] However, there are still many problems to be solved in semiconductor devices. Summary of the Invention

[0004] In view of this, embodiments of the present disclosure provide a semiconductor structure, a manufacturing method thereof, and a memory system to solve at least one problem existing in the prior art.

[0005] In a first aspect, an embodiment of the present disclosure provides a manufacturing method of a semiconductor structure, including:

[0006] Providing a substrate structure; wherein the substrate structure includes a plurality of active pillars arranged in an array along a first direction and a second direction; the active pillars include a first end and a second end arranged along a third direction; the first direction and the second direction intersect and are both perpendicular to the third direction;

[0007] Forming a storage structure on a first side of the active pillar; the storage structure is connected to the first end;

[0008] Forming a plurality of first conductive structures arranged along the first direction on a second side of the active pillar; the first conductive structures extend along the second direction and are connected to the second end; the first side and the second side are two opposite sides of the active pillar along the third direction;

[0009] Forming a first conductive shielding structure between adjacent first conductive structures from the second side; the first conductive shielding structure extends along the second direction;

[0010] Etching the first conductive structures from the second side of the active pillar to form a plurality of first conductive wires arranged along the second direction;

[0011] Etching the first conductive shielding structure from the second side of the active pillar to form a plurality of first conductive shielding wires arranged along the second direction.

[0012] In a second aspect, an embodiment of the present disclosure further provides a semiconductor structure, the semiconductor structure includes a plurality of memory array sheets; the memory array sheets include:

[0013] Base structure; the base structure includes a plurality of active columns arranged in an array along a first direction and a second direction; the active columns include a first end and a second end arranged along a third direction; the first direction and the second direction intersect and are both perpendicular to the third direction;

[0014] A storage structure located on a first side of the active column; the storage structure is connected to the first end of the active column;

[0015] A plurality of first conductive wires arranged along the first direction on a second side of the active column; the first conductive wires extend along the second direction and are connected to the second end of the active column; the first side and the second side are two opposite sides of the active column along the third direction;

[0016] A plurality of first conductive shielding wires arranged along the first direction on a second side of the active column; the first conductive shielding wires are located between adjacent first conductive wires and extend along the second direction.

[0017] In a third aspect, an embodiment of the present disclosure provides a memory system, including:

[0018] The semiconductor structure and the memory controller as described in any one of the above embodiments.

[0019] In the embodiments of the present disclosure, by arranging a plurality of first conductive shielding wires along the first direction on the second side of the active column, during the read and write operations of the memory, by applying a first voltage to the first conductive shielding wires, the coupling effect between adjacent first conductive wires can be reduced. Description of the Drawings

[0020] Figure 1 A circuit connection schematic diagram of an architecture adopting 1T1C provided by an embodiment of the present disclosure;

[0021] Figure 2 A flowchart of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure;

[0022] Figures 3 to 28 A process schematic diagram of a manufacturing method of a semiconductor structure provided by an embodiment of the present disclosure;

[0023] Figures 29 to 30 A structure schematic diagram of a semiconductor structure provided by an embodiment of the present disclosure;

[0024] Figure 31 A schematic diagram of an exemplary electronic device including a memory system provided by an embodiment of the present disclosure;

[0025] Figure 32Schematic block diagram of the SSD provided by the embodiments of the present disclosure;

[0026] Figure 33 Schematic block diagram of the memory provided by the embodiments of the present disclosure. Detailed implementation manners

[0027] To make the technical solutions and advantages of the embodiments of the present disclosure clearer, the technical solutions of the present disclosure will be further elaborated in detail below in combination with the accompanying drawings and embodiments. Although the exemplary implementation methods of the present disclosure are shown in the drawings, it should be understood that the present disclosure can be implemented in various forms and should not be limited by the implementation manners described herein. On the contrary, these implementation manners are provided to enable a more thorough understanding of the present disclosure and to be able to fully convey the scope of the present disclosure to those skilled in the art.

[0028] In the following paragraphs, the present disclosure will be described more specifically by way of example with reference to the accompanying drawings. The advantages and features of the present disclosure will be clearer according to the following description and the claims. It should be noted that the accompanying drawings are all in very simplified forms and use non-precise scales, only for the purpose of facilitating and clearly assisting in explaining the purpose of the embodiments of the present disclosure.

[0029] It can be understood that the meanings of "on...", "above...", and "over..." in the present disclosure should be interpreted in the broadest manner, so that "on..." not only means "on" something "without any intervening features or layers (i.e., directly on something)", but also includes the meaning of "on" something "with intervening features or layers".

[0030] In addition, for the convenience of description, spatial relative terms such as "on...", "above...", "over...", "upper", "upper part", etc. may be used herein to describe the relationship between one element or feature and another element or feature as shown in the figures. Except for the orientation depicted in the drawings, the spatial relative terms are intended to cover different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations) and the spatial relative descriptive words used herein can be interpreted accordingly.

[0031] In the embodiments of the present disclosure, the term "substrate" refers to the material on which subsequent material layers are added. The substrate itself can be patterned. The material added on top of the substrate can be patterned or can remain unpatterned. In addition, the substrate can include various semiconductor materials, such as silicon, silicon germanium, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of non-conductive materials, such as glass, plastic, or sapphire wafers.

[0032] In the embodiments of the present disclosure, the term "layer" refers to a portion of material including a region having a thickness. The layer may extend over the entirety of a structure below or above, or may have a scope smaller than the scope of the structure below or above. Additionally, the layer may be a region of a homogeneous or heterogeneous continuous structure with a thickness less than the thickness of the continuous structure. For example, the layer may be located between the top and bottom surfaces of the continuous structure, or the layer may be between any horizontal planes at the top and bottom surfaces of the continuous structure. The layer may extend horizontally, vertically, and / or along an inclined surface. The layer may include a plurality of sub-layers. For example, an interconnect layer may include one or more conductor and contact sub-layers (wherein interconnect lines and / or via contacts are formed), and one or more dielectric sub-layers.

[0033] In the embodiments of the present disclosure, the terms "first", "second", etc. are used to distinguish similar objects and are not necessarily used to describe a specific order or sequence.

[0034] The semiconductor structures in the embodiments of the present disclosure include, but are not limited to, memories, and the types of memories include, but are not limited to, dynamic random access memories. Hereinafter, taking the semiconductor structure as a dynamic random access memory as an example for exemplary illustration.

[0035] With the development of dynamic random access memory technology, the size of the memory cells is getting smaller and smaller, and its array architecture changes from 8F 2 to 6F 2 and then to 4F 2 ; in addition, based on the requirements for ions and leakage current in dynamic random access memories, the architecture of the memories changes from planar array transistors to recess gate array transistors, then from recess gate array transistors to buried saddle fin array transistors, and then from buried saddle fin array transistors to vertical gate transistors.

[0036] In some embodiments, whether it is a planar transistor, a recess gate array transistor, a buried transistor, or a vertical gate transistor, the dynamic random access memory is composed of a plurality of memory cell structures. Each memory cell structure is mainly composed of a transistor and a memory structure (memory capacitor) controlled by the transistor, that is, the dynamic random access memory includes an architecture of 1 transistor (T, Transistor) and 1 capacitor (C, Capacitance) (1T1C); its main principle of operation is to use the amount of charge stored in the capacitor to represent whether a binary bit (bit) is 1 or 0.

[0037] Figure 1A schematic circuit connection diagram of an architecture using 1T1C provided in an embodiment of the present disclosure is as follows Figure 1 As shown, the drain of the transistor T is connected to the bit line (BL, Bite Line), the source of the transistor T is connected to one electrode plate of the capacitor C, the other electrode plate of the capacitor C is grounded through the ground terminal (GND, Ground), and the gate of the transistor T is connected to the word line (WL, Word Line); a voltage is applied through the word line WL to control the conduction or cutoff of the transistor T, and the bit line BL is used to perform a read or write operation on the transistor T when the transistor T is conducting.

[0038] With the continuous increase in the storage density requirements for dynamic random access memories, the process difficulty in the manufacturing process of memories is becoming increasingly large. How to reduce the process difficulty, reduce the process cost, and improve the performance of memories has become an urgent problem to be solved.

[0039] Based on one or more of the above problems, an embodiment of the present disclosure provides a method for manufacturing a semiconductor structure. Figure 2 A flowchart of a method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure is as follows. As Figure 2 shown, the method for manufacturing a semiconductor structure provided in an embodiment of the present disclosure includes the following steps:

[0040] Step 1001: Provide a substrate structure; wherein, the substrate structure includes a plurality of active pillars arranged in an array along a first direction and a second direction; the active pillars include a first end and a second end arranged along a third direction; the first direction and the second direction intersect and are both perpendicular to the third direction;

[0041] Step 1002: Form a storage structure on a first side of the active pillar; the storage structure is connected to the first end;

[0042] Step 1003: Form a plurality of first conductive structures arranged along the first direction on a second side of the active pillar; the first conductive structures extend along the second direction and are connected to the second end; the first side and the second side are two opposite sides of the active pillar along the third direction;

[0043] Step 1004: Form a first conductive shielding structure between adjacent first conductive structures from the second side; the first conductive shielding structure extends along the second direction;

[0044] Step 1005: Etch the first conductive structure from the second side of the active pillar to form a plurality of first conductive wires arranged along the second direction;

[0045] Step 1006: Etch the first conductive shielding structure from the second side of the active pillar to form a plurality of first conductive shielding lines arranged along the second direction.

[0046] In the embodiments of the present disclosure, by providing a plurality of first conductive shielding lines arranged along the first direction on the second side of the active pillar, during the read and write operations of the memory, by applying a first voltage to the first conductive shielding lines, the coupling effect between adjacent first conductive lines can be reduced.

[0047] Figures 3 to 28 It is a schematic process diagram of a manufacturing method of a semiconductor structure provided in the embodiments of the present disclosure. It should be understood that Figure 2 the steps shown are not exclusive, and other steps may be performed before, after, or between any of the shown operations; Figure 2 the steps shown can be adjusted in sequence according to actual needs. The following combines Figure 2 、 Figures 3 to 28 to detail the manufacturing method of the semiconductor structure provided in the embodiments of the present disclosure.

[0048] The first direction and the second direction in the embodiments of the present disclosure intersect. In some embodiments, the first direction and the second direction are perpendicular. The embodiments of the present disclosure are described by taking the first direction and the second direction being perpendicular as an example.

[0049] Here, the first direction can be the X-axis direction in the drawings of the present disclosure, the second direction can be the Y-axis direction in the drawings of the present disclosure, and the third direction can be the Z-axis direction in the drawings of the present disclosure.

[0050] Figure 3 shows a top view of an intermediate structure for forming a base structure, Figure 4 shows along Figure 3 the cross-sectional views in the aa' and bb' directions in Figure 5 shows a top view of an intermediate structure for forming a base structure, Figure 6 shows along Figure 5 the cross-sectional views in the aa' and bb' directions in Figure 7 shows a top view of the base structure, Figure 8 shows along Figure 7 the cross-sectional views in the aa' and bb' directions in

[0051] In some embodiments, such as Figures 3 to 8As shown, forming the substrate structure 300 includes: providing a substrate 100; etching the substrate 100 to form a plurality of first trenches 101 arranged along the first direction (X direction); the first trenches 101 extend along the second direction (Y direction) and the bottoms are located in the substrate; forming a first dielectric layer 106 in the first trenches 101; etching the substrate 100 and the first dielectric layer 106 to form second trenches 120 arranged along the second direction (Y direction); wherein, the second trenches 120 extend along the first direction (X direction) and the bottoms are located in the substrate 100, and the depth of the second trenches 120 is less than the depth of the first trenches 101; the first trenches 101 and the second trenches 120 divide the substrate 100 into a plurality of active columns and a plurality of first semiconductor structures 110. In some embodiments, the depth of the first trenches 101 is h1 as shown in Figure 4 as shown, and the depth of the second trenches 120 is h2 as shown in Figure 8 as shown, and h2 is less than h1.

[0052] In some embodiments, the substrate 100 may include a single-element semiconductor material substrate (such as a silicon (Si) substrate, a germanium (Ge) substrate, etc.), a compound semiconductor material substrate (such as a silicon germanium (SiGe) substrate, etc.), a silicon-on-insulator (SOI) substrate, a germanium-on-insulator (GeOI) substrate, etc. Exemplarily, the substrate 100 is a silicon substrate.

[0053] In some embodiments, the material of the first dielectric layer 106 includes but is not limited to silicon oxide and silicon nitride.

[0054] Figure 9 is a top view, Figures 10 to 13 is a cross-sectional view along Figure 9 the aa', bb' and cc' directions in

[0055] In some embodiments, as shown in Figures 9 to 11 as shown, a second conductive structure 103 may be formed on the bottom wall and part of the side walls of the second trenches 120. The material of the second conductive structure 103 includes a conductive material.

[0056] In other embodiments, as shown in Figures 7 to 11 as shown, third trenches 130 may also be formed to be alternately arranged with the second trenches 120 along the second direction (Y direction). The depth of the third trenches 130 is also less than the depth of the first trenches 101. A second conductive shielding structure 107 may be formed in the third trenches 130 from the first side 102a of the active column 102; the second conductive shielding structure 107 covers part of the side walls of the adjacent active columns 102 along the second direction; the material of the second conductive shielding structure 107 includes a conductive material.

[0057] The first side 102 a here and the second side 102 b hereinafter are two opposite sides of the active pillar along the third direction.

[0058] In some embodiments, the depth of the third trench 130 is as follows: Figure 8 As shown, h3 is smaller than h1. In some embodiments, the depths of the second trench and the third trench in the substrate may be equal or unequal.

[0059] In some embodiments, the cross-sectional shape of the first groove 101, the second groove 120, and the third groove 130 may be U-shaped. In other embodiments, the cross-sectional shape of the first groove 101, the second groove 120, and the third groove 130 may also be rectangular. The present disclosure does not limit the shapes of the first groove 101, the second groove 120, and the third groove 130.

[0060] In some embodiments, the method of forming the first trench 101 , the second trench 120 , and the third trench 130 includes but is not limited to dry etching, for example, a plasma etching process or a reactive ion etching process.

[0061] In the disclosed embodiment, the second groove 120 and the third groove 130 can be formed simultaneously, that is, the substrate and the first dielectric layer are etched using the same mask, which is conducive to simplifying the process, saving the number of masks, and thus saving process costs.

[0062] In the embodiment of the present disclosure, the second trench 120 and the third trench 130 may be filled respectively to form a second conductive structure 103 and a second conductive shielding structure 107. The second conductive structure 103 extends along the first direction (X direction) and is located between the active pillars 102 adjacent to each other along the second direction (Y direction); the second conductive shielding structure 107 extends along the first direction (X direction) and is located between the active pillars 102 adjacent to each other along the second direction (Y direction). The second conductive shielding structure 107 and the second conductive structure 103 are alternately arranged along the second direction.

[0063] In some embodiments, Figure 10 as well as Figure 11As shown, the method further includes: before forming the second conductive structure 103, forming a gate oxide layer 149 on the sidewalls and bottom wall of the second trench 120 from the first side 102a of the active pillar 102; forming a third conductive material layer 111 covering the sidewalls and bottom wall of the second trench 120 in the second trench 120 formed with the gate oxide layer 149, and then filling the second trench 120 covered with the third conductive material layer 111 to form a fourth dielectric layer 136 to fill the second trench 120 (i.e., the third conductive material layer 111 wraps the fourth dielectric layer 136). Then, the third conductive material layer 111, the first dielectric layer 136 and the fourth dielectric layer 136 are etched back from the first side 102a of the active pillar 102 to form the second conductive structure 103 covering the bottom wall and part of the sidewall of the second trench 120.

[0064] Here, the material of the fourth dielectric layer 136 includes but is not limited to silicon nitride and silicon oxide; the material of the third conductive material layer 111 includes but is not limited to conductive metal or conductive alloy, and the conductive metal may include tungsten or copper, etc.; the material of the gate oxide layer 149 includes but is not limited to silicon oxide.

[0065] In some embodiments, Figures 9 to 11 As shown, a third dielectric layer 135 covering the bottom wall and side walls of the third trench can be filled in the third trench 130 from the first side 102a of the active pillar 102, and then a second conductive material layer 144 can be filled in the third trench covered with the third dielectric layer 135 to fill the third trench (i.e., the third dielectric layer 135 wraps the second conductive material layer 144), and then the second conductive material layer 144 and the third dielectric layer 135 are etched back from the first side 102a of the active pillar 102 to form a second conductive shielding structure 107 covering the bottom wall and part of the side walls of the third trench 130.

[0066] Here, the material of the second conductive material layer 144 includes a conductive material, and exemplarily includes metal tungsten. The material of the third dielectric layer 135 includes, but is not limited to, silicon nitride and silicon oxide.

[0067] In some embodiments, the active pillar 102 includes a first doped region, a channel region, and a second doped region arranged along a third direction. That is, the first end of the active pillar 102 may be the first doped region, and the second end of the active pillar 102 may be the second doped region. The first doped region here may be one of the source and the drain of the transistor, and the second doped region may be the other of the source and the drain of the transistor.

[0068] In some embodiments, Figure 12As shown, in step 1002, a storage structure 160 is formed on the first side 102a of the active column 102, including: forming a stacked structure 200 covering the active column 102 on the first side 102a of the active column 102, and forming a storage structure 160 in the stacked structure 200, and the storage structure 160 is connected to the first doped region of the active column 102.

[0069] In some other embodiments, in step 1002, forming a storage structure 160 on the first side 102a of the active column 102 includes: forming a stacked structure on another substrate, forming a storage structure 160 in the stacked structure, bonding the stacked structure 200 having a plurality of storage structures 160 to the base structure 300, and each storage structure 160 is connected to the first end of an active column 102. The stacked structure 200 and the base structure 300 can be separately formed, so that the process time can be saved and the production efficiency can be improved.

[0070] In some embodiments, the semiconductor structure includes a memory, the memory includes a dynamic random access memory, and the storage structure includes a storage capacitor. The storage capacitor can present various structures. Exemplarily, the storage capacitor includes a cup-shaped, cylindrical or pillar-shaped capacitor.

[0071] In some embodiments, the methods for forming the above gate oxide layer 149, each conductive material layer, each dielectric layer, and the stacked structure 200 include but are not limited to physical vapor deposition (PVD, Physical Vapor Deposition) process, chemical vapor deposition (CVD, Chemical Vapor Deposition) process, atomic layer deposition (ALD, Atomic Layer Deposition) and other processes.

[0072] After performing step 1002, as Figure 13 shown, a carrier wafer 210 is formed on the stacked structure 200 from the first side 102a of the active column 102, and the above substrate 100 is flipped, so that the second side 102b of the active column 102 faces upward. Here, the carrier wafer 210 can be used to carry the substrate 100 during subsequent processing from the second side 102b of the active column 102 and protect the related structures formed on the first side 102a of the active column 102.

[0073] The above embodiments are all processings performed from the first side 102a of the active column 102. The processings performed from the second side 102b of the active column 102 will be specifically introduced below. Here, the first side 102a and the second side 102b are two opposite sides of the active column 102 along the third direction.

[0074] In some embodiments, the base structure further includes a plurality of first semiconductor structures and a first dielectric layer; wherein, the plurality of first semiconductor structures are arranged along the first direction, the first semiconductor structures extend along the second direction and are connected to the second ends of the plurality of active pillars arranged along the second direction, and the first dielectric layer is at least located between the first semiconductor structures adjacent to each other along the first direction.

[0075] In some embodiments, in step S1004, forming the first conductive shielding structure between the adjacent first conductive structures includes:

[0076] Removing the first dielectric layer located between the first semiconductor structures adjacent to each other along the first direction from the second side to form a first filling region;

[0077] Forming the first conductive shielding structure in the first filling region.

[0078] In some embodiments, the first conductive structure covers the sidewalls of the second ends of the active pillars and the sidewalls of the channel regions of the active pillars; the method further includes:

[0079] After removing the first dielectric layer located between the first semiconductor structures adjacent to each other along the first direction from the second side of the active pillar, removing a part of the sidewall of the second end of the active pillar covered by the second conductive structure from the second side of the active pillar to form a second conductive portion and a second filling region; a part of the second conductive portion constitutes a first sub-conductive structure and a second sub-conductive structure that extend along the first direction and are arranged at intervals along the second direction.

[0080] In some embodiments, before forming the first conductive shielding structure in the first filling region, a second dielectric layer is formed in a partial region of the first filling region and the second filling region; the second dielectric layer in the first filling region is located between the first semiconductor structure and the first conductive shielding structure.

[0081] In some embodiments, the base structure further includes a gate oxide layer; the gate oxide layer is at least located between the second conductive structure and the active pillar and between the first semiconductor structure and the second conductive structure; the method further includes:

[0082] Before removing a part of the sidewall of the second end of the active pillar covered by the second conductive structure from the second side of the active pillar, removing the gate oxide layer between the second conductive structure and the sidewall of the second end of the active pillar and the gate oxide layer between the first semiconductor structure and the second conductive structure from the second side of the active pillar to form a third filling region;

[0083] When forming the second dielectric layer in a partial area of the first filling area and the second filling area, the second dielectric layer is also formed in the third filling area.

[0084] In some embodiments, before forming the first conductive shielding structure in the first filling area, a second dielectric layer is formed in a partial area of the first filling area; the second dielectric layer in the first filling area is located between the first semiconductor structure and the first conductive shielding structure.

[0085] In some embodiments, forming a plurality of first conductive structures arranged along the first direction on the second side of the active column includes:

[0086] Forming a first conductive material layer covering the first semiconductor structure from the second side of the active column;

[0087] Performing a heat treatment on the first semiconductor structure and the first conductive material layer to form the first conductive structure.

[0088] In some embodiments, the method includes: etching the first conductive structure from the second side of the active column to form a plurality of first conductive wires arranged along the second direction;

[0089] In some embodiments, the method further includes:

[0090] Etching the second conductive structure from the second side of the active column to form a plurality of second conductive wires arranged along the first direction.

[0091] Etching the first sub-conductive structure and the second sub-conductive structure from the second side to form a plurality of first sub-conductive wires and a plurality of second sub-conductive wires; the plurality of first sub-conductive wires and the plurality of second sub-conductive wires are both arranged along the first direction.

[0092] In some embodiments, the method includes: etching the first conductive shielding structure from the second side of the active column to form a plurality of first conductive shielding wires arranged along the second direction.

[0093] In some embodiments, etching the first conductive structure from the second side of the active column to form a plurality of first conductive wires arranged along the second direction and etching the first conductive shielding structure from the second side of the active column to form a plurality of first conductive shielding wires arranged along the second direction are performed simultaneously.

[0094] In some embodiments, when etching the first conductive structure, the second conductive structure, and the first conductive shielding structure from the second side of the active column, the second conductive shielding structure can also be etched simultaneously to form a plurality of second conductive shielding wires arranged along the first direction.

[0095] In some embodiments, etching the first conductive structure from the second side of the active pillar to form a plurality of first conductive lines arranged along the second direction, etching the first conductive shielding structure from the second side of the active pillar to form a plurality of first conductive shielding lines arranged along the second direction, and etching the second conductive structure from the second side of the active pillar to form a plurality of second conductive lines arranged along the first direction are performed simultaneously.

[0096] In some embodiments, the method further includes:

[0097] Forming a first contact plug connected to the first conductive line from the second side; wherein, the first contact plugs connected to the first conductive lines adjacent to each other along the first direction are respectively located at opposite ends of the first conductive line along the second direction.

[0098] In some embodiments, the method further includes:

[0099] Forming a second contact plug connected to the first conductive shielding line from the second side; wherein, the second contact plugs connected to the first conductive shielding lines adjacent to each other along the first direction are respectively located at opposite ends of the first conductive shielding line along the second direction.

[0100] In some embodiments, forming the first contact plug and forming the second contact plug are performed simultaneously.

[0101] In some embodiments, the method further includes:

[0102] Forming a third contact plug connected to the first sub-conductive line from the second side;

[0103] Forming a fourth contact plug connected to the second sub-conductive line from the second side; the third contact plug and the fourth contact plug connected to the first sub-conductive line and the second sub-conductive line belonging to the same first conductive line are respectively located at opposite ends of the first conductive line along the first direction.

[0104] In some embodiments, the method further includes:

[0105] Forming a fifth contact plug connected to the second conductive shielding line from the second side; wherein, the fifth contact plugs connected to the second conductive shielding lines adjacent to each other along the second direction are respectively located at opposite ends of the second conductive shielding line along the first direction.

[0106] Next, a specific description will be given of the process treatment performed on the second side 102b of the active pillar 102. Figures 14 to 28

[0107] ​Figure 14 Cross-sectional views along Figure 9 the aa', bb' and cc' directions in Figure 9 . Figure 15 is a top view, Figure 16 Cross-sectional views along Figure 15 the aa' and cc' directions in Figure 15 .

[0108] In some embodiments, as Figure 14 shown, the substrate structure 300 includes a plurality of first semiconductor structures 110 and a first dielectric layer 106; wherein, the plurality of first semiconductor structures 110 are arranged along the first direction (X direction), the first semiconductor structures 110 extend along the second direction (Y direction) and are connected to the second ends of the plurality of active pillars 102 arranged along the second direction (Y direction), and the first dielectric layer 106 is at least located between the adjacent first semiconductor structures 110 along the first direction (X direction); a first conductive shielding structure is formed between the adjacent first conductive structures 110, including: as Figure 14 shown, the substrate structure 300 is thinned from the second side 102b of the active pillar 102, so as to expose the first dielectric layer 106 and the first semiconductor structure 110.

[0109] Next, as Figure 16 shown, the first dielectric layer 106 located between the adjacent first semiconductor structures 110 is removed to form a first filling region 113; a part of the second conductive structure 103 covering the side wall of the second end of the active pillar 102 is removed to form a second filling region 112. The second filling region 112 here communicates with the first filling region 113. The remaining part of the second conductive structure 103 constitutes a second conductive portion 103a. The second conductive portion 103a includes a first sub-conductive structure 147 and a second sub-conductive structure 148, and the first sub-conductive structure 147 and the second sub-conductive structure 148 are arranged along the second direction (Y direction) and both extend along the first direction (X direction).

[0110] In some embodiments, as Figures 14 to 16As shown, the base structure 300 further includes a gate oxide layer 149; the gate oxide layer 149 is at least located between the second conductive structure 103 and the active pillar 102 and between the first semiconductor structure 110 and the second conductive structure 103; the method further includes: before removing a part of the second conductive structure 103 covering the side wall of the second end of the active pillar 102 from the second side 102b of the active pillar 102, removing the gate oxide layer 149 between the second conductive structure 103 and the side wall of the second end of the active pillar 102 and the gate oxide layer 149 between the first semiconductor structure 110 and the second conductive structure 103 from the second side 102b of the active pillar 102 to form a third filling region. In the embodiment of the present disclosure, by removing the gate oxide layer 149 between the second conductive structure 103 and the side wall of the second end of the active pillar 102 and the gate oxide layer 149 between the first semiconductor structure 110 and the second conductive structure 103, such that as Figure 16 shown, the remaining gate oxide layer 149 and the second conductive portion 103a cover the side wall of the channel region of the active pillar 102.

[0111] In some embodiments, as Figure 16 shown, the method further includes: removing a part of the third dielectric layer 135 and a part of the second conductive material layer 144 from the second side 102b of the active pillar to form a fourth filling region 133. The remaining second conductive material layer 144 constitutes a second conductive shielding portion 107a, and the second conductive shielding portion 107a covers the side wall of the channel region of the active pillar 102.

[0112] In some embodiments, as Figure 10 shown, an adhesion layer 143 is further formed between the third conductive material layer 111 and the gate oxide layer 149. The material of the adhesion layer 143 includes, but is not limited to, titanium nitride. As Figure 16 shown, when removing a part of the second conductive structure 103 covering the side wall of the second end of the active pillar 102 to form a second filling region 112, the method further includes removing at least a part of the adhesion layer 143.

[0113] Figure 17 is a top view, Figure 18 、 Figure 19 and Figure 20 are cross-sectional views along the Figure 17 aa' and cc' directions in

[0114] Next, as Figures 17 to 19 shown, before forming the first conductive shielding structure 105 in the first filling region 113, a second dielectric layer 114 and a third conductive material layer 115 are formed in the first filling region 113, and the second dielectric layer 114 is formed in the second filling region 112.

[0115] In some embodiments, when forming the second dielectric layer 114 in a partial region of the first filling region 113 and the second filling region 112, the second dielectric layer 114 is also formed in the third filling region and the fourth filling region 133.

[0116] In some embodiments, first, as Figure 18 shown, a second initial dielectric layer 114a and a third initial conductive material layer 115a are formed. The second initial dielectric layer 114a and the third initial conductive material layer 115a are also formed on the first semiconductor structure 110. A partial second initial dielectric layer 114a and a partial third initial conductive material layer 115a can be removed by a planarization process, such that the top surfaces of the finally formed second dielectric layer 114 and the third conductive material layer 115, as Figure 19 shown, are flush with the top surface of the first semiconductor structure 110.

[0117] Figure 22 And Figure 23 respectively show cross-sectional views along the aa' and cc' directions in Figure 21 .

[0118] As Figures 21 to 23 shown, a fifth dielectric layer 139 is formed on the second side 102b of the active pillar. The fifth dielectric layer 139 covers the first semiconductor structure 110 and the third conductive material layer 115. The material of the fifth dielectric layer 139 includes but is not limited to silicon nitride and silicon oxide. The fifth dielectric layer 139 is etched to expose a partial first semiconductor structure 110 and a partial third conductive material layer 115. The partial third conductive material layer 115 between the first semiconductor structures 110 is continuously etched to form a first conductive shielding structure 105.

[0119] In some embodiments, as Figure 23 shown, the method further includes: etching the second conductive portion 103a from the second side 102b of the active pillar 102 to form a second conductive wire 123.

[0120] The specific process of forming the second conductive wire 123 can be etching the fifth dielectric layer 139, the second dielectric layer 114, the third conductive material layer 115, and the second conductive portion 103a to form the second conductive wire 123 and a fifth filling region 134.

[0121] In some embodiments, the second conductive wire 123 includes a first sub-conductive wire 131 and a second sub-conductive wire 132.

[0122] Figure 25 And Figure 26 respectively show cross-sectional views along the aa' and cc' directions in Figure 24 .

[0123] Next, as shown in Figure 24 and Figure 25 , a dielectric material is filled in the fifth filling region 134 to form a first isolation structure 140. The dielectric material here includes but is not limited to silicon nitride and silicon oxide.

[0124] In some embodiments, forming the first conductive line may be as shown in Figure 20 . After the first semiconductor structure 110 is exposed, a first conductive material layer (not shown) is formed on the first semiconductor structure 110, and heat treatment is performed on the first semiconductor structure 110 and the first conductive material layer to form a first conductive structure 170, and then the first conductive structure 170 is etched to form a plurality of first conductive lines arranged along the second direction.

[0125] In other embodiments, it may be as shown in Figure 23 . First, the first semiconductor structure 110 is etched to form a plurality of first semiconductor lines 180 arranged along the second direction, and then as shown in Figure 26 , a first conductive material layer (not shown) is formed on the first semiconductor lines 180, and heat treatment is performed on the first semiconductor lines 180 and the first conductive material layer to form a first conductive line 126.

[0126] In some embodiments, the material of the first conductive structure 170 includes but is not limited to nickel silicide.

[0127] In some embodiments, as shown in Figure 27 , the method further includes: etching the first conductive structure from the second side 102b of the active column 102 to form a plurality of first conductive lines 126 arranged along the second direction.

[0128] In some embodiments, the method further includes: etching the first conductive shielding structure 105 from the second side 102b of the active column 102 to form a first conductive shielding line 108.

[0129] In some embodiments, etching the first conductive structure 110 from the second side 102b of the active column to form a plurality of first conductive lines 126 arranged along the second direction, and etching the first conductive shielding structure 105 from the second side 102b of the active column 102 to form a plurality of first conductive shielding lines 108 arranged along the second direction are performed simultaneously.

[0130] In the embodiments of the present disclosure, the first conductive structure 110 and the first conductive shielding structure 105 can be etched using the same mask, which can simplify the process steps, save the number of masks, and thus save the process cost.

[0131] In some embodiments, etching the first conductive structure from the second side 102b of the active pillar to form a plurality of first conductive lines arranged along the second direction, etching the first conductive shielding structure from the second side 102b of the active pillar to form a plurality of first conductive shielding lines arranged along the second direction, and etching the second conductive structure from the second side 102b of the active pillar to form a plurality of second conductive lines arranged along the first direction are carried out simultaneously.

[0132] In some embodiments, the method further includes: etching the second conductive shielding portion from the second side 102b of the active pillar 102 to form second conductive shielding lines.

[0133] In some embodiments, after forming the first conductive shielding lines, the first conductive lines, and the second conductive shielding lines, the first isolation structure may be formed between the second conductive shielding lines adjacent to each other along the first direction, and the first isolation structure may be formed between the first conductive lines adjacent to each other along the second direction and between the first conductive shielding lines adjacent to each other along the second direction.

[0134] In some specific examples, the second conductive line 123 described above may be a word line, and the first conductive line 126 may be a bit line.

[0135] In some embodiments, forming the first conductive shielding lines, forming the first conductive lines 126, forming the second conductive lines 123, and forming the second conductive shielding lines may be formed simultaneously. That is, the first conductive structure, the first conductive shielding structure, the second conductive portion, and the second conductive shielding portion are etched using the same mask, which can simplify the process, save the number of masks, and thus save the process cost.

[0136] Figure 28 respectively show cross-sectional views along Figure 27 the aa' and cc' directions in

[0137] Next, as Figure 28 shown, an eighth dielectric layer 161 is formed from the second side 102b of the active pillar 102, and the eighth dielectric layer 161 covers the first conductive lines 126, the first conductive shielding lines, the second conductive lines, and the second conductive shielding lines. The eighth dielectric layer 161 is etched to form a first contact plug 127 connected to the first conductive lines in the eighth dielectric layer 161.

[0138] In some embodiments, a second voltage may be applied to the second conductive shielding lines, thereby improving the coupling effect of the active pillars adjacent to each other along the second direction.

[0139] In some embodiments, as Figure 27 and Figure 28As shown, a second contact plug 145 connected to the first conductive shield line 108, a third contact plug 141 connected to the second conductive line 123, and a fourth contact plug 144 connected to the second conductive shield line 109 can also be formed in the eighth dielectric layer 161.

[0140] In some embodiments, as Figure 28 shown, the method further includes removing a part of the first conductive shield line, so that the width of the first conductive shield lines at the edges of two adjacent memory array slices along the first direction becomes smaller along the first direction, facilitating the formation of the second contact plug 145 described above.

[0141] In some embodiments, as Figure 27 shown, the first contact plugs 127 connected to the first conductive lines 126 adjacent to each other along the first direction (X direction) are respectively located at opposite ends of the first conductive lines 126 along the second direction (Y direction). In this way, the first contact plugs 127 connected to the first conductive lines 126 adjacent to each other along the first direction are separated from each other by a relatively large distance and are not easily connected together, and the distance between the first contact plugs adjacent to each other along the first direction is relatively large, so that the problem that the first conductive lines adjacent to each other along the first direction are easily electrically connected under the trend of miniaturization of the semiconductor structure can be improved, thereby improving the performance of the semiconductor structure; in addition, from a process perspective, the process window can be increased and the process difficulty can be reduced.

[0142] In some embodiments, as Figure 27 shown, the method further includes: forming a second contact plug 145 connected to the first conductive shield line 108 from the second side 102b; wherein the second contact plugs 145 connected to the first conductive shield lines 108 adjacent to each other along the first direction are respectively located at opposite ends of the first conductive shield lines 108 along the second direction. In this way, the distance between the second contact plugs adjacent to each other along the first direction is relatively large, so that the process window can be increased and the process difficulty can be reduced.

[0143] In some embodiments, the first contact plug and the second contact plug can be formed simultaneously. That is, the first contact plug 127 and the second contact plug 145 are formed by etching the eighth dielectric layer 161 using the same mask. In this way, the process steps can be saved, the number of masks can be saved, and the process cost can be saved.

[0144] In some embodiments, the method further includes: forming a third contact plug 141 from the second side 102b of the active pillar 102; the third contact plug 141 is connected to the second conductive line 123.

[0145] In some embodiments, as Figure 27As shown, the second conductive wire 123 includes a first sub-conductive wire 131 and a second sub-conductive wire 132. The first sub-conductive wire 131 and the second sub-conductive wire 132 are arranged along the second direction and both extend along the first direction. The first sub-conductive wire 131 covers the sidewalls of the channel regions of multiple active pillars 102 of the first row of active pillars 150, and the second sub-conductive wire 132 covers the sidewalls of the channel regions of multiple active pillars 102 of the second row of active pillars 151. The adjacent first row of active pillars 150 and the second row of active pillars 151 form a row of active pillar group 152, and the second conductive shielding structure 107 is located between adjacent rows of active pillar groups 152. The third contact plug 141 includes a first sub-contact plug 142 and a second sub-contact plug 143. The first sub-contact plug 142 is connected to the first sub-conductive wire 131, and the second sub-contact plug 143 is connected to the second sub-conductive wire 132.

[0146] In some embodiments, forming the first contact plug, forming the second contact plug, and forming the third contact plug can be performed simultaneously. In this way, process steps can be saved, the number of mask plates can be saved, and the process cost can be saved.

[0147] Based on the manufacturing method of the above semiconductor structure, an embodiment of the present disclosure further provides a semiconductor structure. Figure 29 is a top view of the semiconductor structure. Figure 30 is a cross-sectional view of the semiconductor structure along the aa' direction. As Figure 29 and Figure 30 shown, the semiconductor structure includes multiple memory array chips 153; the memory array chip 153 includes:

[0148] A substrate structure 300; the substrate structure 300 includes multiple active pillars 102 arranged in an array along a first direction (for example, the X direction) and a second direction (for example, the Y direction); the active pillars 102 include a first end and a second end arranged along a third direction; the first direction and the second direction intersect and are both perpendicular to the third direction (for example, the Z direction).

[0149] As Figure 30 shown, the memory array chip further includes a memory structure 160 located on the first side 102a of the active pillar 102; the memory structure 160 is connected to the first end of the active pillar 102; the memory structure 160 is located in the stacked structure 200.

[0150] As Figure 29 shown, multiple first conductive wires 126 arranged along the first direction on the second side 102b of the active pillar; the first conductive wires 126 extend along the second direction and are connected to the second end of the active pillar 102; the first side 102a and the second side 102b are the two opposite sides of the active pillar 102 along the third direction.

[0151] A plurality of first conductive shielding lines 108 arranged along the first direction on the second side 102b of the active column 102; the first conductive shielding lines 108 are located between adjacent first conductive lines 126 and extend along the second direction.

[0152] In an embodiment of the present disclosure, the first conductive line 126 may be a bit line.

[0153] In some embodiments, the material of the first conductive shielding line 108 includes a conductive material. Exemplarily, it includes tungsten metal.

[0154] In an embodiment of the present disclosure, a plurality of first conductive shielding lines 108 arranged along the first direction are provided on the second side 102b of the active column 102. During the read and write operations of the memory, a first voltage may be applied to the first conductive shielding lines 108, and the first conductive shielding lines 108 can be used to reduce the coupling effect between adjacent first conductive lines 126.

[0155] In some embodiments, the memory array chip further includes:

[0156] A second dielectric layer; the second dielectric layer is located between the first conductive shielding line and the first conductive line.

[0157] In some embodiments, the material of the second dielectric layer includes but is not limited to silicon nitride and silicon oxide. The second dielectric layer is used to isolate the first conductive shielding line from the first conductive line.

[0158] In some embodiments, as Figure 29 and Figure 30 shown, the memory array chip 153 further includes:

[0159] A first contact plug 127 connected to the first conductive line 126; the first contact plug 127 is located on the second side 102b of the active column 102; the first contact plugs 127 connected to the first conductive lines 126 adjacent along the first direction (X direction) are respectively located on opposite sides of the memory array chip 153 along the second direction (Y direction).

[0160] In some embodiments, the material of the first contact plug 127 includes a conductive material, including but not limited to tungsten metal.

[0161] In an embodiment of the present disclosure, by applying a voltage to the first contact plug 127, the first conductive line 126 corresponding to the first contact plug 127 can be selected.

[0162] The first contact plugs 127 connected to the first conductive lines 126 adjacent along the first direction (X direction) are respectively located at opposite ends of the first conductive lines 126 along the second direction (Y direction). In this way, the first contact plugs 127 connected to the first conductive lines 126 adjacent along the first direction are separated from each other by a relatively large distance and are not easily connected together, and the distance between the first contact plugs adjacent along the first direction is relatively large, so that the problem that the first conductive lines adjacent along the first direction are easily electrically connected under the trend of miniaturization of the semiconductor structure can be improved, thereby improving the performance of the semiconductor structure; in addition, from the process perspective, the process window can be increased and the process difficulty can be reduced.

[0163] In some embodiments, as Figure 29 shown, the memory array sheet 153 further includes:

[0164] a second contact plug 145 connected to the first conductive shielding line 108; the second contact plug 145 is located on the second side 102b of the active pillar; the second contact plugs 145 connected to the first conductive shielding lines 108 adjacent along the first direction (X direction) are respectively located on opposite sides of the memory array sheet 153 along the second direction (Y direction). In this way, the distance between the second contact plugs adjacent along the first direction is relatively large, so that the process window can be increased and the process difficulty can be reduced.

[0165] In some embodiments, the material of the second contact plug 145 includes a conductive material, including but not limited to tungsten.

[0166] In the embodiments of the present disclosure, by applying a voltage to the second contact plug 145, a voltage can be applied to the first conductive shielding line 108, thereby reducing the coupling effect between adjacent first conductive lines 126.

[0167] In some embodiments, as Figure 29 shown, the first contact plug 127 and the second contact plug 145 located on the third side of the opposite sides of the memory array sheet 153 along the second direction are arranged staggeredly along the second direction, and the first contact plug 127 and the second contact plug 145 located on the fourth side of the opposite sides of the memory array sheet along the second direction are arranged staggeredly along the second direction.

[0168] In the embodiments of the present disclosure, the first contact plug 127 and the second contact plug 145 on the same side are arranged staggeredly, avoiding the situation of electrical connection caused by the first contact plug 127 and the second contact plug 145 being too close in the second direction.

[0169] In some embodiments, the size of the first conductive shielding line 108 in the third direction may be the same as the size of the first conductive line 126 in the third direction.

[0170] In other embodiments, the size of the first conductive shielding line 108 in the third direction may also be different from the size of the first conductive line 126 in the third direction.

[0171] In some embodiments, as Figure 29 shown, the semiconductor structure further includes a first isolation structure 140, and the first isolation structure 140 is located between the first conductive lines 126 of the memory array sheets 153 adjacent in the second direction and between the first conductive shielding lines 108 of the memory array sheets adjacent in the second direction.

[0172] In some embodiments, the first isolation structure 140 is also located between the second conductive lines of the memory array sheets 153 adjacent in the first direction and between the second conductive shielding lines of the memory array sheets 153 adjacent in the first direction.

[0173] In the embodiments of the present disclosure, the first isolation structure 140 is used to isolate the first conductive line 126, the first conductive shielding line 108, the second conductive line, and the second conductive shielding line in the adjacent memory array sheets 153, so that the semiconductor structure can perform independent read and write operations in units of the memory array sheets 153; on the other hand, in the embodiments of the present disclosure, etching the first conductive structure to form the first conductive line, etching the first conductive shielding structure to form the first conductive shielding line, etching the second conductive structure to form the second conductive line, etching the second conductive shielding structure to form the second conductive shielding line, forming the first contact plug, and the second contact plug are all performed on the second side 102b of the active column, which facilitates process integration and facilitates the formation of the first conductive shielding line.

[0174] Based on the above semiconductor structure, the embodiments of the present disclosure further provide a memory system, and the memory system includes a memory controller and the semiconductor structure as described in any one of the above embodiments; the memory controller is coupled to the semiconductor structure and is configured to control the semiconductor structure.

[0175] In some embodiments, the memory system includes a solid-state drive and a memory.

[0176] The above semiconductor structure includes but is not limited to a memory, and more specifically includes but is not limited to a dynamic random access memory. The embodiments of the present disclosure take the semiconductor structure as a dynamic random access memory as an example for exemplary illustration.

[0177] The memory in the above embodiments can be used as a buffer memory in a solid-state drive, or the memory in the above embodiments can be used as a storage medium in the memory.

[0178] Figure 31 FIG. shows a schematic block diagram of an exemplary electronic device according to an embodiment of the present application. The electronic device 1 can be a mobile phone, a desktop computer, a laptop computer, a tablet computer, a vehicle computer, a game console, a printer, a positioning device, a wearable electronic device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, or any other suitable electronic device having a memory. As Figure 31 shown, the electronic device 1 can include a host HOST and a memory system 30, and the memory system 30 includes a memory controller 10 and one or more memory devices 20. The host HOST can be a processor of the electronic device (e.g., a Central Processing Unit (CPU) or a Graphic Processing Unit (GPU)). The host HOST can be configured to send data to or receive data from the memory device 20. The memory controller 10 is coupled to the memory device 20 and the host HOST, and is configured to control the memory device 20. The memory controller 10 can manage the data stored in the memory device 20 and communicate with the host HOST.

[0179] The memory controller 10 can be configured to control the operations of the memory device 20, such as read, erase, write, and refresh operations. In some embodiments, the memory controller 10 is further configured to process an Error Correction Code (ECC) for data read from or written to the memory device 20. The memory controller 10 can also perform any other suitable functions, such as formatting the memory device 20.

[0180] In some specific embodiments, the memory controller 10 and one or more memory devices 20 can be integrated into various types of electronic devices. For example, the memory controller 10 can be integrated into the north bridge of a computer motherboard or directly integrated into the computer CPU, and multiple memory devices 20 can be integrated into a memory module. That is, the memory system 30 can be implemented and encapsulated into different types of terminal electronic products.

[0181] The memory controller 10 can send data to / receive data from the host HOST, and can send a command CMD and an address ADDR to the memory device 20. The memory controller 10 can include a command generator 11, an address generator 12, a device interface 13, and a host interface 14. The host interface 14 can receive a command CMD and an address ADDR from the host HOST. The command generator 11 can generate an access command, a row hammer refresh command, etc. by decoding the command CMD received from the host HOST, and can provide the access command and the row hammer refresh command to the memory device 20 through the device interface 13. The access command can be a signal instructing the memory device 20 to write or read data by accessing a row of the memory cell array 22 corresponding to the address ADDR. The row hammer refresh command can be a signal commanding the memory device 20 to perform an additional refresh operation on a word line adjacent to the word line that is intensively accessed in a short period. In other words, an additional refresh operation can be performed on a word line adjacent to the word line that is accessed multiple times in a short period.

[0182] The address generator 12 in the memory controller 10 can generate a row address and a column address to be accessed in the memory cell array 22 by decoding the address ADDR received from the host interface 14. In addition, the memory device 20 can generate an address of a bank to be accessed when the memory cell array 22 includes multiple banks.

[0183] In addition, the memory controller 10 can control memory operations such as writing and reading by providing various signals to the memory device 20 via the device interface 13. For example, the memory controller 10 can provide a write command to the memory device 20. The write command is used to instruct the memory device 20 to perform a write operation to store data in the memory device 20.

[0184] In some embodiments, the memory device 20 includes a memory cell array 22 and peripheral circuits 21; wherein, the memory cell array 22 includes a plurality of banks, each bank includes a plurality of blocks, each block includes a plurality of memory cell rows and a plurality of memory cell columns, each memory cell row is coupled to a corresponding word line, and each memory cell column is coupled to a corresponding bit line. The peripheral circuits 21 can write data to the memory cell array 22 or read data from the memory cell array 22 based on commands CMD and addresses ADDR received from the memory controller 10, or can provide control signals CTRL for refreshing the memory cells included in the memory cell array 22 to the row decoding circuit and the column decoding circuit. In other words, the peripheral circuits 21 can perform all operations to process the data in the memory cell array 22. The peripheral circuits 21 can include: control circuits corresponding to each memory block, such as a sensing amplifier (SA) and a word-line driver (WLD), etc., control circuits corresponding to each bank, such as a row decoding circuit, a column decoding circuit, etc., and control circuits corresponding to all banks, such as a command buffer, a command decoder, an address buffer, a data input / output buffer, a mode register, etc.

[0185] The memory device 20 can be a random access memory (RAM), such as a dynamic random access memory (DRAM), a synchronous DRAM (SDRAM), a static RAM (SRAM), a double data rate SDRAM (DDR SDRAM), a DDR2 SDRAM, a DDR3 SDRAM, a phase change RAM (PRAM), a magnetic RAM (MRAM), a resistive RAM (RRAM), etc. Hereinafter, only DRAM will be taken as an example for illustration.

[0186] Figure 32 Schematic diagram of the composition block diagram of an exemplary SSD according to an embodiment of the present application. Here, the SSD can be understood as a kind of the memory system described above. In this example, the DRAM can be used as a buffer memory. Figure 31 in the foregoing

[0187] As Figure 32As shown, the SSD 30a may include an SSD controller 10a, a buffer memory 20a, and a non-volatile memory 40. The SSD controller 10a may provide a physical connection between the host HOST and the SSD 30a. That is, the SSD controller 10a may provide an interface between the host HOST and the SSD 30a in accordance with the bus format of the host. The SSD controller 10a may decode instructions provided from the host HOST. The SSD controller 10a may access the non-volatile memory 40 based on the decoded result. The buffer memory 20a may temporarily store write data provided from the host HOST or data read from the non-volatile memory 40. When the host HOST issues a read request, if the data present in the non-volatile memory 40 is cached, the buffer memory 20a may support a cache function for directly providing the cached data to the host HOST. The data transfer rate through the bus format of the host (e.g., SATA or SAS) is much higher than the data transfer rate of the memory channel of the SSD 30a. That is, when the interface speed of the host is significantly high, the performance degradation due to the speed difference may be minimized by providing a high-capacity buffer memory 20a. In addition, the buffer memory 20a may store an address mapping table of the non-volatile memory 40. The buffer memory 20a may include, but is not limited to, DRAM. The non-volatile memory 40 is provided as a storage medium of the SSD 30a. The non-volatile memory 40 may include, but is not limited to, NAND-type memory.

[0188] Figure 33 Schematic diagram of the composition block diagram of an exemplary memory according to an embodiment of the present application; here, the memory may be understood as a kind of the memory system described above Figure 32 In this example, DRAM may be used as a storage medium.

[0189] As Figure 33 shown, the memory 30b can be easily attached or installed to an electronic device or detached from the electronic device 1 through the illustrated interface. The memory 30b may include a plurality of volatile memories 20b (e.g., DRAM) and a memory controller 10b. The memory module memory 30b can be used to write data, store data, obtain (or read) data, and / or erase data under the control of a processor of a computer. In some embodiments, the controller memory controller 10b may communicate with the DRAM using at least one communication protocol or technical standard typically associated with, for example, dual in-line memory modules (DIMMs), registered DIMMs (RDIMMs), low-profile DIMMs (LRDIMMs), unregistered DIMMs (UDIMMs), etc.

[0190] It should be noted that Figure 32 the buffer memory 20a in Figure 33 and the volatile memory 20b inFigure 31 An application scenario of the memory device 20.

[0191] In several embodiments provided by the present disclosure, it should be understood that the disclosed devices and methods can be implemented in a non-target manner. The device embodiments described above are merely illustrative. For example, the division of the units is only a logical function division, and there may be other division methods in actual implementation. For example, multiple units or components can be combined, or can be integrated into another system, or some features can be ignored or not executed. Additionally, the couplings between the various components shown or discussed are either direct couplings.

[0192] The features disclosed in several method or device embodiments provided by the present disclosure can be arbitrarily combined without conflict to obtain new method embodiments or device embodiments.

[0193] As described above, the above is only the specific implementation manner of the present disclosure, but the protection scope of the present disclosure is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present disclosure can easily think of changes or substitutions, which should all be covered within the protection scope of the present disclosure. Therefore, the protection scope of the present disclosure should be subject to the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Comprising: Providing a substrate structure; wherein, the substrate structure includes a plurality of active columns arranged in an array along a first direction and a second direction; the active columns include a first end and a second end arranged along a third direction; the first direction and the second direction intersect and are both perpendicular to the third direction; Forming a storage structure on a first side of the active column; the storage structure is connected to the first end; Forming a plurality of first conductive structures arranged along the first direction on a second side of the active column; the first conductive structures extend along the second direction and are connected to the second end; the first side and the second side are two opposite sides of the active column along the third direction; Forming a first conductive shielding structure between adjacent first conductive structures from the second side; the first conductive shielding structure extends along the second direction; Etching the first conductive structures from the second side of the active column to form a plurality of first conductive wires arranged along the second direction; Etching the first conductive shielding structure from the second side of the active column to form a plurality of first conductive shielding wires arranged along the second direction.

2. The manufacturing method according to claim 1, characterized in that, The etching of the first conductive structures from the second side of the active column to form a plurality of first conductive wires arranged along the second direction and the etching of the first conductive shielding structure from the second side of the active column to form a plurality of first conductive shielding wires arranged along the second direction are carried out simultaneously.

3. The manufacturing method according to claim 1, characterized in that, The method further includes: Forming a plurality of second conductive structures; the second conductive structures extend along the first direction and are located between adjacent active columns along the second direction; Etching the second conductive structures from the second side of the active column to form a plurality of second conductive wires arranged along the first direction.

4. The manufacturing method according to claim 3, characterized in that, The etching of the first conductive structures from the second side of the active column to form a plurality of first conductive wires arranged along the second direction, the etching of the first conductive shielding structure from the second side of the active column to form a plurality of first conductive shielding wires arranged along the second direction, and the etching of the second conductive structures from the second side of the active column to form a plurality of second conductive wires arranged along the first direction are carried out simultaneously.

5. The manufacturing method according to claim 1, characterized in that The substrate structure further includes a plurality of first semiconductor structures and a first dielectric layer; wherein, the plurality of first semiconductor structures are arranged along the first direction, the first semiconductor structures extend along the second direction and are connected to the second ends of the plurality of active columns arranged along the second direction, and the first dielectric layer is at least located between adjacent first semiconductor structures along the first direction; the forming of the first conductive shielding structure between adjacent first conductive structures includes: Removing the first dielectric layer located between adjacent first semiconductor structures along the first direction from the second side to form a first filling region; Forming the first conductive shielding structure in the first filling region.

6. The manufacturing method according to claim 5, characterized in that, The method further includes: Before forming the first conductive shielding structure in the first filling region, forming a second dielectric layer in a partial region of the first filling region; the second dielectric layer in the first filling region is located between the first semiconductor structure and the first conductive shielding structure.

7. The manufacturing method according to claim 5, characterized in that, Forming a plurality of first conductive structures arranged along the first direction on the second side of the active column includes: Forming a first conductive material layer covering the first semiconductor structure from the second side of the active column; Performing a heat treatment on the first semiconductor structure and the first conductive material layer to form the first conductive structure.

8. The manufacturing method according to claim 5, characterized in that Forming the base structure includes: Providing a substrate; Etching the substrate to form a plurality of first trenches arranged along the first direction; the first trenches extend along the second direction and the bottoms are located in the substrate; Forming the first dielectric layer in the first trenches; Etching the substrate and the first dielectric layer to form second trenches and third trenches arranged alternately along the second direction; wherein, the second trenches and the third trenches both extend along the first direction and the bottoms are located in the substrate, and the depths of the second trenches and the third trenches are less than the depth of the first trenches; the first trenches, second trenches, and third trenches divide the substrate into a plurality of the active columns and a plurality of the first semiconductor structures.

9. The manufacturing method according to claim 1, characterized in that, The method further includes: Forming a first contact plug connected to the first conductive wire from the second side; wherein, the first contact plugs connected to the first conductive wires adjacent along the first direction are respectively located at opposite ends of the first conductive wire along the second direction.

10. The manufacturing method according to claim 9, wherein, The method further includes: Forming a second contact plug connected to the first conductive shielding wire from the second side; wherein, the second contact plugs connected to the first conductive shielding wires adjacent along the first direction are respectively located at opposite ends of the first conductive shielding wire along the second direction.

11. The manufacturing method according to claim 10, characterized in that, Forming the first contact plug and forming the second contact plug are performed simultaneously.

12. A semiconductor structure, characterized in that, The semiconductor structure includes a plurality of memory array chips; the memory array chip includes: A base structure; the base structure includes a plurality of active columns arranged in an array along a first direction and a second direction; the active column includes a first end and a second end arranged along a third direction; the first direction and the second direction intersect and are both perpendicular to the third direction; A memory structure located on the first side of the active column; the memory structure is connected to the first end of the active column; A plurality of first conductive wires arranged along the first direction on the second side of the active column; the first conductive wires extend along the second direction and are connected to the second end of the active column; the first side and the second side are opposite sides of the active column along the third direction; A plurality of first conductive shielding wires arranged along the first direction on the second side of the active column; the first conductive shielding wires are located between adjacent first conductive wires and extend along the second direction.

13. The semiconductor structure according to claim 12, wherein, The memory array chip further includes: A second dielectric layer; the second dielectric layer is located between the first conductive shielding wire and the first conductive wire.

14. The semiconductor structure according to claim 12, wherein, The memory array chip further includes: A first contact plug connected to the first conductive wire; the first contact plug is located on the second side; the first contact plugs connected to the first conductive wires adjacent to each other along the first direction are respectively located on opposite sides of the memory array sheet along the second direction.

15. The semiconductor structure according to claim 14, wherein, The memory array sheet further includes: A second contact plug connected to the first conductive shielding wire; the second contact plug is located on the second side; the second contact plugs connected to the first conductive shielding wires adjacent to each other along the first direction are respectively located on opposite sides of the memory array sheet along the second direction.

16. The semiconductor structure according to claim 15, wherein, The first contact plug and the second contact plug located on the third side of the opposite sides of the memory array sheet along the second direction are arranged staggeredly along the second direction, and the first contact plug and the second contact plug located on the fourth side of the opposite sides of the memory array sheet along the second direction are arranged staggeredly along the second direction.

17. The semiconductor structure according to claim 12, wherein The material of the first conductive shielding wire includes a conductive material.

18. The semiconductor structure according to claim 12, wherein The dimension of the first conductive shielding wire along the third direction is the same as the dimension of the first conductive wire along the third direction.

19. The semiconductor structure according to claim 12, wherein The semiconductor structure further includes a first isolation structure, and the first isolation structure is located between the first conductive wires of the memory array sheets adjacent to each other along the second direction and between the first conductive shielding wires of the memory array sheets adjacent to each other along the second direction.

20. A memory system, characterized in that, Including the semiconductor structure according to any one of claims 12 to 19 and a controller.

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