Semiconductor structure, preparation method thereof and storage system

Abstract

The invention provides a semiconductor structure, a preparation method thereof and a storage system, relates to the technical field of semiconductor chips, and aims to solve the problem of complex preparation process of the semiconductor structure. The semiconductor structure is provided with an array region and a connection region, and comprises a first surface and a second surface which are oppositely arranged. The semiconductor structure comprises a plurality of gate structures and a plurality of isolation structures which extend along the first direction, and a first medium part located in the connection region. In the second direction, one isolation structure is located between two adjacent gate structures. The isolation structure comprises a first part located in the array region and a second part located in the connection region. In the third direction, the first part comprises a first insulating layer, a conductive layer and a second insulating layer which are sequentially arranged, the first insulating layer is closer to the first surface than the second insulating layer, and the second part at least comprises the second insulating layer. In the first direction, the first dielectric part is at least located at the end of the gate structure.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor chips, and particularly to a semiconductor structure, a manufacturing method thereof, and a storage system. Background Art

[0002] Transistors in semiconductor structures are widely used as switching devices or driving devices in electronic devices. With the development of semiconductor technology, the manufacturing process of semiconductor structures needs to be further optimized. Summary of the Invention

[0003] On the one hand, a semiconductor structure is provided. The semiconductor structure has an array region and a connection region, and includes a first surface and a second surface that are oppositely arranged. The semiconductor structure includes a plurality of gate structures, a plurality of isolation structures, and a first dielectric portion located in the connection region. The gate structures and the isolation structures both extend in a first direction, and in a second direction, an isolation structure is located between two adjacent gate structures. The isolation structure includes a first portion located in the array region and a second portion located in the connection region. In a third direction, the first portion includes a first insulating layer, a conductive layer, and a second insulating layer that are sequentially arranged. The first insulating layer is closer to the first surface than the second insulating layer. The second portion includes at least the second insulating layer. In the first direction, the first dielectric portion is at least located at the end of the gate structure. The first direction and the second direction are parallel to the first surface and intersect, and the third direction is perpendicular to the first surface.

[0004] In some embodiments, the second portion of the isolation structure includes a conductive layer and a second insulating layer that are sequentially arranged in the third direction. In the first direction, the first dielectric portion is located at the ends of the gate structure and the first insulating layer. In the third direction, the first dielectric portion overlaps with the second portion.

[0005] In some embodiments, the portion of the first dielectric portion located at the end of the gate structure is a first sub-portion, and the portion of the first dielectric portion located at the end of the first insulating layer is a second sub-portion. In the second direction, the first sub-portion in at least one of the two gate structures adjacent to the isolation structure overlaps with the second sub-portion in the isolation structure.

[0006] In some embodiments, the two gate structures adjacent to the isolation structure are a first gate structure and a second gate structure respectively. In the second direction, the first sub-portion in the first gate structure and the first sub-portion in the second gate structure both overlap with the second sub-portion in the isolation structure.

[0007] In some embodiments, the gate structure adjacent to the first gate structure and located on the side of the first gate structure away from the isolation structure is the third gate structure, and the gate structure adjacent to the second gate structure and located on the side of the second gate structure away from the isolation structure is the fourth gate structure. The first sub - part in the third gate structure and the first sub - part in the first gate structure are respectively located on both sides of the array region, and the first sub - part in the fourth gate structure and the first sub - part in the second gate structure are respectively located on both sides of the array region.

[0008] In some embodiments, the gate structure adjacent to the first gate structure and located on the side of the first gate structure away from the isolation structure is the third gate structure, and the gate structure adjacent to the second gate structure and located on the side of the second gate structure away from the isolation structure is the fourth gate structure. Along the second direction, the first sub - part in the third gate structure and the first sub - part in the first gate structure overlap, and the first sub - part in the fourth gate structure and the first sub - part in the second gate structure overlap.

[0009] In some embodiments, the two gate structures adjacent to the isolation structure are the first gate structure and the second gate structure respectively. Along the second direction, the first sub - part in the first gate structure and the second sub - part in the isolation structure overlap, and the first sub - part in the second gate structure and the second sub - part in the isolation structure are respectively located on both sides of the array region.

[0010] In some embodiments, the second part of the isolation structure includes a first isolation sub - part and a second isolation sub - part. The first isolation sub - part at least includes a conductive layer and a second insulating layer arranged in sequence along the third direction, and the second isolation sub - part includes a second insulating layer. Along the first direction, the first dielectric part is located at the ends of the gate structure and the conductive layer. Along the third direction, the first dielectric part and the second isolation sub - part overlap.

[0011] In some embodiments, the part of the first dielectric part located at the end of the gate structure is the first sub - part, and the part of the first dielectric part located at the end of the conductive layer is the third sub - part. Along the second direction, the first sub - part in the gate structure and the third sub - part in the isolation structure overlap.

[0012] In some embodiments, the multiple first dielectric parts located on the same side of the array region are an integral structure.

[0013] In some embodiments, the part of the first dielectric part located at the end of the gate structure is the first sub - part. The semiconductor structure further includes multiple first lead - out parts. One end of the first lead - out part close to the second insulating layer is connected to the conductive layer. Along the first direction, the size of the end of the first lead - out part close to the second insulating layer is smaller than the size of the end away from the second insulating layer. Along the second direction, the first lead - out part and the first sub - part overlap.

[0014] In some embodiments, the second part of the isolation structure includes a conductive layer and a second insulating layer arranged in sequence along a third direction. When the first dielectric part overlaps with the second part along the third direction, the overlapping part of the first dielectric part and the second part is the second sub-part, and the first lead-out part penetrates through the second sub-part along the third direction and is connected to the conductive layer. Alternatively, in the second part of the isolation structure, there are a first isolation sub-part and a second isolation sub-part. The first isolation sub-part at least includes a conductive layer and a second insulating layer arranged in sequence along the third direction, and the second isolation sub-part includes a second insulating layer. When the first dielectric part overlaps with the second isolation sub-part along the third direction, the first lead-out part overlaps with at least a part of the first isolation sub-part along the third direction.

[0015] In some embodiments, the semiconductor structure further includes a plurality of second lead-out parts. One end of the second lead-out part close to the second insulating layer is connected to the gate structure. Along a first direction, the size of one end of the second lead-out part close to the second insulating layer is smaller than the size of the end far from the second insulating layer.

[0016] In some embodiments, two adjacent gate structures to the isolation structure are a first gate structure and a second gate structure respectively, and the gate structure adjacent to the first gate structure and located on the side of the first gate structure far from the isolation structure is a third gate structure. Along a second direction, the second lead-out part connected to the first gate structure overlaps with a first sub-part in the third gate structure. And / or, the second lead-out part connected to the third gate structure overlaps with a first sub-part in the first gate structure.

[0017] In some embodiments, the first lead-out parts connected to a plurality of isolation structures are located on the same side of the array region; or, the first lead-out parts connected to a plurality of isolation structures are alternately arranged on both sides of the array region.

[0018] In some embodiments, along the third direction, the distance from the conductive layer of the isolation structure to the first surface is greater than the distance from the gate structure to the first surface.

[0019] In some embodiments, the semiconductor structure further includes a plurality of bit lines, a second dielectric part, and a plurality of third lead-out parts. The bit lines extend along a second direction. The second dielectric part is located at the end of the bit lines along the second direction. One end of the third lead-out part close to the second surface is connected to the bit line. Along the first direction, the size of one end of the third lead-out part close to the second surface is smaller than the size of the end far from the second surface.

[0020] On the other hand, a method for manufacturing a semiconductor structure is provided. The semiconductor structure has an array region and a connection region, and includes a first surface and a second surface disposed opposite to each other. The method for manufacturing the semiconductor structure includes: forming a plurality of gate structures and a plurality of isolation structures; both the gate structures and the isolation structures extend along a first direction, and along a second direction, one isolation structure is located between two adjacent gate structures; the isolation structure includes a first portion located in the array region and a second portion located in the connection region, and along a third direction, the first portion includes a first insulating layer, a conductive layer, and a second insulating layer disposed in sequence, the first insulating layer is closer to the first surface than the second insulating layer, and the second portion includes at least an insulating layer. Forming a first dielectric portion; the first dielectric portion is located in the connection region, and along the first direction, the first dielectric portion is at least located at the end of the gate structure. The first direction and the second direction are parallel to the first surface and intersect, and the third direction is perpendicular to the first surface.

[0021] In some embodiments, forming a plurality of isolation structures and a plurality of gate structures includes: forming a plurality of initial isolation structures and a plurality of initial gate structures; the initial isolation structures include a first insulating layer, a conductive layer, and a second insulating layer stacked in sequence along the third direction, and one ends of two adjacent initial gate structures close to the first surface are connected to each other. Disconnecting two adjacent initial gate structures that are connected to each other from one side of the first surface. Forming a first gap; the first gap exposes at least the first insulating layer of the initial isolation structure and at least one of the two initial gate structures adjacent to the initial isolation structure. Forming a first opening in at least one of the two initial gate structures adjacent to the initial isolation structure through the first gap; the first opening truncates the initial gate structure along the first direction to form a gate structure. Forming a second opening in the initial isolation structure through the first gap; the second opening truncates the first insulating layer of the initial isolation structure along the first direction to form an isolation structure.

[0022] In some embodiments, forming the first gap includes: forming a first filling portion on one side of the initial gate structure close to the first surface, and the first filling portion is located at a position where the first opening is to be formed. Forming an opening on the first surface; the opening overlaps with the initial isolation structure along the third direction; in the second direction, the size of the opening is smaller than the size between two adjacent initial gate structures adjacent to the initial isolation structure. Forming the first gap through the opening; the first gap exposes the first insulating layer of the initial isolation structure, at least one of the two initial gate structures adjacent to the initial isolation structure, and the first filling portion.

[0023] In some embodiments, while forming the second opening in the initial isolation structure through the first gap, the first filling portion is removed.

[0024] In some embodiments, forming a plurality of isolation structures and a plurality of gate structures includes: forming a plurality of initial isolation structures and a plurality of initial gate structures, where the initial isolation structures include a first insulating layer, a conductive layer, and a second insulating layer that are sequentially stacked along a third direction; one ends of two adjacent initial gate structures close to a first surface are connected to each other. Disconnecting the two adjacent initial gate structures that are connected to each other from one side of the first surface to form a first gap; the first gap exposes at least the two adjacent initial gate structures. Forming a first opening in the two adjacent initial gate structures through the first gap; the first opening truncates the initial gate structures along a first direction to form gate structures. Forming a second opening in the initial isolation structures through the first gap; the second opening truncates the first insulating layer and the conductive layer of the initial isolation structures along the first direction to form isolation structures.

[0025] In another aspect, a storage system is provided. The storage system includes a memory and a controller. The memory includes the semiconductor structure as described in any of the above embodiments, and the controller is coupled to the memory to control the memory to store data.

[0026] In another aspect, an electronic device is provided, including the storage system as described above. BRIEF DESCRIPTION OF THE DRAWINGS

[0027] To more clearly illustrate the technical solutions in the present disclosure, the following briefly introduces the drawings required to be used in some embodiments of the present disclosure. Obviously, the drawings in the following description are only the drawings of some embodiments of the present disclosure, and those of ordinary skill in the art can also obtain other drawings based on these drawings. In addition, the drawings in the following description can be regarded as schematic diagrams, and are not limitations on the actual sizes of the products, the actual processes of the methods, the actual timings of the signals, etc. involved in the embodiments of the present disclosure.

[0028] Figure 1 is a block diagram of a storage system according to some embodiments;

[0029] Figure 2 is a block diagram of a storage system according to other embodiments;

[0030] Figure 3 is a three-dimensional structure diagram of a memory according to some embodiments;

[0031] Figure 4 is a cross-sectional view of a memory according to some embodiments;

[0032] Figure 5 is Figure 3 a structural diagram of a storage unit in

[0033] Figure 6 is Figure 5 an equivalent circuit diagram of the storage unit shown;

[0034] Figure 7 A top view of a semiconductor structure provided according to some embodiments;

[0035] Figure 8 is Figure 7 a cross-sectional view taken along section line A1-A2 in

[0036] Figure 9 is Figure 7 a cross-sectional view taken along section line B1-B2 in

[0037] Figure 10 is Figure 7 a cross-sectional view taken along section line C1-C2 in

[0038] Figure 11 is Figure 7 a cross-sectional view taken along section line D1-D2 in

[0039] Figure 12 Another top view of a semiconductor structure provided according to some embodiments;

[0040] Figure 13 Another top view of a semiconductor structure provided according to some embodiments;

[0041] Figure 14 Another top view of a semiconductor structure provided according to some embodiments;

[0042] Figure 15 Another top view of a semiconductor structure provided according to some embodiments;

[0043] Figure 16 is Figure 15 a cross-sectional view taken along section line A3-A4 in

[0044] Figure 17 A flowchart of a method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure;

[0045] Figures 18A to 30 Structural diagrams corresponding to respective steps in a method for manufacturing a semiconductor structure according to some embodiments;

[0046] Figures 31 to 33 Structural diagrams corresponding to respective steps in a method for manufacturing a semiconductor structure according to some embodiments. Detailed implementation manners

[0047] The following will clearly and completely describe the technical solutions in some embodiments of the present disclosure with reference to the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments provided in the present disclosure fall within the scope of protection of the present disclosure.

[0048] In the description of the present disclosure, it should be understood that the orientation or positional relationships indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. are based on the orientation or positional relationships shown in the drawings, and are only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and thus should not be construed as a limitation of the present disclosure.

[0049] Unless the context otherwise requires, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that a specific feature, structure, material or characteristic related to the embodiment or example is included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily referring to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any suitable manner.

[0050] Hereinafter, the terms "first" and "second" are only used for descriptive purposes and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. In the description of the embodiments of the present disclosure, unless otherwise specified, the meaning of "a plurality" is two or more.

[0051] When describing some embodiments, the expressions "coupled" and "connected" and their derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components have direct physical contact or electrical contact with each other. Another example is that when describing some embodiments, the term "coupled" may be used to indicate that two or more components have direct physical contact or electrical contact. However, the term "coupled" may also mean that two or more components do not have direct contact with each other, but still cooperate or interact with each other. The embodiments disclosed herein are not necessarily limited to the content herein.

[0052] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0053] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0054] As used herein, the use of "configured to" or "adapted to" means open and inclusive language, and does not exclude devices that are configured to or adapted to perform additional tasks or steps.

[0055] Additionally, the use of "based on" means open and inclusive because a process, step, calculation, or other action "based on" one or more of the stated conditions or values can, in practice, be based on additional conditions or values beyond those stated.

[0056] As used herein, "about", "substantially", or "approximately" includes the stated value and an average within an acceptable deviation range of a particular value, where the acceptable deviation range is determined by one of ordinary skill in the art in view of the measurement being discussed and the errors associated with the measurement of a particular quantity (i.e., the limitations of the measurement system).

[0057] In the context of the present disclosure, the meanings of "on", "above", and "over" should be construed in the broadest manner such that "on" not only means "directly on something", but also includes "on something" with intervening features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes "above" or "over" something with no intervening features or layers therebetween (i.e., directly on something).

[0058] Exemplary embodiments are described herein with reference to cross-sectional views and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Accordingly, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Thus, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations due to, for example, manufacturing. For example, an etched region shown as rectangular will typically have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0059] Some embodiments of the present disclosure provide an electronic device. The electronic device can be any one of a mobile phone (such as a cell phone), a desktop computer, a tablet computer, a laptop computer, a server, a vehicle-mounted device, a wearable device (such as a smart watch, a smart bracelet, smart glasses, etc.), a mobile power supply, a game console, a digital multimedia player, a printer, a positioning device, a smart sensor, a virtual reality (VR) device, an augmented reality (AR) device, etc.

[0060] The electronic device may include a storage system 1000, and may also include at least one of a central processing unit (CPU) and a cache.

[0061] Figure 1 FIG. is a block diagram of a storage system according to some embodiments. Figure 2 FIG. is a block diagram of a storage system according to other embodiments.

[0062] Some embodiments of the present disclosure also provide a storage system 1000. The storage system 1000 can be integrated into various types of storage devices, for example, included in the same package (such as a universal flash storage (UFS) package or an embedded multi media card (eMMC) package). That is, the storage system 1000 can be applied to and packaged into different types of the above-mentioned electronic devices.

[0063] The storage system 1000 includes a controller 200 and a memory 100. The controller 200 is coupled to the memory 100 to control the memory 100 to store data.

[0064] In some embodiments, referring to Figure 1 , the storage system 1000 includes a controller 200 and a memory 100. The storage system 1000 can be integrated into a memory card. Among them, the memory card can be any one of a PC card (PCMCIA, Personal Computer Memory Card International Association), a compact flash (CF) card, a smart media (SM) card, a memory stick, a multimedia card (MMC), a secure digital memory card (SD) card, and a UFS.

[0065] In still other embodiments, referring to Figure 2, the storage system 1000 includes a controller 200 and a plurality of memories 100, and the storage system 1000 is integrated into a Solid State Drive (SSD).

[0066] For the storage system 1000, in some embodiments, the controller 200 is configured to operate in a low-duty-cycle environment, for example, SD cards, CF cards, Universal Serial Bus (USB) flash drives, or other media used in electronic devices such as personal calculators, digital cameras, mobile phones, etc.

[0067] In other embodiments, the controller 200 is configured to operate in a high-duty-cycle environment SSD or eMMC, and the SSD or eMMC is used as a data storage for mobile devices such as smart phones, tablets, laptops, etc. and enterprise storage arrays.

[0068] In some embodiments, the controller 200 can also be configured to control the operations of the memory 100, such as read, erase, and program operations.

[0069] In some embodiments, the controller 200 can also be configured to manage various functions regarding the data stored in or to be stored in the memory 100, including at least one of bad block management, garbage collection, logical-to-physical address translation, wear leveling.

[0070] In some embodiments, the controller 200 is also configured to process the error correction code for the data read from or written to the memory 100. Of course, the controller 200 can also perform any other suitable functions, such as formatting the memory 100.

[0071] In some embodiments, the controller 200 can be configured to manage the data stored in the memory 100 and communicate with external devices (such as a host). For example, the controller 200 can communicate with external devices through at least one of various interface protocols. It should be noted that the interface protocols include at least one of USB protocol, MMC protocol, Peripheral Component Interconnect (PCI) protocol, PCI Express (PCI-E) protocol, Advanced Technology Attachment (ATA) protocol, Serial ATA protocol, Parallel ATA protocol, Small Computer System Interface (SCSI) protocol, Enhanced Small Disk Interface (ESDI) protocol, Integrated Drive Electronics (IDE) protocol, Firewire protocol.

[0072] Figure 3 It is a three-dimensional structure diagram of a memory provided according to some embodiments. Figure 4 It is a cross-sectional view of a memory provided according to some embodiments.

[0073] It should be noted that, for the convenience of the following description, an XYZ coordinate system is established. In Figure 3 and Figure 4 , the memory 100 extends in the X-Y plane, and the first direction X and the second direction Y are, for example, two orthogonal directions in the plane where the memory 100 is located (for example, the plane where the source layer SL is located): the first direction X is, for example, the extending direction of the word line WL, and the second direction Y is, for example, the extending direction of the bit line BL. The third direction Z is perpendicular to the plane where the memory 100 is located, that is, perpendicular to the X-Y plane.

[0074] Refer to Figure 3 and Figure 4 , some embodiments of the present disclosure provide a memory 100. The memory 100 may include a semiconductor device 10. The memory 100 may further include a peripheral device 20 coupled to the semiconductor device 10, and the peripheral device 20 may be disposed on one side of the semiconductor device 10.

[0075] The semiconductor device 10 may include a memory cell array 11 and a source layer SL. The memory cell array 11 is coupled to the peripheral device 20, the source layer SL is disposed on the side of the memory cell array 11 away from the peripheral device 20, and the source layer SL is coupled to the memory cell array 11.

[0076] The source layer SL may include a semiconductor material, and the semiconductor material is, for example, single-crystalline silicon, single-crystalline germanium, III-V group compound semiconductor material, II-VI group compound semiconductor material, and other suitable semiconductor materials. The source layer SL may be partially or fully doped. Exemplarily, the source layer SL may include a doped region doped with a p-type dopant. The source layer SL may further include an undoped region.

[0077] The memory cell array 11 may include a plurality of memory cells MC arranged in an array along the first direction X and the second direction Y. It should be noted that Figure 3 and Figure 4 the number of the memory cells MC shown is only illustrative, and the embodiments of the present disclosure do not limit the number of the memory cells MC.

[0078] Figure 5 For Figure 3 is a structural diagram of a memory cell. Figure 6 For Figure 5 is an equivalent circuit diagram of the memory cell shown.

[0079] Refer to Figure 5 and Figure 6, the memory cell MC includes a first transistor T1 and a capacitor C. A first terminal of the first transistor T1 is connected to the bit line BL, a second terminal of the first transistor T1 is connected to one plate of the capacitor C, and the other plate of the capacitor C may be connected to the source layer SL. The gate of the first transistor T1 is connected to the word line WL. In this way, a voltage can be applied through the word line WL to control the conduction or cutoff of the first transistor T1, and when the first transistor T1 is conducting, the bit line BL performs a read or write operation on the first transistor T1.

[0080] Continue to refer to Figure 4 , the semiconductor device 10 may further include an array interconnect layer 12. The array interconnect layer 12 may be coupled to the memory cell MC. Among them, the array interconnect layer 12 may include the word line WL and the bit line BL. The word line WL may be coupled to the gate of the first transistor T1 in at least one memory cell MC. The bit line BL may be coupled to the first terminal of the first transistor T1 in at least one memory cell MC.

[0081] In some examples, the array interconnect layer 12 may include one or more first interconnect conductor layers 201, one or more first interlayer insulating layers 202, and a plurality of first contacts 203 insulated from each other by these first interlayer insulating layers 202.

[0082] Among them, the first interconnect conductor layer 201 may include a plurality of bit lines BL and word lines WL (refer to Figure 3 ), etc. Different first interconnect conductor layers 201 may be coupled through the first contacts 203. The plurality of first contacts 203 may include, for example, bit line contacts and / or word line contacts. The bit line contacts are coupled to the bit line BL, and the word line contacts are coupled to the word line WL.

[0083] The materials of the first interconnect conductor layer 201 and the first contacts 203 may be conductive materials, such as one or a combination of tungsten, cobalt, copper, aluminum, and metal silicides, and may also be other suitable materials. The material of the first interlayer insulating layer 202 is an insulating material, such as one or a combination of silicon oxide, silicon nitride, and high-k insulating materials, and may also be other suitable materials.

[0084] Continue to refer to Figure 4, the peripheral device 20 may be disposed, for example, on a side of the memory cell array 11 away from the source layer SL. The peripheral device 20 may include a peripheral circuit configured to control and sense the array devices. The peripheral circuit may be any suitable digital, analog, and / or mixed-signal control and sensing circuit for supporting the operation (or work) of the array devices, including but not limited to page buffers, decoders (e.g., row decoders and column decoders), sense amplifiers, drivers (e.g., word line drivers), charge pumps, current or voltage references, or any active or passive components of the circuit (e.g., transistors, diodes, resistors, or capacitors). The peripheral circuit may also include any other circuits compatible with advanced logic processes, including logic circuits (e.g., processors and programmable logic devices (PLD)) or memory circuits (e.g., static random-access memory (SRAM)).

[0085] Specifically, referring further to Figure 4 , the peripheral device 20 may include a substrate 21, a second transistor T2 disposed on the substrate 21, and a peripheral interconnect layer 22 disposed on the substrate 21. The peripheral circuit may include the second transistor T2.

[0086] Wherein, the material of the substrate 21 may be single-crystalline silicon or other suitable materials, such as silicon germanium, germanium, or silicon-on-insulator thin film.

[0087] The peripheral interconnect layer 22 is coupled to the second transistor T2 to enable the transmission of electrical signals between the transistor T2 and the peripheral interconnect layer 22. The peripheral interconnect layer 22 may include one or more second interconnect conductor layers 221, one or more second interlayer insulation layers 222, and a plurality of second contacts 223 insulated from each other by these second interlayer insulation layers 222. Among them, different second interconnect conductor layers 221 may be coupled through the second contacts 223. The materials of the second interconnect conductor layers 221 and the second contacts 223 may be conductive materials, and the material of the second interlayer insulation layer 222 is an insulating material. The conductive materials and insulating materials can be referred to the above description and will not be elaborated here.

[0088] The peripheral interconnect layer 22 may be coupled to the array interconnect layer 12 so that the semiconductor device 10 and the peripheral device 20 can be coupled. Specifically, since the peripheral interconnect layer 22 is coupled to the array interconnect layer 12, the peripheral circuit in the peripheral device 20 can be coupled to the memory cell MC in the semiconductor device 10 to enable the transmission of electrical signals between the peripheral circuit and the memory cell MC.

[0089] In some possible implementation manners, the peripheral interconnection layer 22 is bonded to the array interconnection layer 12, such that the second contact 223 in the peripheral interconnection layer 22 contacts the corresponding first contact 203 in the array interconnection layer 12, so that the peripheral circuit in the peripheral device 20 can be coupled to the memory cell MC in the semiconductor device 10. Wherein, the surface where the peripheral interconnection layer 22 and the array interconnection layer 12 contact can be referred to as the bonding surface S.

[0090] Some embodiments of the present disclosure provide a semiconductor structure 300. The memory 100 includes this semiconductor structure 300. Exemplarily, the semiconductor structure 300 can be the memory 100. For example, the semiconductor structure 300 includes a semiconductor device 10 and a peripheral device 20. Exemplarily, the semiconductor structure 300 can also be a part of the memory 100. For example, the semiconductor structure 300 is the semiconductor device 10 in the memory 100. The embodiments of the present disclosure do not make specific limitations thereto.

[0091] The structure of the semiconductor structure 300 will be described below.

[0092] Figure 7 Is a top view of a semiconductor structure provided according to some embodiments. Figure 8 Is Figure 7 A cross-sectional view taken along the section line A1-A2 in

[0093] Some embodiments of the present disclosure provide a semiconductor structure 300.

[0094] Refer to Figure 7 , the semiconductor structure 300 has an array region AA and a connection region BB. It can be understood that the array region AA is the region where the memory cell array 11 is located, and the connection region BB is located on at least one side (such as one side, or around) of the array region AA. Refer to Figure 8 , the semiconductor structure 300 includes a relatively arranged first surface 111 and a second surface 112. Exemplarily, the first surface 111 and the second surface 112 are parallel to each other.

[0095] Continue to refer to Figure 7 , the semiconductor structure 300 includes a plurality of isolation structures 120 and a plurality of gate structures 130. The isolation structures 120 and the gate structures 130 both extend along the first direction X. Exemplarily, the gate structures 130 are located in the connection regions BB on both sides (such as the left and right sides) of the array region AA, and the isolation structures 120 are located in the connection regions BB on both sides (such as the left and right sides) of the array region AA.

[0096] Along the second direction Y, an isolation structure 120 is located between two adjacent gate structures 130. For the convenience of the following description, any one of the plurality of isolation structures 120 is referred to as a selected isolation structure 120a, and the two gate structures 130 adjacent to the selected isolation structure 120a are respectively referred to as a first gate structure 131 and a second gate structure 132. The gate structure adjacent to the first gate structure 131 and located on the side of the first gate structure 131 away from the selected isolation structure 120a is referred to as a third gate structure 133, and the gate structure adjacent to the second gate structure 132 and located on the side of the second gate structure 132 away from the selected isolation structure 120a is referred to as a fourth gate structure 134. The isolation structure adjacent to the selected isolation structure 120a is a second isolation structure 120b, and the gate structure adjacent to the second isolation structure 120b and located on the side of the second isolation structure 120b away from the selected isolation structure 120a is a fifth gate structure 135.

[0097] It should be noted that Figure 7 the number of the gate structures 130 and the isolation structures 120 shown in Figure 7 is only illustrative, and the embodiments of the present disclosure are not limited thereto.

[0098] In some embodiments, the semiconductor structure 300 further includes a plurality of bit lines 140. Continuing to refer to Figure 7 , the plurality of bit lines 140 are arranged at intervals in the first direction X. The bit lines 140 extend along the second direction Y. Exemplarily, the bit lines 140 are located in the array region AA and the connection regions BB on the upper and lower sides of the array region AA. Among them, the connection regions BB on the upper and lower sides of the array region AA are not shown in Figure 7 .

[0099] Each bit line 140 is separated into a plurality of active columns 141 by a plurality of gate structures 130 and a plurality of isolation structures 120 arranged along the second direction Y. Exemplarily, the portion of the bit line 140 between the first gate structure 131 and the selected isolation structure 120a is an active column 141, and the portion of the bit line 140 between the selected isolation structure 120a and the second gate structure 132 is an active column 141. The plurality of active columns 141 of the plurality of bit lines 140 are arranged in an array in the first direction X and the second direction Y. In the third direction Z, the bit line 140 extends along the third direction Z and is located between the first surface 111 and the second surface 112. Specifically, the active column 141 is located between the first surface 111 and the second surface 112, and the active column 141 extends along the third direction Z.

[0100] Continuing to refer toFigure 5 Along the third direction Z, the active column 141 includes the first pole, channel, and second pole of the first transistor T1. The first pole and the second pole are the two opposite ends of the active column 141 in the third direction Z, and the channel is located between the first pole and the second pole. For the connection of the first pole and the second pole, reference can be made to the description of the memory cell MC in the foregoing text, which will not be elaborated herein.

[0101] The material of the channel includes semiconductor material, and the materials of the first pole and the second pole may include semiconductor material doped with P-type dopant or N-type dopant. The semiconductor material is, for example, single-crystalline silicon, polycrystalline silicon, single-crystalline germanium, III-V compound semiconductor material, II-VI compound semiconductor material, and other suitable semiconductor materials. The P-type dopant includes boron or gallium. The N-type dopant includes phosphorus or arsenic.

[0102] Continuing to refer to Figure 8 , the gate structure 130 extends along the third direction Z and is located between the first surface 111 and the second surface 112. Exemplarily, the gate structure 130 includes a gate layer and a gate dielectric layer. The gate layer is disposed on the sidewall of the active column 141 to form the gate G of the first transistor T1 (as Figure 5 shown). The gate dielectric layer is disposed between the gate layer and the corresponding active column 141 to insulate the gate layer from the active column 141. The material of the gate layer may be a conductive material, such as titanium nitride, tungsten, and the material of the gate dielectric layer may be an insulating material. For the conductive material and the insulating material, reference can be made to the description in the foregoing text, which will not be elaborated herein.

[0103] It should be noted that the orthographic projection of the channel of the active column 141 on the first reference plane is within the range of the orthographic projection of the gate layer on the first reference plane, so that the first pole and the second pole located at both ends of the channel can be turned on or off under the control of the voltage of the gate layer. The first reference plane is perpendicular to the second direction Y. Based on this, the gate layer and the corresponding active column 141 form the first transistor T1. When the voltage received by the gate layer from the word line WL is greater than the threshold voltage of the first transistor T1, the first transistor T1 is turned on. When the voltage received by the gate layer from the word line WL is less than or equal to the threshold voltage of the first transistor T1, the first transistor T1 is turned off.

[0104] Figure 9 is Figure 7 the cross-sectional view taken along the section line B1-B2 in Figure 10 is Figure 7 the cross-sectional view taken along the section line C1-C2 in

[0105] Continuing to refer to Figure 7 and Figure 8, the isolation structure 120 is located between the first surface 111 and the second surface 112 along the third direction Z. The isolation structure 120 includes a first portion P1 located in the array region AA and a second portion P2 located in the connection region BB.

[0106] See Figure 9 , the first portion P1 includes a first insulating layer 121a, a conductive layer 122a, and a second insulating layer 123a arranged in sequence along the third direction Z. The first insulating layer 121a is closer to the first surface 111 than the second insulating layer 123a, and the conductive layer 122a is located between the first insulating layer 121a and the second insulating layer 123a. The first insulating layer 121a and the second insulating layer 123a function to protect the conductive layer 122a, preventing the conductive layer 122a in the array region AA from being directly exposed, generating leakage current, and affecting signal transmission. An insulating layer is provided between the first portion P1 and the active pillar 141 to prevent the isolation structure 120 from being directly connected to the active pillar 141 and affecting signal transmission.

[0107] The second portion P2 includes at least the second insulating layer 123b. The second insulating layer 123b of the second portion P2 is the same layer as the second insulating layer 123a of the first portion P1. Exemplarily, see Figure 10 , the second portion P2 includes a conductive layer 122b and a second insulating layer 123b arranged in sequence along the third direction Z. The conductive layer 122b is closer to the first surface 111 than the second insulating layer 123b.

[0108] Continue to see Figure 9 , the gate dielectric layer is disposed between the gate layer and the corresponding active pillar 141 to prevent the gate layer from being directly connected to the active pillar 141 and affecting signal transmission.

[0109] Figure 11 For Figure 7 the cross-sectional view taken along the section line D1-D2 in

[0110] In some embodiments, continue to see Figure 7 , the isolation structure 120 may further include a third portion P3. The third portion P3 is located in the connection region BB. Along the first direction X, the third portion P3 may be located between the first portion P1 and the second portion P2, and the third portion P3 may also be located on the side of the first portion P1 away from the second portion P2.

[0111] See Figure 11, the third part P3 includes a first insulating layer 121c, a conductive layer 122c, and a second insulating layer 123c arranged in sequence along the third direction Z. The first insulating layer 121c of the third part P3 and the first insulating layer 121a of the first part P1 are the same layer, the conductive layer 122c of the third part P3 and the conductive layer 122a of the first part P1 are the same layer, and the second insulating layer 123c of the third part P3 and the second insulating layer 123a of the first part P1 are the same layer.

[0112] An insulating layer is provided between the third part P3 and the active pillar 141, and the material of the insulating layer can be the same as that of the dielectric structure 110. In some other implementation manners, the material of the insulating layer can also be different from that of the dielectric structure 110.

[0113] Continue to refer to Figure 7 , the semiconductor structure 300 further includes a first dielectric portion 150. The first dielectric portion 150 is located in the connection region BB. Continue to refer to Figure 8 , the first dielectric portion 150 extends into the semiconductor structure 300 from the first surface 111 along the third direction Z. Along the first direction X, the first dielectric portion 150 is at least located at the end of the gate structure 130, wherein the portion of the first dielectric portion 150 located at the end of the gate structure 130 is the first sub-portion 151. Exemplarily, in the positive projection onto the X-Y plane, a part of the first dielectric portion 150 is located at the end of the gate structure 130, and another part of the first dielectric portion 150 can also overlap with the isolation structure 120.

[0114] That is to say, the first dielectric portion 150 covers at least the gate structure 130 in the second direction Y. For example, the first dielectric portion 150 covers the gate structure 130 and can also cover the isolation structure 120 adjacent to the gate structure 130. In this way, the size of the first dielectric portion 150 in the second direction Y is greater than or equal to the size of the gate structure 130 in the second direction Y, and the size of the first dielectric portion 150 in the second direction Y increases, thereby reducing the process difficulty of forming the first dielectric portion 150 and improving the product production efficiency. The material of the first dielectric portion 150 can be an insulating material, and the insulating material can refer to the description above and will not be elaborated here.

[0115] In some embodiments, during the preparation process of the semiconductor structure 300, two initial gate structures and an initial isolation structure with interconnected bottoms are first formed, where the bottom here refers to the end of the initial gate structure close to the first surface 111. Then, the bottoms of the two initial gate structures are disconnected from the side of the first surface 111, and then a part of the initial gate structure and a part of the initial isolation structure are removed from the side of the second surface 112 to truncate the initial gate structure and the initial isolation structure. Then, a first dielectric portion extending from the second surface 112 into the semiconductor structure 300 is formed from the side of the second surface 112.

[0116] That is to say, two initially connected gate structures at the bottom are disconnected on one side of the first surface 111, and the initially formed gate structure and the initially formed isolation structure are truncated on one side of the second surface, forming a first dielectric portion on one side of the second surface 112. After the two initially connected gate structures at the bottom and the initially formed isolation structure are formed, the preparation process of the semiconductor structure 300 is not concentrated on the same side of the semiconductor structure 300 on one side of the first surface 111 and on one side of the second surface 112 respectively. In this way, the preparation process of the semiconductor structure 300 is converted on one side of the first surface 111 and on one side of the second surface 112, and it is urgent to optimize the preparation process to simplify the process flow.

[0117] In an embodiment of the present disclosure, a part of the isolation structure 120 and the gate structure 130 are truncated by a first dielectric portion 150 extending into the semiconductor structure 300 from one side of the first surface 111. After the two initially connected gate structures at the bottom and the initially formed isolation structure are formed, the preparation process of the semiconductor structure 300 can be concentrated on the same side of the semiconductor structure 300. For example, two initially connected gate structures at the bottom are disconnected on one side of the first surface 111, and the initially formed gate structure and the initially formed isolation structure are truncated on one side of the first surface 111, forming a first dielectric portion 150 on one side of the first surface 111. In this way, the process flow can be simplified and the preparation efficiency of the semiconductor structure 300 can be improved.

[0118] In some embodiments, continue to refer to Figure 8 , the semiconductor structure 300 further includes a plurality of first lead-out portions 160, and the first lead-out portions 160 are connected to the isolation structure 120. Specifically, the first lead-out portions 160 extend into the semiconductor structure 300 from the first surface 111, and one end of the first lead-out portion 160 close to the second insulating layer 123 is connected to the conductive layer 122 of the isolation structure 120. Exemplarily, along the first direction X, the dimension d1 of one end of the first lead-out portion 160 close to the second insulating layer 123 is smaller than the dimension d2 of the end of the first lead-out portion 160 away from the second insulating layer 123. The material of the first lead-out portion 160 is a conductive material, and the conductive material can refer to the above description and will not be elaborated here.

[0119] Continue to refer to Figure 7, along the second direction Y, the first lead-out portion 160 overlaps with the first sub-portion 151. Specifically, taking the X-Z plane as the second reference plane, in the positive projection onto the second reference plane, the first lead-out portion 160 connected to the isolation structure 120 and the first sub-portion 151 in the gate structure 130 adjacent to the isolation structure 120 overlap. Exemplarily, it is selected that the first lead-out portion 160 connected to the isolation structure 120a and the first sub-portion 151 in the first gate structure 131 overlap in the positive projection onto the second reference plane. The overlap between the first lead-out portion 160 and the first sub-portion 151 can increase the process window of the first lead-out portion 160 on the premise of ensuring that there is no short circuit between the first lead-out portion 160 and the adjacent gate structure 130. Among them, the size of the first lead-out portion 160 in the second direction Y can be greater than the sum of the distance between the selected isolation structure 120a and the first gate structure 131 and the size of the selected isolation structure 120a, so as to increase the area occupied by the first lead-out portion 160 in the X-Y plane.

[0120] In some embodiments, referring further to Figure 8 , the semiconductor structure 300 further includes a plurality of second lead-out portions 170. The second lead-out portions 170 are connected to the gate structure 130. Specifically, the second lead-out portions 170 extend from the first surface 111 into the semiconductor structure 300, and one end of the second lead-out portion 170 close to the second insulating layer 123 is connected to the gate structure 130. Exemplarily, along the first direction X, the size d3 of one end of the second lead-out portion 170 close to the second insulating layer 123 is smaller than the size d4 of the end of the second lead-out portion 170 far from the second insulating layer 123. The material of the second lead-out portion 170 is a conductive material, and the conductive material can be referred to the above description and will not be elaborated here. The materials of the first lead-out portion 160 and the second lead-out portion 170 can be the same or different, and the embodiments of the present disclosure do not limit this.

[0121] Both the first lead-out portion 160 and the second lead-out portion 170 are led out from one side of the first surface 111, concentrating the lead-out portions on the same side of the semiconductor structure 300, which is convenient for connection. And in the process of forming the lead-out portions, the first lead-out portion 160 and the second lead-out portion 170 can be formed simultaneously on the same side of the semiconductor structure 300, which is beneficial to simplifying the manufacturing process and improving the product manufacturing efficiency. Compared with the lead-out portions being led out from both sides of the semiconductor structure 300 respectively, leading out from the same side is beneficial to reducing the space occupied by the leads, thereby reducing the size of the semiconductor structure 300 in the third direction Z, which is beneficial to the miniaturization of the semiconductor structure 300.

[0122] In some embodiments, referring further to Figure 7, along the second direction Y, the second lead-out portion 170 connected to the first gate structure 131 overlaps with the first sub-portion 151 in the third gate structure 133. Specifically, in the positive projection onto the second reference plane (X-Z plane), the second lead-out portion 170 connected to the first gate structure 131 and the first sub-portion 151 in the third gate structure 133 overlap. In this way, the settable space of the second lead-out portion 170 is increased, and the dimension of the second lead-out portion 170 in the second direction Y can be greater than the distance between the first gate structure 131 and the third gate structure 133 and the dimension of the third gate structure 133, thereby increasing the area occupied by the second lead-out portion 170 in the X-Y plane, providing a wider process margin / process error for forming the second lead-out portion 170, being beneficial to increasing the process window of the second lead-out portion 170 connected to the first gate structure 131, and preventing short circuits caused by the connection between the second lead-out portions 170 connected to the adjacent first gate structure 131 and the third gate structure 133.

[0123] In some embodiments, continue to refer to Figure 7 , along the second direction Y, the second lead-out portion 170 connected to the third gate structure 133 overlaps with the first sub-portion 151 in the first gate structure 131. Specifically, in the positive projection onto the second reference plane, the second lead-out portion 170 connected to the third gate structure 133 and the first sub-portion 151 in the first gate structure 131 overlap. In this way, the settable space of the second lead-out portion 170 is increased, and the dimension of the second lead-out portion 170 in the second direction Y can be greater than the sum of the distance between the first gate structure 131 and the third gate structure 133 and the dimension of the first gate structure 131, thereby increasing the area occupied by the second lead-out portion 170 in the X-Y plane, providing a wider process margin / process error for forming the second lead-out portion 170, being beneficial to increasing the process window of the second lead-out portion 170 connected to the third gate structure 133, and preventing short circuits caused by the connection between the second lead-out portions 170 connected to the adjacent first gate structure 131 and the third gate structure 133.

[0124] In some embodiments, continue to refer to Figure 7, the first lead-out portions 160 connected to the plurality of isolation structures 120 are alternately arranged on both sides of the array area AA. Exemplarily, the first lead-out portions 160 connected to the selected isolation structure 120a and the second isolation structure 120b are located on both sides of the array area AA, and when the second lead-out portion 170 connected to the fourth gate structure 134 and the fifth gate structure 135 and the first lead-out portion 160 connected to the selected isolation structure 120a are located on the same side of the array area AA, the second lead-out portion 170 connected to the fourth gate structure 134 can be offset to a side away from the second isolation structure 120b, and the second lead-out portion 170 connected to the fifth gate structure 135 can be offset to a side away from the second isolation structure 120b, so as to prevent the second lead-out portion 170 connected to the fourth gate structure 134 and the fifth gate structure 135 from being connected to the first lead-out portion 160 connected to the second isolation structure 120b, and increase the size of the second lead-out portion 170 connected to the fourth gate structure 134 and the fifth gate structure 135 in the second direction Y.

[0125] In some embodiments, see Figure 12 , the first lead-out portions 160 connected to the plurality of isolation structures 120 may also be located on the same side of the array area AA, and the second lead-out portions 170 connected to the gate structures 130 adjacent to the isolation structures 120 may be located on the other side of the array area AA. Since the gate structures 130 are disposed between adjacent isolation structures 120, the second lead-out portions 170 connected to the gate structures 130 are always spaced from the first lead-out portions 160 connected to the isolation structures 120, thereby preventing the first lead-out portions 160 and the second lead-out portions 170 from being connected.

[0126] In some embodiments, see Figure 10 , the second portion P2 of the isolation structure 120 includes a conductive layer 122b and a second insulating layer 123b sequentially arranged along the third direction Z. Exemplarily, the conductive layers 122 of the first portion P1, the second portion P2, and the third portion P3 are the same layer, and the second insulating layers 123 of the first portion P1, the second portion P2, and the third portion P3 are the same layer. The first insulating layer 121 is not arranged on the side of the conductive layer 122b of the second portion P2 away from the second insulating layer 123b.

[0127] Continue to see Figure 7 , Figure 10 and Figure 11, along the first direction X, the first dielectric portion 150 is located at the end of the gate structure 130 and the first insulating layer 121, wherein the portion of the first dielectric portion 150 located at the end of the first insulating layer 121 is the second sub-portion 152, and the second sub-portion 152 is located on the side of the conductive layer 122 away from the second insulating layer 123. That is to say, the second sub-portion 152 is closer to the first surface 111 than the conductive layer 122, and the second sub-portion 152 truncates the first insulating layer 121. Exemplarily, the first sub-portion 151 is located at the end of the first gate structure 131, and, continue to refer to Figure 7 and Figure 10 , the second sub-portion 152 is located at the end of the first insulating layer 121 of the selected isolation structure 120a.

[0128] Along the third direction Z, the first dielectric portion 150 overlaps with the second portion P2. Specifically, the first dielectric portion 150 truncates the first insulating layer 121 of the isolation structure 120 from the side of the first surface 111, and the positive projection of the first dielectric portion 150 on the X-Y plane overlaps with the positive projection of the second portion P2 on the X-Y plane. Exemplarily, continue to refer to Figure 7 , in the positive projection on the X-Y plane, the first dielectric portion 150 covers the end of the gate structure 130, the first dielectric portion 150 also covers the second portion P2 of the isolation structure 120, and the outer contour of the second portion P2 is located within the outer contour of the first dielectric portion 150, or along the first direction X, the outer contour of the second portion P2 coincides with the outer contour of the first dielectric portion 150.

[0129] In this way, during the preparation process of the semiconductor structure 300, before forming the first dielectric portion 150, the gate structure 130 and the first insulating layer 121 of the isolation structure 120 can be truncated only to form a gap for forming the first dielectric portion 150, and it is not necessary to truncate the first insulating layer 121, the conductive layer 122 and the second insulating layer 123 of the isolation structure 120, which can simplify the preparation process.

[0130] The first dielectric portion 150 covers the gate structure 130 and the isolation structure 120 along the second direction Y at the same time. When forming a gap for forming the first dielectric portion 150, a part of the gate structure 130 and a part of the first insulating layer 121 can be removed at the same time to increase the size of the gap along the second direction Y. The larger the size of the gap along the second direction Y, the smaller the process difficulty of forming the gap, thereby reducing the process difficulty of forming the first dielectric portion 150, and further improving the production efficiency of the product. In some embodiments, continue to refer to Figure 7 and Figure 10, along the third direction Z, the first lead-out portion 160 overlaps with the first dielectric portion 150. Specifically, the first lead-out portion 160 penetrates the second sub-portion 152 along the third direction Z and is connected to the conductive layer 122. Exemplarily, the first lead-out portion 160 connected to the isolation structure 120a penetrates the second sub-portion 152 and is connected to the conductive layer 122b. Since the first dielectric portion 150 overlaps with the second part P2, when forming the first lead-out portion 160, a connection hole is directly formed in the area where the first dielectric portion 150 is located, and a conductive material is filled in the connection hole to form the first lead-out portion 160, which increases the process window of the first lead-out portion 160 and facilitates the preparation of the semiconductor structure 300.

[0131] In some embodiments, along the second direction Y, at least one first sub-portion 151 in the two gate structures 130 adjacent to the isolation structure 120 overlaps with the second sub-portion 152 in the isolation structure 120. Specifically, continue to refer to Figure 7 , along the second direction Y, the first sub-portion 151 in the first gate structure 131 and / or the second gate structure 132 overlaps with the second sub-portion 152 in the selected isolation structure 120a. Exemplarily, in the positive projection onto the second reference plane (X-Z plane), the first sub-portion 151 in at least one of the first gate structure 131 and the second gate structure 132 overlaps with the second sub-portion 152 in the selected isolation structure 120a. For example, the second sub-portion 152 in the selected isolation structure 120a only overlaps with the first sub-portion 151 in one of the first gate structure 131 and the second gate structure 132, and does not overlap with the other. In this way, the first dielectric portion 150 covers the isolation structure 120, a gate structure 130 adjacent to the isolation structure 120, and the gap between the isolation structure 120 and the gate structure 130 in the X-Y plane, thereby increasing the size of the first dielectric portion 150 in the second direction Y. Another example is that the second sub-portion 152 in the selected isolation structure 120a overlaps with the first sub-portion 151 in both the first gate structure 131 and the second gate structure 132 at the same time. In this way, the first dielectric portion 150 covers the isolation structure 120, two gate structures 130 adjacent to the isolation structure 120, and the gaps between the isolation structure 120 and the two gate structures 130 in the X-Y plane, thereby increasing the size of the first dielectric portion 150 in the second direction Y.

[0132] The size of the first dielectric portion 150 increases, that is, the process window of the first dielectric portion 150 increases, which is beneficial to the formation of the first dielectric portion 150. The first lead portion 160 connected to the selected isolation structure 120a may overlap with the first gate structure 131 and / or the second gate structure 132 in the X-Z plane. In this way, the size of the first lead portion 160 connected to the selected isolation structure 120a in the second direction Y may be greater than the sum of the distance between the selected isolation structure 120a and at least one adjacent gate structure 130 and the size of the selected isolation structure 120a, thereby increasing the area occupied by the first lead portion 160 in the X-Y plane and facilitating connection.

[0133] Figure 12 Another top view of a semiconductor structure provided according to some embodiments. Figure 13 Another top view of a semiconductor structure provided according to some embodiments. Figure 12 and Figure 13 Only the part of the first dielectric portion 150 located in the gate structure 130 and the isolation structure 120 is shown.

[0134] In some embodiments, referring to Figure 7 、 Figure 12 and Figure 13 along the second direction Y, the first sub-portion 151 in the first gate structure 131 and the first sub-portion 151 in the second gate structure 132 both overlap with the second sub-portion 152 in the isolation structure 120. Specifically, in the positive projection onto the second reference plane, the first sub-portion 151 in the first gate structure 131 and the second gate structure 132 overlap with the second sub-portion 152 in the selected isolation structure 120a.

[0135] Exemplarily, continuing to refer to Figure 7 on the same side of the array region AA, the first sub-portion 151 in the first gate structure 131 and the second gate structure 132 overlaps with the second sub-portion 152 in the selected isolation structure 120a, where the first sub-portion 151 is located at one end of the gate structure 130, that is, one end of the first gate structure 131 is located in the connection region BB. Another exemplarily, referring to Figure 12 and Figure 13 on the same side of the array region AA, the first sub-portion 151 in the first gate structure 131 overlaps with the second sub-portion 152 in the selected isolation structure 120a, and the first sub-portion 151 in the second gate structure 132 overlaps with the second sub-portion 152 in the selected isolation structure 120a. Wherein, along the first direction X, one end of the first gate structure 131 is located in the connection region BB on one side of the array region AA, and the other end is located in the connection region BB on the other side of the array region AA.

[0136] In this way, the first lead-out portion 160 connected to the selected isolation structure 120a can overlap with the first gate structure 131 and the second gate structure 132 in the X-Z plane, and the dimension of the first lead-out portion 160 connected to the selected isolation structure 120a in the second direction Y can be maximally greater than the sum of the distances between the first gate structure 131 and the second gate structure 132, thereby further increasing the area occupied by the first lead-out portion 160 in the X-Y plane and facilitating connection.

[0137] In some embodiments, referring further to Figure 7 , the first sub-portion 151 in the third gate structure 133 and the first sub-portion 151 in the first gate structure 131 are located on both sides of the array region AA. That is to say, the first sub-portion 151 in the third gate structure 133 and the first sub-portion 151 in the first gate structure 131 have no overlap in the second direction Y. In this way, the second lead-out portions 170 respectively connected to the third gate structure 133 and the first gate structure 131 are located on both sides of the array region AA. The available setting space for the second lead-out portion 170 connected to the third gate structure 133 is increased, providing a wider process margin for forming the second lead-out portion 170. The dimension of the second lead-out portion 170 connected to the third gate structure 133 in the second direction Y can be greater than the sum of the distance between the first gate structure 131 and the third gate structure 133 and the dimension of the third gate structure 133, and the dimension of the second lead-out portion 170 connected to the first gate structure 131 in the second direction Y can be greater than the sum of the distance between the first gate structure 131 and the third gate structure 133 and the dimension of the first gate structure 131, thereby further increasing the area occupied by the second lead-out portions 170 connected to the first gate structure 131 and the third gate structure 133 in the X-Y plane and facilitating connection.

[0138] Referring further to Figure 7, the first sub - part 151 in the fourth gate structure 134 and the first sub - part 151 in the second gate structure 132 are respectively located on both sides of the array region AA. That is to say, the first sub - part 151 in the fourth gate structure 134 and the first sub - part 151 in the second gate structure 132 have no overlap along the second direction Y. In this way, the second lead - out parts 170 respectively connected to the fourth gate structure 134 and the second gate structure 132 are located on both sides of the array region AA. The available space for the second lead - out part 170 connected to the fourth gate structure 134 increases, providing a wider process margin for forming the second lead - out part 170. The dimension of the second lead - out part 170 connected to the fourth gate structure 134 in the second direction Y can be greater than the sum of the distance between the second gate structure 132 and the fourth gate structure 134 and the dimension of the fourth gate structure 134. The dimension of the second lead - out part 170 connected to the second gate structure 132 in the second direction Y can be greater than the sum of the distance between the second gate structure 132 and the fourth gate structure 134 and the dimension of the second gate structure 132, thereby further increasing the area occupied by the second lead - out parts 170 connected to the second gate structure 132 and the fourth gate structure 134 in the X - Y plane, which is convenient for connection.

[0139] In some embodiments, continue to refer to Figure 12 and Figure 13 , along the second direction Y, the first sub - part 151 in the third gate structure 133 and the first sub - part 151 in the first gate structure 131 have an overlap.

[0140] Along the second direction Y, the first sub - part 151 in the third gate structure 133 and the first sub - part 151 in the first gate structure 131 have an overlap. That is to say, in the positive projection onto the second reference plane, the first sub - part 151 in the first gate structure 131 and the first sub - part 151 in the third gate structure 133 have an overlap. In this way, the second lead - out part 170 connected to the first gate structure 131 can overlap with the first sub - part 151 in the third gate structure 133, the available space for the second lead - out part 170 increases, and the dimension of the second lead - out part 170 connected to the third gate structure 133 in the second direction Y can be greater than the sum of the distance between the third gate structure 133 and the first gate structure 131 and the dimension of the third gate structure 133. The second lead - out part 170 connected to the third gate structure 133 can overlap with the first sub - part 151 in the first gate structure 131, and the dimension of the second lead - out part 170 connected to the third gate structure 133 in the second direction Y can be greater than the sum of the distance between the third gate structure 133 and the first gate structure 131 and the dimension of the first gate structure 131. Thereby further increasing the area occupied by the second lead - out part 170 connected to the third gate structure 133 or the first gate structure 131 in the X - Y plane, which is convenient for connection.

[0141] Along the second direction Y, the first sub - portion 151 in the fourth gate structure 134 overlaps with the first sub - portion 151 in the second gate structure 132. That is, in the orthographic projection onto the second reference plane, the first sub - portion 151 in the fourth gate structure 134 and the first sub - portion 151 in the second gate structure 132 overlap. In this way, the second lead - out portion 170 connected to the fourth gate structure 134 can overlap with the first sub - portion 151 in the second gate structure 132, increasing the available space for arranging the second lead - out portion 170. The dimension of the second lead - out portion 170 connected to the second gate structure 132 in the second direction Y can be greater than the sum of the distance between the second gate structure 132 and the fourth gate structure 134 and the dimension of the fourth gate structure 134. The second lead - out portion 170 connected to the second gate structure 132 can overlap with the first sub - portion 151 in the fourth gate structure 134, and the dimension of the second lead - out portion 170 connected to the second gate structure 132 in the second direction Y can be greater than the sum of the distance between the second gate structure 132 and the fourth gate structure 134 and the dimension of the second gate structure 132. Thus, the area occupied by the second lead - out portion 170 connected to the second gate structure 132 or the fourth gate structure 134 in the X - Y plane is further increased, facilitating connection.

[0142] The gate structure 130 is truncated by the first dielectric portion 150 in the connection region BB on the same side of the array region AA. The first sub - portions 151 in the first gate structure 131, the second gate structure 132, the third gate structure 133, and the fourth gate structure 134 are located on the same side of the array region AA. In this way, when forming the first dielectric portion 150, the first sub - portions 151 in the first gate structure 131, the second gate structure 132, the third gate structure 133, and the fourth gate structure 134 can be formed simultaneously in the connection region BB on the same side of the array region AA, which is beneficial to simplifying the process flow and improving the product preparation efficiency.

[0143] Figure 14 It is another top - view of a semiconductor structure provided according to some embodiments.

[0144] In some embodiments, refer to Figure 14, along the second direction Y, a first sub - portion 151 in the first gate structure 131 overlaps with a second sub - portion 152 in the isolation structure 120. Specifically, in the positive projection onto the second reference plane, the first sub - portion 151 in the first gate structure 131 overlaps with the second sub - portion 152 in the isolation structure 120. In this way, no second lead - out portion 170 is provided in the overlapping part of the first sub - portion 151 in the first gate structure 131 and the second sub - portion 152 in the isolation structure 120, and a first lead - out portion 160 can be provided in the overlapping part of the isolation structure 120 and the first sub - portion 151. In this way, it is possible to prevent a short - circuit caused by the connection between the first lead - out portion 160 and the second lead - out portion 170. The dimension of the first lead - out portion 160 connected to the isolation structure 120 in the second direction Y can be greater than the sum of the dimension of the isolation structure 120 and the distance between the isolation structure 120 and the first gate structure 131, so as to increase the dimension of the first lead - out portion 160 connected to the isolation structure 120 in the second direction Y.

[0145] The first sub - portion 151 in the second gate structure 132 and the second sub - portion 152 in the isolation structure 120 are respectively located on both sides of the array region AA. The first sub - portion 151 in the first gate structure 131 and the second sub - portion 152 in the isolation structure 120 are located on the same side of the array region AA. In this way, the first lead - out portion 160 connected to the isolation structure 120 and the second lead - out portion 170 connected to the fourth gate structure 134 can be located on both sides of the array region AA. The dimension of the second lead - out portion 170 connected to the fourth gate structure 134 in the second direction Y can be greater than the sum of the dimension of the fourth gate structure 134 and the distance between the second gate structure 132 and the fourth gate structure 134, thereby increasing the area occupied by the second lead - out portion 170 in the X - Y plane, which is convenient for connection. And it is possible to prevent the adjacent lead - out portions from being connected to each other along the second direction Y, affecting signal transmission.

[0146] Figure 15 It is another top - view of a semiconductor structure provided according to some embodiments. Figure 16 is Figure 15 a cross - sectional view taken along the section line A3 - A4 in

[0147] In some embodiments, referring to Figure 15 and Figure 16 , the second part P2 of the isolation structure 120 includes a first isolation sub - portion P21 and a second isolation sub - portion P22.

[0148] The first isolation sub - part P21 at least includes a conductive layer 122 and a second insulating layer 123 arranged in sequence along the third direction Z. Exemplarily, the first isolation sub - part P21 includes a first insulating layer 121, a conductive layer 122, and a second insulating layer 123 arranged in sequence along the third direction Z. The first insulating layer 121 of the first isolation sub - part P21 and the first insulating layer 121 of the first part P1 and the third part P3 are the same layer. The conductive layer 122 of the first isolation sub - part P21 and the conductive layer 122 of the first part P1 and the third part P3 are the same layer. The second insulating layer 123 of the first isolation sub - part P21 and the second insulating layer 123 of the first part P1 and the third part P3 are the same layer. Also exemplarily, the first isolation sub - part P21 includes a conductive layer 122 and a second insulating layer 123 arranged in sequence along the third direction Z.

[0149] The second isolation sub - part P22 includes a second insulating layer 123. The second insulating layer 123 of the first isolation sub - part P21 and the second isolation sub - part P22 are the same layer. On the side of the second insulating layer 123 of the second isolation sub - part P22 close to the first surface 111, there is no conductive layer 122 and first insulating layer 121 arranged.

[0150] Along the first direction X, the first dielectric part 150 cuts off the first insulating layer 121 and the conductive layer 122 of the gate structure 130 and the isolation structure 120. That is to say, a part of the first dielectric part 150 is located at the end of the gate structure 130, and a part is located at the ends of the first insulating layer 121 and the conductive layer 122 of the isolation structure 120. Among them, the part of the first dielectric part 150 located at the end of the conductive layer 122 is the third sub - part 153. The third sub - part 153 is located on the side of the second insulating layer 123 far from the second surface 112. Exemplarily, the first sub - part 151 is located at the end of the first gate structure 131, and the third sub - part 153 is located at the end of the conductive layer 122.

[0151] Along the third direction Z, the first dielectric part 150 overlaps with the second isolation sub - part P22. Specifically, the first dielectric part 150 cuts off the conductive layer 122 of the second isolation sub - part P22 from the first surface 111 side, and the positive projection of the first dielectric part 150 on the X - Y plane overlaps with the positive projection of the second isolation sub - part P22 on the X - Y plane. Exemplarily, continue to refer to Figure 15 , in the positive projection on the X - Y plane, the first dielectric part 150 covers the end of the gate structure 130, and also covers the second isolation sub - part P22. The outer contour of the second isolation sub - part P22 is located inside the outer contour of the first dielectric part 150, or along the first direction X, the outer contour of the second isolation sub - part P22 coincides with the outer contour of the first dielectric part 150.

[0152] In this way, when forming the gap for forming the first dielectric portion 150, a part of the gate structure 130 and a part of the first insulating layer 121 and the conductive layer 122 on the same side of the array region AA can be removed simultaneously to increase the size of the gap along the second direction Y, thereby reducing the process difficulty of forming the first dielectric portion 150 and improving the product production efficiency.

[0153] In some embodiments, referring further to Figure 15 and Figure 16 , along the second direction Y, the first sub-portion 151 in the gate structure 130 and the third sub-portion 153 in the isolation structure 120 overlap. Specifically, in the positive projection onto the second reference plane, the first sub-portion 151 in the gate structure 130 overlaps with the third sub-portion 153 in the isolation structure 120. Exemplarily, the first sub-portion 151 in each of the first gate structure 131, the second gate 132, the third gate structure 133, and the fourth gate structure 134 overlaps with the third sub-portion 153 in the isolation structure 120 in the positive projection onto the X-Z plane. At this time, one end of the first insulating layer 121 and the conductive layer 122 is located in the connection region BB on one side of the array region AA, and along the first direction X, the other ends of the first insulating layer 121 and the conductive layer 122 penetrate through the array region AA and extend to the connection region BB on the other side of the array region AA. In this way, the size of the first dielectric portion 150 along the second direction Y can be greater than or equal to the distance between the first gate structure 131 and the fourth gate structure 134, increasing the size of the first dielectric portion 150 in the second direction Y, reducing the process difficulty of forming the first dielectric portion 150, and further improving the product production efficiency.

[0154] In some embodiments, referring further to Figure 15 and Figure 16 , multiple first dielectric portions 150 on the same side of the array region AA can be an integral structure. The integral structure can penetrate through the connection region BB along the second direction Y. When forming the gap for forming the first dielectric portion 150, gaps that penetrate through multiple gate structures 130 and multiple isolation structures 120 simultaneously along the second direction Y can be formed at the same time. These gaps communicate with each other, and insulating materials can be deposited in these gaps to form multiple first dielectric portions 150 of the integral structure simultaneously, simplifying the preparation process and improving the product preparation efficiency.

[0155] In some embodiments, referring further to Figure 15, the first lead-out portion 160 overlaps at least a part of the first isolation sub-portion P21 along the third direction Z. The first lead-out portion 160 extends from one side of the first surface 111 into the semiconductor structure 300 and is connected to the conductive layer 122 of the first isolation sub-portion P21. Specifically, the positive projection of the first lead-out portion 160 connected to the isolation structure 120 on the X-Y plane overlaps with the positive projection of the first isolation sub-portion P21 on the X-Y plane. Exemplarily, in the positive projection on the X-Y plane, along the first direction X, the entire first lead-out portion 160 coincides with the conductive layer 122 of the first isolation sub-portion P21. Also exemplarily, in the positive projection on the X-Y plane, along the first direction X, a part of the first lead-out portion 160 coincides with the conductive layer 122 of the first isolation sub-portion P21, and another part coincides with the second insulating layer 123 of the second isolation sub-portion P22, so as to realize the lead-out of the conductive layer 122 of the isolation structure 120.

[0156] In some embodiments, continuing to refer to Figure 8 , along the third direction Z, the distance (hereinafter referred to as the first distance) H1 from the conductive layer 122 of the isolation structure 120 to the first surface 111 is greater than the distance (hereinafter referred to as the second distance) H2 from the gate structure 130 to the first surface 111. Wherein, the first distance H1 is the distance from the end of the conductive layer 122 far from the second insulating layer 123 to the first surface 111, and the second distance H2 is the distance from the end of the gate structure 130 close to the first surface 111 to the first surface 111. If the first distance H1 is less than or equal to the second distance H2, then when the gate structure is exposed by a gap, the conductive layer 122 of the isolation structure 120 will also be exposed in the gap. In this way, when the etching solution removes the gate structure, the conductive layer 122 of the isolation structure 120 will also be removed. Thereby affecting the performance of the semiconductor structure 300.

[0157] In some embodiments, continuing to refer to Figure 12 , the semiconductor structure 300 further includes a second dielectric portion 190 and a plurality of third lead-out portions 180.

[0158] The second dielectric portion 190 is located in the connection region BB. The second dielectric portion 190 extends into the semiconductor structure 300 from the first surface 111 along the third direction Z. The second dielectric portion 190 is located at the end of the bit line 140 along the second direction Y. The material of the second dielectric portion 190 is an insulating material, and the insulating material can refer to the above description and will not be elaborated here.

[0159] The third lead-out portion 180 is connected to the bit line 140. Specifically, the third lead-out portion 180 extends from the first surface 111 into the semiconductor structure 300, and the end of the third lead-out portion 180 close to the second insulating layer is connected to the bit line 140. Exemplarily, along the second direction Y, the size of the end of the third lead-out portion 190 close to the second insulating layer is smaller than the size of the end of the third lead-out portion 190 far from the second insulating layer. The third lead-out portion 190, the first lead-out portion 160, and the second lead-out portion 170 are all led out from one side of the first surface 111. In this way, the lead-out portions are concentrated on the same side of the semiconductor structure 300, which is beneficial to the miniaturization of the semiconductor structure 300. Moreover, during the formation of the lead-out portions, the first lead-out portion 160, the second lead-out portion 170, and the third lead-out portion 190 can be formed simultaneously on the same side of the semiconductor structure 300, which is beneficial to simplifying the manufacturing process and improving the product manufacturing efficiency.

[0160] In some embodiments, with continued reference to Figure 7 and Figure 8 , the semiconductor structure 300 further includes a dielectric structure 110. The dielectric structure 110 is located between the gate structure 130 and the isolation structure 120. The material of the dielectric structure 110 may include an insulating material, and the insulating material can be referred to the description above and will not be elaborated here.

[0161] In some embodiments, the material of the first dielectric portion 150 may be the same as the material of the dielectric structure 110. For example, they may both be single-crystalline silicon, preventing the formation of an obvious interface between the first dielectric portion 150 and the dielectric structure 110 due to different materials when depositing to form the first dielectric portion 150.

[0162] In some implementation manners, the materials of the first dielectric portion 150 and the dielectric structure 110 may also be different. Embodiments of the present disclosure provide a method for manufacturing a semiconductor structure.

[0163] Figure 17 is a flowchart of a method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure. Figures 18A to 30 is a structural diagram corresponding to each step in the method for manufacturing a semiconductor structure according to some embodiments.

[0164] Next, with reference to the accompanying drawings, a method for manufacturing a semiconductor structure provided by some embodiments of the present disclosure will be schematically described.

[0165] Referring to Figure 17 and in combination with Figures 18A to 30 , the method for manufacturing the above semiconductor structure includes: S1 to S3.

[0166] S1. Form a plurality of gate structures 130 and a plurality of isolation structures 120.

[0167] Both the gate structure 130 and the isolation structure 120 extend along the first direction X. Along the second direction Y, one isolation structure 120 is located between two adjacent gate structures 130. For the specific structures of the gate structure 130 and the isolation structure 120, reference can be made to the above description and will not be elaborated here.

[0168] See Figure 29 , a dielectric structure 110 is provided between the gate structure 130 and the isolation structure 120. Along the third direction Z, the dielectric structure 110 includes a first surface and a second surface that are oppositely arranged. The relative positions of the first surface and the second surface are the relative positions from the first surface 111 to the second surface 112 of the semiconductor structure 300 described above. For the material of the dielectric structure 110, reference can be made to the above description and will not be elaborated here.

[0169] In some implementation manners, before forming the multiple gate structures 130 and the multiple isolation structures 120, multiple bit lines 140 are first formed. The bit lines 140 extend along the second direction Y and are separated by the multiple gate structures 130 and the multiple isolation structures 120 arranged along the second direction Y into several active pillars 141. For the specific structure of the bit lines 140, reference can be made to the above description and will not be elaborated here.

[0170] Among them, forming the multiple gate structures 130 and the multiple isolation structures 120 may include the following steps:

[0171] S11. Form multiple trenches.

[0172] Figure 18A FIG. is a structural diagram of forming multiple trenches in a method for manufacturing a semiconductor structure according to some embodiments. Figure 18B Is Figure 18A The cross-sectional view taken along the section line E1-E2 in

[0173] See Figure 18A , the multiple trenches include multiple first trenches 101 and multiple second trenches 102. Both the first trenches 101 and the second trenches 102 extend along the first direction X, and the first trenches 101 and the second trenches 102 are alternately arranged in sequence in the second direction Y. The dielectric structure 110 is between the first trenches 101 and the second trenches 102.

[0174] See Figure 18B , the first trenches 101 and the second trenches 102 extend from the second surface 112 towards the first surface 111 along the third direction Z. The bottoms of the first trenches 101 and the second trenches 102 are close to the first surface 111.

[0175] In some examples, a mask layer MASK is further included on one side of the second surface 112 of the dielectric structure 110, and the material of the mask layer MASK can be silicon nitride.

[0176] In some examples, a protective layer is further included between the dielectric structure 110 and the mask layer MASK ( Figure 18B not shown in the figure), and the protective layer can avoid the stress problem caused by the direct contact between the mask layer MASK and the dielectric structure 110. The material of the protective layer can be silicon oxide.

[0177] In some embodiments, the dimension of the first trench 101 along the second direction Y (hereinafter referred to as the width of the first trench 101) is greater than the dimension of the second trench 102 along the second direction Y (hereinafter referred to as the width of the second trench 102). Since the width of the second trench 102 is smaller than the width of the adjacent first trench 101, therefore, the width to be filled in the second trench 102 is smaller. When depositing a conductive material in the first trench 101 and the second trench 102 simultaneously, when the second trench 102 is filled, there are still voids between the sidewalls of the first trench 101, which is beneficial to forming two adjacent initial gate structures with interconnected bottoms in the first trench 101.

[0178] In some embodiments, the dimension of the first trench 101 along the third direction Z (hereinafter referred to as the depth of the first trench 101) is greater than the dimension of the second trench 102 along the third direction Z (hereinafter referred to as the depth of the second trench). Exemplarily, the distance from the bottom of the first trench 101 to the first surface 111 is smaller than the distance from the bottom of the second trench 102 to the first surface 111. In this way, in the subsequent process, the distance from the bottoms of the two initial gate structures with interconnected bottoms to the first surface 111 is smaller than the distance from the bottom of the initial isolation structure to the first surface 111. When using an etching process to disconnect the adjacent initial gate structures, since the bottoms of the initial gate structures are closer to the first surface 111 than the bottoms of the initial isolation structures, the bottoms of the initial gate structures are exposed first during etching, and at this time, the bottoms of the initial isolation structures are not exposed. The etching solution can be directly used to disconnect the two adjacent initial gate structures with interconnected bottoms from one side of the first surface 111, and at this time, the bottoms of the initial isolation structures will not be etched. In this way, it is not necessary to first set a mask layer on one side of the first surface 111, thereby saving process steps and improving the preparation efficiency.

[0179] In some implementation manners, a plurality of second trenches 102 with the same width and depth can be formed first, and then the width and depth of the second trenches 102 can be enlarged by an etching method to form the first trench 101.

[0180] S12. Form a plurality of initial gate structures 30 and a plurality of initial isolation structures 40.

[0181] Figures 19 to 23B FIG. is a structural diagram of each step for forming a plurality of initial gate structures and a plurality of initial isolation structures in a method for preparing a semiconductor structure according to some embodiments.

[0182] Thin film deposition processes such as Chemical Vapor Deposition (CVD for short), Physical Vapor Deposition (PVD for short), or Atomic Layer Deposition (ALD for short) can be used to form two initially interconnected gate structures 30 at the bottom in the first trench 101, where the two initially interconnected gate structures are 30a and 30b respectively.

[0183] Specifically, an insulating material and a conductive material are sequentially deposited in the first trench 101. The insulating material forms an initial gate dielectric layer at the bottom and sidewalls of the first trench 101, and the bottoms of adjacent two initial gate dielectric layers are interconnected. The conductive material forms an initial gate layer at the bottom and sidewalls of the first trench 101, and the bottoms of adjacent two initial gate layers are interconnected.

[0184] A material is deposited in the second trench 102 to form an initial isolation structure 40. The initial isolation structure 40 includes a first insulating layer 121, an initial conductive layer 1221, and an initial second insulating layer 1231 arranged in sequence along the third direction Z. The materials of the first insulating layer 121 and the initial second insulating layer 1231 are insulating materials, and the insulating materials can refer to the description above and will not be elaborated here. The material of the initial conductive layer 1221 is a conductive material, and the conductive material can refer to the description above and will not be elaborated here.

[0185] In some embodiments, forming a plurality of initially interconnected gate structures 30 and a plurality of initial isolation structures 40 includes the following steps:

[0186] S121, referring to Figure 19 , an initially interconnected gate structure 30 is formed in the first trench 101, and the first insulating layer 121 and the initial conductive layer 1221 are sequentially stacked in the second trench 102.

[0187] S122 (optionally), removing the mask layer MASK from one side of the second surface 112, as Figure 20 shown.

[0188] In some other embodiments, if the mask layer MASK is not formed in the above steps, step S123 can be directly executed.

[0189] S123, referring to Figure 21 , forming a first groove CH1 and a second groove CH2.

[0190] Specifically, a part of the initial conductive layer 1221 is removed from the side of the second surface 112 to form a first groove CH1; a part of the initial conductive layer 1221 close to the second surface 112 is removed to become the conductive layer 122. A part of the initial gate structure 30 is removed from the side of the second surface 112 to form a second groove CH2.

[0191] In some implementations, a part of the initial conductive layer 1221 and a part of the initial gate structure 30 can also be directly removed from the side of the mask layer MASK away from the first surface 111.

[0192] S124. Refer to Figure 22 , to form a plurality of initial gate structures 30 and a plurality of initial isolation structures 40.

[0193] Specifically, an insulating material is deposited in the first groove CH1 to form a second insulating layer 123. At this time, the first insulating layer 121, the conductive layer 122, and the second insulating layer 123 stacked in sequence form an initial isolation structure 40. Both ends of the conductive layer 122 are respectively covered by the first insulating layer 121 and the second insulating layer 123, and the first insulating layer 121 is closer to the first surface 111 than the second insulating layer 123. An insulating material is deposited in the second groove CH2 to form a third insulating layer 124, so that one end of the initial gate structure 30 close to the second surface 112 is covered by the third insulating layer 124.

[0194] The insulating material deposited in the second groove CH2 and the insulating material deposited in the first groove CH1 can be the same or different, and the embodiments of the present disclosure do not limit this.

[0195] In some embodiments, the material of the third insulating layer 124 can be the same as the material of the dielectric structure 110.

[0196] In some other implementations, the material of the third insulating layer 124 is different from the material of the dielectric structure 110.

[0197] In some other implementations, the material of the second insulating layer 123 can be the same as the material of the dielectric structure 110.

[0198] S13 (optionally), thinning the dielectric structure 110.

[0199] Figure 23A It is a structural diagram for thinning a dielectric structure in a method for preparing a semiconductor structure according to some embodiments. Figure 23B It is Figure 23A a cross-sectional view taken along the section line F1 - F2 in

[0200] Refer to Figure 23A and Figure 23B, the dielectric structure 110 is thinned from one side of the first surface 111. Since the bottom of the initial gate structure 30 is close to the first surface 111, thinning the dielectric structure 110 from one side of the first surface 111 is conducive to disconnecting the interconnected initial gate structure 30 from the back surface (the first surface 111) of the dielectric structure 110, facilitating subsequent processes to continue operating from one side of the first surface 111.

[0201] S14. Disconnect the two interconnected initial gate structures 30.

[0202] Figure 24A It is a structural diagram of disconnecting two interconnected initial gate structures in the manufacturing method of a semiconductor structure provided according to some embodiments. Figure 24B is Figure 24A a cross-sectional view taken along the section line G1 - G2 in

[0203] See Figure 24A and Figure 24B , disconnect the two adjacent interconnected initial gate structures 30 from one side of the first surface 111. Specifically, an etching process is used to remove the bottoms of the initial gate structures 30a and 30b from one side of the first surface 111, so that the two initial gate structures 30a and 30b are disconnected. Exemplarily, the ends of the initial gate structures 30a and 30b close to the first surface 111 are disconnected.

[0204] S15. Form a first gap K1.

[0205] Figures 25A to 26 It is a structural diagram of each step of forming a first gap in the manufacturing method of a semiconductor structure provided according to some embodiments.

[0206] See Figure 26 , form a first gap K1 in the dielectric structure 110 from one side of the first surface 111. The first gap K1 exposes the first insulating layer 121 of the initial isolation structure 40 and at least one of the two initial gate structures in the initial isolation structure 40, i.e., the initial gate structure 30.

[0207] Among them, the two initial gate structures 30 adjacent to the initial isolation structure 40 include the initial gate structure 30b (hereinafter referred to as the first initial gate structure 30b) and 30c (hereinafter referred to as the second initial gate structure 30c). Exemplarily, see Figure 26 , the first gap K1 exposes the first insulating layer 121 of the initial isolation structure 40, the first initial gate structure 30b, and the second initial gate structure 30c. Another exemplarily, the first gap K1 exposes the initial isolation structure 40 and the first initial gate structure 30b. Another exemplarily, the first gap K1 exposes the initial isolation structure 40 and the second initial gate structure 30c.

[0208] The dimension of the first gap K1 in the second direction Y is larger than the dimension of the initial gate structure 30. In this way, when forming the first opening K11 and the second opening K12, the etching solution enters the dielectric structure 110 from the first gap K1 with a larger dimension, facilitating the subsequent truncation of the initial gate structure 30 and the initial isolation structure 40.

[0209] In some embodiments, forming the first gap K1 includes:

[0210] S151. Forming the first filling portion 205.

[0211] Figure 25A It is a structural diagram for disconnecting two interconnected initial gate structures in a method for manufacturing a semiconductor structure according to some embodiments. Figure 25B For Figure 25A it is a cross-sectional view taken along the section line J1-J2 in

[0212] See Figure 25A and Figure 25B , a first filling portion 205 is formed on one side of the initial gate structure 30 close to the first surface 111. The first filling portion 205 extends from one side of the first surface 111 into the dielectric structure 110. The first filling portion 205 covers two adjacent initial gate structures 30 that were originally interconnected, preventing the initial gate structure 30 from being exposed.

[0213] The material of the first filling portion 205 is an insulating material. The insulating material can be referred to the description above and will not be elaborated here. The material of the first filling portion 205 and the material of the dielectric structure 110 are two different insulating materials, and under the same process conditions, the etching rate of the material of the first filling portion 205 is different from the etching rate of the material of the dielectric structure 110. In this way, when subsequently removing the dielectric structure 110 between the initial isolation structure 40 and the initial gate structure 30, only the dielectric structure 110 can be removed without affecting the first filling portion 205.

[0214] S152. See Figure 26 , forming an opening CH3.

[0215] A mask layer MASK is formed on one side of the first surface 111. An opening CH3 is provided on the mask layer MASK. The opening CH3 overlaps with the initial isolation structure 40 along the third direction Z. Exemplarily, in the positive projection of the outer contour of the opening CH3 on the X-Y plane, it overlaps with the positive projection of the initial isolation structure 40 on the X-Y plane, facilitating the opening CH3 to expose the initial isolation structure 40, and the etching solution can enter the dielectric structure 110 by etching from the position between the upper ends of the initial isolation structure 40 and the initial gate structure 30 through the opening CH3 to form the first gap K1.

[0216] Along the second direction Y, the size of the opening CH3 is smaller than the size between two initial gate structures (the first initial gate structure 30b and the second initial gate structure 30c) adjacent to the initial isolation structure 40. For example, the opening CH3 exposes a part of the initial isolation structure 40 and a part of the dielectric structure 110 located between the initial isolation structure 40 and the first initial gate structure 30b. At this time, in the second direction Y, the size of the opening CH1 is larger than the initial isolation structure 40 and smaller than the distance between the initial isolation structure 40 and the first initial gate structure 30b. Another example is that the opening CH3 exposes a part of the initial isolation structure 40 and a part of the dielectric structure 110 located between the initial isolation structure 40 and the second initial gate structure 30c. At this time, in the second direction Y, the size of the opening CH1 is larger than the initial isolation structure 40 and smaller than the distance between the initial isolation structure 40 and the second initial gate structure 30c. Another example is that the opening CH3 exposes a part of the dielectric structure 110 located between the first initial gate structure 30b and the second initial gate structure 30c and the initial isolation structure 40.

[0217] S153. Continue to refer to Figure 26 , and form a first gap K1 through the opening CH3.

[0218] The first gap K1 is formed by an etching process through the opening CH3. The first gap K1 exposes at least the first insulating layer 121 of the initial isolation structure 40 and at least one of the two initial gate structures adjacent to the initial isolation structure 40, i.e., the initial gate structure 30.

[0219] Since the materials of the first filling portion 205 and the first insulating layer 121 are different from the material of the dielectric structure 110, the first filling portion 205 and the first insulating layer 121 are retained, and only a part of the dielectric structure 110 is removed. Exemplarily, the first gap K1 exposes the first insulating layer 121 of the initial isolation structure 40 and the first initial gate structure 30b, and the first filling portion 205 located on the side of the first initial gate structure 30b close to the first surface 111. Another example is that the first gap K1 exposes the first insulating layer 121 of the initial isolation structure 40 and the second initial gate structure 30c, and the first filling portion 205 located on the side of the second initial gate structure 30c close to the first surface 111. Another example is to refer to Figure 26 , the first gap K1 exposes the first insulating layer 121 of the initial isolation structure 40, the first initial gate structure 30b and the second initial gate structure 30c, and the first filling portion 205 located on the side of the first initial gate structure 30b and the second initial gate structure 30c close to the first surface 111.

[0220] S16. Form a first opening K11.

[0221] Figure 27AIt is a structural diagram of forming a first opening in a method for preparing a semiconductor structure according to some embodiments. Figure 27B It is Figure 27A a cross-sectional view taken along the section line L1-L2 in

[0222] Refer to Figure 27A and Figure 27B , through the first gap K1, at least a part of at least one of the two initial gate structures 30 adjacent to the initial isolation structure 40 is removed in the initial gate structure 30, forming a first opening K11. The first opening K11 truncates the initial gate structure 30 along the first direction X to form a gate structure 130. The bottom of the first opening K11 is close to the second surface 112, and the opening of the first opening K11 is close to the first surface 111. Exemplarily, a part of the first initial gate structure 30b is removed, and the first initial gate structure 30b is truncated by the first opening K11 to form a first gate structure 131. A part of the second initial gate structure 30c is removed, and the second initial gate structure 30c is truncated by the first opening K11 to form a second gate structure 132.

[0223] S17. Form a second opening K12.

[0224] Figure 28A It is a structural diagram of forming a second opening in a method for preparing a semiconductor structure according to some embodiments. Figure 28B It is Figure 28A a cross-sectional view taken along the section line M1-M2 in

[0225] Refer to Figure 28A and Figure 28B , through the first gap K1, a part of the first insulating layer 121 in the initial isolation structure 40 is removed to form a second opening K12. The second opening K12 truncates the first insulating layer 121 of the initial isolation structure 40 along the first direction X to form an isolation structure 120. The bottom of the second opening K12 is close to the conductive layer 122, and the opening of the second opening K12 is close to the first surface 111.

[0226] In some embodiments, the first filling portion 205 can be removed before step S16. When the material of the first filling portion 205 is different from that of the first insulating layer 121, the first filling portion 205 can be removed first, and then a part of the first insulating layer 121 can be removed.

[0227] In some embodiments, when removing a part of the first insulating layer 121 through the first gap K1, the first filling portion 205 is removed simultaneously to save the process flow and improve the preparation efficiency.

[0228] In some other implementation manners, the first filling portion 205 can also be retained to simplify the process flow.

[0229] S2. Refer to Figure 29 to form a first dielectric portion 150.

[0230] Deposit an insulating material from one side of the first surface 111 to form a first dielectric portion 150 in the first gap K1 and the first opening K11 and the second opening K12. Among them, the portion of the first dielectric portion 150 in the first opening K11 is the first sub-portion 151, and the portion of the first dielectric portion 150 in the second opening K12 is the second sub-portion 152. The specific structure of the first dielectric portion 150 can refer to the description above and will not be elaborated here.

[0231] In some embodiments, the method for fabricating the semiconductor structure 300 further includes:

[0232] S3. Refer to Figure 30 to form a plurality of lead-out portions.

[0233] Specifically, the lead-out portions include a first lead-out portion 160 and a second lead-out portion 170. The first lead-out portion 160 and the second lead-out portion 170 extend from one side of the first surface 111 into the dielectric structure 110. The structures and materials of the first lead-out portion 160 and the second lead-out portion 170 can refer to the description above and will not be elaborated here.

[0234] In some embodiments, the method for fabricating the semiconductor structure further includes forming a second dielectric portion and a third lead-out portion. The second dielectric portion and the third lead-out portion extend from one side of the first surface 111 into the dielectric structure 110. The specific structure of the third lead-out portion can refer to the description above and will not be elaborated here.

[0235] The embodiments of the present disclosure further provide a method for fabricating a semiconductor structure, and the fabrication method may include steps S1' to S3'. Among them, S11' to S14' and S2' to S3' specifically refer to S11 to S14 and S2 to S3 above.

[0236] Figures 31 to 33 It is a structural diagram corresponding to each step in the method for fabricating a semiconductor structure according to some embodiments.

[0237] After S14' disconnects the two initial gate structures 30 that are connected to each other, the method for fabricating the semiconductor structure further includes:

[0238] S15'. Refer to Figure 31 to form a first gap K1.

[0239] A first gap K1 is formed in the dielectric structure 110 from one side of the first surface 111. The first gap K1 exposes at least two adjacent initial gate structures 30. Exemplarily, the first gap K1 exposes the first initial gate structure 30b and the initial gate structure 30a. Additionally, exemplarily, the first gap K1 exposes the first initial gate structure 30b and the initial gate structure 30a, as well as the first insulating layer 121 of the initial isolation structure 40 that is located on the side of the first initial gate structure 30b away from the initial gate structure 30a and adjacent to the first initial gate structure 30b.

[0240] The dimension of the first gap K1 in the second direction Y is greater than the dimension of the initial gate structure 30. In this way, when forming the first opening K11 and the second opening K12, the etching solution enters the dielectric structure 110 from the first gap K1 with a larger dimension, facilitating subsequent truncation of the initial gate structure 30 and the initial isolation structure 40.

[0241] S16’, see Figure 32 , to form the first opening K11.

[0242] A part of the initial gate structure 30 is removed through the first gap K1 to form the first opening K11. The first opening K11 truncates the initial gate structure 30 along the first direction X to form a gate structure. Exemplarily, a part of the gate structure between two adjacent initial isolation structures 40 is removed through an etching process. Among them, the first opening K11 extends from one side of the first surface 111 into the dielectric structure 110, and the first opening K11 truncates the initial gate structure 30 along the first direction X to form the gate structure 130. The bottom of the first opening K11 is close to the second surface 112, and the opening of the first opening K11 is close to the first surface 111.

[0243] S17’, see Figure 33 , to form the second opening K12.

[0244] A part of the first insulating layer 121 and a part of the conductive layer 122 in the initial isolation structure 40 are removed through the first gap K1 to form the second opening K12. The second opening K12 truncates the first insulating layer 121 and the conductive layer 122 of the initial isolation structure 40 along the first direction X to form the isolation structure 120. The bottom of the second opening K12 is close to the second insulating layer 123, and the opening of the second opening K12 is close to the first surface 111.

[0245] During the preparation process of the semiconductor structure 300, after forming two initial gate structures and an initial isolation structure interconnected at the bottom, the preparation process of the semiconductor structure 300 is concentrated on the same side of the semiconductor structure 300 (for example, the side of the first surface 111), the two initial gate structures interconnected at the bottom are disconnected on the side of the first surface 111, the initial gate structure and the initial isolation structure are cut off on the side of the first surface 111, and the first dielectric portion 150 is formed on the side of the first surface 111, which can simplify the process flow and improve the preparation efficiency of the semiconductor structure 300.

[0246] The above is only a specific embodiment of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by a person skilled in the art within the technical scope disclosed by the present invention should be included in the protection scope of the present invention. Therefore, the protection scope of the present invention should be based on the protection scope of the claims.

Claims

1. A semiconductor structure, characterized in that, A semiconductor structure having an array region and a connection region, including a first surface and a second surface which are oppositely arranged; the semiconductor structure includes: a plurality of gate structures and a plurality of isolation structures; both the gate structures and the isolation structures extend in a first direction, and in a second direction, one of the isolation structures is located between two adjacent gate structures; the isolation structure includes a first part located in the array region and a second part located in the connection region, and in a third direction, the first part includes a first insulating layer, a conductive layer, and a second insulating layer arranged in sequence, the first insulating layer is closer to the first surface than the second insulating layer, and the second part at least includes the second insulating layer; and a first dielectric part located in the connection region; in the first direction, the first dielectric part is at least located at an end of the gate structure; the first direction and the second direction are parallel to the first surface and intersect, and the third direction is perpendicular to the first surface.

2. The semiconductor structure according to claim 1, characterized in that, The second part of the isolation structure includes a conductive layer and a second insulating layer arranged in sequence in the third direction; the first dielectric part is also located at an end of the first insulating layer; In the third direction, the first dielectric part overlaps with the second part.

3. The semiconductor structure according to claim 2, wherein a part of the first dielectric part located at an end of the gate structure is a first sub-part, and a part of the first dielectric part located at an end of the first insulating layer is a second sub-part; In the second direction, the first sub-part in at least one of the two gate structures adjacent to the isolation structure overlaps with the second sub-part in the isolation structure.

4. The semiconductor structure according to claim 3, wherein The two gate structures adjacent to the isolation structure are a first gate structure and a second gate structure respectively. In the second direction, the first sub-part in the first gate structure and the first sub-part in the second gate structure both overlap with the second sub-part in the isolation structure.

5. The semiconductor structure according to claim 4, wherein The gate structure adjacent to the first gate structure and located on the side of the first gate structure away from the isolation structure is a third gate structure, and the gate structure adjacent to the second gate structure and located on the side of the second gate structure away from the isolation structure is a fourth gate structure; The first sub-part in the third gate structure and the first sub-part in the first gate structure are respectively located on two sides of the array region, and the first sub-part in the fourth gate structure and the first sub-part in the second gate structure are respectively located on two sides of the array region.

6. The semiconductor structure according to claim 4, wherein The gate structure adjacent to the first gate structure and located on the side of the first gate structure away from the isolation structure is a third gate structure, and the gate structure adjacent to the second gate structure and located on the side of the second gate structure away from the isolation structure is a fourth gate structure; In the second direction, the first sub-part in the third gate structure overlaps with the first sub-part in the first gate structure, and the first sub-part in the fourth gate structure overlaps with the first sub-part in the second gate structure.

7. The semiconductor structure according to claim 3, wherein The two gate structures adjacent to the isolation structure are a first gate structure and a second gate structure respectively; Along the second direction, a first sub - portion in the first gate structure overlaps with a second sub - portion in the isolation structure, and the first sub - portions in the second gate structure and the isolation structure are respectively located on two sides of the array region.

8. The semiconductor structure according to claim 1, wherein The second portion of the isolation structure includes a first isolation sub - portion and a second isolation sub - portion. The first isolation sub - portion at least includes a conductive layer and a second insulating layer arranged in sequence along a third direction, and the second isolation sub - portion includes a second insulating layer; along the first direction, the first dielectric portion is located at the ends of the gate structure and the conductive layer. Along the third direction, the first dielectric portion overlaps with the second isolation sub - portion.

9. The semiconductor structure according to claim 8, wherein The portion of the first dielectric portion located at the end of the gate structure is the first sub - portion, and the portion of the first dielectric portion located at the end of the conductive layer is the third sub - portion. Along the second direction, the first sub - portion in the gate structure overlaps with the third sub - portion in the isolation structure.

10. The semiconductor structure according to claim 9, characterized in that, The plurality of first dielectric portions located on the same side of the array region are of an integral structure.

11. The semiconductor structure according to claim 1, wherein The portion of the first dielectric portion located at the end of the gate structure is the first sub - portion. The semiconductor structure further includes: A plurality of first lead - out portions, one end of the first lead - out portion close to the second insulating layer is connected to the conductive layer. Along the first direction, the size of the end of the first lead - out portion close to the second insulating layer is smaller than the size of the end far from the second insulating layer; along the second direction, the first lead - out portion overlaps with the first sub - portion.

12. The semiconductor structure according to claim 11, wherein When the second portion of the isolation structure includes a conductive layer and a second insulating layer arranged in sequence along the third direction, and along the third direction, the first dielectric portion overlaps with the second portion, the overlapping portion of the first dielectric portion and the second portion is the second sub - portion, and the first lead - out portion penetrates through the second sub - portion along the third direction to be connected to the conductive layer; Or, When the second portion of the isolation structure includes a first isolation sub - portion and a second isolation sub - portion, the first isolation sub - portion at least includes a conductive layer and a second insulating layer arranged in sequence along the third direction, the second isolation sub - portion includes a second insulating layer, and along the third direction, the first dielectric portion overlaps with the second isolation sub - portion, the first lead - out portion overlaps with at least a part of the first isolation sub - portion along the third direction.

13. The semiconductor structure according to claim 11, wherein It further includes: A plurality of second lead - out portions, one end of the second lead - out portion close to the second insulating layer is connected to the gate structure; Along the first direction, the size of the end of the second lead - out portion close to the second insulating layer is smaller than the size of the end far from the second insulating layer.

14. The semiconductor structure according to claim 13, wherein, Two gate structures adjacent to the isolation structure are respectively a first gate structure and a second gate structure, and the gate structure adjacent to the first gate structure and located on the side of the first gate structure far from the isolation structure is a third gate structure; Along the second direction, the second lead portion connected to the first gate structure overlaps with the first sub-portion in the third gate structure; and / or, the second lead portion connected to the third gate structure overlaps with the first sub-portion in the first gate structure.

15. The semiconductor structure according to claim 13, wherein The first lead portions connected to the plurality of isolation structures are located on the same side of the array region; or, the first lead portions connected to the plurality of isolation structures are alternately disposed on both sides of the array region.

16. The semiconductor structure according to claim 1, wherein, Along the third direction, the distance from the conductive layer of the isolation structure to the first surface is greater than the distance from the gate structure to the first surface.

17. The semiconductor structure according to any one of claims 1 to 16, characterized in that, Further comprising: a plurality of bit lines extending along the second direction; a second dielectric portion located at the end of the bit line along the second direction; a plurality of third lead portions, one end of the third lead portion close to the second surface is connected to the bit line, and along the first direction, the size of the end of the third lead portion close to the second surface is smaller than the size of the end far from the second surface.

18. A method for preparing a semiconductor structure, characterized in that, The semiconductor structure has an array region and a connection region, and the semiconductor structure includes a first surface and a second surface arranged opposite to each other; The manufacturing method of the semiconductor structure includes: forming a plurality of gate structures and a plurality of isolation structures; both the gate structure and the isolation structure extend along the first direction, and along the second direction, one isolation structure is located between two adjacent gate structures; the isolation structure includes a first part in the array region and a second part in the connection region, along the third direction, the first part includes a first insulating layer, a conductive layer and a second insulating layer arranged in sequence, the first insulating layer is closer to the first surface than the second insulating layer, and the second part at least includes an insulating layer; forming a first dielectric portion; the first dielectric portion is located in the connection region and at least located at the end of the gate structure along the first direction; The first direction and the second direction are parallel to and intersect with the first surface, and the third direction is perpendicular to the first surface.

19. The manufacturing method of the semiconductor structure according to claim 18, wherein forming a plurality of isolation structures and a plurality of gate structures includes: forming a plurality of initial isolation structures and a plurality of initial gate structures; the initial isolation structure includes a first insulating layer, a conductive layer and a second insulating layer stacked in sequence along the third direction, and one ends of two adjacent initial gate structures close to the first surface are connected to each other; disconnecting two adjacent initial gate structures connected to each other from one side of the first surface; forming a first gap; the first gap exposes at least the first insulating layer of the initial isolation structure and at least one of the two initial gate structures adjacent to the initial isolation structure; forming a first opening in at least one of the two initial gate structures adjacent to the initial isolation structure through the first gap; the first opening truncates the initial gate structure along the first direction to form a gate structure; Form a second opening in the initial isolation structure through the first gap; the second opening truncates the first insulating layer of the initial isolation structure along the first direction to form an isolation structure.

20. The method for manufacturing a semiconductor structure according to claim 19, wherein the forming of the first gap includes: Form a first filling portion on a side of the initial gate structure close to the first surface, the first filling portion being located at a position where a first opening is to be formed; Form an opening on the first surface; the opening overlaps with the initial isolation structure along a third direction; along a second direction, the size of the opening is smaller than the size between two adjacent initial gate structures adjacent to the initial isolation structure; Form a first gap through the opening; the first gap exposes at least one gate structure among the first insulating layer of the initial isolation structure, two adjacent initial gate structures adjacent to the initial isolation structure, and the first filling portion.

21. The method for manufacturing a semiconductor structure according to claim 20, wherein While forming the second opening in the initial isolation structure through the first gap, remove the first filling portion.

22. The method for manufacturing a semiconductor structure according to claim 19, wherein forming a plurality of isolation structures and a plurality of gate structures includes: Form a plurality of initial isolation structures and a plurality of initial gate structures, the initial isolation structure including a first insulating layer, a conductive layer, and a second insulating layer sequentially stacked along a third direction; one ends of two adjacent initial gate structures close to the first surface are connected to each other; Disconnect two adjacent initial gate structures that are connected to each other from one side of the first surface; Form a first gap; the first gap exposes at least two adjacent initial gate structures; Form a first opening in two adjacent initial gate structures through the first gap; the first opening truncates the initial gate structure along the first direction to form a gate structure; Form a second opening in the initial isolation structure through the first gap; the second opening truncates the first insulating layer and the conductive layer of the initial isolation structure along the first direction to form an isolation structure.

23. A storage system, characterized in that, including: a memory including the semiconductor structure according to any one of claims 1 to 17; a controller coupled to the memory to control the memory to store data.

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