One time programmable primitives and related methods

Abstract

The invention relates to a one-time programmable primitive and a related method. The present application relates to a one time programmable (otp) cell, the otp cell comprising: a selector device having a channel region; an otp capacitor having an otp capacitor dielectric associated with the selector device; an isolation dielectric having an isolation dielectric thickness tiso; the otp capacitor dielectric includes a first dielectric in a first region and a second dielectric in a second region, the second dielectric having a second thickness t2 less than the isolation dielectric thickness tiso, and the first dielectric having a first thickness t1 less than the second thickness t2, where the first region is embedded in the second region.

Description

Technical Field

[0001] The present application relates to a one-time programmable element. Background Art

[0002] A one-time programmable (OTP) element can be regarded as a non-volatile memory element. In the so-called antifuse technology, the OTP element can be changed to a conductive state. During programming, for example in response to an electrical stress (such as a voltage or current pulse) applied for programming, the state of the OTP element can change from non-conductive to conductive. Summary of the Invention

[0003] Examples of the present application relate to a one-time programmable (OTP) element.

[0004] In an embodiment of claim 1, the OTP element includes a selector device and an OTP capacitor, wherein the OTP capacitor dielectric is associated with the selector device. The OTP capacitor dielectric includes a first dielectric having a first thickness t1 and a second dielectric having a second thickness t2, where t1 is less than t2. Additionally, t2 is less than t iso , t iso is the thickness of the isolation dielectric. Wherein, a first region having the first (i.e., thinner) dielectric is embedded in a second region having the second dielectric, and the second dielectric is thicker than the first dielectric but still thinner than the isolation dielectric.

[0005] When the first region is embedded in the second region and t1 < t2, for example when observed in a vertical cross-section, a stepped dielectric can be provided. This can, for example, improve the programming quality, such as increasing the reliability of dielectric breakdown when a programming pulse is applied. By using different thicknesses (t1 < t2 < t iso ), dielectric breakdown can be forced to occur away from the edge of the thick isolation dielectric, which can, for example, increase reproducibility (e.g., from element to element or from batch to batch). This design can also provide a significant accumulation during programming, such as providing a defined or suitable voltage drop across the capacitor dielectric.

[0006] Additional embodiments and features are provided in this description and the drawings and in the dependent claims. Wherein, independent of the specific claim types, individual features will be disclosed, and the present disclosure relates to aspects of devices and apparatuses, and also to aspects of methods and uses. If, for example, an OTP element manufactured in a certain way is described, this will also be regarded as a disclosure of the corresponding manufacturing method. Generally, the solution of the present application is to provide an OTP element, such as an antifuse element, which includes an OTP capacitor having a capacitor dielectric with different thicknesses, for example, having a smaller thickness t1 in a first region compared to the second thickness t2 in a second region.

[0007] The first dielectric and / or the second dielectric and / or the isolation dielectric can be made of any insulating material (such as silicon oxide). The isolation dielectric can at least partially surround the OTP element, as seen for example in a vertical top view. In an exemplary embodiment, the isolation dielectric is, for example, a LOCOS oxide obtained from local oxidation of silicon. Alternatively, it can be, for example, a field oxide, such as arranged on a first side of the semiconductor body, or part of a shallow trench isolation (STI), such as recessed in a shallow trench for the first side of the semiconductor body.

[0008] The OTP capacitor dielectric is associated with a selector device, for example a control pulse (that is, a programming pulse) can propagate through the selector device to the OTP capacitor dielectric. Specifically, the control pulse can be transferred through the channel region to the OTP capacitor dielectric, and the selector device or the channel region is switched to a conductive state for this purpose, for example. In addition to the channel region, the selector device can include a gate region for controlling the current flow or conductivity of the channel region (for example, the following lateral channel).

[0009] In the semiconductor body, the channel region of the selector device can be formed. The semiconductor body can include, for example, a semiconductor substrate combined with one or several epitaxial semiconductor layers. The isolation dielectric can be arranged on a first side of the semiconductor body, and the first side can also be referred to as the front side. The OTP capacitor can also be arranged on the first side, for example integrated with the selector device or connected in series to the selector device, as will be described in more detail below.

[0010] On the first side of the semiconductor body, a wiring structure can be arranged, which can include one or several metallization layers. For the isolation between the wiring structure and the semiconductor body, an insulating layer can be placed in the middle in the vertical direction on the first side of the semiconductor body, and the isolation dielectric is, for example, thinner than the insulating layer.

[0011] In the OTP capacitor dielectric, a first region (first dielectric) can be embedded in a second region (second dielectric). When observed in a vertical top view, the first region can be laterally surrounded by the second region. The second region can, for example, surround the first region on all sides; in each vertical cross-section through the first dielectric, the first dielectric can be directly merged into the second dielectric on both sides. The first dielectric can be surrounded by the second dielectric on all lateral sides. Irrespective of these details, the first and second dielectrics can be arranged at the same height, for example on a common lateral plane extending through the first and second dielectrics.

[0012] In an embodiment, when observed in a vertical cross-section, the second dielectric merges directly into the isolation dielectric on at least one side. The corresponding cross-sectional plane passes through the first dielectric, for example, at a position substantially in the center of the OTP capacitor dielectric and parallel to the length direction of the channel region. The length direction may be the direction of current flow in the channel. The second dielectric may merge into the isolation dielectric in steps or obliquely. At least one side where the second dielectric directly merges into the isolation dielectric may be, for example, the side facing away from the channel region of the selector device. In some embodiments, as observed in a vertical cross-section parallel to the length direction, the second dielectric may directly merge into the isolation dielectric on both sides.

[0013] In a vertical cross-section passing through the first dielectric and perpendicular to the length direction of the channel region (e.g., perpendicular to the direction of current flow in the channel), the second dielectric may directly merge into the isolation dielectric on both sides. In other words, the second dielectric may be embedded in the isolation dielectric at least in the lateral direction perpendicular to the length direction. As seen in a vertical top view, for example, when observing the front or upper side of a semiconductor die including OTP elements along the vertical direction, the isolation dielectric may surround the first and second dielectrics in a U-shape (see Figure 2c the illustration of / 3c) or surround the first and second dielectrics in a box shape on all sides (see Figure 1c the illustration of).

[0014] In an embodiment, the second thickness t2 is at least 1.5 times the first thickness t1, and another lower limit is, for example, at least 2 times t1. A possible upper limit of the second thickness t2 can, for example, not exceed 20 times, 15 times, or 10 times the first thickness t1.

[0015] In an embodiment, the isolation dielectric thickness t iso is at least 10 times, 15 times, or 20 times the second thickness t2, where a possible upper limit may be 100 times, 80 times, 60 times, or 50 times t2. Comparing the thicknesses t iso , t2, and t1, the difference between t2 and t1 may be less than the difference between t iso and t2. The second thickness t2 may be within the range of the gate dielectric thickness of the selector device or equal to the gate dielectric thickness of the selector device (see details below), and the isolation dielectric is, for example, significantly thicker.

[0016] The first thickness t1 may be at least 1.5 nm and / or at most 5 nm. The second thickness t2 may be at least 4 nm and / or at most 30 nm. The isolation dielectric thickness t iso may be at least 100 nm and / or at most 900 nm.

[0017] As described above, the selector device may have a gate region for controlling the current flow or conductivity of the channel region. The gate region may include a gate electrode and a gate dielectric that capacitively couples the gate electrode to the channel region. In an embodiment, the gate dielectric of the selector device has the same thickness as a second dielectric. It may be formed of the same material, for example deposited in the same process step. In other words, the second dielectric may be made of a gate oxide (such as silicon oxide).

[0018] In an embodiment, the centroid of the second region is located within the first region. This relates to a vertical top view, and the centroid is the geometric center of the second region. In other words, the first region may be centered within the second region.

[0019] In an embodiment, the area ratio of the first region (first dielectric) to the second region (second dielectric) is at least 1 / 100, with additional lower limits being, for example, 3 / 100 and 5 / 100. Alternatively or additionally, the area ratio may not exceed 3 / 4, 1 / 2, 1 / 4, or 1 / 5. Specifically, considering the contour of the second region, the area of the second region may be obtained by subtracting the first region from the area inside the contour (the second region has a "hole" where the first region is arranged).

[0020] In an embodiment, the first capacitor electrode of the otp capacitor is arranged below the capacitor dielectric, for example embedded in the semiconductor body. The first capacitor electrode may be a doped region in the semiconductor body, for example arranged on the first side of the semiconductor body. It can be formed, for example, in an epitaxial layer or layer system arranged on a semiconductor substrate.

[0021] In an embodiment, the channel region of the selector device reaches below the otp capacitor dielectric, for example below the first dielectric. On the otp capacitor dielectric, a second capacitor electrode may be arranged, which also serves as the gate electrode of the selector device in an embodiment. In other words, the otp capacitor is embedded in the selector device. The integrated gate electrode / second capacitor electrode may be formed, for example, in a polysilicon layer, for example a polysilicon electrode.

[0022] In an embodiment, the corresponding selector device with the embedded otp capacitor is not provided with a drain region. In other words, the body region of the selector device may serve as the first capacitor electrode, and the second capacitor electrode above also serves as the gate electrode.

[0023] In an alternative embodiment, for example in addition to the source region and the body region, the selector device includes a drain region. A channel region may be formed in the body region, for example laterally located between the source region and the drain region. In combination with the embedded otp capacitor discussed above, the drain region of the selector device may be used as a first capacitor electrode, for example arranged below the otp capacitor dielectric. The source region and the drain region may have a first doping type, and the body region has a second doping type. In an exemplary embodiment, the first type is n-type and the second type is p-type.

[0024] In an embodiment, the second capacitor electrode arranged on the otp capacitor dielectric and the gate electrode of the selector device are electrically isolated from each other. This may be an alternative to an embedded second capacitor electrode also serving as a gate electrode. The gate and capacitor electrodes electrically isolated from each other may be connected as a word line and a bit line, the gate electrode of the selector device being for example a word line and the second capacitor electrode being for example a bit line.

[0025] Although electrically isolated from each other, the gate electrode and the second capacitor electrode of the selector device may be formed in the same material layer. This may for example be a polysilicon layer in which a polysilicon gate electrode and a polysilicon capacitor electrode are formed.

[0026] In an embodiment, the selector device includes a drift region. The drift region may be arranged beside the body region, which may for example be a depletable region. In the case where the selector device has a drain region, the drift region may be made of the same doping type as the drain region but with a lower doping concentration. The drift region may then be arranged laterally between the body region and the drain region.

[0027] In an embodiment, the isolation dielectric at least partially covers the drift region. As observed in a vertical cross-section, the isolation dielectric may be arranged laterally between the source region / body region of the selector device and the otp capacitor. Seen in a vertical top view, a second region (second dielectric) may be embedded in a third region made of the isolation dielectric. The second dielectric may then merge directly into the isolation dielectric in each lateral direction.

[0028] The drain region of the selector device may be used as a first capacitor electrode, see the above comments. In an alternative embodiment, the drain region of the selector device is arranged laterally beside the otp capacitor. The otp capacitor may be connected in series to the drain region of the selector device, for example the first capacitor electrode is connected in series to the drain region. For example via a doping region that also serves as the first capacitor electrode (see above), such an electrical connection may be formed in the semiconductor body, and / or for example via a metallization layer, such an electrical connection may be formed in a wiring structure on the semiconductor body.

[0029] The embodiment relates to a semiconductor die including an OTP element. Additionally, at least one of a DMOS device, a CMOS device, or a bipolar device may be formed in the semiconductor die, for example integrated in the same semiconductor body. In other words, the OTP element may be integrated, for example, in a BD or BCD technology (bipolar, CMOS, DMOS). In an embodiment, the selector device and the DMOS device may have the same gate dielectric thickness.

[0030] In an embodiment, a method of manufacturing an OTP element or a semiconductor die is provided. It may include:

[0031] - forming a selector device;

[0032] - forming an OTP capacitor having an OTP capacitor dielectric;

[0033] - forming an isolation dielectric.

[0034] Wherein, at least to some extent, the formation of the selector device and the formation of the OTP capacitor may be completed simultaneously. For example, the gate electrode of the selector device and the second capacitor electrode may be fabricated simultaneously, and / or the second dielectric and the gate dielectric of the selector device may be fabricated simultaneously, and / or the first capacitor electrode and the drain region of the selector device may be fabricated simultaneously.

[0035] In an embodiment, a method of programming a plurality of OTP elements is provided. It may include: causing breakdown of the capacitor dielectric of at least one of the OTP elements in the OTP element by a control pulse (e.g., a programming pulse). BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Hereinafter, the OTP element, the semiconductor die, and the related methods are explained in more detail by means of exemplary embodiments. Among them, individual features may also be relevant to the present disclosure in different combinations.

[0037] Figure 1a A first embodiment of the OTP element is shown in a vertical cross-section;

[0038] Figure 1b Shown Figure 1a A detailed view of the OTP capacitor dielectric of the OTP element;

[0039] Figure 1c Shown in a vertical top view Figure 1a The OTP element;

[0040] Figure 2a A second embodiment of the OTP element is shown in a vertical cross-section;

[0041] Figure 2b Shown Figure 2aDetailed view of the OTP capacitor dielectric of the OTP element, with the sectional plane parallel to the length direction;

[0042] Figure 2c Shown in a vertical top view Figure 2a of the OTP element;

[0043] Figure 2d Shown Figure 2a detailed view of the OTP capacitor dielectric of the OTP element of a, c, with the sectional plane perpendicular to the length direction;

[0044] Figure 3a A third embodiment of the OTP element is shown in a vertical cross-section;

[0045] Figure 3b Shown Figure 3a detailed view of the OTP capacitor dielectric of the OTP element, with the sectional plane parallel to the length direction;

[0046] Figure 3c Shown in a vertical top view Figure 3a of the OTP element;

[0047] Figure 3d Shown Figure 3a detailed view of the OTP capacitor dielectric of the OTP element of a, c, with the sectional plane perpendicular to the length direction;

[0048] Figure 4 A semiconductor die having a plurality of OTP elements is shown;

[0049] Figure 5a Some manufacturing steps are summarized;

[0050] Figure 5b A method of using the OTP element is illustrated. Detailed Description

[0051] Figure 1a A one-time programmable (OTP) element 10 is shown in a vertical cross-section. The OTP element 10 includes a selector device 20 and an OTP capacitor 40. The OTP capacitor 40 includes a first capacitor electrode 41, a second capacitor electrode 42, and an OTP capacitor dielectric 50 located between the capacitor electrodes 41, 42 in the vertical direction. Due to the reason of picture representation, the OTP capacitor dielectric 50 is only schematically shown in Figure 1a and is discussed in more detail with reference to Figure 1b

[0052] Figure 1a ​The selector device 20 includes a source region 25, a body region 21, and a drain region 26. Additionally, a drift region 27 may be laterally disposed between the body region 21 and the drain region 26. In the illustrated example, the source region 25, the drain region 26, and the drift region 27 are n-doped, and the drift region 27 has a lower concentration compared to the drain region 26. In the body region 21 (in this example, the body region 21 is p-doped), a channel region 21.1 is formed. Through the gate electrode 22, the current flow in the channel region can be controlled. Through the gate dielectric 23, the gate electrode 22 is capacitively coupled to the channel region 21.1, where the gate dielectric 23 is not shown in more detail as a dedicated element for the same reasons as those mentioned for the otp capacitor dielectric 50.

[0053] Laterally between the selector device 20 and the otp capacitor 40, an isolation dielectric 60 is disposed. It partially covers the drift region 27 and surrounds the otp capacitor dielectric 50 (see Figure 1c ). In the illustrated example, the isolation dielectric is a LOCOS structure, i.e., obtained by local oxidation of silicon. As an example, it may have a thickness t of approximately 350 nm iso .

[0054] Figure 1b An enlarged view is shown (see the dashed line in Figure 1a ), and the capacitor dielectric 50 is illustrated in more detail. The capacitor dielectric 50 includes a first dielectric 51 having a first thickness t1 and a second dielectric 52 having a second thickness t2, where the first thickness t1 is less than the second thickness t2. In the illustrated example, the second thickness t2 is approximately twice the first thickness t1 (t1 is, for example, 2.5 nm and t2 is 5 nm). As discussed in the general description, a thinner dielectric embedded in a thicker dielectric can, for example, improve the programming quality, such as providing a reliable dielectric breakdown. In the illustrated embodiment, the first capacitor electrode 41 is a doped region 126 in the semiconductor body 30, where the doped region 126 also forms the drain region 26 of the selector device 20.

[0055] Figure 1c The otp cell 10 is illustrated in a vertical top view Figure 1a . Generally, in the present disclosure, like reference numerals indicate like elements or elements having similar functions, and are also respectively referred to the descriptions of other drawings. The gate electrode 22 widely covers the selector device 20, and on the left side, the body implant and the source region 25 of the body region 21 are visible.

[0056] Below the second capacitor electrode 42 of the OTP capacitor 40, the capacitor dielectric 50 is arranged (shown by the dashed line). The first dielectric 51 is arranged in the first region 71, and the second dielectric 52 is arranged in the second region 72. The first dielectric 51 is delimited by the second dielectric 52 on all lateral sides. In the illustrated example, the first region 71 is arranged at a rather central position in the second region 72. For example, the centroid 72.1 of the second region 72 is located in the first region 71. The isolation dielectric 60 is arranged in the third region 73, and the capacitor dielectric 50 is embedded in the third region 73.

[0057] Figure 1a , the cross-sectional plane of a and b is parallel to the length direction 80, and the length direction 80 is the direction of current flow in the channel region ( Figure 1c not labeled). The channel region is covered by the gate electrode 22. For illustration, the lateral extension 86 of the channel region is labeled.

[0058] Figure 2a Another OTP element 10 with a selector device 20 and an OTP capacitor 40 is illustrated. As in Figure 1a the embodiment, the first capacitor electrode 41 is a doped region 126 embedded in the semiconductor body 30. However, the drain region 26 of the selector device 20 is a separate doped region, and the OTP capacitor 40 is connected in series to the drain region 26, for example, connected to the selector device 20. The doped region 126 may have the same doping type as the drain region 26, such as n-doping, but with a lower doping concentration.

[0059] As in Figure 1a the example, the gate electrode 22 of the selector device and the second capacitor electrode 42 are formed in the same material layer 90. In the illustrated example, they are formed in the polysilicon layer 91. However, the gate electrode 22 and the second capacitor electrode 42 are electrically isolated from each other and can be connected as word lines and bit lines.

[0060] Figure 1a and 2a the difference between the embodiments lies in the arrangement of the isolation dielectric 60. In Figure 2a , the isolation dielectric 60 is not provided between the channel region 21.1 and the OTP capacitor 40. In the length direction 80, the second dielectric 52 is directly merged into the isolation dielectric 60 only on one side, that is, directly merged into the isolation dielectric 60 on the right side in the Figure 2b detailed view. In addition, the OTP capacitor dielectric 50 includes the first dielectric 51 and the second dielectric 52 with different thicknesses t1 and t2, as discussed in detail for Figure 1b .

[0061] As inFigure 2c As indicated in the vertical top view of Figure 2c (where the channel region is not labeled), the lateral extension 86 of the channel region corresponds to the extension of the gate electrode 22 in the length direction 80. Between the gate electrode 22 and the second capacitor electrode 42, the drain region 26 of the selector device 20 is visible. The OTP capacitor dielectric 50 is disposed below the second capacitor electrode 42 and includes a first dielectric 51 in a first region 71 and a second dielectric 52 in a second region 72. Compared with the embodiments of Figure 1a , c, the third region 73 with the isolation dielectric 60 extends only in a U-shape around the OTP capacitor dielectric 50 (see also Figure 2b for the cross-sectional view).

[0062] Figure 2d Another cross-sectional view showing the capacitor dielectric 50 is presented, where the cross-sectional plane is perpendicular to the length direction 80 (see Figure 2c in BB for comparison). In the cross-sectional view of Figure 2d , the second dielectric 52 merges directly into the isolation dielectric 60 on both sides.

[0063] Figure 3a Another OTP element 10 with a selector device 20 and an OTP capacitor 40 is illustrated. The channel region 21.1 formed in the body region 21 extends between the source region 25 and the drain region 26, which also serves as the first capacitor electrode 41. The channel region 21.1 reaches below the capacitor dielectric 50, see Figure 3a and 3b for comparison. Compared with the above embodiments, the second capacitor electrode 42 is formed integrally with the gate electrode 22. In other words, the second capacitor electrode 42 also serves as the gate electrode 22 of the selector device 20. In the illustrated example, a continuous polysilicon plate is provided for the selector device 20 and the OTP capacitor 40.

[0064] Figure 3b A detailed view of the OTP capacitor dielectric 50 is shown in a cross-sectional plane parallel to the length direction 80, see the comments regarding Figure 1b and 2b . Only on one side, that is, on the right side in Figure 3b , the second dielectric 52 merges directly into the isolation dielectric 60.

[0065] Figure 3c The vertical top view of Figure 2c illustrates the first region 71 embedded in the second region 72, where the third region 73 with the isolation dielectric 60 surrounds the OTP capacitor dielectric 50 in a U-shape, see Figure 2cComments in. In a vertical cross-section perpendicular to the length direction 80, the second dielectric 52 is incorporated into the isolation dielectric 60 on both sides, see Figure 3d .

[0066] Figure 4 Schematically illustrates the integration of a plurality of OTP elements 10 in a semiconductor die 1. The OTP elements 10 are arranged on a first side 30.1 of a semiconductor body 30, where a metallization system 130 provided for wiring is arranged on an insulating layer 140 located on the first side 30.1 of the semiconductor body 30. The metallization system 130 may include one or more metallization layers, but is only schematically shown. To connect to individual structures formed in the semiconductor body 30, vertical interconnects extending through the insulating layer 140 may be provided, which are not shown in detail here.

[0067] Together with the OTP elements 10, a DMOS device 150 and / or a CMOS device 160 and / or a bipolar device 170 may be provided. For example, in combination with lateral or vertical current routing, such as through a sinker injection (not shown), the DMOS device 150 can be used for load switching. The CMOS device 170 can allow the integration of logic functions, and / or the bipolar device 170 can be used for protection structures.

[0068] Figure 5a Summarize some manufacturing steps, such as the formation 181 of the selector device 20, the formation 182 of the OTP capacitor 40 having the OTP capacitor dielectric 50, and the formation 183 of the isolation dielectric 60. To at least some extent, these steps can be completed simultaneously.

[0069] Figure 5b Summarize some method steps for programming one or more OTP elements 10. It includes: providing 191 a plurality of OTP elements 10, selecting 192 at least one OTP element 10 that must be programmed (permanently switched to a conductive state), and causing 193 the breakdown of the OTP capacitor dielectric 50 of one or more corresponding elements 10 through a control pulse.

[0070] In the form of the following examples, the embodiments and features of the present application can be summarized as:

[0071] 1. A one-time programmable (OTP) element (10), comprising:

[0072] A selector device (20) having a channel region (21.1);

[0073] An OTP capacitor (40) having an OTP capacitor dielectric (50) associated with the selector device (20);

[0074] Isolation dielectric (60) having an isolation dielectric thickness t iso ;

[0075] The otp capacitor dielectric (50) includes a first dielectric (51) in a first region (71) and a second dielectric (52) in a second region (72),

[0076] The second dielectric (52) has a second thickness t2 that is less than the isolation dielectric thickness t iso of the second thickness t2,

[0077] and the first dielectric (51) has a first thickness t1 that is less than the second thickness t2, wherein the first region (71) is embedded in the second region (72).

[0078] 2. The otp element (10) according to Example 1, wherein as observed in a vertical cross-section passing through the first dielectric (51) and parallel to the length direction (80) of the channel region (21.1), the second dielectric (52) is directly incorporated into the isolation dielectric (60) on at least one side.

[0079] 3. The otp element (10) according to Example 1 or 2, wherein as observed in a vertical cross-section passing through the first dielectric (51) and perpendicular to the length direction (80) of the channel region (21.1), the second dielectric (52) is directly incorporated into the isolation dielectric (60) on both sides.

[0080] 4. The otp element (10) according to any one of the preceding examples, wherein the second thickness t2 is at least 1.5 times and / or at most 20 times the first thickness t1.

[0081] 5. The otp element (10) according to any one of the preceding examples, wherein the isolation dielectric thickness t iso is at least 10 times and / or at most 100 times the second thickness t2.

[0082] 6. The otp element (10) according to any one of the preceding examples, having at least one of the following cases:

[0083] The first thickness t1 is at least 1.5 nm and / or at most 5 nm,

[0084] The second thickness t2 is at least 4 nm and / or at most 30 nm, and

[0085] The isolation dielectric thickness t iso is at least 100 nm and / or at most 900 nm.

[0086] 7. The OTP primitive (10) as described in any of the previous examples, wherein the selector device (20) includes a gate electrode (22) and a gate dielectric (23) that capacitively couples the gate electrode (22) to the channel region (21.1), and wherein the gate dielectric (23) has the same thickness as the second dielectric (52).

[0087] 8. The OTP primitive (10) as described in any of the previous examples, wherein, when viewed in a vertical top view, the centroid (72.1) of the second region (72) is located within the first region (71).

[0088] 9. The OTP primitive (10) as described in any of the previous examples, wherein the first region (71) and the second region (72) have an area ratio of at least 1 / 100 and / or at most 3 / 4.

[0089] 10. The OTP primitive (10) as described in any of the previous examples, wherein the OTP capacitor (40) includes a first capacitor electrode (41) located beneath the OTP capacitor dielectric (50), and wherein the first capacitor electrode (41) is a doped region (126) embedded in the semiconductor body (30).

[0090] 11. The OTP primitive (10) as described in any of the previous examples, wherein the OTP capacitor (40) includes a second capacitor electrode (42) on the OTP capacitor dielectric (50), wherein the channel region (21.1) reaches beneath the OTP capacitor dielectric (50), and wherein the second capacitor electrode (42) also serves as the gate electrode (22) of the selector device (20).

[0091] 12. The OTP primitive (10) as described in any of Examples 1 to 10, wherein the selector device (20) includes a source region (25), a body region (21), and a drain region (26), and a channel region (21.1) formed in the body region (21) is laterally located between the source region (25) and the drain region (26).

[0092] 13. The OTP primitive (10) as described in Example 12 in combination with one of Examples 1 to 10, wherein the second capacitor electrode (42) of the OTP capacitor (40) and the gate electrode (22) of the selector device (20) are formed in the same material layer (90), such as a polysilicon layer (91), and are electrically isolated from each other.

[0093] 14. The OTP primitive (10) as described in any of the previous examples, wherein the selector device (20) further includes a drift region (27).

[0094] 15. The OTP primitive (10) as described in Example 14, wherein the isolation dielectric (60) covers at least a portion of the drift region (27), and the second region (72) is embedded in a third region (73) made of the isolation dielectric (60).

[0095] 16. The opt primitive (10) as described in Examples 10 and 12, optionally in combination with one of Examples 13 to 15, wherein the drain region (26) of the selector device (20) serves as the first capacitor electrode (41) under the OTP capacitor dielectric (50).

[0096] 17. The opt primitive (10) as described in Example 12, optionally in combination with one of Examples 13 to 16, wherein the drain region (26) of the selector device (20) is laterally arranged beside the first capacitor electrode (41) under the OTP capacitor dielectric (50) and is electrically connected in series to the first capacitor electrode (41) under the OTP capacitor dielectric (50).

[0097] 18. A semiconductor die (1), comprising:

[0098] The OTP primitive (10) as described in any of the previous examples; and

[0099] At least one of a DMOS device (150), a CMOS device (160), or a bipolar device (170).

[0100] 19. The semiconductor die (1) as described in Example 18, wherein the gate dielectrics (23) of the selector device (20) and the DMOS device (150) have the same thickness.

[0101] 20. A method of manufacturing the OTP primitive (10) as described in any of Examples 1 to 17 or the semiconductor die (1) as described in Example 18 or 19, comprising:

[0102] - Forming (181) the selector device (20);

[0103] - Forming (182) the OTP capacitor (40) having the OTP capacitor dielectric (50);

[0104] - Forming (183) the isolation dielectric (60).

[0105] 21. A method of programming a plurality of OTP primitives (10) as described in any of Examples 1 to 17 in a semiconductor die (1) as described in Example 18 or 19, for example, comprising:

[0106] - Cause breakdown of the OTP capacitor dielectric (50) of at least one OTP element (10) among the OTP elements (10) by controlling a pulse.

Claims

1. One-time programmable (OTP) element (10), comprising: Selector device (20) having a channel region (21.1); OTP capacitor (40) having an OTP capacitor dielectric (50) associated with the selector device (20); Isolation dielectric (60) having an isolation dielectric thickness t iso ; The OTP capacitor dielectric (50) includes a first dielectric (51) in a first region (71) and a second dielectric (52) in a second region (72), The second dielectric (52) has a second thickness t2 that is less than the isolation dielectric thickness t iso ​ And the first dielectric (51) has a first thickness t1 that is less than the second thickness t2, Wherein the first region (71) is embedded in the second region (72).

2. The OTP element (10) according to claim 1, wherein as observed in a vertical cross-section passing through the first dielectric (51) and parallel to the length direction (80) of the channel region (21.1), the second dielectric (52) directly merges into the isolation dielectric (60) on at least one side.

3. The OTP element (10) according to claim 1 or 2, wherein as observed in a vertical cross-section passing through the first dielectric (51) and perpendicular to the length direction (80) of the channel region (21.1), the second dielectric (52) directly merges into the isolation dielectric (60) on both sides.

4. The OTP element (10) according to any one of the preceding claims, wherein the second thickness t2 is at least 1.5 times and / or at most 20 times the first thickness t1.

5. The OTP element (10) according to any one of the preceding claims, wherein the isolation dielectric thickness t iso is at least 10 times and / or at most 100 times the second thickness t2.

6. The OTP element (10) according to any one of the preceding claims, having at least one of the following: The first thickness t1 is at least 1.5 nm and / or at most 5 nm, The second thickness t2 is at least 4 nm and / or at most 30 nm, and The thickness t of the isolation dielectric iso is at least 100 nm and / or at most 900 nm.

7. The OTP element (10) according to any one of the preceding claims, the selector device (20) includes a gate electrode (22) and a gate dielectric (23) that capacitively couples the gate electrode (22) to the channel region (21.1), wherein the gate dielectric (23) has the same thickness as the second dielectric (52).

8. The OTP element (10) according to any one of the preceding claims, wherein in a vertical top view, the centroid (72.1) of the second region (72) is located in the first region (71).

9. The OTP element (10) according to any one of the preceding claims, wherein the first region (71) and the second region (72) have an area ratio of at least 1 / 100 and / or at most 3 / 4.

10. The OTP element (10) according to any one of the preceding claims, the OTP capacitor (40) includes a first capacitor electrode (41) below the OTP capacitor dielectric (50), wherein the first capacitor electrode (41) is a doped region (126) embedded in the semiconductor body (30).

11. The OTP element (10) as claimed in any one of the preceding claims, wherein the OTP capacitor (40) comprises a second capacitor electrode (42) on the OTP capacitor dielectric (50), wherein the channel region (21.1) reaches below the OTP capacitor dielectric (50), and the second capacitor electrode (42) also serves as the gate electrode (22) of the selector device (20).

12. The OTP element (10) as claimed in any one of claims 1 to 10, wherein the selector device (20) comprises a source region (25), a body region (21) and a drain region (26), and the channel region (21.1) formed in the body region (21) is laterally located between the source region (25) and the drain region (26).

13. The OTP element (10) as claimed in claim 12 in combination with one of claims 1 to 10, wherein the second capacitor electrode (42) of the OTP capacitor (40) and the gate electrode (22) of the selector device (20) are formed in the same material layer (90), such as a polysilicon layer (91), and are electrically isolated from each other.

14. The OTP element (10) as claimed in any one of the preceding claims, wherein the selector device (20) further comprises a drift region (27).

15. The OTP element (10) as claimed in claim 14, wherein the isolation dielectric (60) covers at least a part of the drift region (27), and the second region (72) is embedded in a third region (73) made of the isolation dielectric (60).

16. The opt element (10) as claimed in claims 10 and 12, optionally in combination with one of claims 13 to 15, wherein the drain region (26) of the selector device (20) serves as the first capacitor electrode (41) below the OTP capacitor dielectric (50).

17. The opt element (10) as claimed in claim 12, optionally in combination with one of claims 13 to 16, wherein the drain region (26) of the selector device (20) is laterally arranged beside the first capacitor electrode (41) below the OTP capacitor dielectric (50) and is electrically connected in series to the first capacitor electrode (41) below the OTP capacitor dielectric (50).

18. A semiconductor die (1), comprising: the OTP element (10) as claimed in any one of the preceding claims; and at least one of a DMOS device (150), a CMOS device (160) or a bipolar device (170).

19. The semiconductor die (1) as claimed in claim 18, wherein the gate dielectric (23) of the selector device (20) and the gate dielectric of the DMOS device (150) have the same thickness.

20. A method of manufacturing the OTP element (10) as claimed in any one of claims 1 to 17 or the semiconductor die (1) as claimed in claim 18 or 19, comprising: - Forming (181) the selector device (20); - Forming (182) the OTP capacitor (40) having the OTP capacitor dielectric (50); - Forming (183) the isolation dielectric (60).

21. A method of programming a plurality of OTP primitives (10) as described in any one of claims 1 to 17 in a semiconductor die (1) as described in, for example, claim 18 or 19, comprising: - Causing breakdown of the OTP capacitor dielectric (50) of at least one OTP primitive (10) in the OTP primitives (10) by a control pulse.

Images