Fast recovery diode and preparation method and application thereof

Abstract

The invention discloses a fast recovery diode and a preparation method and application thereof. The fast recovery diode comprises a substrate, a first epitaxial layer, a second epitaxial layer, an oxide layer, a first electrode and a second electrode. The second epitaxial layer is located on the side, away from the substrate, of the first epitaxial layer, a groove-shaped second type doped ion implantation region is arranged on the side, away from the first epitaxial layer, of the second epitaxial layer, and the inner side wall in the second type doped ion implantation region has higher second type doping concentration. The oxide layer has a gap for defining a second type doped ion implantation region. When the device is close to a working current, the current flows in an outer channel of the groove-shaped structure with relatively low doping concentration in the second type doped ion implantation region, so that low implantation efficiency is realized, the reverse overshoot current of the fast recovery diode under the working current is reduced, and finally, the time required for reverse recovery of the device can be effectively reduced.

Description

Technical Field

[0001] The present application relates to the technical field of semiconductor devices, and particularly relates to a fast recovery diode and its manufacturing method and application. Background Art

[0002] With the rapid development of the new energy field, the performance of power devices faces higher challenges. To reduce the energy loss of the power supply system, the core requirement is to further optimize the switching loss and conduction loss of power devices. Among them, the optimization directions of switching devices (such as MOSFETs, IGBTs) include increasing the channel density, reducing the impedance of the drift region, reducing the chip thickness, etc. Along with the performance improvement of switching devices, the freewheeling device also needs to obtain higher dv / dt tolerance, lower conduction voltage drop, faster turn-off speed, lower turn-off stress, etc.

[0003] Currently, traditional freewheeling devices generally use fast recovery diodes. The fast recovery diode belongs to the PIN junction diode. To achieve good ohmic contact, high-concentration doping needs to be realized on the anode surface, and a relatively thick voltage-resistant layer is used to provide sufficient blocking voltage. For example, for silicon material devices, a voltage-resistant layer of more than 60 μm is required for a voltage rating of 650V, and a voltage-resistant layer of more than 100 μm is required for a voltage rating of 1200V; for silicon carbide material devices, a voltage-resistant layer of more than 6 μm is required for a voltage rating of 650V, and a voltage-resistant layer of more than 10 μm is required for a voltage rating of 1200V.

[0004] When the freewheeling device is conducting, the large injection effect occurs in the voltage-resistant layer, providing a large number of electrons and holes that can be used for conduction, and reducing the resistance of the voltage-resistant layer. These electrons and holes are called excess carriers. When the freewheeling device needs to be turned off, these stored majority carriers need to be exported through the anode and the cathode. The time required to export this part of the majority carriers and form a blocking voltage between the anode and the cathode is the reverse recovery time of the fast recovery diode. Reducing this time is very helpful for high-speed switching usage scenarios. Therefore, it is necessary to improve the traditional fast recovery diode. Summary of the Invention

[0005] The present application aims to at least solve one of the technical problems existing in the prior art. For this purpose, the present application provides a fast recovery diode and its manufacturing method and application.

[0006] In the first aspect of the present application, a fast recovery diode is provided, which includes:

[0007] A substrate having a first-type doping;

[0008] A first epitaxial layer located on one side of the substrate, the first epitaxial layer having a first-type doping;

[0009] The second epitaxial layer is located on the side of the first epitaxial layer away from the substrate, and the second epitaxial layer has a first-type doping; on the side of the second epitaxial layer away from the first epitaxial layer, there is a grooved second-type doping ion implantation region, and the inner sidewall in the second-type doping ion implantation region has a higher second-type doping concentration;

[0010] The oxide layer is located on the side of the second epitaxial layer away from the first epitaxial layer, and the oxide layer has a void for defining the second-type doping ion implantation region;

[0011] The first electrode includes a first part and a second part that are interconnected. The first part is located on the side of the oxide layer away from the second epitaxial layer, and the second part is located in the void and contacts the second-type doping ion implantation region;

[0012] The second electrode is located on the side of the substrate away from the first epitaxial layer.

[0013] The fast recovery diode according to the embodiment of the present application has at least the following beneficial effects:

[0014] By using the distribution structure of different concentrations in the second-type doping ion implantation region, when the device is near the operating current point, the current flows through the outer channel of the grooved structure with a lower doping concentration in the second-type doping ion implantation region, and when it is greater than the operating current point, the current flows through the channel of the inner sidewall with a higher doping concentration. Thus, the anode injection efficiency has the characteristic of self-adjustment at different current densities. When near the operating current point, the current flows through the outer channel, achieving a low injection efficiency, reducing the reverse overshoot current of the fast recovery diode at the operating current, and ultimately being able to effectively reduce the time required for the device to reverse recover.

[0015] Among them, the operating current refers to the current that the device needs to process when the device conducts or turns off. According to the temperature or power that the device can withstand, a relatively reasonable operating current is defined as the operating current point.

[0016] In some embodiments of the present application, the aspect ratio of the second-type doping ion implantation region is 1:(5 - 20).

[0017] In some embodiments of the present application, the initial doping concentration at the position other than the inner sidewall in the second-type doping ion implantation region is 5×10 14 ~1×10 19 / cm 3 , and the initial doping concentration of the inner sidewall is 1×10 14 ~1×10 19 / cm 3 . In some embodiments of the present application, the thickness of the oxide layer is 500 Å - 20000 Å.

[0018] In some embodiments of the present application, an insulating layer is further provided between the oxide layer and the first electrode.

[0019] In some embodiments of the present application, a passivation layer is further provided on the side of the first electrode away from the oxide layer.

[0020] In a second aspect of the present application, a method for manufacturing a fast recovery diode is provided. The manufacturing method includes the following steps:

[0021] A first epitaxial layer, a second epitaxial layer, and an oxide layer are sequentially formed on a substrate;

[0022] Void spaces are formed in the oxide layer by etching;

[0023] The second epitaxial layer is subjected to a first ion implantation by the void spaces, and a grooved second-type doped ion implantation region is formed by etching;

[0024] The surface of the second-type doped ion implantation region is subjected to a second ion implantation, and the bottom portion of the second ion implantation is removed by etching;

[0025] A first electrode and a second electrode are formed.

[0026] In some embodiments of the present application, the implantation dose of the first ion implantation is 5×10 12 ~1×10 14 / cm 2 。

[0027] In some embodiments of the present application, the energy of the first ion implantation is 20 - 2000 keV.

[0028] In some embodiments of the present application, the implantation dose of the second ion implantation is 1×10 12 ~1×10 14 / cm 2 。

[0029] In some embodiments of the present application, the energy of the second ion implantation is 20 - 100 keV.

[0030] In a third aspect of the present application, an electronic system is provided. The electronic system includes the aforementioned fast recovery diode.

[0031] In a fourth aspect of the present application, an electrical device is provided. The electrical device includes the aforementioned fast recovery diode or the aforementioned electronic system.

[0032] In the above-mentioned fast recovery diode, through the design of different shaped structures of the oxide layer, different voids can be formed, thereby autonomously changing the shape of the second-type doped ion implantation region, achieving different effective areas, decoupling the implantation efficiency from the effective area of the chip, and facilitating the adjustment of different implantation efficiencies. The anode of this device is self-aligned etched through the oxide layer shielding, forming a distribution morphology of different concentrations of the second doping type. Therefore, through reasonable design of the above two advantages, when the device is near the operating current, the current flows through the channel with lower second-type doping, and when the operating current is larger, the current flows through the channel with higher second-type doping. Thus, the anode implantation efficiency has the characteristic of self-adjustment at different current densities. At the same time, when near the operating current, the current flows through the channel with lower second-type doping, achieving a low implantation efficiency, reducing the reverse overshoot current of the fast recovery diode at the operating current, and ultimately reducing the time required for the device to reverse recover.

[0033] Additional aspects and advantages of the present application will be given in part in the following description, become apparent in part from the following description, or be learned through the practice of the present application. BRIEF DESCRIPTION OF THE DRAWINGS

[0034] Figure 1 is a structural diagram of a traditional fast recovery PIN diode.

[0035] Figure 2 is a schematic structural diagram of a self-aligned fast recovery diode in some embodiments of the present application.

[0036] Figure 3 is a schematic diagram of forming a first epitaxial layer on a substrate in some embodiments of the present application.

[0037] Figure 4 is a schematic diagram of forming a second epitaxial layer on the first epitaxial layer in some embodiments of the present application.

[0038] Figure 5 is a schematic diagram of forming an oxide layer on the second epitaxial layer in some embodiments of the present application.

[0039] Figure 6 is a schematic diagram of forming a first photoresist layer on the oxide layer in some embodiments of the present application.

[0040] Figure 7 is a schematic diagram of the oxide layer transferring the pattern of the first photoresist layer in some embodiments of the present application.

[0041] Figure 8 is a schematic diagram of performing a primary ion implantation using the voids of the oxide layer in some embodiments of the present application.

[0042] Figure 9 In some embodiments of the present application, it is a schematic diagram of forming a topography with a certain aspect ratio on the surface of the second epitaxial layer 230 by etching.

[0043] Figure 10 In some embodiments of the present application, it is a schematic diagram of performing secondary ion implantation using the voids in the oxide layer.

[0044] Figure 11 In some embodiments of the present application, it is a schematic diagram of retaining the highly doped inner sidewalls by etching after secondary ion implantation.

[0045] Figure 12 In some embodiments of the present application, it is a schematic diagram of growing an insulating layer on the surfaces of the oxide layer and the second-type doped ion implantation region.

[0046] Figure 13 In some embodiments of the present application, it is a schematic diagram of forming a second photoresist layer on the insulating layer.

[0047] Figure 14 In some embodiments of the present application, it is a schematic diagram of forming contact hole patterns in the insulating layer by photolithography.

[0048] Figure 15 In some embodiments of the present application, it is a schematic diagram of forming a first electrode.

[0049] Figure 16 In some embodiments of the present application, it is a schematic diagram of forming a passivation layer having a pad region and a protection region on the surface of the first electrode.

[0050] Figure 17 In some embodiments of the present application, it is a schematic diagram of substrate thinning.

[0051] Reference numerals: Substrate 101, Buffer layer 102, Voltage-resistant layer 103, Anode 104, Anode electrode 105, Cathode 106, Substrate 210, First epitaxial layer 220, Second epitaxial layer 230, Second-type doped ion implantation region 231, Inner sidewall 232, Oxide layer 240, First electrode 250, First part 251, Second part 252, Second electrode 260, Insulating layer 270, Passivation layer 280, Pad region 281, First photoresist layer 310, Second photoresist layer 320, Second doping region 330. Detailed embodiments

[0052] The following will clearly and completely describe the concept of this application and the technical effects produced in combination with the embodiments, so as to fully understand the purpose, features and effects of this application. Obviously, the described embodiments are only a part of the embodiments of this application, rather than all embodiments. Based on the embodiments of this application, other embodiments obtained by those skilled in the art without creative efforts all fall within the scope of protection of this application.

[0053] The embodiments of this application will be described in detail below. The described embodiments are exemplary and are only used to explain this application, and should not be construed as a limitation of this application.

[0054] In the description of this application, the meaning of "several" is more than one, the meaning of "multiple" is more than two, "greater than", "less than", "exceeding", etc. are understood as not including the number itself, and "above", "below", "within", etc. are understood as including the number itself. If the first and second are described only for the purpose of distinguishing technical features, they should not be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence of the indicated technical features.

[0055] Unless otherwise defined, all technical and scientific terms used in this application have the same meaning as commonly understood by those skilled in the technical field to which this application belongs. The terms used herein are only for the purpose of describing the embodiments of this application and are not intended to limit this application. The specific features, structures, materials or characteristics described may be combined in a suitable manner in any one or more embodiments or examples.

[0056] Reference Figure 1 , which shows the structure of a traditional fast recovery diode. Adopting a PIN structure, it includes a cathode 106, a substrate 101, a buffer layer 102, a voltage withstand layer 103, an anode 104, and an anode electrode 105 arranged in sequence. To achieve good ohmic contact, it is necessary to achieve 1×10 19 ~1×10 20 / cm 3The doping concentration is required, and at the same time, a relatively thick voltage withstand layer 103 and a buffer layer 102 are needed to provide sufficient blocking voltage. For silicon material devices, the blocking voltage is generally 10V / μm. For a voltage class of 650V, a voltage withstand layer 103 with a thickness of at least 60μm is required, and for a voltage class of 1200V, a voltage withstand layer 103 with a thickness of at least 100μm is required. For silicon carbide material devices, the blocking voltage is generally 100V / um. For a voltage class of 650V, a voltage withstand layer 103 with a thickness of at least 6μm is required, and for a voltage class of 1200V, a voltage withstand layer 103 with a thickness of at least 10μm is required. When the fast recovery diode is conducting, a large injection effect occurs in the voltage withstand layer 103, providing a large number of electrons and holes that can be used for conduction. These electrons and holes, called excess carriers, reduce the resistance of the voltage withstand layer 103. When the fast recovery diode needs to be turned off, these stored excess carriers (which can also be called majority carriers) need to be exported through the anode 105 and the cathode 106. The time to export this part of the majority carriers and form a blocking voltage between the anode 105 and the cathode 106 is the reverse recovery time of the fast recovery diode. Reducing this time is very helpful for the fast recovery diode to be used in high-speed switching scenarios. Therefore, it is necessary to improve the traditional fast recovery diode.

[0057] Accordingly, a first aspect of the present application proposes a fast recovery diode. Referring to Figure 2 , the fast recovery diode includes a substrate 210, a first epitaxial layer 220, a second epitaxial layer 230, an oxide layer 240, a first electrode 250, and a second electrode 260.

[0058] Among them, the first epitaxial layer 220 and the second epitaxial layer 230 are sequentially arranged on the substrate 210. The first epitaxial layer 220 is located on one side of the substrate 210, and the second epitaxial layer 230 is located on the side of the first epitaxial layer 220 away from the substrate 210. The substrate 210, the first epitaxial layer 220, and the second epitaxial layer 230 all have a first-type doping.

[0059] In the embodiments of the present application, the first epitaxial layer 220 is used as the buffer layer of the device, and the second epitaxial layer 230 is used as the voltage withstand layer of the device. According to the softness and avalanche ability requirements of the fast recovery diode, buffer layers and voltage withstand layers with different thicknesses and doping concentrations can be adopted. In some embodiments, the doping concentrations of the first-type doping of the substrate 210, the first epitaxial layer 220, and the second epitaxial layer 230 are different. In some specific embodiments among them, the doping concentration in the substrate 210 is generally much higher than that of the first epitaxial layer 220 and the second epitaxial layer 230, and it only serves as a mechanical support and electrical connection. In some specific embodiments among them, the doping concentration of the first-type doping in the second epitaxial layer 230 is higher than that of the first epitaxial layer 220. In some embodiments, the differences in the doping concentrations of the first-type doping of the substrate 210, the first epitaxial layer 220, and the second epitaxial layer 230 result in different resistivities of the three. In some embodiments, the resistivity of the first epitaxial layer 220 is 0.01 - 5 Ω·cm, for example, it can be 0.01 Ω·cm, 0.02 Ω·cm, 0.05 Ω·cm, 0.1 Ω·cm, 0.2 Ω·cm, 0.5 Ω·cm, 1 Ω·cm, 2 Ω·cm, 3 Ω·cm, 4 Ω·cm, 5 Ω·cm; the resistivity of the second epitaxial layer 230 is 10 - 50 Ω·cm, for example, it can be 10 Ω·cm, 12 Ω·cm, 14 Ω·cm, 15 Ω·cm, 16 Ω·cm, 18 Ω·cm, 20 Ω·cm, 25 Ω·cm, 30 Ω·cm, 35 Ω·cm, 40 Ω·cm, 45 Ω·cm, 50 Ω·cm. Specifically, taking a silicon-based substrate as an example, the resistivity of the first epitaxial layer is 1 Ω·cm, and the resistivity of the second epitaxial layer is 20 Ω·cm.

[0060] In some embodiments, the thickness of the substrate 210 is 100 - 1000 μm, for example, it can be 100 μm, 200 μm, 300 μm, 400 μm, 500 μm, 600 μm, 700 μm, 800 μm, 900 μm, 1000 μm. In some embodiments, the thickness of the first epitaxial layer 220 can be, for example, 0.1 - 20 μm, for example, it can be 0.1 μm, 0.2 μm, 0.3 μm, 0.4 μm, 0.5 μm, 0.6 μm, 0.8 μm, 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 15 μm, 16 μm, 18 μm, 20 μm. In some embodiments, the thickness of the second epitaxial layer 230 can be, for example, 40 - 100 μm, for example, it can be 40 μm, 45 μm, 50 μm, 55 μm, 60 μm, 65 μm, 70 μm, 75 μm, 80 μm, 85 μm, 90 μm, 95 μm, 100 μm.

[0061] The oxide layer 240 is located on the side of the second epitaxial layer 230 away from the first epitaxial layer 220. In some embodiments, the thickness of the oxide layer 240 is For example, it can be The oxide layer 240 has voids for defining a second-type doped ion implantation region. Thus, a groove-shaped second-type doped ion implantation region 231 is provided at a position on the side of the second epitaxial layer 230 corresponding to the voids and away from the first epitaxial layer 220. Among them, the second-type doped ion implantation region 231 refers to a region doped with a second-type dopant by ion implantation. Through the setting of such voids, the oxide layer 240 can form the required second-type doped ion implantation region 231 as a self-aligned structure on the second epitaxial layer 230. At the same time, it should be noted that the inner sidewall 232 of the second-type doped ion implantation region 231 has a higher doping concentration of the second-type dopant than other positions of the second-type doped ion implantation region 231. In some embodiments, the aspect ratio D:W of the second-type doped ion implantation region 231 is 1:(5-20), for example, it can be 1:5, 1:6, 1:8, 1:10, 1:12, 1:14, 1:15, 1:16, 1:18, 1:20. In some embodiments, the material of the oxide layer 240 is an oxide of the main element of the material of the substrate 210. For example, when the substrate is silicon-based, the oxide layer 240 is a silicon oxide.

[0062] The first electrode 250 includes a first part 251 and a second part 252 that are interconnected. The first part 251 is located on the side of the oxide layer 240 away from the second epitaxial layer 230, and the second part 252 is located in the voids and contacts the second-type doped ion implantation region 231. It should be noted that the contact means that the second part 252 penetrates to the bottom of the groove-shaped structure of the second-type doped ion implantation region 231 and contacts the bottom of the second-type doped ion implantation region 231; at the same time, the second part 252 also penetrates to both sides of the second-type doped ion implantation region 231 and contacts its inner sidewall 232.

[0063] In addition, the second electrode 260 is located on the side of the substrate 210 away from the first epitaxial layer 220. In some embodiments, the material of the second electrode 260 is titanium nickel silver. In some embodiments, the thickness of the second electrode 260 is For example, it can be

[0064] In some embodiments, an insulating layer 270 is further provided between the oxide layer 240 and the first electrode 250. In some embodiments, the material of the insulating layer 270 includes one or more of silicon oxide, silicon nitride, oxygen-rich nitride, etc. In some embodiments, the thickness of the insulating layer 270 is For example, it can be In some embodiments, a contact hole pattern is formed in the insulating layer 270 on the oxide layer 240.

[0065] In some embodiments, a passivation layer 280 is further provided on one side of the first electrode 250 away from the oxide layer 240. In some embodiments, the material of the passivation layer 280 includes one or more of polyimide, silicon oxide, silicon nitride, oxygen-rich nitride, etc. In some embodiments, the thickness of the passivation layer 280 is For example, it can be In some embodiments, the passivation layer 280 has a pad area exposing the first electrode 250 and a protection area protecting the first electrode 250 on the first electrode 250.

[0066] In the above fast recovery diode, the first-type doping and the second-type doping are used to respectively represent two different doping types, including N-type doping and P-type doping. For example, the first-type doping can be N-type doping and the second-type doping can be P-type doping, or the first-type doping can be P-type doping and the second-type doping can be N-type doping. Among them, the doping elements for P-type doping include but are not limited to at least one of B, Al, and Ga, and the doping elements for N-type doping include but are not limited to at least one of P, Sb, and As.

[0067] The second aspect of the present application proposes a manufacturing method of the aforementioned fast recovery diode, which specifically includes the following steps S100 to S500:

[0068] Refer to Figures 3 to 5 , S100: A first epitaxial layer 220, a second epitaxial layer 230, and an oxide layer 240 are sequentially formed on the substrate 210. In some embodiments, the first epitaxial layer 220, the second epitaxial layer 230, and the oxide layer 240 can be formed by any one of molecular beam epitaxy (MBE), chemical vapor deposition (CVD), atomic layer deposition (ALD), sputtering deposition, etc.

[0069] S200: A void 241 is formed in the oxide layer 240 by etching. Specifically, refer to Figures 6 to 7 , a photoresist is coated on the oxide layer 240, and the pattern on the mask is defined on the first photoresist layer 310 by exposure. The thickness of the first photoresist layer 310 is determined by the damage thickness of the first photoresist layer 310 in the subsequent etching process. In some embodiments, the thickness of the first photoresist layer 310 is 1 to 5 μm. Subsequently, the pattern is transferred to the oxide layer 240 by dry etching or wet etching, and the first photoresist layer 310 is removed, so that the corresponding pattern is formed by the void 241 of the etched oxide layer 240.

[0070] S300: Perform a first ion implantation on the second epitaxial layer through the voids, and form a groove-shaped second-type doped ion implantation region by etching. Refer to Figure 8 , utilize the oxide layer 240 to perform a first ion implantation on the second epitaxial layer 230 through the void 241, thereby forming a second-type doped ion implantation region 231, wherein the impurity of the first ion implantation is the second-type doping. In some embodiments, it is also necessary to thermally activate the implanted impurities after the first ion implantation. In some embodiments, since the second-type doped ion implantation region requires a certain depth, the element used for doping is an element with a relatively large diffusion coefficient, such as boron (P-type doping), phosphorus (N-type doping). In some embodiments, at least one of BCl3, BBr3, and B2H6 is used as the gas source for boron doping in the second-type doped ion implantation region. In some embodiments, at least one of PCl3, PBr3, and PH3 is used as the gas source for phosphorus doping in the second-type doped ion implantation region. In some embodiments, the initial doping concentration of the first ion implantation is 5×10 14 ~1×10 19 / cm 3 , for example, it can be 5×10 14 / cm 3 , 6×10 14 / cm 3 , 8×10 14 / cm 3 , 1×10 15 / cm 3 , 2×10 15 / cm 3 , 5×10 15 / cm 3 , 1×10 16 / cm 3 , 2×10 16 / cm 3 , 5×10 16 / cm 3 , 1×10 17 / cm 3 , 2×10 17 / cm 3 , 5×10 17 / cm 3 , 1×10 8 / cm 3 , 2×10 18 / cm 3 , 5×10 18 / cm 3 , 1×10 19 / cm 3. In some embodiments, the implantation energy of the primary ion implantation is 20 - 2000 keV, for example, it can be 20 keV, 30 keV, 50 keV, 100 keV, 200 keV, 300 keV, 500 keV, 1000 keV, 1500 keV, 2000 keV. Refer to Figure 9 , by using etching, a self-aligned blocking effect is formed through the oxide layer 240, and a topography with a certain depth (D) to width (W) ratio is formed on the surface of the second epitaxial layer 230, making the second-type doped ion implantation region 241 become groove-shaped. In some embodiments, the depth-to-width ratio D:W can be 1:5 - 20.

[0071] S400: Perform secondary ion implantation on the surface of the second-type doped ion implantation region, and remove the bottom part of the secondary ion implantation through etching. Refer to Figure 10 , by performing secondary ion implantation of the second doping type on the surface of the second-type doped ion implantation region 231, a second doping region 330 is formed on the surface of the second-type doped ion implantation region 231. In some embodiments, after ion implantation, thermal activation of the implanted impurities is further included. In some embodiments, in order to ensure that the second doping region remains on the surface of the second-type doped ion implantation region 231, an element with a relatively small diffusion coefficient is used for ion implantation, such as trivalent source boron fluoride or arsenic. In some embodiments, AsH3 is used for arsenic doping in the second-type doped ion implantation region. In some embodiments, the initial doping concentration of the secondary ion implantation is 1×10 14 ~1×10 19 / cm 3 , for example, it can be 1×10 14 / cm 3 , 2×10 14 / cm 3 , 5×10 14 / cm 3 , 6×10 14 / cm 3 , 8×10 14 / cm 3 , 1×10 15 / cm 3 , 2×10 15 / cm 3 , 5×10 15 / cm 3 , 1×10 16 / cm 3 , 2×10 16 / cm 3 , 5×10 16 / cm 3 , 1×10 17 / cm 3 , 2×1017 / cm 3 、5×10 17 / cm 3 、1×10 8 / cm 3 、2×10 18 / cm 3 、5×10 18 / cm 3 、1×10 19 / cm 3 。In some embodiments, the implantation energy of the secondary ion implantation is 20 - 100 keV, for example, it can be 20 keV, 30 keV, 40 keV, 50 keV, 60 keV, 70 keV, 80 keV, 90 keV, 100 keV. In some embodiments, the energy of the primary ion implantation is greater than that of the secondary implantation. For example, the energy of the primary ion implantation is 2 times, 3 times, 4 times, 5 times, 10 times, 20 times, 50 times, 100 times or more than that of the secondary ion implantation. Refer to Figure 11 , by means of etching, a self-aligned blocking effect is formed through the oxide layer 240 to form a deeper topography on the surface of the second-type doped ion implantation region 231, thereby removing a part of the bottom of the second-type doped ion implantation region 231 in the second doping region 330 and retaining a part of its inner sidewall 232.

[0072] Among them, the initial doping concentration refers to the bulk concentration unit of the implantation dose. The difference in the initial doping concentration between the primary ion implantation and the secondary ion implantation is not significant, but there is a difference in the implantation energy, and the former will undergo an additional thermal process and has a stronger diffusion effect. Therefore, under a greater diffusion effect, the final doping concentration at positions other than the inner sidewall will be lower, while the inner sidewall has a higher doping concentration.

[0073] S500: Form the first electrode and the second electrode.

[0074] In some embodiments, S500 includes S510: Grow an insulating layer 270 on the surfaces of the oxide layer 240 and the second-type doped ion implantation region 231; S520: Form the first electrode and the second electrode.

[0075] In some embodiments, S510 includes S511: Refer to Figure 12 , grow an insulating layer 270 on the surfaces of the oxide layer 240 and the second-type doped ion implantation region 231; S512: Refer to Figure 13 , apply a photoresist on the surface of the insulating layer 270, and define the pattern (a contact hole in some embodiments) on the mask plate on the second photolithography layer 320 through exposure; S513: Refer to Figure 14, after a pattern is formed on the second photoresist layer 320, the pattern is transferred to the insulating layer 270 by etching (such as dry etching) to form a patterned insulating layer 270.

[0076] In some embodiments, S520 includes S521: forming a first electrode and S522: forming a second electrode. In some embodiments, referring to Figure 15 , S521 includes depositing a metal to form the first electrode 250. In some embodiments, the metal includes at least one of an aluminum-copper alloy, an aluminum-silicon-copper alloy, etc. In some embodiments, the thickness of the first electrode 250 is 1 to 20 μm, for example, it can be 1 μm, 2 μm, 3 μm, 4 μm, 5 μm, 6 μm, 8 μm, 10 μm, 12 μm, 14 μm, 15 μm, 16 μm, 18 μm, 20 μm. In some embodiments, after forming the first electrode 250, S521 further includes forming a circuit link layer by a lithography method similar to the previous one (including coating photoresist and etching by dry or wet-dry mixing methods after exposure). In some embodiments, referring to Figure 16 , after depositing a metal to form the first electrode 250, S521 includes forming a passivation layer 280. In some embodiments, similar to the previous one, the passivation layer 280 forms a corresponding passivation layer pattern by a lithography method (including coating photoresist and etching by dry or wet-dry mixing methods after exposure). Thus, the passivation layer 280 is opened to form a pad area 281 exposing the first electrode 250 (this part of the area can be used for metal soldering in the subsequent process), and a protection area formed by the unexposed part.

[0077] In some embodiments, referring to Figure 17 and Figure 2 , S522: forming the second electrode includes: thinning the substrate 210, and then forming the second electrode 260 on the substrate 210 by a method such as evaporation or sputtering. In some embodiments, the substrate is thinned to a suitable thickness such as 100 to 300 μm, specifically, it can be 100 μm, 150 μm, 200 μm, 250 μm, 300 μm. In some embodiments, the material of the second electrode 260 includes titanium-nickel-silver. In some embodiments, the thickness of the second electrode 260 is in for example, it can be In some embodiments, ohmic contact is achieved after annealing, and the carrier lifetime in the device is controlled by electron irradiation.

[0078] Based on the above analysis of the structure and process, the fast recovery diode provided by the embodiments of the present application has the following advantages compared with the traditional fast recovery diode shown in Figure 1 :

[0079] 1. By introducing an oxide layer, which, as an insulator, cannot participate in conduction and thus cannot provide electrons or holes, this region cannot achieve a large injection effect, reducing the injection efficiency per unit area. At the same time, the second-type doped ion injection region of the adjacent groove structure can smooth the electric field distribution and prevent the breakdown voltage from decreasing.

[0080] 2. Through the self-aligned structure formed by introducing the oxide layer, the concentration peak of the high-concentration distribution formed during the first ion injection is removed after etching. The concentration of the second-type doped ion injection region can be reduced to a level of 1×10 15 / cm 3 in this way, thereby reducing the injection efficiency per unit area.

[0081] 3. Through the self-aligned structure formed by introducing the oxide layer, after the second ion injection, the surface high-concentration doped region such as the second doped region is removed, and only the inner sidewall of the second-type doped ion injection region, which is a high-concentration doped region, is retained. The high-concentration inner sidewall provides a current channel only when the current passing through the device is very large, preventing the device from burning out due to overheating caused by excessive current. At the operating current, because its area accounts for a relatively small proportion and its conductivity is weak, the corresponding resistance is larger than the resistance formed at other positions of the second-type doped ion injection region. Therefore, it does not participate in the large injection process during the operating current. At the same time, the high-concentration inner sidewall is formed on the sidewall through self-aligned etching, so its occupied area can be flexibly controlled by controlling the etching depth.

[0082] Among them, the role of the second-type doped ion injection region existing in a large area is to withstand the electric field and participate in conduction in the anode region of the fast recovery diode. The role of the inner sidewall with a higher doping concentration and a smaller area is to participate in conducting current when the operating current is large. Therefore, near the operating current, the other parts of the second-type doped ion injection region provide the current channel, and when operating at a large current, the inner sidewall participates in conduction. Their doping concentrations are different, their areas are different, and the current-conducting channels provided are different. When these two regions are combined in a device, compared with traditional diodes, different injection efficiencies, that is, different current-conducting channels, can be achieved at different currents.

[0083] The fast recovery diode provided in the embodiment of the present application has the above characteristics, reducing the injection efficiency on the front side. Therefore, the overshoot current during reverse recovery can be reduced, thereby indirectly reducing the reverse recovery time and increasing the softness of reverse recovery. At the same time, due to the existence of the high-concentration doped region of the inner sidewall, the large-current passing ability of the fast recovery diode provided in the embodiment of the present application is ensured not to decay.

[0084] The following describes the present application in conjunction with specific embodiments.

[0085] Example 1

[0086] This embodiment provides a fast recovery diode, and its structure refers to Figure 2 , including a substrate 210, a first epitaxial layer 220, a second epitaxial layer 230, an oxide layer 240, a first electrode 250, a second electrode 260, an insulating layer 270, and a passivation layer 280.

[0087] Among them, the first epitaxial layer 220 and the second epitaxial layer 230 are sequentially arranged on the substrate 210. The first epitaxial layer 220 is located on one side of the substrate 210, and the second epitaxial layer 230 is located on the side of the first epitaxial layer 220 away from the substrate 210. The substrate 210, the first epitaxial layer 220, and the second epitaxial layer 230 are all doped with a first type. The oxide layer 240 is located on the side of the second epitaxial layer 230 away from the first epitaxial layer 220. There are voids on the oxide layer 240 for defining a second type doped ion implantation region. Thus, a grooved second type doped ion implantation region 231 is provided at a position on the second epitaxial layer 230 corresponding to the voids and away from the first epitaxial layer 220. The aspect ratio D:W of the second type doped ion implantation region 231 is 1:5. The first electrode 250 includes a first part 251 and a second part 252 that are interconnected. The first part 251 is located on the side of the oxide layer 240 away from the second epitaxial layer 230, and the second part 252 is located in the voids and contacts the second type doped ion implantation region 231. The second electrode 260 is located on the side of the substrate 210 away from the first epitaxial layer 220. An insulating layer 270 is provided between the oxide layer 240 and the first electrode 250. A passivation layer 280 is further provided on the side of the first electrode 250 away from the oxide layer 240.

[0088] The preparation process of this fast recovery diode is as Figures 3 to 17 , and the specific steps are as follows:

[0089] Step S1: Grow a first epitaxial layer with the same doping type as a buffer layer on an N-type doped silicon substrate by chemical vapor deposition. The thickness of the buffer layer is 10 μm, and the resistivity is 1 Ω·cm.

[0090] Step S2: Continuously grow a second epitaxial layer with the same doping type as a voltage withstand layer on the first epitaxial layer by chemical vapor deposition. The thickness of the voltage withstand layer is 50 μm, and the resistivity is 20 Ω·cm.

[0091] Step S3: Deposit silicon dioxide with a thickness of as the oxide layer on the second epitaxial layer.

[0092] Step S4: Spin-coat photoresist on the oxide layer, and define the circuit diagram pattern on the mask on the first photoresist layer through exposure. The thickness of the first photoresist layer is 3 μm.

[0093] Step S5: Transfer the circuit pattern onto the oxide layer by dry etching and remove the first photoresist layer.

[0094] Step S6: Perform a primary ion implantation of B2H6 into the second epitaxial layer through the gaps in the circuit pattern of the oxide layer to fabricate a P-type doped ion implantation region with an initial doping concentration of 1×10 15 / cm 3 , and the implantation energy is 1000 keV. Then thermally activate the implanted impurities.

[0095] Step S7: Utilize dry etching to form a self-aligned blocking effect through the thick oxide layer, creating a morphology with an aspect ratio of 1:5 on the surface of the second epitaxial layer, and finally forming a grooved second-type doped ion implantation region.

[0096] Step S8: Perform a secondary ion implantation of BF3 onto the surface of the second-type doped ion implantation region through the gaps in the circuit pattern of the oxide layer to form a second doping region on the surface of the second-type doped ion implantation region, with an initial doping concentration of 1×10 16 / cm 3 , and the implantation energy is 100 keV. Then thermally activate the implanted impurities.

[0097] Step S9: Once again utilize dry etching to form a self-aligned blocking effect through the oxide layer, creating a deeper morphology on the surface of the second-type doped ion implantation region, removing the bottom of the second doping region while retaining the inner sidewalls of the second doping region.

[0098] Step S10: Grow a silicon nitride insulating layer with a thickness of on the surfaces of the oxide layer and the second-type doped ion implantation region by chemical vapor deposition.

[0099] Step S11: Spin-coat photoresist on the surface of the insulating layer and define the contact hole pattern on the mask plate onto the second photoresist layer through exposure.

[0100] Step S12: After the contact hole pattern is achieved on the second photoresist layer, transfer the pattern onto the insulating layer by dry etching.

[0101] Step S13: Deposit an aluminum-copper alloy by sputtering, then spin-coat photoresist, and form a circuit link layer as the first electrode with a thickness of 5 μm through exposure and dry etching.

[0102] Step S14: Form a polyimide passivation layer with a thickness of by coating on the surface of the first electrode, and then open the passivation layer through lithography to form a pad region and a protection region.

[0103] Step S15: Thin the substrate to 200 μm.

[0104] Step S16: Form a titanium-nickel-silver back metal with a thickness of on the substrate by sputtering as the second electrode, and achieve ohmic contact after annealing, and control the carrier lifetime in the device by means of electron irradiation.

[0105] In the above-mentioned fast recovery diode, through the design of different shaped structures of the oxide layer, different voids can be formed, thereby autonomously changing the shape of the second-type doped ion implantation region, achieving different effective areas, decoupling the injection efficiency and the effective area of the chip, and facilitating the adjustment of different injection efficiencies. The anode of this device is self-aligned etched through the shielding of the oxide layer, forming a distribution morphology of different concentrations of the second doping type. Therefore, through reasonable design of the above two advantages, when the device is near the operating current, the current flows through the channel with lower second-type doping, and when the operating current is large, the current flows through the channel with higher second-type doping. Thus, the anode injection efficiency has the characteristic of self-adjustment at different current densities. At the same time, when near the operating current, the current flows through the channel with lower second-type doping, achieving a low injection efficiency, reducing the reverse overshoot current of the fast recovery diode at the operating current, and finally reducing the time required for the device to reverse recover.

[0106] The present application has been described in detail above in conjunction with the embodiments, but the present application is not limited to the above embodiments. Within the scope of knowledge possessed by those of ordinary skill in the art, various changes can be made without departing from the gist of the present application. In addition, without conflict, the embodiments of the present application and the features in the embodiments can be combined with each other.

Claims

1. Fast recovery diode, characterized in that, Comprising: A substrate having a first-type doping; A first epitaxial layer located on one side of the substrate, the first epitaxial layer having a first-type doping; A second epitaxial layer located on the side of the first epitaxial layer away from the substrate, the second epitaxial layer having a first-type doping; a groove-shaped second-type doping ion implantation region is provided on the side of the second epitaxial layer away from the first epitaxial layer, and the inner sidewall in the second-type doping ion implantation region has a higher second-type doping concentration; An oxide layer located on the side of the second epitaxial layer away from the first epitaxial layer, the oxide layer having a void for defining the second-type doping ion implantation region; A first electrode, the first electrode comprising a first part and a second part that are interconnected, the first part being located on the side of the oxide layer away from the second epitaxial layer, and the second part being located in the void and in contact with the second-type doping ion implantation region; A second electrode located on the side of the substrate away from the first epitaxial layer.

2. The fast recovery diode according to claim 1, characterized in that The aspect ratio of the depth to width of the second-type doping ion implantation region is 1:(5 - 20).

3. The fast recovery diode according to claim 1, characterized in that, The initial doping concentration of the second type of doped ion implantation region at positions other than the inner sidewall is 5×10 14 ~1×10 19 / cm 3 , and the initial doping concentration of the inner sidewall is 1×10 14 ~1×10 19 / cm 3 .

4. The fast recovery diode according to claim 1, wherein The thickness of the oxide layer is 500 Å to 20,000 Å.

5. The fast recovery diode according to claim 1, characterized in that, An insulating layer is further provided between the oxide layer and the first electrode, and / or a passivation layer is further provided on the side of the first electrode away from the oxide layer.

6. The preparation method of the fast recovery diode according to any one of claims 1 to 5, characterized in that, Comprising the following steps: Sequentially forming a first epitaxial layer, a second epitaxial layer, and an oxide layer on the substrate; Forming a void in the oxide layer by etching; Performing a first ion implantation on the second epitaxial layer through the void, and forming a groove-shaped second-type doping ion implantation region by etching; Performing a second ion implantation on the surface of the second-type doping ion implantation region, and removing the bottom second ion implantation part by etching; Forming a first electrode and a second electrode.

7. The preparation method according to claim 6, characterized in that, The implantation dose of the primary ion implantation is 5×10 12 ~1×10 14 / cm 2 , and / or the energy of the primary ion implantation is 20 - 2000 keV.

8. The preparation method according to claim 6, characterized in that, The implantation dose of the secondary ion implantation is 1×10 12 ~1×10 14 / cm 2 , and / or, the energy of the secondary ion implantation is 20 - 100 keV.

9. An electronic system, characterized in that, Comprising the fast recovery diode according to any one of claims 1 to 5.

10. Electrical equipment, characterized in that, Comprising the fast recovery diode according to any one of claims 1 to 5 or the electronic system according to claim 9.

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