Semiconductor structure manufacturing method, semiconductor structure, electronic device and electronic equipment

Abstract

The invention discloses a semiconductor structure manufacturing method, a semiconductor structure, an electronic device and electronic equipment, and aims to solve the technical problem that the resistance between a channel layer and a source electrode structure and the resistance between the channel layer and a drain electrode structure are relatively large. When the first groove is formed, the thickness of the channel layer corresponding to the gap is reduced, and when the second groove is formed, the part of the channel layer corresponding to the gap is removed, that is, the part of the channel layer with the smaller thickness is removed, so that the contact area between the channel layer and the electrode structure is increased, and the resistance between the channel layer and the electrode structure is reduced.

Description

Technical Field

[0001] The embodiments of the present application relate to the technical field of semiconductor manufacturing, and in particular, to a method for manufacturing a semiconductor structure, a semiconductor structure, an electronic device, and an electronic equipment. Background Art

[0002] The gate all around (GAA) transistor has been widely used due to its high control ability. The gate all around transistor includes a plurality of gate layers and a plurality of channel layers alternately stacked. One end of the channel layer is connected to the source structure, and the other end of the channel layer is connected to the drain structure. The thickness of the part of the channel layer in contact with the source structure and the drain structure is small, resulting in a large resistance between the channel layer and the source structure and the drain structure. Summary of the Invention

[0003] The embodiments of the present application provide a method for manufacturing a semiconductor structure, a semiconductor structure, an electronic device, and an electronic equipment, which can reduce the resistance between the channel layer and the source structure and the drain structure.

[0004] In a first aspect, the embodiments of the present application provide a method for manufacturing a semiconductor structure, including: forming a stacked structure on a substrate, the stacked structure including a plurality of sacrificial layers and a plurality of channel layers alternately stacked; forming a plurality of dummy gate structures on the stacked structure, the plurality of dummy gate structures being arranged at intervals; forming a first mask layer on each dummy gate structure, the first mask layer covering the side walls adjacent to the dummy gate structure and the stacked structure; forming a second mask layer on the first mask layer; using the second mask layer as a mask to remove part of the stacked structure to form a plurality of first grooves, the first grooves extending to the substrate; removing part of the sacrificial layer at the groove walls of the first grooves to form voids; removing the second mask layer; using the first mask layer as a mask to form second grooves extending to the substrate; and forming electrode structures in contact with each channel layer at the second grooves.

[0005] In the method for manufacturing a semiconductor structure provided by the embodiments of the present application, when forming the voids, part of the channel layer in contact with the sacrificial layer will be removed, resulting in a reduction in the thickness of the channel layer corresponding to the voids. When forming the second grooves, part of the channel layer corresponding to the voids will be removed, that is, the part of the channel layer with a small thickness will be removed, thereby increasing the contact area between the channel layer and the electrode structure and reducing the resistance between the channel layer and the electrode structure.

[0006] In some embodiments that may include the above embodiments, before forming the second mask layer on the first mask layer, it further includes: forming a stop layer on the first mask layer, the etching selectivity of the stop layer being different from the etching selectivities of both the first mask layer and the second mask layer; before using the first mask layer as a mask to form second grooves extending to the substrate, it further includes: removing the stop layer. By setting like this, when removing the second mask layer, the stop layer can protect the first mask layer from being damaged.

[0007] In some embodiments that may include the above embodiments, removing a part of the sacrificial layer at the first groove sidewall to form a void includes: while removing a part of the sacrificial layer at the first groove sidewall, a part of the channel layer in contact with the sacrificial layer is removed to form a thinning region on the channel layer. With such a setting, the sacrificial layer in the void can be completely removed to avoid residual sacrificial layer in the void.

[0008] In some embodiments that may include the above embodiments, forming a second groove extending to the substrate using the first mask layer as a mask includes: while forming the second groove, at least a part of the thinning regions on each channel layer are also removed. With such a setting, the thickness of the channel layer at the exposed part is larger, that is, the contact area between the channel layer and the electrode structure is increased, and thus the resistance between the channel layer and the electrode structure is reduced.

[0009] In some embodiments that may include the above embodiments, before removing the second mask layer, it further includes: forming a filling body in the void. With such a setting, the filling body can support the channel layer at the void to avoid the channel layer falling off in subsequent manufacturing processes; in addition, the filling body can also isolate the sacrificial layer to isolate the gate layer and the electrode structure.

[0010] In some embodiments that may include the above embodiments, forming a filling body in the void includes: forming a first dielectric layer at the sidewall of the first groove, and a part of the first dielectric layer fills the void to form the filling body; removing the first dielectric layer at the sidewall of the first groove. With such a setting, the manufacturing is simple, and it can ensure that the void is filled with the filling body.

[0011] In some embodiments that may include the above embodiments, forming an electrode structure in contact with each channel layer at the second groove includes: based on the channel layer at the sidewall of each second groove, forming the electrode structure by epitaxial growth. With such a setting, the electrode structure formed by epitaxial growth and the channel layer form an integral structure, which can reduce the resistance between the channel layer and the electrode structure.

[0012] In some embodiments that may include the above embodiments, after forming an electrode structure in contact with each channel layer at the second groove, it further includes: replacing the sacrificial layer with a gate layer and connecting the gate layers. Each gate layer corresponding to each sub-stack structure serves as the gate of a surrounding gate transistor, each channel layer corresponding to the sub-stack structure serves as the channel of the surrounding gate transistor, the electrode structure at one end of the sub-stack structure serves as the source of the surrounding gate transistor, and the electrode structure at the other end of the sub-stack structure serves as the drain of the surrounding gate transistor.

[0013] Second aspect, an embodiment of the present application further provides a semiconductor structure, which is obtained by the semiconductor structure manufacturing method as described above. The semiconductor structure provided by the embodiment of the present application is obtained by the semiconductor structure manufacturing method in the above embodiment. Therefore, both can solve the same technical problems and achieve the same technical effects.

[0014] Third aspect, an embodiment of the present application further provides an electronic device, including a packaging substrate and the semiconductor structure as described above, and the semiconductor structure is disposed on the packaging substrate.

[0015] The electronic device provided by the embodiment of the present application includes the semiconductor structure in any of the above embodiments. Therefore, both can solve the same technical problems and achieve the same technical effects.

[0016] Fourth aspect, an embodiment of the present application further provides an electronic device, including: a circuit board and the electronic device as described above, and the electronic device is disposed on the circuit board.

[0017] The electronic device provided by the embodiment of the present application includes the semiconductor device in any of the above embodiments. Therefore, both can solve the same technical problems and achieve the same technical effects. Description of the Drawings

[0018] Figure 1 It is a schematic structural diagram of a planar transistor in the related art;

[0019] Figure 2 It is a schematic structural diagram of a fin field effect transistor in the related art;

[0020] Figure 3 It is a schematic structural diagram of a gate-all-around transistor in the related art;

[0021] Figure 4 It is a cross-sectional view of a gate-all-around transistor in the related art;

[0022] Figure 5 It is a flowchart of the semiconductor structure manufacturing method provided by the embodiment of the present application;

[0023] Figure 6 It is a perspective view after forming a second mask layer in the conductor structure manufacturing method provided by the embodiment of the present application;

[0024] Figure 7 It is a cross-sectional view after forming a second mask layer in the conductor structure manufacturing method provided by the embodiment of the present application;

[0025] Figure 8 It is a perspective view after forming a first groove in the conductor structure manufacturing method provided by the embodiment of the present application;

[0026] Figure 9Cross-section after forming the first groove in the method for manufacturing a conductor structure provided by an embodiment of the present application Figure 1 ;

[0027] Figure 10 Stereogram after forming a void in the method for manufacturing a conductor structure provided by an embodiment of the present application;

[0028] Figure 11 Cross-section after forming a void in the method for manufacturing a conductor structure provided by an embodiment of the present application;

[0029] Figure 12 Cross-section after forming the first dielectric layer in the method for manufacturing a conductor structure provided by an embodiment of the present application;

[0030] Figure 13 Cross-section after removing the first dielectric layer at the wall of the first groove in the method for manufacturing a conductor structure provided by an embodiment of the present application;

[0031] Figure 14 Cross-section after removing the second mask layer in the method for manufacturing a conductor structure provided by an embodiment of the present application;

[0032] Figure 15 Cross-section after forming the second groove in the method for manufacturing a conductor structure provided by an embodiment of the present application;

[0033] Figure 16 Cross-section after forming the electrode structure in the method for manufacturing a conductor structure provided by an embodiment of the present application;

[0034] Figure 17 Cross-section after forming the first groove in the method for manufacturing a conductor structure provided by an embodiment of the present application Figure 2 。

[0035] Description of reference numerals: 10: substrate; 101: shallow trench isolation structure; 20: stacked structure; 201: channel layer; 202: sacrificial layer; 203: gate layer; 204: channel structure; 205: filling body; 206: first dielectric layer; 207: void; 208: thinning region; 210: sub-stacked structure; 30: dummy gate structure; 301: hard mask; 302: first hard mask; 303: second hard mask; 304: second dielectric layer; 305: isolation layer; 306: first mask layer; 307: second mask layer; 308: stop layer; 310: source structure; 320: drain structure; 401: first groove; 402: second groove. Detailed implementation manners

[0036] Next, the technical solutions in the embodiments of the present application will be described with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments.

[0037] Hereinafter, terms such as "first", "second", etc. are for descriptive purposes only and should not be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, features defined with "first", "second", etc. may explicitly or implicitly include one or more such features.

[0038] In addition, in the embodiments of the present application, orientation terms such as "upper", "lower", "left", "right", "horizontal", and "vertical" are defined relative to the orientation in which the components in the drawings are schematically placed. It should be understood that these directional terms are relative concepts, which are used for relative description and clarification and can change accordingly with the change of the orientation in which the components in the drawings are placed.

[0039] In the embodiments of the present application, unless otherwise clearly defined and limited, the term "connection" should be understood in a broad sense. For example, "connection" can be a fixed connection, an electrical connection, or a detachable connection, or integrated; it can be directly connected or indirectly connected through an intermediate medium.

[0040] With the gradual development of semiconductor technology, transistors have gradually evolved from planar transistors to fin field-effect transistors (FinFETs) and gate-all-around transistors (GAAs). Among them, as Figure 1 shown, the planar transistor includes a channel layer 201 and a gate layer 203 stacked on the channel layer 201, and the control of the planar transistor can be achieved through the gate layer 203. As Figure 2 shown, the fin field-effect transistor includes a fin-shaped channel structure 204, and the gate layer 203 covers the top surface and two side surfaces of the channel structure 204 to increase the contact area between the gate layer 203 and the channel structure 204, thereby improving the control ability of the fin field-effect transistor.

[0041] As Figure 3 and Figure 4 shown, the gate-all-around transistor includes a plurality of channel layers 201 stacked, a gate layer 203 is provided between adjacent channel layers 201, the plurality of gate layers 203 are connected, one end of the channel layer 201 is connected to the source structure 310, the other end of the channel layer 201 is connected to the drain structure 320, and each channel layer 201 is located between the source structure 310 and the drain structure 320. During fabrication, in order to prevent the source structure 310 and the drain structure 320 from contacting the gate layer 203, generally, a plurality of channel layers 201 and a plurality of sacrificial layers are alternately stacked to form a stacked structure, and then a part of the sacrificial layers at both ends of the stacked structure is removed by etching to form voids, and a filler 205 is filled in the voids. Then, the source structure 310 is formed at one end of the stacked structure, and the drain structure 320 is formed at the other end of the stacked structure 20.

[0042] However, when removing partial sacrificial layers at both ends of the stacked structure, a part of the channel layer 201 adjacent to the sacrificial layer is removed, resulting in a smaller thickness of the part of the channel layer 201 that contacts the source structure 310 and the drain structure 320 ( Figure 4 at A in

[0043] ), leading to a relatively large resistance between the channel layer 201 and the source structure 310 and the drain structure 320. Figure 5 Please refer to

[0044] According to an embodiment of the present application, a method for fabricating a semiconductor structure is provided for fabricating a semiconductor structure, which may include a gate-all-around transistor. The method includes:

[0045] Please refer to Figure 6 and Figure 7 , a plurality of sacrificial layers 202 and a plurality of channel layers 201 are alternately stacked. Exemplarily, a sacrificial layer 202 may be first formed on the substrate 10, and then a channel layer 201 is formed on the sacrificial layer 202, and then another sacrificial layer 202 is formed on the channel layer 201, and so on. Of course, a channel layer 201 may also be first formed on the substrate 10, and then a sacrificial layer 202 is formed on the channel layer 201, and then another channel layer 201 is formed on the sacrificial layer 202, and so on.

[0046] In an embodiment of the present application, the material of the substrate 10 may include silicon (Si), germanium (Ge), etc. The material of the channel layer 201 may include silicon, germanium, etc., and the channel layer 201 may serve as the channel of the gate-all-around transistor. The material of the sacrificial layer 202 may include silicon germanium (SiGe), silicon oxide (SiOx), silicon nitride (SiN), etc. The present application does not limit the material of the sacrificial layer 202, as long as the etching selectivity of the sacrificial layer 202 is different from that of the channel layer 201.

[0047] In some embodiments, the stacked structure 20 may extend along a first direction ( Figure 6 the X direction in Figure 6 ) on the substrate 10, and there may be multiple stacked structures 20, and the multiple stacked structures 20 may be spaced along a second direction (

[0048] Figure 6 the Y direction in

[0048] that is perpendicular to the first direction on the substrate 10. Adjacent stacked structures 20 may be isolated by a shallow trench isolation structure 101; Exemplarily, a shallow trench isolation structure 101 may be formed in the substrate 10 between adjacent stacked structures 20, and the material of the shallow trench isolation structure 101 may include silicon oxide, silicon oxynitride (SiON), etc.After forming the stacked structure 20, continuing to refer to Figure 5 , the method for fabricating a semiconductor structure provided by the embodiments of the present application further includes:

[0049] S102: Form a plurality of dummy gate structures on the stacked structure, and the plurality of dummy gate structures are arranged at intervals.

[0050] Continuing to refer to Figure 6 and Figure 7 , exemplarily, the plurality of dummy gate structures 30 can be arranged at intervals along the first direction; the material of the dummy gate structure 30 can include single-crystalline silicon, polycrystalline silicon, etc.

[0051] It can be understood that during fabrication, an isolation layer 305 can be first formed on the surface of the stacked structure 20 facing away from the substrate 10 and on the side surfaces adjacent to this surface; then a dummy gate layer is formed on the isolation layer 305, and a hard mask 301 is formed on the dummy gate layer. Using the hard mask 301 as a mask, part of the dummy gate layer and the isolation layer 305 are removed to form a plurality of dummy gate structures 30 arranged at intervals, and each dummy gate structure 30 is isolated from the stacked structure 20 by the isolation layer 305. Among them, the material of the isolation layer 305 can include silicon oxide, silicon oxynitride, etc.

[0052] In the above implementation, the hard mask 301 can include a first hard mask 302 and a second hard mask 303 arranged in a stacked manner. The second hard mask 303 is located between the dummy gate layer and the first hard mask 302. The material of the first hard mask 302 can include silicon oxide, silicon oxynitride, etc., and the material of the second hard mask 303 can include silicon nitride, etc.

[0053] After forming the dummy gate structure 30, continuing to refer to Figure 5 , the method for fabricating a semiconductor structure provided by the embodiments of the present application further includes:

[0054] S103: Form a first mask layer on each dummy gate structure, and the first mask layer covers the sidewalls of the dummy gate structure adjacent to the stacked structure.

[0055] Continuing to refer to Figure 6 and Figure 7 , exemplarily, the material of the first mask layer 306 can include silicon nitride, silicon oxynitride, etc.

[0056] It can be understood that while the first mask layer 306 covers the sidewalls of the dummy gate structure 30 adjacent to the stacked structure 20, the first mask layer 306 also covers the surface of the dummy gate structure 30 facing away from the substrate 10.

[0057] After forming the first mask layer 306, continuing to refer to Figure 5 , the method for fabricating a semiconductor structure provided by the embodiments of the present application further includes:

[0058] S104: A second mask layer is formed on the first mask layer.

[0059] Continuing to refer to Figure 6 and Figure 7 , exemplarily, the second mask layer 307 can completely cover the first mask layer 306, and the material of the second mask layer 307 can include silicon oxide, silicon oxynitride, etc.

[0060] After forming the second mask layer 307, continuing to refer to Figure 5 , the semiconductor structure manufacturing method provided by the embodiments of the present application further includes:

[0061] S105: Using the second mask layer as a mask to remove part of the stacked structure to form a plurality of first grooves, and the first grooves extend to the substrate.

[0062] Please refer to Figure 8 and Figure 9 , exemplarily, part of the stacked structure 20 can be removed by dry etching or wet etching, etc., to form the first grooves 401 extending to the substrate 10, and the first grooves 401 divide the stacked structure 20 into a plurality of sub-stacked structures 210.

[0063] After forming the first grooves 401, continuing to refer to Figure 5 , the semiconductor structure manufacturing method provided by the embodiments of the present application further includes:

[0064] S106: Removing part of the sacrificial layer at the groove walls of the first grooves to form voids.

[0065] Please refer to Figure 10 and Figure 11 , it can be understood that since the etching selectivity ratio of the sacrificial layer 202 is not equal to the etching selectivity ratio of the channel layer 201, a selective etching method can be used to remove part of the sacrificial layer 202 at the groove walls of the first grooves 401; that is to say, removing part of the sacrificial layer 202 close to the first grooves 401 in the sub-stacked structures 210 to form voids 207.

[0066] As Figure 12 shown, after forming the voids 207, a filler 205 can be filled in the voids 207, and the filler 205 can support the channel layer 201 at the voids 207 to prevent the channel layer 201 from falling off during subsequent manufacturing processes; in addition, the filler 205 can also isolate the sacrificial layer 202. Exemplarily, the material of the filler 205 can include insulating materials such as silicon carbon oxide (SiCO), silicon oxynitrogen carbon (SiOCN), etc.

[0067] Exemplarily, forming the filling body 205 in the gap 207 includes: forming a first dielectric layer 206 at the groove wall of the first groove 401, and partially filling the first dielectric layer 206 in the gap 207 to form the filling body 205. As Figure 13 shown, after that, the first dielectric layer 206 at the groove wall of the first groove 401 is removed to retain the filling body 205 located in the gap 207. With such a setting, the manufacturing is simple, and it can be ensured that the filling body 205 fills the gap 207.

[0068] After forming the gap 207, continue to refer to Figure 5 , the semiconductor structure manufacturing method provided by the embodiment of the present application further includes:

[0069] S107: Remove the second mask layer.

[0070] As Figure 14 shown, exemplarily, the second mask layer 307 can be removed by dry etching or wet etching, and the embodiment of the present application does not limit this.

[0071] In some embodiments, the etching selectivity ratios of the first mask layer 306 and the second mask layer 307 may not be equal. Correspondingly, when removing the second mask layer 307, the first mask layer 306 is retained.

[0072] After removing the second mask layer 307, continue to refer to Figure 5 , the semiconductor structure manufacturing method provided by the embodiment of the present application further includes:

[0073] S108: Form a second groove extending to the substrate with the first mask layer as a mask.

[0074] As Figure 15 shown, exemplarily, the part of the sub-stack structure 210 covered by the second mask layer 307 as shown in Figure 12 can be removed by wet etching or dry etching to form a second groove 402 extending to the substrate 10, and the second groove 402 communicates with the first groove 401.

[0075] After forming the second groove 402, continue to refer to Figure 5 , the semiconductor structure manufacturing method provided by the embodiment of the present application further includes:

[0076] S109: Form an electrode structure in contact with each channel layer at the second groove.

[0077] As Figure 16 shown, the electrode structure 30 can be filled in the second groove 402 and the first groove 401, and the electrode structure 30 can be used as the source or drain of the surrounding gate transistor. With Figure 16Taking the shown orientation as an example, the electrode structure 30 on the left side of the sub-stack structure 210 can be the source of the surrounding gate transistor, and the electrode structure 30 on the right side of the sub-stack structure 210 is the drain of the surrounding gate transistor.

[0078] Exemplarily, based on the channel layer 201 at the groove walls of each second groove 402, the electrode structure 30 is formed by means of epitaxial growth. The electrode structure 30 formed by means of epitaxial growth and the channel layer 201 form an integral structure, which can reduce the resistance between the channel layer 201 and the electrode structure.

[0079] In the embodiments of the present application, after the electrode structure is formed, each sacrificial layer 202 can be replaced with a gate layer, and the gate layers are connected, so that each gate layer corresponding to each sub-stack structure 210 serves as the gate of a surrounding gate transistor, each channel layer 201 corresponding to the sub-stack structure 210 serves as the channel of the surrounding gate transistor, the electrode structure 30 at one end of the sub-stack structure 210 serves as the source of the surrounding gate transistor, and the electrode structure 30 at the other end of the sub-stack structure 210 serves as the drain of the surrounding gate transistor.

[0080] In the above implementation manner, the gate layer can include a gate metal layer and a gate dielectric layer wrapped outside the gate metal layer. Exemplarily, the material of the gate metal layer can include tungsten, copper, etc., and the material of the gate dielectric layer can include high-k materials such as hafnium oxide.

[0081] The method for manufacturing a semiconductor structure provided by the embodiments of the present application, as Figure 6 and Figure 7 shown, the stack structure 20 includes a plurality of sacrificial layers 202 and a plurality of channel layers 201 that are alternately stacked, and a plurality of dummy gate structures 30 are formed at intervals on the stack structure 20; then a first mask layer 306 is formed on the dummy gate structures 30, and the first mask layer 306 covers the side walls adjacent to the stack structure 20 of the dummy gate structures 30; a second mask layer 307 is formed on the first mask layer 306, and then a part of the stack structure 20 is removed using the second mask layer 307 as a mask to form a plurality of first grooves 401 extending to the substrate 10 (as Figure 8 and Figure 9 shown); after that, a part of the sacrificial layer 202 at the groove walls of the first grooves 401 is removed to form voids 207 (as Figure 10 and Figure 11 shown); the second mask layer 307 is removed, and then a second groove 402 extending to the substrate 10 is formed using the first mask layer 306 as a mask (as Figure 15 shown), and an electrode structure in contact with each channel layer 201 is formed at the second groove 402. Through the above settings, when the voids 207 are formed, a part of the channel layer 201 in contact with the sacrificial layer 202 will be removed (as Figure 11As shown, it causes the thickness of the channel layer 201 corresponding to the gap 207 to decrease. When forming the second groove 402, a part of the channel layer 201 corresponding to the gap 207 will be removed (as Figure 15 shown), that is, the part of the channel layer 201 with a smaller thickness is removed, thereby increasing the contact area between the channel layer 201 and the electrode structure 30 and reducing the resistance between the channel layer 201 and the electrode structure 30.

[0082] Continuing to refer to Figure 11 , it can be understood that although the etching selectivity of the sacrificial layer 202 is not equal to that of the channel layer 201, when removing a part of the sacrificial layer 202 at the groove wall of the first groove 401, a part of the channel layer 201 in contact with the sacrificial layer 202 will also be removed, thereby forming a thinning region 208 on the channel layer 201, making the thickness of the channel layer 201 decrease. Such a setting can remove all the sacrificial layer 202 in the gap 207 to avoid residual sacrificial layer 202 in the gap 207.

[0083] In order to have a sufficiently large filling body 205 between the gate layer 203 and the electrode structure, generally a larger gap 207 needs to be formed. Correspondingly, the thickness of the formed thinning region 208 is larger in the direction perpendicular to the substrate 10, further reducing the thickness of the channel layer 201. In the embodiment of the present application, as Figure 15 shown, when forming the second groove 402, at least a part of the thinning region 208 (as Figure 11 shown) will be removed to make the thickness of the exposed channel layer 201 larger, that is, increasing the contact area between the channel layer 201 and the electrode structure, and thus reducing the resistance between the channel layer 201 and the electrode structure.

[0084] Continuing to refer to Figure 6 and Figure 7 , in the implementation where the etching selectivities of the first mask layer 306 and the second mask layer 307 are not equal, the thickness of the first mask layer 306 can be (such as etc.), and the thickness of the second mask layer 307 can be (such as etc.). Such a setting makes the thickness of the second mask layer 307 larger. When forming the second groove 402 (as Figure 15 shown), the width of the second groove 402 in the first direction is larger, further increasing the contact area between the channel layer 201 and the electrode structure.

[0085] Such as Figure 17As shown, in other embodiments, the etching selectivity of the first mask layer 306 and the second mask layer 307 is equal or similar. Correspondingly, before forming the second mask layer 307, a stop layer 308 needs to be formed on the first mask layer 306, and the etching selectivity of the stop layer 308 is not equal to that of the first mask layer 306 and the second mask layer 307. When removing the second mask layer 307, the stop layer 308 can protect the first mask layer 306 from being damaged. Before forming Figure 15 the second groove 402 shown in FIG., the stop layer 308 needs to be removed to ensure that the width of the second groove 402 in the first direction is larger.

[0086] Exemplarily, the material of the stop layer 308 may include silicon oxide, silicon oxynitride, etc. The embodiments of the present application do not limit the material of the stop layer 308, as long as it is ensured that the etching selectivity of the stop layer 308 is not equal to that of the first mask layer 306 and the second mask layer 307.

[0087] As Figure 17 shown, in the implementation where the etching selectivity of the first mask layer 306 and the second mask layer 307 is equal or similar, the sum of the thickness of the first mask layer 306 and the thickness of the stop layer 308 may be (such as etc.), and the thickness of the second mask layer 307 may be (such as etc.). With such a setting, on the premise that the sum of the thicknesses of the first mask layer 306, the stop layer 308, and the second mask layer 307 is not too large, the thickness of the second mask layer 307 is kept relatively large to ensure that the width of the formed second groove 402 in the first direction is larger.

[0088] Continuing to refer to Figure 6 and Figure 7 , in the embodiments of the present application, before forming the first mask layer 306, a second dielectric layer 304 may be formed on the dummy gate structure 30. The second dielectric layer 304 may cover the sidewalls of the dummy gate structure 30 adjacent to the stacked structure 20 and the hard mask 301. The material of the second dielectric layer 304 may include low dielectric constant materials (Low-k) such as silicon oxycarbonitride (SiOCN). The capacitance effect between the ring gate transistors can be reduced through the second dielectric layer 304.

[0089] The embodiments of the present application further provide an electronic device, which may include a mobile phone, a computer, a tablet computer, a smart bracelet, a smart watch, AR, VR, etc. The embodiments of the present application do not limit the electronic device. The electronic device includes a circuit board and electronic components arranged on the circuit board. The electronic components may include a central processing unit (CPU), a memory, etc. The electronic components are electrically connected to the circuits on the circuit board.

[0090] In the above implementation, the electronic device may include a package substrate and a semiconductor structure, and the semiconductor structure is packaged on the package substrate. Exemplarily, a package circuit may be provided on the package substrate, the semiconductor structure is electrically connected to the package circuit, and the package circuit is connected to the circuit on the circuit board to achieve electrical connection between the semiconductor structure and the circuit board. It can be understood that the above semiconductor structure can be obtained by using the semiconductor structure manufacturing method in the above embodiment.

[0091] In the implementation where the electronic device is a central processing unit, the gate-all-around transistor in the semiconductor structure may be a logic device of the central processing unit. In the implementation where the electronic device is a memory, the gate-all-around transistor in the semiconductor structure may be a switching device. The embodiments of the present application do not limit the function of the gate-all-around transistor.

[0092] As mentioned above, the above is only the specific implementation manner of the embodiments of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims.

Claims

1. A method for fabricating a semiconductor structure, characterized in that, Comprising: Forming a stacked structure on a substrate, the stacked structure including a plurality of sacrificial layers and a plurality of channel layers alternately stacked; Forming a plurality of dummy gate structures on the stacked structure, the plurality of dummy gate structures being spaced apart; Forming a first mask layer on each of the dummy gate structures, the first mask layer covering the sidewalls of the dummy gate structures adjacent to the stacked structure; Forming a second mask layer on the first mask layer; Using the second mask layer as a mask to remove part of the stacked structure to form a plurality of first grooves, the first grooves extending to the substrate; Removing part of the sacrificial layer at the sidewalls of the first grooves to form voids; Removing the second mask layer; Using the first mask layer as a mask to form second grooves extending to the substrate; Forming electrode structures in contact with each of the channel layers at the second grooves.

2. The method for fabricating a semiconductor structure according to claim 1, wherein Before forming the second mask layer on the first mask layer, further comprising: Forming a stop layer on the first mask layer, the etching selectivity of the stop layer being unequal to both the etching selectivity of the first mask layer and the etching selectivity of the second mask layer; Before forming the second grooves extending to the substrate using the first mask layer as a mask, further comprising: removing the stop layer.

3. The method for fabricating a semiconductor structure according to claim 1 or 2, characterized in that, Removing part of the sacrificial layer at the sidewalls of the first grooves to form voids includes: Removing part of the sacrificial layer at the sidewalls of the first grooves while removing part of the channel layer in contact with the sacrificial layer to form a thinning region on the channel layer.

4. The method for fabricating a semiconductor structure according to claim 3, wherein, Using the first mask layer as a mask to form second grooves extending to the substrate includes: When forming the second grooves, at least part of the thinning regions on each of the channel layers are also removed.

5. The method for fabricating a semiconductor structure according to any one of claims 1-4, wherein Before removing the second mask layer, further comprising: Forming a filler in the voids.

6. The method for fabricating a semiconductor structure according to claim 5, wherein, Forming a filler in the voids includes: Forming a first dielectric layer at the sidewalls of the first grooves, and part of the first dielectric layer filling the voids to form the filler; Removing the first dielectric layer at the sidewalls of the first grooves.

7. The method for fabricating a semiconductor structure according to any one of claims 1-6, characterized in that, Forming electrode structures in contact with each of the channel layers at the second grooves includes: Based on the channel layers at the sidewalls of each of the second grooves, forming electrode structures by epitaxial growth.

8. The method for fabricating a semiconductor structure according to any one of claims 1-7, characterized in that, After forming electrode structures in contact with each of the channel layers at the second grooves, further comprising: Replacing the sacrificial layers with gate layers, and connecting each of the gate layers.

9. A semiconductor structure, characterized in that, The semiconductor structure is obtained by the semiconductor structure manufacturing method according to any one of claims 1-8.

10. An electronic device, characterized in that, A packaging substrate and the semiconductor structure according to claim 9, the semiconductor structure being disposed on the packaging substrate.

11. An electronic device, characterized in that, Comprising: A circuit board and the electronic device according to claim 10, the electronic device being disposed on the circuit board.

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