Semiconductor device and preparation method thereof

Abstract

The invention provides a semiconductor device and a preparation method thereof, relates to the technical field of semiconductor chips, and aims to solve the problem that the performance of the semiconductor device may be affected by doping more Mg between a grid electrode and a barrier layer of the semiconductor device. The semiconductor structure comprises a substrate, a channel layer, a barrier layer, a first functional layer, a first electrode, a second electrode and a grid electrode, the substrate, the channel layer and the barrier layer are sequentially stacked; the first functional layer is arranged on the side, away from the channel layer, of the barrier layer; the grid electrode is located between the first electrode and the second electrode and located on the side, away from the substrate, of the first functional layer; the first electrode and the second electrode are positioned on one side, away from the substrate, of the channel layer; wherein the material of the first functional layer comprises AlGaN; the first functional layer comprises a first sub-part, the content of Al atoms in the part, away from the substrate, of the first sub-part is smaller than the content of Al atoms in the part, close to the substrate, of the first sub-part in the first direction, and the first direction is the direction perpendicular to the substrate.

Description

Technical Field

[0001] The present disclosure relates to the technical field of semiconductor chips, and in particular, to a semiconductor device and a method for manufacturing the same. Background Art

[0002] A High Electron Mobility Transistor (HEMT) is a field effect transistor based on a heterojunction structure. Utilizing the energy band structure difference between different semiconductor materials, the conduction band bottom forms an energy band step at the heterojunction interface, thereby forming a quantum well. Electrons are distributed in the quantum well to form a two-dimensional electron gas (2DEG) with high concentration and high mobility that moves freely along the heterojunction interface and is restricted in the direction perpendicular to the interface, thus achieving high-performance electron transport.

[0003] With the increasing requirements for the breakdown voltage capability of semiconductor devices, for traditional depletion-type semiconductor devices, that is, when the gate bias is zero, the two-dimensional electron gas remains conducting, making the semiconductor device usually in the normally-on mode. There are problems in aspects such as the safety and energy consumption of such depletion-type semiconductor devices, and it is difficult to meet the application requirements.

[0004] Enhancement-type semiconductor devices can remain in the off state without a gate voltage and only turn on and conduct when a positive gate voltage is applied, reducing energy consumption and improving the safety of semiconductor devices. The normally-off characteristic can be achieved by introducing a P-type GaN (P-GaN) film doped with Mg between the gate and the barrier layer, but doping with more Mg may affect the performance of the semiconductor device. Summary of the Invention

[0005] Embodiments of the present disclosure provide a semiconductor device and a method for manufacturing the same, aiming to solve the problem that doping with more Mg between the gate and the barrier layer of a semiconductor device may affect the performance of the semiconductor device.

[0006] To achieve the above object, the embodiments of the present disclosure adopt the following technical solutions: On the one hand, a semiconductor device is provided. The semiconductor device includes: a substrate, a channel layer, a barrier layer, a first functional layer, a first electrode, a second electrode, and a gate.

[0007] The substrate, the channel layer, and the barrier layer are sequentially stacked. The first functional layer is disposed on a side of the barrier layer away from the channel layer. The gate is located between the first electrode and the second electrode, and the gate is located on a side of the first functional layer away from the substrate. The first electrode and the second electrode are located on a side of the barrier layer away from the substrate.

[0008] Among them, the material of the first functional layer includes: AlGaN; the first functional layer includes: a first sub - part. Along the first direction, which is perpendicular to the substrate, the content of Al atoms in the part of the first sub - part away from the substrate is less than that in the part close to the substrate.

[0009] For the semiconductor device provided by the above - mentioned embodiment of the present disclosure, on the one hand, AlGaN (aluminum gallium nitride) is a semiconductor material with high electron mobility and high breakdown voltage. In the first sub - part, the content of Al atoms in the part close to the substrate is relatively high, which causes the conduction - band offset at the heterojunction interface where the material of the barrier layer and the channel layer form a heterojunction structure to increase, forming a relatively high energy - band barrier. This will raise the conduction - band energy level in the region of the gate close to the barrier layer, making it higher than the Fermi level at zero gate voltage, and an enhancement - type semiconductor device can be realized. At the same time, doping Mg between the gate and the barrier layer is avoided, which affects the crystal quality of the film layer and the stability at higher temperatures, thus affecting the performance of the semiconductor device. And the relatively high barrier will increase the voltage range required for the gate to control the two - dimensional electron gas, causing the threshold voltage of the semiconductor device to drift positively, and improving the threshold voltage of the semiconductor device. On the other hand, the material of the first sub - part, that is, AlGaN, has a wider bandgap, which can reduce gate leakage.

[0010] In some embodiments, the first functional layer further includes: a second sub - part. Along the first direction, the content of Al atoms in the part of the second sub - part away from the substrate is greater than that in the part close to the substrate.

[0011] Among them, the change amount of the content of Al atoms per unit thickness in the second sub - part is less than that in the first sub - part.

[0012] In some embodiments, the first functional layer further includes: a third sub - part. The third sub - part is located on the side of the first sub - part away from the substrate. Along the first direction, the content of Al atoms in the third sub - part remains unchanged.

[0013] In some embodiments, the semiconductor device includes: the first sub - part, the second sub - part, and the third sub - part, and the number of at least one of the first sub - part, the second sub - part, and the third sub - part is multiple.

[0014] In some embodiments, the content range of Al atoms in the part of the first sub - part away from the substrate is 0% - 90%, and the content range of Al atoms in the part close to the substrate is 10% - 99.9%.

[0015] In some embodiments, the content range of Al atoms in the part of the second sub - part away from the substrate is 10% - 99.9%, and the content range of Al atoms in the part close to the substrate is 0% - 99%.

[0016] In some embodiments, the material of the first functional layer further includes at least one of Mg element, Be element, and Si element.

[0017] In some embodiments, the thickness range of the first functional layer is 10 nm to 500 nm.

[0018] In some embodiments, the semiconductor device further includes a second functional layer. The second functional layer is disposed between the barrier layer and the first functional layer.

[0019] The material of the second functional layer includes at least one of doped or undoped GaN, doped or undoped AlGaN, doped or undoped InGaN, and doped or undoped InAlGaN.

[0020] In some embodiments, the thickness range of the second functional layer is 1 nm to 50 nm.

[0021] On the other hand, a method for manufacturing a semiconductor device is provided. The method for manufacturing the semiconductor device includes: Forming a channel layer on one side of a substrate.

[0022] Forming a barrier layer on the side of the channel layer away from the substrate.

[0023] Forming a first functional layer on the side of the barrier layer away from the substrate, wherein the material of the first functional layer includes AlGaN. The first functional layer includes a first sub - part, and the content of Al atoms in the part of the first sub - part away from the substrate is less than the content of Al atoms in the part close to the substrate.

[0024] Forming a first electrode, a second electrode, and a gate located between the first electrode and the second electrode. The gate is located on the side of the first functional layer away from the substrate, and the first electrode and the second electrode are located on the side of the channel layer away from the substrate, to obtain the semiconductor device.

[0025] It can be understood that for the method for manufacturing a semiconductor device provided in the above embodiments of the present disclosure, the beneficial effects that can be achieved can refer to the beneficial effects of the semiconductor device in the above text, and will not be elaborated here.

[0026] In some embodiments, forming the first functional layer on the side of the barrier layer away from the substrate includes: In an atmosphere of an Al source, a Ga source, and an N source, during the formation of the first functional layer, the concentration of the Al source gradually decreases. Or, when the concentrations of the Al source, the Ga source, and the N source remain unchanged, the temperature is gradually decreased in the temperature range of 900 °C to 1400 °C to form the first functional layer. Description of the Drawings

[0027] To more clearly illustrate the technical solutions in the present disclosure, the following will briefly introduce the accompanying drawings required for some embodiments of the present disclosure. Obviously, the accompanying drawings in the following description are only the accompanying drawings of some embodiments of the present disclosure. For those of ordinary skill in the art, other accompanying drawings can also be obtained based on these drawings. In addition, the accompanying drawings in the following description can be regarded as schematic diagrams and do not limit the actual dimensions of the products involved in the embodiments of the present disclosure, the actual processes of the methods, etc.

[0028] Figure 1 It is a schematic structural diagram of a semiconductor device according to some embodiments; Figure 2 It is a schematic energy band diagram of a depletion-type semiconductor device according to some embodiments; Figure 3 It is a schematic structural diagram of a semiconductor device according to some other embodiments; Figure 4 It is a schematic energy band diagram of an enhancement-type semiconductor device according to some embodiments; Figure 5 It is a schematic structural diagram of a first functional layer according to some embodiments; Figure 6 It is a schematic structural diagram of a semiconductor device according to some other embodiments; Figure 7 It is a flowchart of a method for manufacturing a semiconductor device according to some embodiments; Figure 8 It is a structural diagram corresponding to each step in the method for manufacturing a semiconductor device according to some embodiments; Figure 9 It is a structural diagram corresponding to each step in the method for manufacturing a semiconductor device according to some other embodiments; Figure 10 It is a structural diagram corresponding to each step in the method for manufacturing a semiconductor device according to Embodiment 1; Figure 11 It is a structural diagram corresponding to each step in the method for manufacturing a semiconductor device according to Comparative Example 1; Figure 12 It is a transfer characteristic curve diagram of the semiconductor device of Embodiment 1 and the semiconductor device of Comparative Example 1; Figure 13 It is an energy band diagram of the semiconductor device of Embodiment 1 and the semiconductor device of Comparative Example 1. Detailed implementation manners

[0029] Next, the technical solutions in some embodiments of the present disclosure will be clearly and completely described in conjunction with the accompanying drawings. Obviously, the described embodiments are only a part of the embodiments of the present disclosure, rather than all of the embodiments. Based on the embodiments provided by the present disclosure, all other embodiments obtained by those of ordinary skill in the art belong to the scope of protection of the present disclosure.

[0030] In the description of the present disclosure, it should be understood that the orientation or positional relationship indicated by the terms "center", "upper", "lower", "front", "rear", "left", "right", "vertical", "horizontal", "top", "bottom", "inner", "outer", etc. is based on the orientation or positional relationship shown in the accompanying drawings. It is only for the convenience of describing the present disclosure and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore should not be construed as a limitation of the present disclosure.

[0031] Unless otherwise required by the context, throughout the specification and claims, the term "comprising" is to be construed in an open, inclusive sense, i.e., "including, but not limited to". In the description of the specification, the terms "one embodiment", "some embodiments", "exemplary embodiments", "exemplarily" or "some examples", etc. are intended to indicate that specific features, structures, materials or characteristics related to the embodiment or example are included in at least one embodiment or example of the present disclosure. The schematic representations of the above terms are not necessarily directed to the same embodiment or example. In addition, the specific features, structures, materials or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0032] "At least one of A, B, and C" has the same meaning as "at least one of A, B, or C", and both include the following combinations of A, B, and C: only A, only B, only C, the combination of A and B, the combination of A and C, the combination of B and C, and the combination of A, B, and C.

[0033] "A and / or B" includes the following three combinations: only A, only B, and the combination of A and B.

[0034] In the content of the present disclosure, the meanings of "on...", "above", and "over" should be interpreted in the broadest manner, such that "on..." not only means "directly on something", but also includes the meaning of "on something" with intermediate features or layers therebetween, and "above" or "over" not only means "above" or "over" something, but also includes the meaning of "above" or "over" something without intermediate features or layers therebetween (i.e., directly on something).

[0035] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thickness of layers and regions is exaggerated for clarity. Thus, variations in the shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include shape deviations resulting from, for example, manufacturing. For example, an etched region shown as rectangular will generally have curved features. Thus, the regions shown in the drawings are schematic in nature, and their shapes are not intended to depict the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0036] As used herein, the term "substrate" refers to a material on which subsequent material layers can be added. The substrate itself can be patterned. The materials added to the substrate can be patterned or can remain unpatterned. Additionally, the substrate can include a variety of semiconductor materials such as silicon, germanium, gallium arsenide, indium phosphide, etc. Alternatively, the substrate can be made of a non-conductive material such as glass, plastic, or a sapphire wafer.

[0037] Semiconductor: A semiconductor is a material whose electrical conductivity at room temperature is between that of a conductor and an insulator; semiconductors include intrinsic semiconductors and doped semiconductors. A pure semiconductor without impurities and defects, where the concentration of electrons and holes inside is equal, is called an intrinsic semiconductor. A semiconductor doped with a certain amount of impurities is called a doped semiconductor or non-intrinsic semiconductor. Among them, the impurities doped in the doped semiconductor can provide a certain concentration of carriers (such as holes or electrons, where a doped semiconductor doped with impurities that provide electrons (such as pentavalent phosphorus) is also called an n-type semiconductor or an N (negative) -type semiconductor, and a doped semiconductor doped with impurities that provide holes (such as trivalent boron) is also called a p-type semiconductor or a P (positive) -type semiconductor). When this occurs, it can improve the electrical conductivity of the intrinsic semiconductor. Generally, the greater the carrier concentration, the lower the resistivity of the semiconductor and the better its conductivity. In the embodiments of the present disclosure, this type of doped semiconductor is also called a conductive semiconductor. For example, a conductive silicon carbide material doped with impurities such as nitrogen N, boron B, aluminum Al, etc. In addition, when the impurities doped in the doped semiconductor can perform impurity compensation on the doped semiconductor, the donor electrons just fill the acceptor energy level but do not provide electrons and holes to the conduction band and valence band, making the semiconductor material with a wider bandgap have a resistivity similar to that of an insulator. For example, in the embodiments of the present disclosure, doping a silicon carbide material with a transition metal achieves impurity compensation for the silicon carbide material, thereby increasing the resistivity of the silicon carbide material. This type of doped semiconductor is also called a semi-insulating semiconductor or a semi-insulator, or has semi-insulator characteristics.

[0038] Unless otherwise defined, all technical terms used herein have the same meaning as commonly understood by one of ordinary skill in the art. In this disclosure, "at least one" means one or more, and "a plurality" means two or more. "And / or" describes the relationship between associated objects and indicates that three relationships can exist. For example, A and / or B can represent: A exists alone, A and B exist simultaneously, or B exists alone, where A and B can be singular or plural. The character " / " generally indicates an "or" relationship between the associated objects before and after. "At least one of the following" or similar expressions refer to any combination of these items, including any combination of single items or plural items. For example, at least one of a, b, or c can represent: a, b, c, a and b, a and c, b and c, or a, b, and c, where a, b, and c can be single or multiple. Additionally, in the embodiments of this disclosure, terms such as "first" and "second" do not limit the quantity and order.

[0039] The technical solutions of this disclosure can be applied to electronic devices, which can be different types of user devices or terminal devices such as computers, mobile phones, tablet computers, wearable devices, and in-vehicle devices; the electronic device can also be a network device such as a base station. The electronic device can also be a device such as a power amplifier used in the above-mentioned electronic devices. The specific form of the above-mentioned electronic device is not particularly limited in the embodiments of this disclosure.

[0040] A High Electron Mobility Transistor (HEMT) is a field-effect transistor based on a heterojunction structure. Utilizing the energy band structure difference between different semiconductor materials, the bottom of the conduction band forms an energy band step at the heterojunction interface, thereby forming a quantum well. Electrons are distributed in the quantum well, forming a two-dimensional electron gas with high concentration and high mobility that moves freely along the heterojunction interface and is restricted in the direction perpendicular to the interface, thus achieving high-performance electron transport.

[0041] In some embodiments, a semiconductor device 100 is provided. As Figure 1 shown, the semiconductor device 100 includes: a substrate 10, a channel layer 12, and a barrier layer 13 stacked in sequence; and a first electrode 15, a second electrode 16, and a gate 17.

[0042] The gate 17 is located between the first electrode 15 and the second electrode 16, and the gate 17 is located on the side of the barrier layer 13 away from the substrate 10, and the first electrode 15 and the second electrode 16 are located on the side of the channel layer 12 away from the substrate 10.

[0043] The substrate 10 is the foundation of the semiconductor device 100. The substrate 10 provides physical and electrical support and is usually made of silicon, gallium arsenide, or other semiconductor materials.

[0044] The first pole 15 and the second pole 16 are electrodes of the semiconductor device 100, and a voltage can be applied to regulate the carrier flow in the channel layer 12.

[0045] In some examples, the first pole 15 is the source electrode and the second pole 16 is the drain electrode.

[0046] In still other examples, the first pole 15 is the drain electrode and the second pole 16 is the source electrode.

[0047] The gate 17 is used to control the carrier flow at the heterojunction interface between the channel layer 12 and the barrier layer 13. When a voltage is applied, a channel for lifting electrons or holes is formed in the channel layer 12, thereby realizing the switching function of the semiconductor device 100. The material of the channel layer 12 includes at least one of group III-V compounds, such as GaN, AlGaN, InGaN, or InAlGaN, etc.

[0048] The material of the barrier layer 13 includes at least one of group III-V compounds with different components and a wider bandgap than the channel layer 12, such as AlN or AlGaN, etc.

[0049] The channel layer 12 and the barrier layer 13 can form a heterojunction structure, generating 2DEG (the part outlined by the dashed box) at the interface.

[0050] In some examples, a buffer layer 11 is further included between the substrate 10 and the channel layer 12, which can buffer the stress that may occur between the substrate 10 and the channel layer 12 materials, make the lattice match between the substrate 10 and the channel layer 12 materials, reduce the thermal stress and physical strain caused by temperature changes, and thus reduce the formation of defects.

[0051] In some examples, a passivation layer 18 is further included on the side of the barrier layer 13 away from the substrate 10, which can effectively protect the surface of the semiconductor device 100, prevent the influence of environmental factors (such as oxygen and moisture) on the semiconductor device 100, and also reduce the influence brought by surface defects and impurities, thereby improving the stability and long-term reliability of the semiconductor device 100.

[0052] As the requirements for the breakdown voltage capability of the semiconductor device 100 are getting higher and higher, the semiconductor device 100 with an AlN / AlGaN heterojunction structure has excellent electrical characteristics such as higher pressure and temperature resistance, low on-resistance, low on-loss, and high switching speed. Among them, the source electrode, drain electrode, and two-dimensional electron gas of the semiconductor device 100 form an ohmic contact, enabling the two-dimensional electron gas to transport along the heterojunction interface to form a current.

[0053] The semiconductor device 100 includes a depletion-type semiconductor device 100A and an enhancement-type semiconductor device 100B.

[0054] When the gate 17 is biased to zero, the two-dimensional electron gas remains conducting, and the semiconductor device 100 is in the normally-on mode, that is, the depletion-type semiconductor device 100A. As Figure 2 shown, Figure 2 is the energy band diagram of the depletion-type semiconductor device 100A, Ec is the energy at the bottom of the conduction band, is the energy, is the change in the Fermi level, is the energy difference at the bottom of the conduction band, is the barrier height. The material of the barrier layer 13 (such as AlGaN) and the material of the channel layer 12 (such as GaN) form a heterojunction structure, such as an AlGaN / GaN heterojunction, which will form an energy band well at the bottom of the conduction band at the heterojunction interface due to polarization, thereby generating a two-dimensional electron gas. And when the gate 17 is biased to zero, due to the existence of the energy band well, the two-dimensional electron gas remains conducting, that is, the normally-on mode. There are problems in terms of the safety and energy consumption of the depletion-type semiconductor device 100A, and the drive circuit is also more complex and costly, making it difficult to meet the application requirements.

[0055] The enhancement-type semiconductor device 100B can remain in the off state when the gate 17 is biased to zero, that is, the normally-off mode. It conducts electricity only when a positive gate 17 voltage is applied, which reduces energy consumption and improves the safety of the semiconductor device 100.

[0056] In some implementation manners, in order to form the enhancement-type semiconductor device 100B, a P-type GaN (P-GaN) film doped with Mg is introduced between the gate 17 and the barrier layer 13. The holes formed by the Mg acceptors in the P-type GaN recombine with the electrons of the two-dimensional electron gas, and the two-dimensional electron gas at the interface can be depleted when the gate 17 is biased to zero, realizing the normally-off characteristic. However, the incorporation of more Mg may affect the performance of the semiconductor device 100.

[0057] In some examples, when preparing the semiconductor device 100, when forming the gate 17, at a relatively high temperature, the Mg element will inevitably diffuse into the barrier layer 13 and the channel layer 12, which will greatly hinder the increase of the threshold voltage of the semiconductor device 100 and damage the performance of the semiconductor device 100; or, during the high-temperature annealing process of the first electrode 15 and the second electrode 16, the Mg element will also diffuse into the barrier layer 13 and the channel layer 12, which will limit the annealing temperature of the first electrode 15 and the second electrode 16, resulting in a decrease in the performance of the semiconductor device 100. At the same time, due to the low activation efficiency of the Mg element, more doping will cause serious lattice damage and affect the leakage performance of the semiconductor device 100.

[0058] In some other examples, in order to prevent the activation of Mg elements, Mg-H bonds are formed by hydrogen ion implantation on the film layer of the gate 17 (the material is P-GaN) to prevent the activation of Mg elements, that is, to form a high-resistance P-GaN. However, during the use of the semiconductor device 100, the relatively high temperature will slowly open the Mg-H bonds, activate Mg, cause the failure of the high-resistance P-GaN, thus affecting the stability of the semiconductor device 100 and restricting its application in the high-voltage field.

[0059] Based on this, an embodiment of the present disclosure provides a semiconductor device 100. As Figure 3 shown, the semiconductor device 100 includes: a substrate 10, a channel layer 12, a barrier layer 13, a first functional layer 14, a first electrode 15, a second electrode 16, and a gate 17.

[0060] The substrate 10, the channel layer 12, and the barrier layer 13 are sequentially stacked; the first functional layer 14 is disposed on a side of the barrier layer 13 away from the channel layer 12. The gate 17 is located between the first electrode 15 and the second electrode 16, and the gate 17 is located on a side of the first functional layer 14 away from the substrate 10. The first electrode 15 and the second electrode 16 are located on a side of the barrier layer 13 away from the substrate 10.

[0061] Among them, as Figure 5 shown, in combination with Figure 3 , the material of the first functional layer 14 includes: AlGaN, and the first functional layer 14 includes: a first sub-part 141. Along the first direction Y, the content of Al atoms in the part of the first sub-part 141 away from the substrate 10 is less than the content of Al atoms in the part close to the substrate 10. The first direction Y is a direction perpendicular to the substrate 10.

[0062] That is to say, along the first direction Y perpendicular to and away from the substrate 10, the content of Al atoms in the first functional layer 14 gradually decreases.

[0063] On one hand, AlGaN (aluminum gallium nitride) is a semiconductor material with high electron mobility and high breakdown voltage. In the first sub - part 141, the content of Al atoms is higher in the part closer to the substrate 10, which causes an increase in the conduction - band offset at the heterojunction interface where the material of the barrier layer 13 and the channel layer 12 form a heterojunction structure, forming a higher energy - band barrier. This will increase the conduction - band energy level in the region of the gate 17 close to the barrier layer 13, making it higher than the Fermi level when the gate 17 is biased to zero, and an enhancement - mode semiconductor device 100B can be realized. At the same time, doping Mg between the gate 17 and the barrier layer 13 is avoided, which affects the crystal quality of the film layer and the stability at higher temperatures, and further affects the performance of the semiconductor device 100. Also, the higher energy - band barrier will expand the voltage range required for the gate 17 to control the two - dimensional electron gas, resulting in a positive drift of the threshold voltage (Vth) of the semiconductor device 100, and improving the threshold voltage of the semiconductor device 100. On the other hand, the wider bandgap of the material of the first sub - part 141, that is, AlGaN, can reduce the leakage current of the gate 17.

[0064] As Figure 4 shown, Figure 4 FIG. is a schematic energy - band diagram of the enhancement - mode semiconductor device 100B, Ec is the energy of the bottom of the conduction band, is the energy, is the energy difference at the bottom of the conduction band. The material of the barrier layer 13 (such as AlGaN) and the material of the channel layer 12 (such as GaN) form a heterojunction structure, for example, expressed as an AlGaN / GaN heterojunction. Due to the polarization effect, an energy - band well is formed at the bottom of the conduction band at the AlGaN / GaN heterojunction interface, and then a two - dimensional electron gas is generated. After introducing the first functional layer 14 (AlGaN) on one side of the gate 17, the energy - band position of the AlGaN / GaN heterojunction can be increased. When the energy - band position of the heterojunction is higher than the Fermi level, the energy - band well is no longer effective and the two - dimensional electron gas is depleted. The semiconductor device 100 is in the off state without external gate 17 voltage control, that is, the normally - off mode is realized, that is, the enhancement - mode semiconductor device 100B.

[0065] In some embodiments, as Figure 5 shown, combined with Figure 3 , the first functional layer 14 further includes: a second sub - part 143. Along the first direction Y, the content of Al atoms in the part of the second sub - part 143 far from the substrate 10 is greater than the content of Al atoms in the part close to the substrate 10.

[0066] Among them, the change amount per unit thickness of the Al - atom content in the second sub - part 143 is less than the change amount per unit thickness of the Al - atom content in the first sub - part 141.

[0067] That is to say, along the first direction Y perpendicular to and away from the substrate 10, there is a tendency for the content of Al atoms to increase in a part of the first functional layer 14. That is, when the first functional layer 14 includes a first sub-part 141 and a second sub-part 143 on the side of the first sub-part 141 away from the substrate 10, along the first direction Y perpendicular to and away from the substrate 10, the content of Al atoms in the first functional layer 14 first decreases and then increases.

[0068] It can be understood that in the second sub-part 143, as the content of Al atoms increases, a stronger polarization field and a higher concentration of electron gas can be effectively formed, forming a PN junction with the first sub-part 141 (by different doping processes, one side forms an N-type semiconductor and the other side forms a P-type semiconductor, and the region near the interface of the two semiconductors is the PN junction). That is, as the content of Al atoms in the first sub-part 141 decreases, this region forms a P-type semiconductor (with holes as the main carriers), and as the content of Al atoms in the second sub-part 143 increases, this region forms an N-type semiconductor (with electrons as the main carriers). Then, a PN junction is formed in the region near the interface between the first sub-part 141 and the second sub-part 143. At this interface, carriers diffuse due to the concentration difference, leaving immobile impurity ions, forming a built-in electric field (from the N region to the P region), and finally reaching dynamic equilibrium to form a depletion layer. The depletion region can form a high potential barrier to hinder the tunneling of carriers, thereby suppressing the tunneling effect; and the depletion region also acts as an insulating barrier to prevent direct carrier injection between the gate 17 and the drain, thereby reducing the gate 17 leakage current. At the same time, the electric field distribution can be effectively adjusted to avoid excessive concentration of the electric field in some regions, thereby increasing the breakdown voltage of the semiconductor device 100. Moreover, by precisely controlling the content of Al atoms in the first sub-part 141 and the second sub-part 143, the threshold voltage can be finely adjusted between the two to achieve more flexible and repeatable threshold voltage regulation.

[0069] In some embodiments, as Figure 5 shown, in combination with Figure 3 , the first functional layer 14 further includes: a third sub-part 142. The third sub-part 142 is located on the side of the first sub-part 141 away from the substrate 10. Along the first direction Y, the content of Al atoms in the third sub-part 142 remains unchanged.

[0070] That is to say, in the first functional layer 14, on the side of the first sub-part 141 away from the barrier layer 13, along the first direction Y perpendicular to and away from the substrate 10, there may also be a part with an unchanged content of Al atoms.

[0071] Understandably, keeping the content of Al atoms in the third sub - part 142 unchanged can effectively reduce the accumulation of stress and defects in the first functional layer 14 caused by concentration changes, thereby contributing to maintaining the stability of the entire semiconductor device 100 structure. Also, due to the unchanged content of Al atoms in the third sub - part 142, the third sub - part 142 can serve as a stable electric field structure, making the electric field in the first functional layer 14 more uniform when the gate 17 is turned off, which helps to maintain the stability of the threshold voltage.

[0072] In some embodiments, the first functional layer 14 includes: a first sub - part 141, a second sub - part 143, and a third sub - part 142, and the number of at least one of the first sub - part 141, the second sub - part 143, and the third sub - part 142 is multiple.

[0073] Understandably, through the combined and coordinated action of the first sub - part 141, the second sub - part 143, and the third sub - part 142, not only can a normally - off enhancement - type semiconductor device 100B be realized, the threshold voltage be optimized, the reliability of the semiconductor device 100 be improved, but also the gate 17 leakage can be reduced, the semiconductor device 100's tolerance to the electric field can be effectively increased, a more complex electric field distribution can be formed, thereby enhancing the breakdown voltage performance of the semiconductor device 100 and reducing the breakdown risk. Also, through the combined and coordinated action of the first sub - part 141, the second sub - part 143, and the third sub - part 142, the threshold voltage of the semiconductor device 100 can be flexibly regulated.

[0074] Exemplarily, as Figure 5 shown, at least one of the first sub - part 141, the second sub - part 143, and the third sub - part 142 is located in a different layer from another of the first sub - part 141, the second sub - part 143, and the third sub - part 142.

[0075] Understandably, the first sub - part 141, the second sub - part 143, and the third sub - part 142 being located in different layers can utilize different materials and doping concentrations to achieve optimal performance and enhance the performance of the semiconductor device 100.

[0076] In some embodiments, the content range of Al atoms in the part of the first sub - part 141 far from the substrate 10 is 0% - 90%, and the content range of Al atoms in the part of the first sub - part 141 close to the substrate 10 is 10% - 99.9%.

[0077] Exemplarily, the content of Al atoms in the part of the first sub - part 141 far from the substrate 10 can be 90%, 80%, 50%, 30% or 0%, etc., and there is no limitation here.

[0078] Exemplarily, the content of Al atoms in the part of the first sub - part 141 close to the substrate 10 can be 99.9%, 80%, 50%, 30% or 10%, etc., and there is no limitation here.

[0079] Understandably, the above settings help to form a two-dimensional electron gas with a relatively high concentration, improve the conductivity and mobility of the semiconductor device 100, and can also better regulate the threshold voltage, enabling the entire semiconductor device 100 to have better performance in switching operations and improving the switching frequency and efficiency.

[0080] In some embodiments, the content of Al atoms in the portion of the second sub-part 143 away from the substrate 10 ranges from 10% to 99.9%, and the content of Al atoms in the portion close to the substrate 10 ranges from 0% to 99%.

[0081] Exemplarily, the content of Al atoms in the portion of the second sub-part 143 away from the substrate 10 can be 99.9%, 80%, 50%, 30% or 10%, etc., and there is no limitation here.

[0082] Exemplarily, the content of Al atoms in the portion of the second sub-part 143 close to the substrate 10 can be 99%, 80%, 50%, 30% or 0%, etc., and there is no limitation here.

[0083] Understandably, the above settings can enable the semiconductor device 100 to withstand a higher voltage, isolate the electron gas in different regions at the same time, reduce the leakage current, increase the breakdown voltage of the semiconductor device 100, and enhance the stability of the semiconductor device 100 under high-power conditions.

[0084] In some embodiments, the material of the first functional layer 14 further includes at least one of Mg element, Be element and Si element.

[0085] Understandably, doping Mg and Be elements into AlGaN can compensate for the surface state charges of the first functional layer 14, thereby regulating the threshold voltage shift of the semiconductor device 100, optimizing the performance of the semiconductor device 100, and improving the stability of the semiconductor device 100. Doping Si element into AlGaN can optimize the carrier concentration and improve the performance and reliability of the semiconductor device 100.

[0086] In some embodiments, the thickness of the first functional layer 14 ranges from 10 nm to 500 nm.

[0087] Exemplarily, the thickness of the first functional layer 14 can be 10 nm, 80 nm, 100 nm, 200 nm, 300 nm or 500 nm, etc., and there is no limitation here.

[0088] Understandably, setting the thickness of the first functional layer 14 within the range of 10 nm to 500 nm can ensure sufficient polarization cancellation effect, avoiding the normally-on failure caused by the insufficient thickness (< 10 nm) of the first functional layer 14; or avoiding the decrease in the control ability of the gate 17 and the influence on the switching speed due to the excessive thickness (> 500 nm) of the first functional layer 14; it can effectively modulate the polarization electric field of the barrier layer 13, effectively deplete the two-dimensional electron gas in the channel layer 12, and make the semiconductor device 100 in the off state when the voltage of the gate 17 is 0.

[0089] In some embodiments, as Figure 6 shown, the semiconductor device 100 further includes: a second functional layer 19. The second functional layer 19 is disposed between the barrier layer 13 and the first functional layer 14.

[0090] The material of the second functional layer 19 includes at least one of doped or undoped GaN, doped or undoped AlGaN, doped or undoped InGaN, and doped or undoped InAlGaN.

[0091] Understandably, by using at least one of the above-mentioned doped or undoped GaN, doped or undoped AlGaN, doped or undoped InGaN, and doped or undoped InAlGaN, i.e., undoped GaN / AlGaN, for the second functional layer 19, a high-mobility transition layer can be formed to reduce the interface scattering between the barrier layer 13 and the first functional layer 14, and a heterojunction is formed between the second functional layer 19 and the barrier layer 13, thereby improving the breakdown voltage performance of the semiconductor device 100.

[0092] In some embodiments, the thickness range of the second functional layer 19 is 1 nm to 50 nm.

[0093] Exemplarily, the thickness of the second functional layer 19 can be 1 nm, 10 nm, 30 nm, 40 nm, or 50 nm, etc., and there is no limitation here.

[0094] Understandably, setting the thickness of the second functional layer 19 within the range of 1 nm to 50 nm can avoid the penetration of interface defects caused by the too thin thickness (< 1 nm) of the second functional layer 19, or avoid the unnecessary series resistance that may be introduced due to the too thick thickness (> 50 nm) of the second functional layer 19; it can effectively modulate the polarization electric field of the AlGaN / GaN heterojunction and assist the first functional layer 14 to achieve stable normally-off characteristics.

[0095] Embodiments of the present disclosure provide a method for manufacturing a semiconductor device 100. As Figure 7 and Figure 8 shown, the method for manufacturing the semiconductor device 100 includes: S1 to S4.

[0096] S1: Form a channel layer 12 on one side of the substrate 10.

[0097] Exemplarily, the substrate 10 can be one of a sapphire flat substrate, a sapphire nano-patterned substrate, an Si substrate, a silicon carbide substrate, a QST substrate, and an AlN single crystal substrate.

[0098] Exemplarily, the thickness range of the channel layer 12 can be 50 nm to 500 nm.

[0099] Exemplarily, the material of the channel layer 12 includes one or more groups of III-V compounds, including at least one of GaN, AlGaN, InGaN, and InAlGaN.

[0100] In some examples, before forming the channel layer 12, it further includes: forming a buffer layer 11 with a thickness range of 300 nm to 5000 nm on one side of the substrate 10; the forming method can be Metal-organic Chemical Vapor Deposition (MOCVD) technology.

[0101] S2: Form a barrier layer 13 on the side of the channel layer 12 away from the substrate 10.

[0102] Exemplarily, the barrier layer 13 includes one or more groups of III-V compounds with different components and a wider bandgap than the channel layer 12, including at least one of AlN and AlGaN.

[0103] Exemplarily, the thickness range of the barrier layer 13 is 10 nm to 40 nm.

[0104] S3: Form a first functional layer 14 on the side of the barrier layer 13 away from the substrate 10, wherein the material of the first functional layer 14 includes: AlGaN. The first functional layer 14 includes: a first sub-part 141, and the content of Al atoms in the part of the first sub-part 141 away from the substrate 10 is less than the content of Al atoms in the part close to the substrate 10.

[0105] In some examples, after forming the first functional layer 14, it further includes: depositing a dielectric material on the side of the first functional layer 14 away from the barrier layer 13 and on the side of the barrier layer 13 away from the substrate 10 to form a passivation layer 18 with a thickness range of 50 nm to 400 nm. The deposition methods include any one of plasma enhanced atomic layer deposition (PEALD), atomic layer deposition (ALD), plasma enhance chemical vapor deposition (PECVD), and low pressure chemical vapor deposition (LPCVD) processes. The dielectric material includes at least one of SiO2, SiN, Al2O3, and AlON.

[0106] S4: Form a first electrode 15, a second electrode 16, and a gate 17 located between the first electrode 15 and the second electrode 16. The gate 17 is located on the side of the first functional layer 14 away from the substrate 10, and the first electrode 15 and the second electrode 16 are located on the side of the barrier layer 13 away from the substrate 10, thereby obtaining the semiconductor device 100.

[0107] It can be understood that the above steps S1 to S4 provide a method for manufacturing a semiconductor device 100. The beneficial effects that can be achieved can refer to the beneficial effects of the semiconductor device 100 in the above text and will not be elaborated here.

[0108] In some embodiments, forming the first functional layer 14 on the side of the barrier layer 13 away from the substrate 10 in S3 includes: In an atmosphere of an Al source, a Ga source, and an N source, during the formation of the first functional layer 14, the concentration of the Al source gradually decreases. Alternatively, when the concentrations of the Al source, the Ga source, and the N source remain unchanged, the temperature is gradually decreased in a temperature range of 900 °C to 1400 °C to form the first functional layer 14.

[0109] Exemplarily, as Figure 8 shown, forming the first functional layer 14 on the side of the barrier layer 13 away from the substrate 10 in S3 includes: S3.1A to S3.2A.

[0110] S3.1A: Form an initial functional layer 14A in an atmosphere of an Al source, a Ga source, and an N source. During the formation of the initial functional layer 14A, the concentration of the Al source gradually decreases, or, with the concentrations of the Al source, Ga source, and N source remaining unchanged, the temperature is gradually decreased in the temperature range of 900°C to 1400°C to form the initial functional layer 14A. The initial functional layer 14A includes a first part 14a and a second part 14b. The first part 14a is located between the pre-formed gate 17 and the barrier layer 13, and the second part 14b is the part other than the first part 14a.

[0111] Exemplarily, the gradual decrease in the concentration of the Al source can reduce the content of the Al source, or can increase the content of the Ga source to gradually decrease the concentration of the Al source.

[0112] Exemplarily, in an atmosphere of an Al source, a Ga source, and an N source and in the temperature range of 1200°C to 1400°C, the content of Al in AlGaN is a first content; in an atmosphere of the same amounts of the Al source, Ga source, and N source and in the temperature range of 900°C to 1100°C, the content of Al in AlGaN is a second content, and the second content is less than the first content. Therefore, by setting the temperature range for forming the initial functional layer 14A to gradually decrease from 1200°C to 1400°C to the range of 900°C to 1100°C, AlGaN with a gradually decreasing concentration of the Al source can be obtained.

[0113] S3.2A: Remove the second part 14b to form a first functional layer 14.

[0114] Exemplarily, the removal of the second part 14b can be inductively coupled plasma etching.

[0115] Here, when removing the second part 14b, a part of the barrier layer 13 can be removed.

[0116] It can be understood that in S3, by directly forming the first functional layer 14 on the side of the barrier layer 13 away from the substrate 10 using an Al source, a Ga source, and an N source, the introduction of Mg can be avoided, thereby realizing non-intrusive p-type doping and improving the performance of the semiconductor device 100.

[0117] Exemplarily, as Figure 9 shown, forming the first functional layer 14 on the side of the barrier layer 13 away from the substrate 10 in S3 includes: S3.1B to S3.4B.

[0118] S3.1B: Provide a mask plate P.

[0119] S3.2B: The mask plate P covers the region of the barrier layer 13 other than the region (the framed part) of the pre-formed gate 17.

[0120] S3.3B: Form the initial functional layer 14A, where the initial functional layer 14A covers the mask plate P and the region of the pre-formed gate 17 of the barrier layer 13.

[0121] Exemplarily, gradually reducing the concentration of the Al source can reduce the content of the Al source and can also increase the content of the Ga source to gradually reduce the concentration of the Al source.

[0122] Exemplarily, in an atmosphere of an Al source, a Ga source, and an N source and in a temperature range of 1200°C to 1400°C, the content of Al in AlGaN is a first content; in an atmosphere of the same amounts of the Al source, the Ga source, and the N source and in a temperature range of 900°C to 1100°C, the content of Al in AlGaN is a second content, and the second content is less than the first content. Therefore, by setting the temperature range for forming the initial functional layer 14A to gradually decrease from 1200°C to 1400°C to within the range of 900°C to 1100°C, AlGaN with a gradually decreasing concentration of the Al source can be obtained.

[0123] S3.4B: Remove the mask plate P, and the part of the initial functional layer 14A that covers the region of the pre-formed gate 17 of the barrier layer 13 forms the first functional layer 14.

[0124] It can be understood that the mask plate is provided to protect the region of the barrier layer 13 other than the region of the pre-formed gate 17, so that only the region of the pre-formed gate 17 is exposed. Then, the initial functional layer 14A is formed, and then the mask plate is removed, so that the part of the initial functional layer 14A that covers the region of the pre-formed gate 17 of the barrier layer 13 forms the first functional layer 14.

[0125] In some embodiments, S3 forms the first functional layer 14 on the side of the barrier layer 13 away from the substrate 10, and further includes: Form the second sub-part 143. The content of Al atoms in the part of the second sub-part 143 away from the substrate 10 is greater than the content of Al atoms in the part close to the substrate 10. The change amount of the content of Al atoms in the second sub-part 143 is less than the change amount of the content of Al atoms in the first sub-part 141, and the thickness of the second sub-part 143 is greater than the thickness of the first sub-part 141.

[0126] Exemplarily, the content of the Al source can be increased, or the content of the Ga source can be reduced to gradually increase the concentration of the Al source.

[0127] Exemplarily, in an atmosphere of an Al source, a Ga source, and an N source and in a temperature range of 900°C to 1100°C, the content of Al in AlGaN is the third content; in an atmosphere of the same amounts of the Al source, the Ga source, and the N source and in a temperature range of 1200°C to 1400°C, the content of Al in AlGaN is the fourth content, and the third content is less than the fourth content. Therefore, by setting the temperature range for forming the second sub - part 143 to gradually increase from 900°C to 1100°C to within the range of 1200°C to 1400°C, AlGaN with a gradually increasing concentration of the Al source can be obtained.

[0128] It can be understood that the beneficial effects achievable by the formed second sub - part 143 are the same as those of the second sub - part 143 in the above text, and will not be elaborated here.

[0129] In some embodiments, S3 forms a first functional layer 14 on the side of the barrier layer 13 away from the substrate 10, and further includes: Forming a third sub - part 142, which is located on the side of the first sub - part 141 away from the substrate 10. The content of Al atoms in the third sub - part 142 remains unchanged.

[0130] It can be understood that the beneficial effects achievable by the formed third sub - part 142 are the same as those of the third sub - part 142 in the above text, and will not be elaborated here.

[0131] Embodiment 1 Embodiment 1 provides a semiconductor device 100. As Figure 10 shown, the manufacturing method of the semiconductor device 100 includes: T1 - T7.

[0132] T1: Deposit and form a buffer layer 11 on one side of the substrate 10; then deposit and form a channel layer 12 on the side of the buffer layer 11 away from the substrate 10.

[0133] T2: Deposit and form a barrier layer 13 on the side of the channel layer 12 away from the buffer layer 11.

[0134] T3: Deposit and form an initial functional layer 14A on the side of the barrier layer 13 away from the channel layer 12, clean, perform photolithography, and pre - form the region of the gate 17. The initial functional layer 14A includes a first part 14a and a second part 14b. The first part 14a is located between the pre - formed gate 17 and the barrier layer 13, and the second part 14b is the part other than the first part 14a.

[0135] T4: Remove the second part 14b to form the first functional layer 14. Among them, the thickness of the first functional layer 14 is 30 nm, and the content of Al atoms in the first functional layer 14 gradually decreases from 80% to 0% along the first direction Y perpendicular to and away from the substrate 10.

[0136] T5: Repair the etched surface damage and deposit an initial passivation layer 18A on the side of the first functional layer 14 away from the barrier layer 13.

[0137] Exemplarily, the repair method can be annealing, wet etching, and dry etching, etc.

[0138] T6: Pre-form a first pole 15 region and a second pole 16 region on the side of the initial passivation layer 18A away from the barrier layer 13 respectively. Etch away the initial passivation layer 18A in the pre-formed first pole 15 region, the initial passivation layer 18A, the barrier layer 13, and a part of the channel layer 12 in the pre-formed second pole 16 region. Deposit metal on the channel layer 12 to form the first pole 15 and the second pole 16, and then anneal.

[0139] Exemplarily, the first pole 15 can be a source electrode.

[0140] Exemplarily, the second pole 16 can be a drain electrode.

[0141] T7: Etch away the initial passivation layer 18A in the region of the pre-formed gate 17 to form a passivation layer 18, and deposit gate metal in the region of the pre-formed gate 17 to form the gate 17.

[0142] Comparative Example 1 Comparative Example 1 provides a semiconductor device 100. As Figure 11 shown, the manufacturing method of the semiconductor device 100 includes: N1~N6.

[0143] N1: Deposit and form a buffer layer 11 on one side of the substrate 10; then deposit and form a channel layer 12 on the side of the buffer layer 11 away from the substrate 10.

[0144] N2: Deposit and form a barrier layer 13 on the side of the channel layer 12 away from the buffer layer 11.

[0145] N3: Deposit and form an initial passivation layer 18A on the side of the barrier layer 13 away from the channel layer 12.

[0146] N4: Pre-form a first pole 15 region and a second pole 16 region on the side of the initial passivation layer 18A away from the barrier layer 13 respectively. Etch away the initial passivation layer 18A in the pre-formed first pole 15 region, the initial passivation layer 18A, the barrier layer 13, and a part of the channel layer 12 in the pre-formed second pole 16 region. Deposit metal on the channel layer 12 to form the first pole 15 and the second pole 16, and then anneal.

[0147] Exemplarily, the first pole 15 can be a source electrode.

[0148] Exemplarily, the second pole 16 can be a drain electrode.

[0149] N5: Perform lithography for cleaning, pre-form the region of the gate 17, and etch away the initial passivation layer 18A in the region of the pre-formed gate 17 to form the passivation layer 18.

[0150] N6: Deposit gate metal in the region of the pre-formed gate 17 to form the gate 17.

[0151] Test the transfer characteristics of the semiconductor device 100 of Example 1 and the semiconductor device 100 of Comparative Example 1. As Figure 12 shown, Figure 12 is the transfer characteristic curve graph of the semiconductor device 100 of Example 1 and the semiconductor device 100 of Comparative Example 1. It can be seen that the threshold voltage of the semiconductor device 100 of Example 1 is 0.66V, and the threshold voltage of the semiconductor device 100 of Comparative Example 1 is -1.92V. The threshold voltage of the semiconductor device 100 of Example 1 increases by 2.58V compared with that of the semiconductor device 100 of Comparative Example 1, realizing the enhancement-type semiconductor device 100B.

[0152] Test the energy bands of the semiconductor device 100 of Example 1 and the semiconductor device 100 of Comparative Example 1. As Figure 13 shown, Figure 13 is the energy band diagram of the semiconductor device 100 of Example 1 and the semiconductor device 100 of Comparative Example 1. The horizontal axis is the thickness of the semiconductor device 100, with the unit of μm. It can be seen that at the same thickness, the conduction band and valence band of the semiconductor device 100 of Example 1 are higher than those of the semiconductor device 100 of Comparative Example 1, indicating that the semiconductor device 100 of Example 1 has higher electron mobility and better conductivity.

[0153] The above description is only the specific implementation manner of the present invention, but the protection scope of the present invention is not limited thereto. Any changes or substitutions that can be easily thought of by those skilled in the art within the technical scope disclosed by the present invention should be covered within the protection scope of the present invention. Therefore, the protection scope of the present invention should be subject to the protection scope of the claims.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate, a channel layer, and a barrier layer stacked in sequence; And, A first functional layer disposed on a side of the barrier layer away from the channel layer; A first electrode, a second electrode, and a gate located between the first electrode and the second electrode, the gate being located on a side of the first functional layer away from the substrate, and the first electrode and the second electrode being located on a side of the barrier layer away from the substrate; Wherein, the material of the first functional layer includes: AlGaN; the first functional layer includes: a first sub - portion, along a first direction, the content of Al atoms in a portion of the first sub - portion away from the substrate is less than the content of Al atoms in a portion close to the substrate, and the first direction is perpendicular to the substrate.

2. The semiconductor device according to claim 1, wherein The first functional layer further includes: a second sub - portion, along the first direction, the content of Al atoms in a portion of the second sub - portion away from the substrate is greater than the content of Al atoms in a portion close to the substrate; Wherein, the change amount per unit thickness of the content of Al atoms in the second sub - portion is less than the change amount per unit thickness of the content of Al atoms in the first sub - portion.

3. The semiconductor device according to claim 1, characterized in that The first functional layer further includes: a third sub - portion, the third sub - portion being located on a side of the first sub - portion away from the substrate; Along the first direction, the content of Al atoms in the third sub - portion remains unchanged.

4. The semiconductor device according to claim 3, wherein The semiconductor device includes: the first sub - portion, the second sub - portion, and the third sub - portion, and the number of at least one of the first sub - portion, the second sub - portion, and the third sub - portion is multiple.

5. The semiconductor device according to claim 1, wherein The content range of Al atoms in a portion of the first sub - portion away from the substrate is 0% - 90%, and the content range of Al atoms in a portion close to the substrate is 10% - 99.9%.

6. The semiconductor device according to claim 2, wherein, The content range of Al atoms in a portion of the second sub - portion away from the substrate is 10% - 99.9%, and the content range of Al atoms in a portion close to the substrate is 0% - 99%.

7. The semiconductor device according to claim 1, wherein The material of the first functional layer further includes: at least one of Mg element, Be element, and Si element.

8. The semiconductor device according to claim 1, characterized in that, The thickness range of the first functional layer is 10nm - 500nm.

9. The semiconductor device according to claim 1, wherein Further comprising: A second functional layer disposed between the barrier layer and the first functional layer; The material of the second functional layer includes: at least one of doped or undoped GaN, doped or undoped AlGaN, doped or undoped InGaN, and doped or undoped InAlGaN.

10. The semiconductor device according to claim 9, wherein, The thickness range of the second functional layer is 1nm - 50nm.

11. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming a channel layer on one side of a substrate; Forming a barrier layer on a side of the channel layer away from the substrate; Forming a first functional layer on a side of the barrier layer away from the substrate; wherein, the material of the first functional layer includes: AlGaN; the first functional layer includes: a first sub - portion, and the content of Al atoms in a portion of the first sub - portion away from the substrate is less than the content of Al atoms in a portion close to the substrate; Form a first electrode, a second electrode, and a gate located between the first electrode and the second electrode, the gate being located on the side of the first functional layer away from the substrate, and the first electrode and the second electrode being located on the side of the channel layer away from the substrate, to obtain the semiconductor device.

12. The method for manufacturing a semiconductor device according to claim 11, wherein, Forming a first functional layer on the side of the barrier layer away from the substrate includes: In an atmosphere of an Al source, a Ga source, and an N source, during the process of forming the first functional layer, the concentration of the Al source gradually decreases; or, Under the condition that the concentrations of the Al source, the Ga source, and the N source remain unchanged, gradually decrease the temperature in the temperature range of 900 °C to 1400 °C to form the first functional layer.

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