Semiconductor structure and preparation method thereof
By adopting a structural design with a light-doped region and a heavily doped region in the depletion type MOSFET, and using polystrips and side wall shading for ion implantation, the cost problems brought about by the additional implantation region and photocosm in the prior art are solved, and low-cost and high-efficiency current control is achieved.
Patent Information
- Application Number
- CN202510517807.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2025-04-23
- Publication Date
- 2025-07-18
AI Technical Summary
The preparation process of existing depletion MOSFETs requires additional N-type injection zones and photocoats, which increases process and equipment costs, while the device size needs to be increased to ensure the current channel is closed, resulting in an increase in product costs.
Using a structural design with multiple light doped regions bordering the first and second heavily doped regions, ion implantation is carried out through polystrips and side wall shading to form a current channel between the drain region and the source region, without additional implantation steps and photomasks, and is compatible with existing MOS device processes.
The process and equipment costs are reduced, the unit cost of the product is maintained, and the current channel is shut down without increasing the device size, and the preparation method is compatible with the existing processes.
Smart Images
Figure CN120343946A_ABST
Abstract
Description
Technical Field
[0001] This application relates to the field of semiconductor technology, and particularly to a semiconductor structure and a method for manufacturing the same. Background Art
[0002] Power MOSFETs are most commonly used in switches. In applications such as startup circuits, surge protection, solid-state relays, and constant current sources, power MOSFETs need to operate as normally "on" switches, that is, when the gate voltage is zero, the power MOSFET is turned on and current flows through it, and when the gate voltage is negative, the power MOSFET is turned off and no current flows through it. Such power MOSFETs are generally referred to as depletion-mode MOSFETs.
[0003] The most common structure of a depletion-mode MOSFET is to implant an additional N-type implantation region on the surface of a P-well so that conduction can occur between the drain region and the source region without applying a gate voltage, and the current channel can be turned off by applying a negative voltage to the gate to invert the surface of the P-well.
[0004] The disadvantage of this structure is that the additional N-type implantation region requires an additional implantation step and an additional photomask to be fabricated, so the process cost and equipment cost are increased; moreover, the additional N-type implantation region also requires increasing the size of the MOS device (MOSFET) (mainly because the gate length is increased) to ensure that the current channel can be turned off, thus increasing the unit cost of the product to a certain extent. Summary of the Invention
[0005] The purpose of this application is to provide a semiconductor structure and a method for manufacturing the same, which do not require additional implantation steps or additional photomasks, and do not require an increase in size, and have a lower cost.
[0006] To achieve the above object, this application provides the following technical solutions:
[0007] This application provides a semiconductor structure, which includes:
[0008] A well region;
[0009] A first heavily doped region and a second heavily doped region, the first heavily doped region and the second heavily doped region are located in the well region and are separated from each other, and the conduction types of the first heavily doped region and the second heavily doped region are opposite to the conduction type of the well region;
[0010] A plurality of lightly doped regions are located in a well region between the first heavily doped region and the second heavily doped region. The upper surface of the lightly doped regions is flush with the upper surface of the well region. Along the direction from the first heavily doped region to the second heavily doped region, the plurality of lightly doped regions are arranged in continuous connection, and are adjacent to the first heavily doped region and the second heavily doped region. The conductivity type of the lightly doped regions is the same as that of the first heavily doped region and the second heavily doped region;
[0011] Polycrystalline strips, the number of the polycrystalline strips is multiple, and each polycrystalline strip is located above the interface of adjacent lightly doped regions.
[0012] In one embodiment, the plurality of polycrystalline strips are arranged separately from each other; the number of the lightly doped regions is greater than the number of the polycrystalline strips.
[0013] In one embodiment, any one of the polycrystalline strips simultaneously covers partial structures of two adjacent lightly doped regions.
[0014] In one embodiment, along the direction from the first heavily doped region to the second heavily doped region, the depth of the lightly doped region below the middle position of the polycrystalline strip is less than the depth of the lightly doped regions below the two side positions of the polycrystalline strip.
[0015] In one embodiment, the semiconductor structure further includes: sidewalls located on both sides of each polycrystalline strip.
[0016] In one embodiment, the polycrystalline strips and the sidewalls completely cover the lightly doped regions between the first heavily doped region and the second heavily doped region.
[0017] The present application also provides a preparation method of a semiconductor structure for preparing the semiconductor structure as described above. The preparation method includes:
[0018] Performing well ion implantation on a semiconductor substrate to form a well region;
[0019] Preparing and forming polycrystalline strips above the well region;
[0020] Using the polycrystalline strips as a mask, performing lightly doped ion implantation on the well region to form lightly doped regions in the well region. The number of the lightly doped regions is multiple, and they are arranged in continuous connection with each other. The conductivity type of the lightly doped regions is opposite to that of the well region;
[0021] Perform heavy doping ion implantation on the well region to form phase-separated first and second heavily doped regions in the well region. All the lightly doped regions are located between the first heavily doped region and the second heavily doped region, and the outermost lightly doped regions are respectively adjacent to the first heavily doped region and the second heavily doped region. The conductivity type of the lightly doped regions is the same as that of the first heavily doped region and the second heavily doped region.
[0022] In one embodiment, after performing light doping ion implantation on the well region, the preparation method further includes:
[0023] Form sidewalls on both sides of the polysilicon strip;
[0024] Using the polysilicon strip and the sidewalls as masks, perform heavy doping ion implantation on the well region.
[0025] In one embodiment, when performing light doping ion implantation on the well region, the well region is ion implanted at a preset tilt angle, and the tilt angle is the angle formed by the ion implantation direction and the plane direction of the semiconductor substrate.
[0026] In one embodiment, before performing well ion implantation on the semiconductor substrate, the preparation method further includes:
[0027] Form a plurality of isolation structures on the semiconductor substrate, an active region is formed between adjacent isolation structures, and the well region is formed in the active region.
[0028] Compared with the prior art, the technical solution of the present application has the following beneficial effects:
[0029] For the semiconductor structure and its preparation method of the present application, multiple lightly doped regions are connected to each other and are adjacent to the first heavily doped region and the second heavily doped region (one of the first heavily doped region and the second heavily doped region serves as the drain region and the other serves as the source region), thus simultaneously forming a current channel between the drain region and the source region (the lightly doped region is originally the connection region between the drain region, the source region and the channel, enabling a gradual change in the electric field intensity and weakening the peak value of the electric field intensity). Without an additional implantation region, there is no need for additional implantation steps and additional photomasks, so the process cost and equipment cost are reduced.
[0030] Moreover, the lightly doped region is an essential structure of the MOS device. Therefore, in essence, no new structure is added to the MOS device, and it is not necessary to increase the size of the MOS device to ensure that the current channel can be turned off. Therefore, the unit cost of the product remains at a relatively low level.
[0031] The preparation method can also be compatible with the existing process for preparing ordinary MOS devices, only requiring a slight adjustment of the photomask for preparing the polysilicon strip, reducing the preparation cost. Description of the Drawings
[0032] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those skilled in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.
[0033] Figure 1 It is a side cross-sectional view of a semiconductor structure provided by the first embodiment of the present application;
[0034] Figures 2 - 6 They are respectively side cross-sectional views of the semiconductor structures obtained in each step during the manufacturing method of a semiconductor structure provided by the second embodiment of the present application. Specific Embodiments
[0035] The following will clearly and completely describe the technical solutions in the embodiments of the present application. Obviously, the described embodiments are only some embodiments of the present application, rather than all embodiments. Based on the embodiments in the present application, all other embodiments obtained by those skilled in the art without creative efforts belong to the scope of protection of the present application. It should be noted that the description order of the following embodiments does not limit the preferred order of the embodiments of the present application. And in the following embodiments, the descriptions of each embodiment have their own emphases. For the parts not detailed in a certain embodiment, reference can be made to the relevant descriptions of other embodiments.
[0036] Figure 1 It is a side cross-sectional view of a semiconductor structure provided by the first embodiment of the present application. Please refer to Figure 1 As shown, the semiconductor structure of the present application may include:
[0037] Well region 1.
[0038] In Figure 1 In the shown embodiment, the conductivity type of well region 1 is P-type and can be represented as PW. Of course, in other embodiments, the conductivity type of well region 1 can also be N-type and can be represented as NW. For ease of description, the following other structures to be introduced will be described based on the P-type well region 1.
[0039] In this embodiment, well region 1 can be formed on a semiconductor substrate 10. In a specific embodiment, semiconductor substrate 10 can be a silicon substrate.
[0040] Please continue to refer to Figure 1 As shown, the semiconductor structure of the present application may further include:
[0041] A first heavily doped region 2 and a second heavily doped region 3, the first heavily doped region 2 and the second heavily doped region 3 are located within the well region 1 and are separated from each other, and the conduction types of the first heavily doped region 2 and the second heavily doped region 3 are opposite to the conduction type of the well region 1.
[0042] In Figure 1 In the illustrated embodiment, the conduction types of the first heavily doped region 2 and the second heavily doped region 3 are N-type and can be represented as N+.
[0043] In this embodiment, one of the first heavily doped region 2 and the second heavily doped region 3 serves as the drain region and the other serves as the source region. In Figure 1 In the illustrated embodiment, the first heavily doped region 2 serves as the drain region D and the second heavily doped region 3 serves as the source region S.
[0044] Please continue to refer to Figure 1 As shown, the semiconductor structure of the present application may further include:
[0045] A plurality of lightly doped regions 4 (abbreviated as LDD, Lightly Doped Drain), located within the well region 1 between the first heavily doped region 2 and the second heavily doped region 3, the upper surface of the lightly doped region 4 is flush with the upper surface of the well region 1, and along the direction from the first heavily doped region 2 to the second heavily doped region 3, the plurality of lightly doped regions 4 are continuously connected and arranged, and are contiguous with the first heavily doped region 2 and the second heavily doped region 3.
[0046] Specifically, continue to refer to Figure 1 , among the continuously connected and arranged plurality of lightly doped regions 4, the lightly doped regions 4 at both ends are respectively contiguous (in contact) with the first heavily doped region 2 and the second heavily doped region 3.
[0047] In this embodiment, the conduction type of the lightly doped region 4 is the same as the conduction types of the first heavily doped region 2 and the second heavily doped region 3.
[0048] In Figure 1In the illustrated embodiment, the conductivity type of the lightly doped region 4 is also N-type, and the number is four. Different from general existing MOS devices, not only is the number of the lightly doped regions 4 in this application relatively large, but all the lightly doped regions 4 in this application are continuously and adjacently arranged with each other (two lightly doped regions 4 in existing MOS devices do not contact each other), and the two outermost lightly doped regions 4 are respectively in contact with the first heavily doped region 2 and the second heavily doped region 3 (the drain region and the source region respectively), thus forming a current channel between the drain region and the source region. Without applying a voltage to the gate to be introduced later, the drain region and the source region can be made conductive, and applying a negative voltage to the gate to invert the lightly doped region 4 can turn off the current channel. In this way, the well region 1, the first heavily doped region 2, the second heavily doped region 3, the lightly doped region 4, and the gate to be introduced later form a depletion-type NMOS.
[0049] In the above embodiment, the semiconductor structure does not have an additional implantation region to form a current channel between the drain region and the source region, so there is no need for additional implantation steps and additional photomasks, thus reducing the process cost and equipment cost. Moreover, the lightly doped region 4 is originally the connection region between the drain region, the source region, and the channel, enabling a gradual change in the electric field intensity and weakening the peak value of the electric field intensity. It is a necessary structure for MOS devices. Therefore, in essence, no new structure is added to the MOS device, and the size of the MOS device does not need to be increased to ensure that the current channel can be turned off. Therefore, the unit cost of the product remains at a relatively low level.
[0050] In addition, the light and heavy of the lightly doped region 4 and the heavily doped region are relative to each other. Specifically, the ion concentration of the doping can be adaptively set according to the specific parameter requirements of different products, which is well known to those skilled in the art.
[0051] Please continue to refer to Figure 1 as shown, the semiconductor structure of this application may further include:
[0052] Polycrystalline strips 5, the number of the polycrystalline strips 5 is multiple, each of the polycrystalline strips 5 is located above the interface of adjacent lightly doped regions 4, and all the polycrystalline strips 5 together serve as the gate (GATE) of a MOS device, and together with the well region 1, the first heavily doped region 2, the second heavily doped region 3, and the lightly doped region 4, form a MOS device.
[0053] In this embodiment, the number of the lightly doped regions 4 is greater than the number of the polycrystalline strips 5. For example, if the number of the lightly doped regions 4 is N, then the number of the polycrystalline strips 5 is N - 1.
[0054] In Figure 1In the illustrated embodiment, the number of polycrystalline strips 5 is three, and the multiple polycrystalline strips 5 are arranged separately from each other. The three polycrystalline strips 5 together serve as the gate of a MOS device, and together with the well region 1, the first heavily doped region 2, the second heavily doped region 3, and the lightly doped region 4, they form a MOS device. In this way, during the ion implantation for preparing the lightly doped region 4, the polycrystalline strips 5 can be used as a mask, so that the lightly doped region 4 naturally gradually extends from the lower sides of the two sides of the polycrystalline strip 5 to the lower side of the middle position of the polycrystalline strip 5. Moreover, the multiple polycrystalline strips 5 together serve as the gate of a MOS device, and the size of each polycrystalline strip 5 is relatively small. The two lightly doped regions 4 formed by gradually extending from the two side positions to the middle position below each polycrystalline strip 5 are relatively easy to contact (if the size of the polycrystalline strip 5 is large, it will be difficult for the two lightly doped regions 4 to contact). The lightly doped region 4 formed in this way will also cause each polycrystalline strip 5 to simultaneously cover a partial structure of the adjacent two lightly doped regions 4. Specifically, it covers the partial structure of the lightly doped region 4 extending from the two side positions of the polycrystalline strip 5 into the lower position of the polycrystalline strip 5 (there is also a partial structure of the lightly doped region 4 between the adjacent two polycrystalline strips 5).
[0055] Moreover, along the direction from the first heavily doped region 2 to the second heavily doped region 3, the depth of the lightly doped region 4 below the middle position of the polycrystalline strip 5 is less than the depth of the lightly doped region 4 below the two side positions of the polycrystalline strip 5. Because the lightly doped region 4 naturally gradually extends from the lower sides of the two side positions of the polycrystalline strip 5 to the lower side of the middle position of the polycrystalline strip 5, the lightly doped region 4 below the two side positions of the polycrystalline strip 5 is formed first. As the implantation time progresses, its depth gradually increases. The lightly doped region 4 below the middle position of the polycrystalline strip 5 is formed later. As long as the two lightly doped regions 4 extending from the two sides to the middle of the polycrystalline strip 5 are in contact, a current channel between the drain region and the source region can be formed, so its depth is relatively small. Also because the depth of the lightly doped region 4 below the middle position of the polycrystalline strip 5 is less than the depth of the lightly doped region 4 below the two side positions, when a negative voltage is applied to the polycrystalline strip 5 (serving as the gate), the lightly doped region 4 in the middle position is more likely to be fully inverted to turn off the current channel, which ensures that the current channel can be turned off in time when it needs to be turned off without increasing the size of the device, so the unit cost of the product remains at a relatively low level.
[0056] Continue to refer to Figure 1 , in one of the embodiments, among the multiple continuously connected and arranged lightly doped regions 4, the structure of the lightly doped region 4 in the middle region can be different from the structure of the lightly doped regions 4 at both ends. That is, the structure of the lightly doped region 4 in the middle region can be U-shaped, while the structure of the lightly doped regions 4 at both ends can be semi-U-shaped.
[0057] In one embodiment, along the direction from the first heavily doped region 2 to the second heavily doped region 3, the width of the lightly doped region 4 in the middle region can be twice the width of the lightly doped regions 4 at both ends, so that the lightly doped region 4 in the middle region can be located below two adjacent polysilicon strips 5 at the same time.
[0058] Please continue to refer to Figure 1 As shown, the semiconductor structure of the present application may further include:
[0059] Sidewalls 6 located on both sides of each of the polysilicon strips 5.
[0060] The sidewalls 6 can shield (protect) the lightly doped region 4. In Figure 1 the shown embodiment, the polysilicon strips 5 and the sidewalls 6 completely cover the lightly doped region 4 between the first heavily doped region 2 and the second heavily doped region 3, that is, all the polysilicon strips 5 and the sidewalls 6 can completely cover the lightly doped region 4; in this way, the polysilicon strips 5 and the sidewalls 6 can be used as a shield during the ion implantation in the preparation of the first heavily doped region 2 and the second heavily doped region 3, and a special photomask does not have to be used, reducing the cost.
[0061] The second embodiment of the present application provides a method for manufacturing a semiconductor structure for manufacturing the semiconductor structure as described above. The manufacturing method may include:
[0062] Performing well ion implantation on the semiconductor substrate 10 to form a well region 1.
[0063] To enable readers to more conveniently and quickly understand the manufacturing method provided by the present application, the following will combine Figures 2 - 6 to illustrate the manufacturing method of the present application, Figures 2 - 6 which are respectively the side cross-sectional views of the semiconductor structures obtained in each step during the process of a method for manufacturing a semiconductor structure provided by the second embodiment of the present application.
[0064] Please refer to Figure 2 As shown, before performing well ion implantation on the semiconductor substrate 10, a plurality of isolation structures 11 may be first formed on the semiconductor substrate 10, an active region 12 is formed between adjacent isolation structures 11, and the well region 1 is formed within the active region 12.
[0065] In Figure 2 the shown specific embodiment, the semiconductor substrate 10 may be a silicon substrate, the isolation structure 11 may be a shallow trench isolation structure (STI), or may be a local oxidation of silicon isolation structure (LOCOS), and an active region 12 is formed between adjacent isolation structures 11.
[0066] Please refer to Figure 3As shown, after the active region 12 is formed, well ion implantation is performed on the semiconductor substrate 10 to form the well region 1. That is, the well ion implantation is performed within the active region 12, and the well region 1 is formed within the active region 12.
[0067] In Figure 3 In the specific embodiment shown, the conductive type of the ions for the well ion implantation is P-type, which can be denoted as PW. As for the specific ions implanted, energy, concentration, etc., they can be selected according to actual needs, and those skilled in the art can easily understand this.
[0068] Please refer to Figure 4 As shown, after the well region 1 is formed, the manufacturing method may further include:
[0069] Form a polycrystalline strip 5 above the well region 1.
[0070] In this embodiment, for any semiconductor structure, multiple polycrystalline strips 5 are simultaneously formed. These multiple polycrystalline strips 5 will ultimately serve as the gate of the semiconductor structure together. Therefore, relatively speaking, the size of each polycrystalline strip 5 formed in this application is relatively smaller than the size of the polycrystalline strip 5 serving as the gate in the existing solution. In this embodiment, the number of polycrystalline strips 5 is two. In the Figure 1 specific embodiment shown above, the number of polycrystalline strips 5 is three. The specific number of polycrystalline strips 5 can be set according to actual needs.
[0071] In one embodiment, the forming of the polycrystalline strip above the well region may include: forming a polycrystalline material layer that covers the surface of the well region; forming a photoresist layer that covers the polycrystalline material layer; forming a photoresist pattern based on a preset photomask. The preset photomask includes multiple photomask patterns, the number of the photomask patterns is equal to the number of polycrystalline strips to be formed above the well region, and the positions of the photomask patterns match the positions of the respective polycrystalline strips to be formed above the well region; using the photoresist pattern as a mask, performing an etching process on the polycrystalline material layer to form multiple polycrystalline strips located above the well region.
[0072] Please refer to Figure 5 As shown, after the polycrystalline strip 5 is formed, the manufacturing method may further include:
[0073] Using the polycrystalline strip 5 as a shield, performing a lightly doped ion implantation on the well region 1 to form lightly doped regions 4 within the well region 1. The number of the lightly doped regions 4 is multiple, and they are continuously connected and arranged with each other. The conductive type of the lightly doped regions 4 is opposite to the conductive type of the well region 1.
[0074] In Figure 5In the specific embodiment shown, the conductivity type of the ions in the lightly doped ion implantation is N-type. Due to the shielding of the polycrystalline strip 5, the lightly doped regions 4 are first formed in the well regions 1 on both sides of the polycrystalline strip 5 and then slowly extend to the well regions 1 under the polycrystalline strip 5. Since the size of the polycrystalline strip 5 in this application is relatively small, the two lightly doped regions 4 gradually extending from both sides of each polycrystalline strip 5 to the middle are easily in contact with each other under the middle position of each polycrystalline strip 5, and the lightly doped regions 4 formed between adjacent polycrystalline strips 5 are naturally in contact with each other.
[0075] In order to ensure that the lightly doped regions 4 are in contact with each other, in one embodiment, when performing the lightly doped ion implantation on the well region 1, the well region 1 is ion-implanted at a preset tilt angle A, where the tilt angle A is the angle formed by the ion implantation direction and the plane direction of the semiconductor substrate 10. Figure 5 In the specific embodiment shown, the tilt angle A is 45 degrees instead of 90 degrees (the aforementioned well ion implantation is 90 degrees), which can ensure that the ions are implanted under the polycrystalline strip 5, and further ensure that the two lightly doped regions 4 gradually extending from both sides of each polycrystalline strip 5 to the middle are in contact with each other under the middle position of the polycrystalline strip 5.
[0076] Please refer to Figure 6 As shown, after forming the lightly doped regions 4, the manufacturing method may further include:
[0077] Performing a heavily doped ion implantation on the well region 1 to form a first heavily doped region 2 and a second heavily doped region 3 that are phase-separated in the well region 1. All the lightly doped regions 4 are located between the first heavily doped region 2 and the second heavily doped region 3, and the outermost lightly doped regions 4 are respectively adjacent to the first heavily doped region 2 and the second heavily doped region 3. The conductivity type of the lightly doped regions 4 is the same as that of the first heavily doped region 2 and the second heavily doped region 3.
[0078] In Figure 6 In the specific embodiment shown, the conductivity type of the ions in the heavily doped ion implantation is also N-type. The formed first heavily doped region 2 and second heavily doped region 3 are respectively adjacent to the outermost lightly doped regions 4. The first heavily doped region 2 and the second heavily doped region 3 serve as the drain region and the source region of the MOS device respectively. All the lightly doped regions 4 form a current channel between the drain region and the source region. The drain region and the source region can be turned on without applying a voltage on the gate, and the current channel can be turned off by applying a negative voltage on the gate to invert the lightly doped regions 4. Thus, a depletion-type NMOS is formed.
[0079] In one embodiment, after performing the lightly doped ion implantation on the well region 1, the manufacturing method further includes:
[0080] Forming sidewalls 6 on both sides of the polycrystalline strip 5;
[0081] Using the polycrystalline strip 5 and the sidewall 6 as masks, heavy doping ion implantation is performed on the well region 1.
[0082] The sidewall 6 can mask the underlying lightly doped region 4. Moreover, it can also be used together with the polycrystalline strip 5 as a mask for heavy doping ion implantation. In this way, there is no need to use a dedicated photomask (when there is no sidewall 6 in the foregoing embodiment, a dedicated photomask is required for heavy doping ion implantation), which reduces the cost.
[0083] As can be seen from the above, the preparation method of the present application can be fully compatible with the existing process for manufacturing ordinary MOS devices. Only a slight adjustment to the photomask for preparing the polycrystalline strip 5 is needed to form multiple polycrystalline strips 5, so that the underlying lightly doped regions 4 below the multiple polycrystalline strips 5 are in contact. Furthermore, by using the multiple interconnected lightly doped regions 4 as the current channel between the drain region and the source region at the same time, there is no need for a separate implantation step and photomask to form a separate implantation region as the current channel, which reduces the manufacturing cost.
[0084] Compared with the prior art, the technical solution of the present application has the following beneficial effects:
[0085] In the semiconductor structure and its preparation method of the present application, multiple lightly doped regions are interconnected and border on the first heavily doped region and the second heavily doped region (one of the first heavily doped region and the second heavily doped region serves as the drain region and the other serves as the source region), thus simultaneously forming the current channel between the drain region and the source region (the lightly doped region is originally the connection region between the drain region, the source region and the channel, enabling a gradual change in the electric field strength and weakening the peak value of the electric field strength). There is no need for an additional implantation region, and thus no additional implantation step and additional photomask are required, so the process cost and equipment cost are reduced.
[0086] Moreover, the lightly doped region is an essential structure of the MOS device. Therefore, in essence, no new structure is added to the MOS device, and it is not necessary to increase the size of the MOS device to ensure that the current channel can be turned off. Therefore, the unit cost of the product remains at a relatively low level.
[0087] The preparation method can also be compatible with the existing process for manufacturing ordinary MOS devices. Only a slight adjustment to the photomask for preparing the polycrystalline strip is needed, which reduces the manufacturing cost.
[0088] As described above, it is only the specific implementation manner of the present application, but the protection scope of the present application is not limited thereto. Any person skilled in the art within the technical scope disclosed by the present application can easily think of changes or substitutions, which should all be covered within the protection scope of the present application. Therefore, the protection scope of the present application shall be subject to the protection scope of the claims. In addition, specific examples are used in the specification to elaborate on the principle and implementation manner of the present application. The description of the above embodiments is only used to help understand the method and its core idea of the present application, and the content of this specification should not be construed as a limitation to the present application.
Claims
1. A semiconductor structure, characterized in that, The semiconductor structure includes: A well region; A first heavily doped region and a second heavily doped region, the first heavily doped region and the second heavily doped region are located within the well region and are separated from each other, and the conduction types of the first heavily doped region and the second heavily doped region are opposite to the conduction type of the well region; Multiple lightly doped regions, located within the well region between the first heavily doped region and the second heavily doped region, the upper surfaces of the lightly doped regions are flush with the upper surface of the well region, along the direction from the first heavily doped region to the second heavily doped region, the multiple lightly doped regions are continuously connected and arranged, and are adjacent to the first heavily doped region and the second heavily doped region, and the conduction type of the lightly doped region is the same as the conduction types of the first heavily doped region and the second heavily doped region; Polycrystalline strips, the number of the polycrystalline strips is multiple, and each polycrystalline strip is located above the interface of adjacent lightly doped regions.
2. The semiconductor structure according to claim 1, wherein The multiple polycrystalline strips are separated from each other; the number of the lightly doped regions is greater than the number of the polycrystalline strips.
3. The semiconductor structure according to claim 1, wherein Each polycrystalline strip simultaneously covers partial structures of adjacent two lightly doped regions.
4. The semiconductor structure according to claim 1, wherein Along the direction from the first heavily doped region to the second heavily doped region, the depth of the lightly doped region below the middle position of the polycrystalline strip is less than the depth of the lightly doped regions below the two side positions of the polycrystalline strip.
5. The semiconductor structure according to claim 1, wherein The semiconductor structure further includes: sidewalls located on both sides of each polycrystalline strip.
6. The semiconductor structure according to claim 5, wherein The polycrystalline strips and the sidewalls completely cover the lightly doped regions between the first heavily doped region and the second heavily doped region.
7. A method for manufacturing a semiconductor structure, for manufacturing the semiconductor structure as claimed in claim 1, characterized in that, The preparation method includes: Performing well ion implantation on a semiconductor substrate to form a well region; Preparing and forming polycrystalline strips above the well region; Using the polycrystalline strips as a mask, performing lightly doped ion implantation on the well region to form lightly doped regions within the well region, the number of the lightly doped regions is multiple, and they are continuously connected and arranged with each other, and the conduction type of the lightly doped regions is opposite to the conduction type of the well region; Performing heavily doped ion implantation on the well region to form a separated first heavily doped region and a second heavily doped region within the well region, all the lightly doped regions are located between the first heavily doped region and the second heavily doped region, and the two outermost lightly doped regions are respectively adjacent to the first heavily doped region and the second heavily doped region, and the conduction type of the lightly doped regions is the same as the conduction types of the first heavily doped region and the second heavily doped region.
8. The preparation method according to claim 7, characterized in that, After performing lightly doped ion implantation on the well region, the preparation method further includes: Forming sidewalls on both sides of the polycrystalline strips; Using the polycrystalline strips and the sidewalls as a mask, performing heavily doped ion implantation on the well region.
9. The preparation method according to claim 7, wherein, Performing lightly doped ion implantation on the well region is to perform ion implantation on the well region at a preset tilt angle, and the tilt angle is the included angle formed by the direction of ion implantation and the plane direction of the semiconductor substrate.
10. The preparation method according to claim 7, characterized in that, Before performing well ion implantation on the semiconductor substrate, the preparation method further includes: Forming multiple isolation structures on the semiconductor substrate, an active region is formed between adjacent isolation structures, and the well region is formed within the active region.