Formation method of semiconductor structure

Abstract

A forming method of a semiconductor structure comprises the steps that a substrate is provided, a first sacrificial layer and a channel lamination layer located on the first sacrificial layer are formed on the substrate, the channel lamination layer comprises a plurality of channel layers and second sacrificial layers located between the channel layers, and a gate structure stretching across the channel lamination layer is formed on the substrate; removing the channel lamination layer and the first sacrificial layer on the two sides of the gate structure to form a groove exposing the top of the substrate; after the groove is formed, transversely removing a part of width of the second sacrificial layer, and forming an inner groove communicated with the groove between the channel layers; forming a protection layer which at least covers part of the side wall of the first sacrificial layer and exposes the end part of the channel layer at the bottom of the groove; forming an inner side wall in the inner groove; after the inner side wall is formed, the protection layer and the first sacrificial layer are removed, and a through groove communicated with the groove is formed; forming a bottom isolation layer exposing the end part of the channel layer in the through groove; and forming a source-drain doping layer in the groove. According to the embodiment of the invention, the difficulty of forming the through groove is reduced, and the quality of the bottom isolation layer is improved.

Description

Technical Field

[0001] Embodiments of the present invention relate to the field of semiconductor manufacturing, and in particular, to a method for forming a semiconductor structure. Background Art

[0002] With the rapid development of the semiconductor integrated circuit (IC) industry, semiconductor technology has continuously advanced towards smaller process nodes driven by Moore's law, enabling integrated circuits to develop in the direction of smaller volume, higher circuit precision, and higher circuit complexity.

[0003] In order to better meet the requirements of device size scaling, semiconductor processes have gradually started to transition from planar transistors to three-dimensional transistors with higher efficiency, such as gate-all-around (GAA) transistors. In a gate-all-around transistor, the gate surrounds the region where the channel is located from all sides. Compared with planar transistors, the gate of a gate-all-around transistor has a stronger control ability over the channel and can better suppress the short-channel effect.

[0004] However, the performance of current semiconductor structures still needs to be improved. Summary of the Invention

[0005] The problem solved by the embodiments of the present invention is to provide a method for forming a semiconductor structure to improve the performance of the semiconductor structure.

[0006] To solve the above problem, embodiments of the present invention further provide a method for forming a semiconductor structure, including: providing a substrate, on which a first sacrificial layer is formed, and a channel stack located on the first sacrificial layer, the channel stack including a plurality of channel layers stacked in sequence along the longitudinal direction, and a second sacrificial layer located between adjacent channel layers; forming a gate structure across the channel stack on the substrate, the gate structure covering a part of the top and part of the sidewalls of the channel stack; removing the channel stack and the first sacrificial layer on both sides of the gate structure to form a groove exposing the top of the substrate; after forming the groove, transversely removing a part of the width of the second sacrificial layer in a direction perpendicular to the sidewall of the gate structure to form an inner trench communicating with the groove between the channel layers; forming a protective layer covering at least a part of the sidewall of the first sacrificial layer at the bottom of the groove, the protective layer exposing the ends of the channel layers; forming an inner sidewall covering the sidewall of the second sacrificial layer in the inner trench; after forming the inner sidewall, removing the protective layer and the first sacrificial layer to form a through groove communicating with the groove; forming a bottom isolation layer exposing the ends of the channel layers in the through groove; forming source-drain doping layers connected to both ends of the channel layers in the groove.

[0007] Compared with the prior art, the technical solution of the embodiment of the present invention has the following advantages:

[0008] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a protective layer covering at least a portion of the side walls of the first sacrificial layer is formed at the bottom of the groove, the protective layer exposes the end of the channel layer, and a portion of the width of the second sacrificial layer is laterally removed. After an inner groove intersecting the groove is formed between the channel layers, an inner sidewall covering the sidewall of the second sacrificial layer is formed in the inner groove. After the inner sidewall is formed, the protective layer and the first sacrificial layer are removed. Since the inner sidewall covers the sidewall of the second sacrificial layer, it protects the sidewall of the second sacrificial layer, so that in the process of removing the protective layer and the first sacrificial layer, the probability of the second sacrificial layer being damaged is reduced; moreover, the protective layer at least covers part of the sidewall of the first sacrificial layer and exposes the end of the channel layer, so that the inner sidewall does not completely cover the sidewall of the first sacrificial layer, so that in the process of removing the first sacrificial layer, it is convenient to remove the first sacrificial layer through the exposed sidewall of the first sacrificial layer, thereby reducing the difficulty of forming the through groove and improving the quality of the through groove, and correspondingly reducing the difficulty of forming the bottom isolation layer and improving the quality of the bottom isolation layer, which is beneficial to improving the off-state leakage current and improving the performance of the semiconductor structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0009] Figures 1 to 2 It is a schematic diagram of the structure of a semiconductor structure;

[0010] Figure 3 It is a schematic diagram of the structure of another semiconductor structure;

[0011] Figures 4 to 15 It is a structural schematic diagram corresponding to each step in another method for forming a semiconductor structure;

[0012] Figures 16 to 27 It is a schematic structural diagram corresponding to each step in an embodiment of a method for forming a semiconductor structure of the present invention. DETAILED DESCRIPTION

[0013] At present, the performance of semiconductor structures still needs to be improved. Now, combining a semiconductor structure, we analyze the reasons why the performance of semiconductor structures needs to be improved.

[0014] Figures 1 to 2 It is a structural diagram of a semiconductor structure. Figure 1 is a cross-sectional view at the gate structure position and along the extending direction of the gate structure, Figure 2 It is a cross-sectional view at the position of the channel protrusion structure and along the extending direction of the channel protrusion structure.

[0015] Reference Figures 1 to 2 A semiconductor structure includes: a substrate 10; a channel raised structure 11 suspended on the substrate 10. The channel raised structure 11 longitudinally includes a plurality of spaced channel layers 12; a gate structure 13 spanning across the channel raised structure 11 and covering a part of the top and part of the sidewalls of the channel raised structure 11. The gate structure 13 also surrounds and covers the channel layers 12; inner sidewalls 14 located at the ends of the gate structure 13 between adjacent channel layers 12, and at the ends of the gate structure 13 between adjacent channel layers 12 and the substrate 10; source-drain doping layers 15 located on the substrate 10 on both sides of the gate structure 13 and connected to both ends of the channel layers 12.

[0016] It has been found through research that as the semiconductor process nodes continue to decrease following Moore's Law, when the semiconductor process transitions from a Fin Field-Effect Transistor (FinFET) to a gate-all-around transistor with a smaller size, compared with the FinFET, the height dimension of each channel of the gate-all-around transistor is smaller. Also, since the bottommost channel is connected to the substrate 10 (as shown by the circled area A in Figure 1 ), and due to the limitation of process precision, the off-state leakage current of the bulk region in the substrate 10 under the channel raised structure 11 increases, that is, the "fat-fin effect", which affects the performance of the semiconductor structure.

[0017] Therefore, in order to improve the above problems, another semiconductor structure is proposed. Figure 3 is a schematic structural diagram of another semiconductor structure.

[0018] Reference Figure 3 A semiconductor structure includes: a substrate 10'; a thermal oxidation bottom isolation layer 16' located on the substrate 10'. A channel raised structure 11' is suspended on the substrate 10' and the thermal oxidation bottom isolation layer 16'. The channel raised structure 11' longitudinally includes a plurality of spaced channel layers 12'; a gate structure 13' spanning across the channel raised structure 11' and covering a part of the top and part of the sidewalls of the channel raised structure 11'. The gate structure 13' also surrounds and covers the channel layers 12'; inner sidewalls 14' located at the ends of the gate structure 13' between adjacent channel layers 12', and at the ends of the gate structure 13' between adjacent channel layers 12' and the thermal oxidation bottom isolation layer 16'; source-drain doping layers 15' located on the thermal oxidation bottom isolation layer 16' on both sides of the gate structure 13' and connected to both ends of the channel layers 12'.

[0019] Since the thermal oxidation bottom isolation layer 16′ is usually formed by a thermal oxidation process, and the process time of the thermal oxidation process is usually also closely related to the channel width, the thermal oxidation process is often difficult to control. In addition, the high temperature during the thermal oxidation process also easily causes atoms in the channel layer 12′ and the sacrificial layer (not shown in the figure) adjacent to the channel layer 12′ to diffuse into adjacent film layers (such as the sacrificial layer, the channel layer 12′, etc.), damaging the interface between adjacent film layers. Thus, in the step of removing the sacrificial layer to form the gate structure 13′, the probability of damage to the channel layer 12′ is increased, which in turn easily affects the performance of the semiconductor structure.

[0020] For this reason, another method for forming a conductor structure is proposed. Figures 4 to 15 It is a schematic structural diagram corresponding to each step in another method for forming a semiconductor structure.

[0021] Refer to Figures 4 to 5 , a substrate 20 is provided, a first sacrificial layer 21 is formed on the substrate 20, and a channel stack 22 is located on the first sacrificial layer 21. The channel stack 22 includes a plurality of channel layers 23 stacked in sequence along the longitudinal direction, and a second sacrificial layer 24 is located between adjacent channel layers 23. A gate structure 25 is formed on the substrate 20 across the channel stack 22, and the gate structure 25 covers a part of the top and part of the side walls of the channel stack 22.

[0022] Refer to Figure 6 , remove the channel stack 22 with a partial thickness on both sides of the gate structure 25 to form a groove 31, and the groove 31 exposes the top of the channel layer 23 closest to the substrate 20.

[0023] Refer to Figure 7 , after forming the groove 31, along the direction perpendicular to the side wall of the gate structure 25, laterally remove a part of the width of the second sacrificial layer 24 to form an inner groove 32 communicating with the groove 31 between the channel layers 23.

[0024] Refer to Figure 8 , form an inner sidewall 26 covering the side wall of the second sacrificial layer 24 in the inner groove 32.

[0025] Refer to Figures 9 to 10 , after forming the inner sidewall 26, remove the first sacrificial layer 21 through the groove 31 to form a through groove 33 communicating with the groove 31.

[0026] Refer to Figures 11 to 12 , form a bottom isolation layer 27 exposing the end of the channel layer 23 in the through groove 33.

[0027] Refer to Figures 13 to 14, a source-drain doping layer 28 connected to both ends of the channel layer 23 is formed in the groove 31.

[0028] In the above method, first, the channel stack 22 with a partial thickness on both sides of the gate structure 25 is removed to form a groove 31, then a part of the second sacrificial layer 24 with a partial width is removed laterally, an inner groove 32 communicating with the groove 31 is formed between the channel layers 23, and an inner sidewall 26 is formed in the inner groove 32; generally, the thickness of the channel layer 23 is relatively small, so that in the step of forming the groove 31, the process window with the top of the channel layer 23 closest to the substrate 20 (i.e., the top of the bottommost channel layer 23) as the stop position is small and the process difficulty is high. It is easy to expose the top of the first sacrificial layer 21, so that in the process of laterally removing a part of the second sacrificial layer 24 with a partial width, it is also easy to laterally remove a part of the first sacrificial layer 21 with a partial width. Correspondingly, it is easy to make the inner sidewall 26 also cover the entire sidewall of the first sacrificial layer 21, so that in the step of forming the through groove 33, it is difficult to remove the first sacrificial layer 21.

[0029] To solve the above technical problems, an embodiment of the present invention provides a method for forming a semiconductor structure, including: providing a substrate, on which a first sacrificial layer and a channel stack located on the first sacrificial layer are formed, the channel stack includes a plurality of channel layers stacked in sequence longitudinally, and a second sacrificial layer located between adjacent channel layers, a gate structure spanning the channel stack is formed on the substrate, and the gate structure covers a part of the top and a part of the sidewall of the channel stack; removing the channel stack and the first sacrificial layer on both sides of the gate structure to form a groove exposing the top of the substrate; after forming the groove, laterally removing a part of the second sacrificial layer with a partial width in a direction perpendicular to the sidewall of the gate structure to form an inner groove communicating with the groove between the channel layers; forming a protective layer covering at least a part of the sidewall of the first sacrificial layer at the bottom of the groove, the protective layer exposing the ends of the channel layers; forming an inner sidewall covering the sidewall of the second sacrificial layer in the inner groove; after forming the inner sidewall, removing the protective layer and the first sacrificial layer to form a through groove communicating with the groove; forming a bottom isolation layer exposing the ends of the channel layers in the through groove; forming a source-drain doping layer connected to both ends of the channel layer in the groove.

[0030] In the method for forming a semiconductor structure provided by an embodiment of the present invention, a protective layer is formed at the bottom of the groove to cover at least a part of the sidewalls of the first sacrificial layer. The protective layer exposes the ends of the channel layers. A part of the second sacrificial layer with a certain width is removed laterally. After an inner groove communicating with the groove is formed between the channel layers, an inner sidewall covering the sidewalls of the second sacrificial layer is formed in the inner groove. After the inner sidewall is formed, the protective layer and the first sacrificial layer are removed. Since the inner sidewall covers the sidewalls of the second sacrificial layer, it plays a protective role for the sidewalls of the second sacrificial layer, reducing the probability of damage to the second sacrificial layer during the removal of the protective layer and the first sacrificial layer. Moreover, the protective layer covers at least a part of the sidewalls of the first sacrificial layer and exposes the ends of the channel layers, so that the inner sidewall does not completely cover the sidewalls of the first sacrificial layer. During the removal of the first sacrificial layer, it is convenient to remove the first sacrificial layer through the sidewalls exposed by the first sacrificial layer, thereby reducing the difficulty of forming the through groove, improving the quality of the through groove, correspondingly reducing the difficulty of forming the bottom isolation layer, improving the quality of the bottom isolation layer, and further facilitating the improvement of the off-state leakage current and enhancing the performance of the semiconductor structure.

[0031] In order to make the above objects, features, and advantages of the embodiments of the present invention more obvious and understandable, the following detailed description of the specific embodiments of the present invention will be given in conjunction with the accompanying drawings.

[0032] Figures 15 to 27 It is a schematic structural diagram corresponding to each step in an embodiment of the method for forming a semiconductor structure of the present invention.

[0033] Reference Figure 15 , a substrate 100 is provided. A first sacrificial layer 110 is formed on the substrate 100, and a channel stack 120 is formed on the first sacrificial layer 110. The channel stack 120 includes a plurality of channel layers 121 stacked in sequence longitudinally, and a second sacrificial layer 122 located between adjacent channel layers 121. A gate structure 130 spanning the channel stack 120 is formed on the substrate 100, and the gate structure 130 covers a part of the top and part of the sidewalls of the channel stack 120.

[0034] The substrate 100 is used to provide a process platform for subsequent process steps.

[0035] In this embodiment, an example of forming a gate-all-around (GAA) transistor is used for illustration. In other embodiments, the forming method can also be used to form a fork-sheet transistor or a complementary field-effect transistor (CFET).

[0036] In this embodiment, the substrate 100 includes a substrate (not labeled), and the substrate is a silicon substrate. In other embodiments, the material of the substrate may also be other materials such as germanium, silicon germanide, silicon carbide, gallium arsenide, or indium gallium arsenide, and the substrate may also be other types of substrates such as silicon-on-insulator substrate or germanium-on-insulator substrate.

[0037] The first sacrificial layer 110 is used to occupy a spatial position for the subsequent formation of the bottom isolation layer. Moreover, by forming the first sacrificial layer 110 to occupy the spatial position, the method of forming the bottom isolation layer by thermal oxidation process is avoided, thereby reducing the probability of atoms in the channel layer 121 and the second sacrificial layer 122 diffusing into adjacent film layers (such as the second sacrificial layer 122, the channel layer 121, etc.) due to high temperature, and correspondingly reducing the probability of damaging the interface between adjacent film layers. Furthermore, in the subsequent step of removing the second sacrificial layer 122, the probability of damage to the channel layer 121 and the substrate 100 is reduced.

[0038] In this embodiment, the material of the first sacrificial layer 110 includes one or more of silicon germanide (SiGe), germanium (Ge), silicon carbide (SiC), cobalt silicide (CoSi), nickel silicide (NiSi), gallium arsenide (GaAs), indium arsenide (InAs), indium gallium arsenide (InGaAs), and indium phosphide (InP). In other embodiments, the first sacrificial layer may also be selected from other III-V semiconductor materials having an etching selectivity between the corresponding material of the substrate and the corresponding material of the channel layer.

[0039] As an example, the material of the first sacrificial layer 110 is silicon germanide.

[0040] In the subsequent process of removing the first sacrificial layer 110, the etching selectivity between silicon germanide and silicon is relatively high. Therefore, by setting the material of the first sacrificial layer 110 as silicon germanide and the material of the substrate as silicon, the influence of the first sacrificial layer 110 removal process on the substrate can be effectively reduced, which is beneficial to improving the quality of the substrate.

[0041] The channel stack 120 provides a process basis for the subsequent formation of the channel layer 121 with a suspended space.

[0042] The channel layer 121 is used to form the conductive channel of the MOS transistor, and the second sacrificial layer 122 is used to support the channel layer 121, thereby providing a process basis for the subsequent realization of the suspended space setting of the channel layer 121. The second sacrificial layer 122 is also used to occupy a spatial position for the subsequent formation of the device gate structure.

[0043] Here, the longitudinal direction refers to the normal direction of the top surface of the substrate 100.

[0044] In this embodiment, it is illustrated by taking the number of the channel layers 121 as three as an example. In other embodiments, the number of the channel layers may also be two, four, etc.

[0045] In this embodiment, the materials of the first sacrificial layer 110 and the second sacrificial layer 122 are the same.

[0046] The same materials of the first sacrificial layer 110 and the second sacrificial layer 122 are beneficial to combining the subsequent process of removing the first sacrificial layer 110 with the existing process, and thus are beneficial to improving process compatibility, reducing process risks and costs.

[0047] Correspondingly, in this embodiment, the material of the second sacrificial layer 122 may also include one or more of silicon germanide, germanium, silicon carbide, cobalt silicide, nickel silicide, gallium arsenide, indium arsenide, indium gallium arsenide, and indium phosphide.

[0048] As an example, the material of the second sacrificial layer 122 is also silicon germanide.

[0049] Specifically, the germanium content concentration of the first sacrificial layer 110 is greater than that of the second sacrificial layer 122.

[0050] The greater germanium content concentration of the first sacrificial layer 110 than that of the second sacrificial layer 122 is beneficial to increasing the etching selectivity between the material corresponding to the first sacrificial layer 110 and the materials corresponding to the substrate and the channel layer 121, and thus is beneficial to further combining with the existing process.

[0051] In other embodiments, the materials of the first sacrificial layer and the second sacrificial layer may also be different.

[0052] In this embodiment, the material of the channel layer 121 may be one or more of silicon, germanium, silicon germanide, and III-V group semiconductor materials, and there is an etching selectivity between the material corresponding to the channel layer 121 and the material corresponding to the first sacrificial layer 110.

[0053] The etching selectivity between the material corresponding to the channel layer 121 and the material corresponding to the first sacrificial layer 110 is beneficial to reducing the influence of the process of removing the first sacrificial layer 110 on the channel layer 121, and thus is beneficial to improving the quality of the channel layer 121 and further beneficial to improving the device performance.

[0054] As an example, it is illustrated by taking the formation of an NMOS transistor as an example. The material of the channel layer 121 is silicon; the material of the second sacrificial layer 122 is silicon germanide.

[0055] In the subsequent process of removing the second sacrificial layer 122, the etching selectivity between silicon germanide and silicon is relatively high. Therefore, by setting the material of the second sacrificial layer 122 as silicon germanide and the material of the channel layer 121 as silicon, the influence of the removal process of the second sacrificial layer 122 on the channel layer 121 can be effectively reduced, thereby improving the quality of the channel layer 121 and further facilitating the improvement of device performance.

[0056] In other embodiments, when forming a PMOS transistor, to improve the performance of the PMOS transistor, a silicon germanide channel technology can be adopted, that is, the material of the channel layer is silicon germanide and the material of the second sacrificial layer is silicon.

[0057] In some other embodiments, based on actual process requirements, other materials can also be selected for the channel layer and the second sacrificial layer.

[0058] In this embodiment, in the step of providing the substrate 100, a shallow trench isolation (STI) structure (not shown in the figure) is formed on the substrate 100 between adjacent channel stacks 120, and the sidewalls of the channel stacks 120 are exposed by the shallow trench isolation structure.

[0059] The shallow trench isolation structure is used to isolate adjacent devices or adjacent channel stacks 120.

[0060] Specifically, the material of the shallow trench isolation structure is silicon oxide. In other embodiments, the material of the shallow trench isolation structure can also be other insulating materials such as silicon nitride or silicon oxynitride.

[0061] The gate structure 130 is a dummy gate structure, which is used to occupy a spatial position for the subsequent formation of the device gate structure.

[0062] In this embodiment, the gate structure 130 includes a dummy gate oxide layer (not shown in the figure) and a dummy gate layer (not shown in the figure) located on the dummy gate oxide layer. As an example, the material of the dummy gate oxide layer includes one or several of silicon oxide and silicon oxynitride. As an example, the material of the dummy gate layer includes polysilicon or amorphous silicon.

[0063] In this embodiment, a gate mask structure 134 is further formed on the top of the gate structure 130.

[0064] The gate mask structure 134 serves as an etching mask for forming the gate structure 130 and is also used to protect the top of the gate structure 130.

[0065] Specifically, the gate mask structure 134 includes a first hard mask layer 135 covering the top of the gate structure 130, a second hard mask layer 136 covering the first hard mask layer 135, and a third hard mask layer 137 covering the second hard mask layer 136.

[0066] More specifically, the material of the first hard mask layer 135 is silicon oxide, the material of the second hard mask layer 136 is silicon nitride, and the material of the third hard mask layer 137 is silicon oxide, that is, the hard mask structure 134 is an (Oxide-Nitride-Oxide) structure.

[0067] In this embodiment, after providing the substrate 100, before removing the channel stack 120 and the first sacrificial layer 110 on both sides of the gate structure 130 to form a groove exposing the top of the substrate 100, it further includes: forming sidewalls 131 on the sidewalls of the gate structure 130.

[0068] The sidewalls 131 are used to protect the sidewalls of the gate structure 130 during the formation of the semiconductor structure, and are also used to define the positions of the source / drain doping layers.

[0069] Specifically, the sidewalls 131 are used as an etching mask during the formation of the groove.

[0070] It should be noted that the sidewalls 131 can be a single-layer structure or a stacked structure, and the materials of the sidewalls 131 include one or more of silicon nitride (SiN), silicon carbide (SiC), silicon carbon oxide (SiCO), silicon carbon oxynitride (SiCON), and silicon boron nitride (SiBN).

[0071] Correspondingly, in this embodiment, the sidewalls 131 also cover the sidewalls of the gate mask structure 134.

[0072] Refer to Figure 16 , remove the channel stack 120 and the first sacrificial layer 110 on both sides of the gate structure 130 to form a groove 210 exposing the top of the substrate 100.

[0073] Removing the channel stack 120 and the first sacrificial layer 110 on both sides of the gate structure 130 to form a groove 210 exposing the top of the substrate 100, that is, during the process of removing the channel stack 120 and the first sacrificial layer 110 on both sides of the gate structure 130, the top of the substrate 100 is used as the stop position. Compared with the thickness of the channel layer 121, the thickness of the substrate 100 is usually larger. Therefore, compared with the solution using the top of the channel layer closest to the substrate as the stop position, the process window for forming the groove 210 is increased, and the process difficulty is correspondingly reduced; moreover, using the top of the substrate 100 as the stop position enables the sidewalls of the first sacrificial layer 110 to be completely exposed, which also facilitates the subsequent formation of a protective layer covering at least part of the sidewalls of the first sacrificial layer 110, thereby avoiding the inner sidewalls covering the entire sidewalls of the first sacrificial layer, and thus it is difficult to remove the first sacrificial layer subsequently.

[0074] The groove 210 is used to provide space for the subsequent formation of the source-drain doping layer, and the sidewalls of the groove 210 also expose the sidewalls of the channel stack 120, so as to laterally remove a part of the width of the second sacrificial layer 122 in a direction perpendicular to the sidewalls of the gate structure 130.

[0075] Reference Figure 17 , after forming the groove 210, a part of the width of the second sacrificial layer 122 is laterally removed in a direction perpendicular to the sidewalls of the gate structure 130, and an inner groove 220 communicating with the groove 210 is formed between the channel layers 121.

[0076] The inner groove 220 is used to provide a spatial position for the subsequent formation of the inner sidewall.

[0077] In this embodiment, in the step of forming the inner groove 220 communicating with the groove 210 between the channel layers 121, a part of the width of the first sacrificial layer 110 is also laterally removed, and an inner groove 220 communicating with the groove 210 is formed between the channel layer 121 and the substrate 100.

[0078] By laterally removing a part of the width of the first sacrificial layer 110 and forming an inner groove 220 communicating with the groove 210 between the channel layer 121 and the substrate 100, when the first sacrificial layer 110 is removed later, it is convenient to remove the first sacrificial layer 110 via the inner groove 220 communicating with the groove 210, reducing the removal amount of the first sacrificial layer 110, thereby reducing the difficulty of the process for removing the first sacrificial layer 110.

[0079] Reference Figures 18 to 19 , a protective layer 140 covering at least a part of the sidewalls of the first sacrificial layer 110 is formed at the bottom of the groove 210, and the protective layer 140 exposes the ends of the channel layer 121.

[0080] Forming a protective layer 140 covering at least a part of the sidewalls of the first sacrificial layer 110 at the bottom of the groove 210, and the protective layer 140 exposes the ends of the channel layer 121, so that the inner sidewall does not completely cover the sidewalls of the first sacrificial layer 110, making it convenient to remove the first sacrificial layer 110 through the exposed sidewalls of the first sacrificial layer 110 during the subsequent removal of the first sacrificial layer 110, thereby reducing the difficulty of forming the through groove later, improving the quality of the through groove, correspondingly reducing the difficulty of forming the bottom isolation layer, improving the quality of the bottom isolation layer, and further being beneficial to improving the off-state leakage current and enhancing the performance of the semiconductor structure.

[0081] In this embodiment, in the step of forming the protective layer 140, the protective layer 140 covers the entire sidewalls of the first sacrificial layer 110.

[0082] In the step of forming the protective layer 140, the protective layer 140 covers the entire sidewalls of the first sacrificial layer 110, such that the subsequently formed inner sidewalls will not cover the sidewalls of the first sacrificial layer 110. Thus, during the process of removing the first sacrificial layer 110, the sidewalls of the first sacrificial layer 110 are completely exposed, further reducing the difficulty of forming a through groove by removing the first sacrificial layer 110.

[0083] In other embodiments, in the step of forming the protective layer, when the protective layer covers a portion of the sidewalls of the first sacrificial layer, the height of the sidewalls of the first sacrificial layer covered by the protective layer is greater than 50% of the height of the sidewalls of the first sacrificial layer.

[0084] The height of the sidewalls of the first sacrificial layer covered by the protective layer being greater than 50% of the height of the sidewalls of the first sacrificial layer is conducive to a relatively large exposed sidewall area of the first sacrificial layer during the process of removing the first sacrificial layer.

[0085] In this embodiment, in the step of forming the protective layer 140, the material of the protective layer 140 includes one or more of spin on carbon (SOC), Spin-on hardmasks (SOH), and Spin-on glass (SOG).

[0086] Spin on carbon, Spin-on hardmasks, and Spin-on glass have good filling properties and are easy to remove, which helps to reduce the process difficulty of forming the protective layer 140 and removing the protective layer 140.

[0087] In this embodiment, the step of forming the protective layer 140 includes: as Figure 18 shown, forming a protective material layer 145 in the groove 210, and the protective material layer 145 also covers the sidewalls of the first sacrificial layer 110; as Figure 19 shown, removing a first portion of the thickness of the protective material layer 145 to expose the end of the channel layer 121, and the remaining protective material layer 145 covers at least a portion of the sidewalls of the first sacrificial layer 110 and serves as the protective layer 140.

[0088] First forming a protective material layer 145 covering the sidewalls of the first sacrificial layer 110 in the groove 210, and then removing a first portion of the thickness of the protective material layer 145 to expose the end of the channel layer 121, with the remaining protective material layer 145 covering at least a portion of the sidewalls of the first sacrificial layer 110 and serving as the protective layer 140, is conducive to reducing the process difficulty of forming the protective layer 140.

[0089] It should be noted that the process of forming the protective material layer 145 in the groove 210 includes a spin coating process or a spraying process. As an example, the process of forming the protective material layer 145 in the groove 210 includes a spin coating process. The spin coating process is beneficial to making the thickness uniformity of the protective material layer 145 better, so that the thickness uniformity of the protective layer 140 is better.

[0090] It should also be noted that the process of removing the first part of the thickness of the protective material layer 145 includes an isotropic etching process. The isotropic etching process has the characteristic of isotropy, which is convenient for removing the protective material layer 145 in the inner groove 220 between the channel layers 121, so as to facilitate the subsequent formation of the inner sidewall covering the sidewall of the second sacrificial layer 122. As an example, the process of removing the first part of the thickness of the protective material layer 145 includes an isotropic wet etching process. The isotropic wet etching process is easy to achieve a high etching selectivity between the object to be etched (i.e., the protective material layer 145) and other film layers (such as the channel layer 121, the substrate), thereby reducing the damage to other film layers.

[0091] In this embodiment, in the step of forming the inner groove 220 communicating with the groove 210 between the channel layers 121, a part of the width of the first sacrificial layer 110 is also laterally removed to form the inner groove 220 communicating with the groove 210 between the channel layer 121 and the substrate 100. Correspondingly, in the step of forming the protective layer 140 covering at least a part of the sidewall of the first sacrificial layer 110 at the bottom of the groove 210, the protective layer 140 covers at least a part of the sidewall of the first sacrificial layer 110 in the inner groove 220. That is to say, in this embodiment, first, a part of the width of the second sacrificial layer 122 is laterally removed to form the inner groove 220 communicating with the groove 210 between the channel layers 121, and then, in the bottom of the groove 210 and the inner groove 220, a protective layer 140 covering at least a part of the sidewall of the first sacrificial layer 110 is formed.

[0092] In other embodiments, it is also possible to first form a protective layer covering at least a part of the sidewall of the first sacrificial layer at the bottom of the groove, and then laterally remove a part of the width of the second sacrificial layer to form an inner groove communicating with the groove between the channel layers.

[0093] Reference Figure 20 , an inner sidewall 150 covering the sidewall of the second sacrificial layer 122 is formed in the inner groove 220.

[0094] An inner wall 150 covering the sidewalls of the second sacrificial layer 122 is formed in the inner groove 220. The inner wall 150 is used to protect the second sacrificial layer 122, reducing the probability of damage to the second sacrificial layer 122 during the removal of the protective layer 140 and the first sacrificial layer 110. The inner wall 150 is also used to isolate the source-drain doping layer from the device gate structure, increasing the distance between the source-drain doping layer and the device gate structure, thereby reducing the parasitic capacitance between the source-drain doping layer and the device gate structure.

[0095] In this embodiment, in the step of forming the inner wall 150, the material of the inner wall 150 includes one or more of silicon nitride, silicon carbide, silicon carbonitride, silicon carbon oxynitride, silicon boron nitride, and low-K dielectric materials. As an example, the material of the inner wall 150 includes a low-K dielectric material (such as silicon carbonitride, etc.). The material of the inner wall 150 including a low-K dielectric material is beneficial to further reducing the parasitic capacitance between the source-drain doping layer and the device gate structure. In other embodiments, the material of the inner wall can also be other insulating materials.

[0096] In this embodiment, in the step of forming the protective layer 140 covering at least a part of the sidewalls of the first sacrificial layer 110 at the bottom of the groove 210, the protective layer 140 covers at least a part of the sidewalls of the first sacrificial layer 110 in the inner groove 220. Correspondingly, after forming the protective layer 140, the inner wall 150 is formed in the remaining inner groove 220.

[0097] Reference Figure 21 After forming the inner wall 150, the protective layer 140 and the first sacrificial layer 110 are removed to form a through groove 230 communicating with the groove 210.

[0098] Since the inner wall 150 covers the sidewalls of the second sacrificial layer 122, it protects the sidewalls of the second sacrificial layer 122, reducing the probability of damage to the second sacrificial layer 122 during the removal of the protective layer 140 and the first sacrificial layer 110. Moreover, the protective layer 140 covers at least a part of the sidewalls of the first sacrificial layer 110 and exposes the ends of the channel layer 121, so that the inner wall 150 does not completely cover the sidewalls of the first sacrificial layer 110, facilitating the removal of the first sacrificial layer 110 through the exposed sidewalls of the first sacrificial layer 110 during the removal of the first sacrificial layer 110, thereby reducing the difficulty of forming the through groove 230, improving the quality of the through groove 230, correspondingly reducing the difficulty of forming the bottom isolation layer subsequently, improving the quality of the bottom isolation layer, and further being beneficial to improving the off-state leakage current and enhancing the performance of the semiconductor structure.

[0099] The through groove 230 is used to provide a spatial position for the subsequent formation of the bottom isolation layer.

[0100] It should be noted that the through groove 230 is used as the first through groove.

[0101] Specifically, after forming the inner sidewall 150, the protective layer 140 is removed; after removing the protective layer 140, the first sacrificial layer 110 is removed to form a through groove 230 communicating with the groove 210.

[0102] In this embodiment, the process of removing the protective layer 140 and the first sacrificial layer 110 includes an isotropic etching process or an isotropic etching process and an ashing process.

[0103] The isotropic etching process can achieve a high etching selectivity ratio, which is beneficial to reducing the probability of damage to other film layers (such as the channel layer 121 and the substrate 100) when removing the protective layer 140 and the first sacrificial layer 110. The ashing process has the characteristics of low cost and less by-products, thus facilitating the reduction of residues.

[0104] In a specific embodiment, after removing the protective layer 140 by using an isotropic wet etching process or an ashing process, the first sacrificial layer 110 is removed by using an isotropic wet etching process or an isotropic dry etching process.

[0105] The isotropic wet etching process has relatively low cost and simple operation steps. The isotropic dry etching process is beneficial to reducing the probability of residue of the first sacrificial layer 110.

[0106] Specifically, when removing the first sacrificial layer 110 by using an isotropic dry etching process, the process temperature of the dry etching process is less than 600 degrees Celsius.

[0107] The process temperature of the dry etching process being less than 600 degrees Celsius is beneficial to reducing the probability of atoms in the channel layer 121 and the second sacrificial layer 122 diffusing into adjacent film layers.

[0108] Reference Figures 22 to 23 , a bottom isolation layer 160 exposing the end of the channel layer 121 is formed in the through groove 230.

[0109] The bottom isolation layer 160 is used to isolate the channel layer 121 and the substrate 100, thus being beneficial to reducing the gate parasitic capacitance and improving the operating speed of the semiconductor device. Moreover, the subsequent formed source-drain doping layer can also be isolated from the substrate 100 through the bottom isolation layer 160, thus being beneficial to reducing the probability of source-drain punch-through, improving the control force of the device gate structure on the channel, correspondingly improving the short-channel effect, and further reducing the off-state leakage current and correspondingly reducing the power consumption of the semiconductor device.

[0110] In this embodiment, in the step of forming the bottom isolation layer 160, the bottom isolation layer 160 is also formed on the substrate 100 at the bottom of the groove 210.

[0111] The bottom isolation layer 160 is also formed on the substrate 100 at the bottom of the groove 210, which is beneficial to further improve the isolation effect of the bottom isolation layer 160 on the source-drain doping layer, thereby being beneficial to further reducing the probability of source-drain punch-through.

[0112] Specifically, in the step of forming the bottom isolation layer 160, the top of the bottom isolation layer 160 in the groove 210 is lower than the top of the bottom isolation layer 160 in the through-groove 230.

[0113] The top of the bottom isolation layer 160 in the groove 210 being lower than the top of the bottom isolation layer 160 in the through-groove 230 is beneficial to making the volume of the subsequently formed source-drain doping layer larger, correspondingly capable of providing greater stress, thereby being beneficial to improving the carrier mobility, and further being beneficial to further improving the performance of the semiconductor structure.

[0114] More specifically, in the step of forming the bottom isolation layer 160, the difference between the thickness H1 of the bottom isolation layer 160 in the through-groove 230 and the thickness H2 of the bottom isolation layer 160 in the groove 210 is less than 5 times the thickness H3 of the channel layer 121.

[0115] The difference between the thickness H1 of the bottom isolation layer 160 in the through-groove 230 and the thickness H2 of the bottom isolation layer 160 in the groove 210 being less than 5 times the thickness H3 of the channel layer 121 is beneficial to reducing the difficulty of forming the subsequently formed source-drain doping layer and improving the quality of the source-drain doping layer.

[0116] In this embodiment, the step of forming the bottom isolation layer 160 includes: forming a bottom isolation material layer 165 in the through-groove 230 and the groove 210 (as Figure 22 shown); removing the bottom isolation material layer 165 in the groove 210 to expose the substrate 100 at the bottom of the groove 210, and the remaining bottom isolation material layer 165 serves as the bottom isolation layer 160; or, removing a second part of the thickness of the bottom isolation material layer 165 in the groove 210 so that the remaining bottom isolation material layer 165 exposes the end of the channel layer 121, and the remaining bottom isolation material layer 165 serves as the bottom isolation layer 160, and the bottom isolation layer 160 is also formed on the substrate 100 at the bottom of the groove 210 (as Figure 23 shown).

[0117] First forming a bottom isolation material layer 165 in the through-groove 230 and the groove 210, and then removing the bottom isolation material layer 165 in the groove 210 to expose the substrate 100 at the bottom of the groove 210, or removing a second part of the thickness of the bottom isolation material layer 165 in the groove 210 so that the remaining bottom isolation material layer 165 exposes the end of the channel layer 121, is beneficial to reducing the difficulty of forming the bottom isolation layer 160.

[0118] It should be noted that the process for forming the bottom isolation material layer 165 includes one or more of Flowable Chemical Vapor Deposition (FCVD), plasma-enhanced CVD (PECVD), High Temperature Chemical Vapor Deposition (HTCVD), and Low Pressure Chemical Vapor Deposition (LPCVD).

[0119] As an example, the process for forming the bottom isolation material layer 165 includes the flowable chemical vapor deposition process. The flowable chemical vapor deposition process has better fluidity and ideal filling ability, which is beneficial to reducing the probability of defects such as voids formed in the bottom isolation material layer 165.

[0120] It should also be noted that the process for removing the bottom isolation material layer 165 includes the Certas gas etching process or the SiCoNi etching process. As an example, the process for removing the bottom isolation material layer 165 includes the Certas gas etching process.

[0121] The Certas gas etching process is easy to achieve a high etching selectivity between the etched object (the bottom isolation material layer 165) and other film layers (such as the channel layer 121, the inner sidewall 150, etc.), thereby improving the uniformity of the height of the bottom isolation layer 160. Moreover, the Certas gas etching process does not require plasma bombardment, thereby reducing the damage to other film layers.

[0122] In this embodiment, in the step of forming the bottom isolation layer 160, the material of the bottom isolation layer 160 includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon carbonitride oxide, silicon boronitride, and low-K dielectric materials. As an example, the material of the bottom isolation layer 160 includes one or two of silicon oxide and low-K dielectric materials.

[0123] Silicon oxide is a commonly used material in the semiconductor manufacturing field and has high process compatibility, which is beneficial to reducing the formation difficulty and process cost of the bottom isolation layer 160.

[0124] The low-K dielectric material refers to a dielectric material with a relative dielectric constant lower than 3.9. Selecting the low-K dielectric material is beneficial to further reducing the parasitic capacitance between the source-drain doping layer and the device gate structure.

[0125] Reference Figure 24 , a source-drain doping layer 170 connected to both ends of the channel layer 121 is formed in the groove 210.

[0126] The source-drain doping layer 170 is used as the source or drain of the formed transistor. When the MOS transistor is operating, the source-drain doping layer 170 is used to provide a carrier source.

[0127] In this embodiment, in the step of forming the bottom isolation layer 160, the bottom isolation layer 160 is also formed on the substrate 100 at the bottom of the groove 210. Correspondingly, in the step of forming the source-drain doping layer 170, the source-drain doping layer 170 is formed on the bottom isolation layer 160 at the bottom of the groove 210.

[0128] Continue to refer to Figure 24 In this embodiment, after forming the source-drain doping layer 170, it further includes: forming an interlayer dielectric layer 180 on the shallow trench isolation structure on the side of the gate structure 130, and the interlayer dielectric layer 180 covers the source-drain doping layer 170.

[0129] The interlayer dielectric layer 180 is used to achieve electrical isolation between adjacent semiconductor structures.

[0130] Specifically, the material of the interlayer dielectric layer 180 is silicon oxide. In other embodiments, the material of the interlayer dielectric layer can also be other suitable dielectric materials.

[0131] Refer to Figure 25 In this embodiment, after forming the interlayer dielectric layer 180, it further includes: removing the gate mask structure 134 to expose the top of the gate structure 130.

[0132] Removing the gate mask structure 134 to expose the top of the gate structure 130 facilitates the subsequent removal of the gate structure 130 from the top position of the gate structure 130.

[0133] Specifically, after forming the interlayer dielectric layer 180, the gate mask structure 134 is removed, and during the removal of the gate mask structure 134, a part of the thickness of the interlayer dielectric layer 180 is also removed.

[0134] Refer to Figure 26 In this embodiment, after forming the interlayer dielectric layer 180, it further includes: removing the gate structure 130, forming an opening 250 at the position of the gate structure 130, and the opening 250 exposes the top and sidewalls of the channel layer 121; through the opening 250, removing the second sacrificial layer 122 to form a second through groove 240 between the channel layers 121.

[0135] The opening 250 and the second through groove 240 are used to provide a spatial position for the subsequent formation of the device gate structure.

[0136] Refer to Figure 27 In the opening 250 and the second through groove 240, a device gate structure 190 is filled, and the device gate structure 190 surrounds the channel layer 121.

[0137] During device operation, the device gate structure 190 is used to control the opening and closing of the conductive channel.

[0138] The device gate structure 190 includes a gate dielectric layer (not shown in the figure) and a gate electrode layer covering the gate dielectric layer (not shown in the figure).

[0139] The gate dielectric layer is used to isolate the gate electrode layer from the substrate.

[0140] The material of the gate dielectric layer includes one or more of HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, Al2O3, SiO2, and La2O3.

[0141] In this embodiment, the device gate structure 190 is a metal gate structure. Therefore, the material of the gate electrode layer includes one or more of TiN, TaN, Ta, Ti, TiAl, W, Al, TiSiN, and TiAlC. The gate electrode layer includes a work function layer and an electrode layer covering the work function layer, or may only include the work function layer.

[0142] Correspondingly, the gate dielectric layer includes a high-k gate dielectric layer. The material of the high-k gate dielectric layer is a high-k dielectric material, which refers to a dielectric material with a relative dielectric constant greater than that of silicon dioxide. Specifically, the material of the high-k gate dielectric layer can be selected from HfO2, ZrO2, HfSiO, HfSiON, HfTaO, HfTiO, HfZrO, or Al2O3, etc. As an example, the material of the high-k gate dielectric layer is HfO2.

[0143] In other embodiments, the device gate structure can also be a polysilicon gate structure.

[0144] It should be noted that the semiconductor structure can be formed by the formation method described in the foregoing embodiments, or can be formed by other formation methods. For a specific description of the semiconductor structure described in this embodiment, reference can be made to the corresponding description in the foregoing embodiments, and details are not repeated herein.

[0145] Although the present invention is disclosed as above, the present invention is not limited thereto. Any person skilled in the art can make various changes and modifications without departing from the spirit and scope of the present invention. Therefore, the protection scope of the present invention should be determined by the scope defined by the claims.

Claims

1. A method for forming a semiconductor structure, characterized in that, Including: Providing a substrate, on which a first sacrificial layer is formed, and a channel stack located on the first sacrificial layer, the channel stack includes a plurality of channel layers stacked in sequence longitudinally, and a second sacrificial layer located between adjacent channel layers, a gate structure is formed on the substrate across the channel stack, and the gate structure covers part of the top and part of the sidewalls of the channel stack; Removing the channel stack and the first sacrificial layer on both sides of the gate structure to form a groove exposing the top of the substrate; After forming the groove, along a direction perpendicular to the sidewall of the gate structure, transversely removing a part of the width of the second sacrificial layer to form an inner groove communicating with the groove between the channel layers; Forming a protective layer at the bottom of the groove covering at least part of the sidewall of the first sacrificial layer, and the protective layer exposes the ends of the channel layers; Forming an inner sidewall covering the sidewall of the second sacrificial layer in the inner groove; After forming the inner sidewall, removing the protective layer and the first sacrificial layer to form a through groove communicating with the groove; Forming a bottom isolation layer exposing the ends of the channel layers in the through groove; Forming source-drain doping layers connected to both ends of the channel layers in the groove; 2. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the protective layer, the protective layer covers the entire sidewall of the first sacrificial layer; 3. The method for forming a semiconductor structure according to claim 1, wherein In the step of forming the protective layer, when the protective layer covers part of the sidewall of the first sacrificial layer, the height of the sidewall of the first sacrificial layer covered by the protective layer is greater than 50% of the height of the sidewall of the first sacrificial layer; 4. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming an inner groove communicating with the groove between the channel layers, also transversely removing a part of the width of the first sacrificial layer to form an inner groove communicating with the groove between the channel layer and the substrate; In the step of forming a protective layer at the bottom of the groove covering at least part of the sidewall of the first sacrificial layer, the protective layer at least covers part of the sidewall of the first sacrificial layer in the inner groove; After forming the protective layer, forming an inner sidewall in the remaining inner groove; 5. The method for forming a semiconductor structure according to any one of claims 1 to 4, characterized in that The materials of the first sacrificial layer and the second sacrificial layer are the same; 6. The method for forming a semiconductor structure according to any one of claims 1 to 4, characterized in that, The step of forming the protective layer includes: Forming a protective material layer in the groove, and the protective material layer also covers the sidewall of the first sacrificial layer; Removing a first part of the thickness of the protective material layer to expose the ends of the channel layers, and the remaining protective material layer at least covers part of the sidewall of the first sacrificial layer and serves as the protective layer; 7. The method for forming a semiconductor structure according to claim 6, wherein The process of removing the first part of the thickness of the protective material layer includes an isotropic etching process; 8. The method for forming a semiconductor structure according to claim 6, wherein, The process of forming the protective material layer in the groove includes a spin coating process or a spraying process; 9. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the protective layer, the material of the protective layer includes one or more of spin-on carbon, spin-on hard mask, and spin-on glass; 10. The method for forming a semiconductor structure according to claim 1, wherein, The process of removing the protective layer and the first sacrificial layer includes an isotropic etching process or an isotropic etching process and an ashing process; 11. The method for forming a semiconductor structure according to claim 1, wherein, The step of forming the bottom isolation layer includes: Forming a bottom isolation material layer in the through groove and the groove; Remove the bottom isolation material layer in the groove to expose the substrate at the bottom of the groove, and the remaining bottom isolation material layer serves as the bottom isolation layer; alternatively, remove a second part of the thickness of the bottom isolation material layer in the groove so that the remaining bottom isolation material layer exposes the end of the channel layer, and the remaining bottom isolation material layer serves as the bottom isolation layer, and the bottom isolation layer is also formed on the substrate at the bottom of the groove.

12. The method for forming a semiconductor structure according to claim 11, wherein, The process for removing the bottom isolation material layer includes a Certas gas-phase etching process or a SiCoNi etching process.

13. The method for forming a semiconductor structure according to claim 12, wherein, The process for forming the bottom isolation material layer includes one or more of a flowable chemical vapor deposition process, a plasma-enhanced chemical vapor deposition process, a high-temperature chemical vapor deposition process, and a low-pressure chemical vapor deposition process.

14. The method for forming a semiconductor structure according to claim 1 or 11, characterized in that, In the step of forming the bottom isolation layer, the bottom isolation layer is also formed on the substrate at the bottom of the groove; In the step of forming the source / drain doping layer, the source / drain doping layer is formed on the bottom isolation layer at the bottom of the groove.

15. The method for forming a semiconductor structure according to claim 14, wherein, In the step of forming the bottom isolation layer, the top of the bottom isolation layer in the groove is lower than the top of the bottom isolation layer in the through groove.

16. The method for forming a semiconductor structure according to claim 15, wherein In the step of forming the bottom isolation layer, the difference in thickness between the bottom isolation layer in the through groove and the bottom isolation layer in the groove is less than 5 times the thickness of the channel layer.

17. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the bottom isolation layer, the material of the bottom isolation layer includes one or more of silicon oxide, silicon nitride, silicon carbide, silicon carbon oxide, silicon carbonitride oxide, silicon boronitride, and low-K dielectric materials.

18. The method for forming a semiconductor structure according to claim 1, wherein, In the step of forming the inner sidewall, the material of the inner sidewall includes one or more of silicon nitride, silicon carbide, silicon carbon oxide, silicon carbonitride oxide, silicon boronitride, and low-K dielectric materials.

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