Semiconductor element and manufacturing method thereof

Abstract

The invention provides a semiconductor element and a manufacturing method thereof. The semiconductor element comprises a substrate, a fin, a gate structure, a single diffusion isolation structure and a capacitor gate structure. The substrate has first regions and second regions, wherein the second regions are located between adjacent first regions. The fin is disposed on the substrate, wherein the fin in the second region includes a heavily doped region. The gate structure is disposed on the fin and in the first region. The single diffusion isolation structure is disposed on the fin and in the second region. The capacitor gate structure is disposed on the fin and in the second region, wherein the capacitor gate structure is disposed on the single diffusion isolation structure. The semiconductor element provided by the invention has the effects of high integration level, high density and high efficiency, and can have relatively good reliability.

Description

Technical Field

[0001] The present invention relates to a semiconductor device and a method for manufacturing the same, and more particularly to a fin field-effect transistor device including a metal-oxide-semiconductor capacitor and a method for manufacturing the same. Background Art

[0002] As semiconductor device technology gradually develops in the direction of miniaturization, many technologies using fin field-effect transistor (FinFET) devices to replace planar transistor devices have been proposed in recent years. In order to continuously improve the integration, density, and performance of semiconductor devices, it is still necessary to further improve the electrical performance and process yield of fin field-effect transistor devices through process or / and structural design.

[0003] For example, when applying a metal-oxide-semiconductor capacitor (MOSCAP) to the architecture of a fin field-effect transistor device, a heavily doped region must be doped in the fin to make it highly conductive; however, when subsequently growing an oxide layer on the fin using, for example, a thermal oxidation process, the fin including the heavily doped region will consume too much during the process of growing the oxide layer, causing the top of the fin to become conical after the oxide layer is grown, which will reduce the reliability of the finally formed semiconductor device.

[0004] Furthermore, the formation of the metal-oxide-semiconductor capacitor also limits the area available for setting the transistor. Summary of the Invention

[0005] Some embodiments of the present invention provide a semiconductor device that has the effects of high integration, high density, and high performance, and can have relatively good reliability.

[0006] The semiconductor device provided according to some embodiments of the present invention includes a substrate, fins, a gate structure, a single diffusion isolation structure, and a capacitor gate structure. The substrate has a first region and a second region, where the second region is located between adjacent first regions. The fins are disposed on the substrate, and the fins located in the second region include a heavily doped region. The gate structure is disposed on the fins and is located in the first region. The single diffusion isolation structure is disposed on the fins and is located in the second region. The capacitor gate structure is disposed on the fins and is located in the second region, where the capacitor gate structure is disposed on the single diffusion isolation structure.

[0007] Some other embodiments of the present invention provide a method for manufacturing a semiconductor device, and the manufactured semiconductor device has the effects of high integration, high density, and high performance, and can have relatively good reliability.

[0008] A method for manufacturing a semiconductor structure according to some other embodiments of the present invention includes the following steps. First, fins are formed on a substrate, where the fins span a first region and a second region of the substrate, and the second region is located between adjacent first regions. Next, a single diffusion isolation structure is formed in the second region of the substrate, where the extending direction of the single diffusion isolation structure is perpendicular to the extending direction of the fins, and the single diffusion isolation structure spans the fins. Then, a heavily doped region is formed in the fins located in the second region. Subsequently, a gate structure and a capacitor gate structure are respectively formed on the fins in the first region and the second region of the substrate, where the capacitor gate structure is disposed on the single diffusion isolation structure.

[0009] Based on the above, in the semiconductor device and its manufacturing method provided by the present invention, by forming the capacitor gate structure in the second region of the substrate, the area of the first region for forming the gate structure does not need to be reduced, so that the semiconductor device provided by the present invention can have effects such as high integration, high density, and high performance. Moreover, the capacitor gate structure formed in the second region of the substrate is disposed on the single diffusion isolation structure. Therefore, the phenomenon that the top of the fin in the second region becomes conical due to the formation of the heavily doped region can be alleviated, so that the semiconductor device provided by the present invention can have relatively good reliability. Description of the Drawings

[0010] Figure 1A is a partial top view schematic diagram of a semiconductor device according to an embodiment of the present invention;

[0011] Figure 1B is Figure 1A a partial cross-sectional schematic diagram taken along the cutting line A-A' of

[0012] Figure 1C is Figure 1A a partial cross-sectional schematic diagram taken along the cutting line B-B' of

[0013] Figure 2 is a flowchart schematic diagram of a manufacturing method of a semiconductor device according to an embodiment of the present invention. Detailed Description of the Embodiments

[0014] Examples are presented below and in combination with the drawings to describe the present invention in detail, but the examples provided are not used to limit the scope of the present invention. In addition, the drawings of the present invention are only for illustrative purposes, and specific elements in the drawings are not drawn according to the actual ratio. For the convenience of the reader's understanding, in the following description, the same elements will be identified by the same symbols.

[0015] Figure 1A is a partial top view schematic diagram of a semiconductor device according to an embodiment of the present invention, Figure 1B is a partial cross-sectional schematic diagram taken along the cutting line A-A' of Figure 1A andFigure 1C Based on Figure 1A The partial cross-sectional schematic diagram cut out by the section line B-B’.

[0016] Please also refer to Figure 1A 、 Figure 1B and Figure 1C which show the semiconductor element 10 of this embodiment. In this embodiment, the semiconductor element 10 includes a substrate 100, fins 200, a gate structure 300, a single diffusion isolation structure 400, and a capacitor gate structure 500.

[0017] The material of the substrate 100 includes, for example, elemental semiconductors, compound semiconductors, alloy semiconductors, or other suitable materials. For example, the substrate 100 can be a silicon substrate or a silicon on insulator (SOI) substrate, but the present invention is not limited thereto.

[0018] The substrate 100 includes, for example, a first region R1 and a second region R2, where the second region R2 is located between adjacent first regions R1. The first region R1 is, for example, a transistor region, and the fin field effect transistors to be introduced later are disposed thereon, which will not be elaborated here. The second region R2 is, for example, a capacitor region, which was originally, for example, a dummy region disposed between adjacent transistor regions, and the metal oxide semiconductor capacitors to be introduced later are disposed thereon, which will not be elaborated here.

[0019] In this embodiment, the second region R2 of the substrate 100 includes a heavily doped region HD. The doping ions in the heavily doped region HD are, for example, N-type ions. For example, the doping ions in the heavily doped region HD can include phosphorus ions or arsenic ions, but the present invention is not limited thereto. By forming the heavily doped region HD in the second region R2 of the substrate 100, its conductivity can be increased, making it available as one terminal of the metal oxide semiconductor capacitor to be introduced later, which will not be elaborated here.

[0020] The fins 200 are, for example, disposed on the substrate 100. In some embodiments, the fins 200 extend along the direction X to span the first region R1 and the second region R2 of the substrate 100. It should be noted that the number of the fins 200 is not Figures 1A to 1C limited by the partial top view schematic diagram shown. Specifically, the semiconductor element 10 can include a plurality of fins 200, where the plurality of fins 200 have a specific distance from each other and all extend along the direction X.

[0021] The gate structure 300 is disposed on the fin 200, for example. In some embodiments, the gate structure 300 extends along the direction Y (which is perpendicular to the direction X). In the present embodiment, the gate structure 300 is located in the first region R1 of the substrate 100. Therefore, the gate structure 300 can span the fins 200 located in the first region R1 of the substrate 100.

[0022] In some embodiments, the gate structure 300 includes a gate dielectric layer 302 and a gate 304. The gate dielectric layer 302 is disposed on the fin 200, for example. In some embodiments, the material of the gate dielectric layer 302 may include silicon oxide, silicon nitride, silicon oxynitride, or a combination thereof, but the present invention is not limited thereto. In other embodiments, the material of the gate dielectric layer 302 may include a material having a high dielectric constant, which may include hafnium dioxide, zirconium dioxide, or other suitable materials. The gate 304 is disposed on the gate dielectric layer 302, for example. In some embodiments, the material of the gate 304 may include polysilicon or amorphous silicon, but the present invention is not limited thereto.

[0023] In some embodiments, source / drain regions 310 may be provided in the fins 200 on one side of the gate structure 300. The source / drain regions 310 may include an epitaxial layer, for example. In some embodiments, the material of the epitaxial layer may include silicon phosphide or silicon carbide, but the present invention is not limited thereto. In other embodiments, the material of the epitaxial layer may include silicon germanide.

[0024] Based on this, the semiconductor device 10 of the present embodiment includes a fin field effect transistor TFT, which includes the aforementioned gate structure 300 and source / drain regions 310, wherein the fin 200 covered by the gate structure 300 serves as the channel region of the fin field effect transistor TFT.

[0025] In addition, in some embodiments, contact plugs 310P are disposed on and electrically connected to the source / drain regions 310P of the fin field effect transistor TFT, wherein the contact plugs 310P extend along the direction Z. The contact plugs 310P may each include a barrier layer (not shown) and a metal layer (not shown), wherein the material of the barrier layer may include titanium, titanium nitride, tantalum, tantalum nitride, or a combination thereof, and the material of the metal layer may include tungsten, copper, aluminum, titanium-aluminum alloy, or a combination thereof, but the present invention is not limited thereto.

[0026] The single-diffusion isolation structure 400 is disposed on the fin 200, for example. In some embodiments, the single-diffusion isolation structure 400 extends along the direction Y and is located in the second region R2 of the substrate 100. The single-diffusion isolation structure 400 can, for example, divide the fin 200 into two parts. Specifically, the substrate 100 includes, for example, a groove 100Gr located in the second region R2 and extending along the direction Y, where the fin 200 extending along the direction X is separated by the groove 100Gr, and the single-diffusion isolation structure 400 is disposed in the groove 100Gr, for example. In some embodiments, the material of the single-diffusion isolation structure 400 includes silicon oxide, but the present invention is not limited thereto. In other embodiments, the material of the single-diffusion isolation structure 400 can include silicon nitride, silicon oxynitride, or a combination thereof.

[0027] The capacitor gate structure 500 is disposed on the fin 200, for example. In some embodiments, the capacitor gate structure 500 extends along the direction Y. In this embodiment, the capacitor gate structure 500 is located in the second region R2 of the substrate 100. Thus, the capacitor gate structure 500 can span the fin 200 located in the second region R2 of the substrate 100.

[0028] In some embodiments, the capacitor gate structure 500 includes a capacitor dielectric layer 502 and a capacitor gate 504. The capacitor dielectric layer 502 is disposed on the fin 200, for example. In some embodiments, the material of the capacitor dielectric layer 502 can be the same as or similar to the material of the foregoing gate dielectric layer 302, which will not be elaborated herein. The capacitor gate 504 is disposed on the capacitor dielectric layer 502, for example. In some embodiments, the material of the capacitor gate 504 can be the same as or similar to the material of the foregoing gate 304, which will not be elaborated herein.

[0029] The capacitor gate structure 500 is disposed on the single-diffusion isolation structure 400, for example. In this embodiment, the capacitor gate structure 500 and the single-diffusion isolation structure 400 partially overlap. Specifically, the capacitor gate structure 500 partially overlaps the single-diffusion isolation structure 400 in the direction Z, and the width of the capacitor gate structure 500 in the direction X can be greater than the width of the single-diffusion isolation structure 400 in the direction X, so that a part of the capacitor gate structure 500 can be disposed between the segmented fins 200.

[0030] In some embodiments, dummy source / drain regions 510 can be disposed in the fins 200 on both sides of the capacitor gate structure 500. The material of the dummy source / drain regions 510 can be the same as or similar to the material of the foregoing source / drain regions 310, which will not be elaborated herein.

[0031] Based on this, the semiconductor element 10 of this embodiment includes a capacitor CAP, which includes the aforementioned capacitor gate 504, capacitor dielectric layer 502, heavily doped region HD in the fin 200, and dummy source / drain region 510. Among them, the capacitor gate 504 serves as one terminal of the capacitor CAP, and the heavily doped region HD and the dummy source / drain region 510 serve as the other terminal of the capacitor CAP. That is, the capacitor CAP of this embodiment is a metal-oxide-semiconductor capacitor (MOSCAP).

[0032] In addition, in some embodiments, a contact plug 500P is disposed on and electrically connected to the capacitor gate structure 500 of the capacitor CAP, and a contact plug 510P is disposed on and electrically connected to the dummy source / drain region 510P of the capacitor CAP, wherein the contact plug 500P and the contact plug 510P extend along the direction Z. The materials of the contact plug 500P and the contact plug 510P may be the same as or similar to the material of the aforementioned contact plug 310P, which will not be elaborated here.

[0033] Based on the above, by disposing the capacitor CAP in the second region R2 of the substrate 100, the second region R2 that was originally a dummy region can be effectively utilized. Therefore, the capacitor CAP can be disposed without reducing the components originally disposed in the first region R1 of the substrate 100, so that the semiconductor element 10 of this embodiment can have effects such as high integration, high density, and high performance.

[0034] Furthermore, since the single diffusion isolation structure 400 is disposed in the second region R2 of the substrate 100, the phenomenon that the top of the fin 200 located in the second region R2 becomes conical due to the formation of the heavily doped region HD can be alleviated, as shown in Figure 1C shown, so that the semiconductor element 10 of this embodiment can have relatively good reliability.

[0035] Figure 2 It is a schematic flow chart of a manufacturing method of a semiconductor element according to an embodiment of the present invention. It should be noted that Figure 2 the embodiments of Figures 1A to 1C can follow the component numbers and partial contents of the embodiments of

[0036] wherein the same or approximate numbers are used to represent the same or approximate components, and the description of the same technical content is omitted.

[0037] The fin 200 straddles, for example, the first region R1 and the second region R2 of the substrate 100. In some embodiments, the fin 200 can be fabricated by a technique of sidewall image transfer (SIT), which can be formed by performing the following processes, but the present invention is not limited thereto. (1) Provide a layout pattern to a computer system and perform appropriate calculations to define the corresponding pattern in a photomask; (2) Subsequently, through photolithography and etching processes, a plurality of equidistant and equi-width patterned sacrificial layers (not shown) can be formed on the substrate 100, and their individual appearances are strip-shaped; (3) Then, deposition and etching processes are sequentially performed to form spacer walls (not shown) on the sidewalls of the patterned sacrificial layers; (4) Subsequently, the patterned sacrificial layers are removed, and an etching process is performed under the coverage of the spacer walls, so that the pattern formed by the spacer walls is transferred into the substrate 100; (5) Then, with a fin cut process, the desired patterned structure is obtained, such as Figure 1A the strip-shaped patterned fin 200 shown.

[0038] In some other embodiments, the fin 200 can be formed by performing the following processes. (1) Form a patterned mask (not shown) on the substrate 100; (2) Use the patterned mask to perform an etching process on the substrate 100 to form the fin 200 in the substrate 100.

[0039] In still some other embodiments, the fin 200 can be formed by performing the following processes. (1) Form a patterned mask (not shown) on the substrate 100; (2) Use the patterned mask to perform an epitaxial process on the substrate 100 to grow a semiconductor layer such as silicon germanium on the substrate 100, and this semiconductor layer can serve as the corresponding fin 200.

[0040] Next, a single diffusion isolation structure 400 is formed in the second region R2 of the substrate 100, wherein the extending direction of the single diffusion isolation structure 400 is perpendicular to the extending direction of the fin 200, and the single diffusion isolation structure 400 straddles the fin 200. Based on this, the single diffusion isolation structure 400 can, for example, divide the fin 200 into two parts.

[0041] The method for forming the single-diffusion isolation structure 400 can be formed, for example, by performing the following processes, but the present invention is not limited thereto. (1) A patterned mask (not shown) is formed on the substrate 100, wherein the patterned mask covers the first region R1 of the substrate 100; (2) The fin 200 and the substrate 100 are etched using the patterned mask to remove a part of the fin 200 located in the second region R2, and further remove a part of the substrate 100 under the original fin 200 to form a groove 100Gr, which separates the fin 200 into two parts; (3) A dielectric layer is disposed in the groove 100Gr to form the single-diffusion isolation structure 400, wherein the top surface of the single-diffusion isolation structure 400 is lower than the top surface of the fin 200.

[0042] The dielectric layer can be disposed in the groove 100Gr, for example, by performing the following processes, but the present invention is not limited thereto. (3-1) Fill the groove 100Gr with the dielectric layer; (3-2) Use a re-etching process to remove a part of the dielectric layer in the groove 100Gr, so that the top surface of the etched single-diffusion isolation structure 400 is lower than the top surface of the fin 200.

[0043] In some embodiments, before forming the single-diffusion isolation structure 400 in the second region R2 of the substrate 100, a shallow trench isolation structure (not shown) can be formed in the first region R1 of the substrate 100, wherein the shallow trench isolation structure surrounds the fin 200. The method for forming the shallow trench isolation structure is, for example, to first form a silicon oxide layer covering the fin 200 on the substrate 100 using a flowable chemical vapor deposition (FCVD) process, and then use a chemical mechanical polishing (CMP) process and / or an etching process to remove a part of the silicon oxide layer.

[0044] Then, a heavily doped region HD is formed in the second region R2 of the substrate. The heavily doped region HD can be formed, for example, by performing the following process, but the present invention is not limited thereto. (1) A patterned mask (not shown) is formed on the substrate 100, wherein the patterned mask covers the first region R1 of the substrate 100; (2) An ion implantation process IMP is performed on the second region R2 of the substrate 100 using the patterned mask; (3) A rapid thermal processing (RTP) is performed on the substrate 100 to form the heavily doped region HD in the second region R2 of the substrate. In some embodiments, the doped ions implanted in the ion implantation process IMP are N-type ions, which may include phosphorus ions or arsenic ions, but the present invention is not limited thereto. By forming the heavily doped region HD in the second region R2 of the substrate 100, its conductivity can be increased, making it available as a terminal of a metal oxide semiconductor capacitor, which will not be elaborated here.

[0045] It is worth noting that due to the formation of the heavily doped region HD in the second region R2 of the substrate, which results in a relatively high doping concentration, the fin 200 located in the second region R2 of the substrate is more amorphous than the fin 200 located in the first region R1 of the substrate. In this case, when a rapid thermal processing and / or a thermal oxidation process is performed on the substrate 100 to form the dielectric layer IL to be introduced later, the fin 200 located in the second region R2 of the substrate is consumed faster than the fin 200 located in the first region R1 of the substrate.

[0046] In this regard, since the single diffusion isolation structure 400 is provided in the second region R2 of the substrate 100, the phenomenon that the top of the fin 200 located in the second region R2 becomes conical due to the formation of the heavily doped region HD can be alleviated, so that the semiconductor device 10 of this embodiment can have relatively good reliability.

[0047] After that, a gate structure 300 and a capacitor gate structure 500 are respectively formed on the fins 200 in the first region R1 and the second region R2. In some embodiments, the gate structure 300 and the capacitor gate structure 500 can be fabricated using a gate first process or a gate last process according to the process requirements, and the present invention is not limited thereto.

[0048] The gate structure 300 and the capacitor gate structure 500 can be formed, for example, by performing the following processes, but the present invention is not limited thereto. (1) A dielectric layer IL is formed on the substrate 100 by a thermal oxidation process or a deposition process; (2) A gate material layer (not shown) is formed on the dielectric layer IL by a deposition process, and the above deposition process may include, for example, a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, or an atomic layer deposition (ALD) process; (3) A patterning process is used to remove part of the dielectric layer IL and the gate material layer on the substrate 100 once or successively to form a gate dielectric layer 302 and a gate 304 in the first region R1, and a capacitor dielectric layer 502 and a capacitor gate 504 in the second region R2.

[0049] It should be noted that the remaining descriptions of the gate structure 300 and the capacitor gate structure 500 can refer to the foregoing embodiments and will not be repeated here.

[0050] Next, source / drain regions 310 and dummy source / drain regions 510 are respectively formed in the fins 200 in the first region R1 and the second region R2. The source / drain regions 310 and the dummy source / drain regions 510 can be formed, for example, by performing the following processes, but the present invention is not limited thereto. (1) The gate structure 300 and the capacitor gate structure 500 are used as masks to etch the fins 200 in the first region R1 and the second region R2 of the substrate 100 respectively to form recesses 200Gr, and additional masks may also be provided, which is not limited in the present invention; (2) An epitaxial growth process is performed to form an epitaxial layer in the recesses 200Gr of the fins 200, where the epitaxial layer in the first region R1 of the substrate 100 can be used as the source / drain region 310, and the epitaxial layer in the second region R2 of the substrate 100 can be used as the dummy source / drain region 510.

[0051] After the source / drain regions 310 and dummy source / drain regions 510 are formed, a fin field-effect transistor TFT and a capacitor CAP are formed respectively. The fin field-effect transistor TFT includes a gate structure 300 and source / drain regions 310, where the fin 200 covered by the gate structure 300 serves as the channel region of the fin field-effect transistor TFT. The capacitor CAP includes a capacitor gate 504, a capacitor dielectric layer 502, a heavily doped region HD in the fin 200, and dummy source / drain regions 510, where the capacitor gate 504 serves as one terminal of the capacitor CAP, and the heavily doped region HD and the dummy source / drain regions 510 serve as the other terminal of the capacitor CAP. That is, the capacitor CAP in this embodiment is a metal-oxide semiconductor capacitor.

[0052] After that, a contact plug 500P can be formed on the capacitor gate structure 500 of the capacitor CAP, and a contact plug 510P can be formed on the dummy source / drain region 510 of the capacitor CAP. For the remaining introductions of the contact plug 500P and the contact plug 510P, reference can be made to the foregoing embodiments, and details will not be repeated here.

[0053] So far, the fabrication of the semiconductor device 10 is completed. Although the manufacturing method of the semiconductor device 10 in this embodiment is described by taking the above method as an example, however, the manufacturing method of the semiconductor device of the present invention is not limited thereto. It is worth noting that the semiconductor device 10 in this embodiment is a fin field-effect transistor device including a metal-oxide semiconductor capacitor, but the semiconductor device of the present invention is not limited thereto.

[0054] In summary, in the semiconductor device and its manufacturing method provided by the present invention, by forming a capacitor gate structure in the second region (originally a dummy region) of the substrate, the area of the first region (transistor region) of the substrate used to form the gate structure can be not reduced, so that the semiconductor device provided by the present invention can have effects such as high integration, high density, and high performance. Furthermore, the capacitor gate structure formed in the second region of the substrate is disposed on a single diffusion isolation structure. Therefore, the phenomenon that the top of the fin in the second region becomes conical due to the formation of the heavily doped region can be alleviated, so that the semiconductor device provided by the present invention can have relatively good reliability.

[0055] Finally, it should be noted that: the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that: they can still modify the technical solutions recorded in the foregoing embodiments, or perform equivalent replacements on some or all of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the scope of the technical solutions of the embodiments of the present invention.

Claims

1. A semiconductor device, characterized in that, Comprising: A substrate having a first region and a second region, wherein the second region is located between adjacent first regions; Fins disposed on the substrate, wherein the fins located in the second region include heavily doped regions; A gate structure disposed on the fins and located in the first region; A single diffusion isolation structure disposed on the fins and located in the second region; And A capacitor gate structure disposed on the fins and located in the second region, wherein the capacitor gate structure is disposed on the single diffusion isolation structure.

2. The semiconductor device according to claim 1, wherein the capacitor gate structure partially overlaps the single diffusion isolation structure.

3. The semiconductor device according to claim 1, wherein the top surface of the single diffusion isolation structure is lower than the top surface of the fins.

4. The semiconductor device according to claim 1, further comprising: Dummy source / drain regions disposed in the fins on both sides of the capacitor gate structure.

5. The semiconductor device according to claim 1, wherein the dummy source / drain regions include epitaxial layers.

6. A method for manufacturing a semiconductor device, characterized in that, Comprising: Forming fins on a substrate, wherein the fins span a first region and a second region of the substrate, and the second region is located between adjacent first regions; Forming a single diffusion isolation structure in the second region of the substrate, wherein the extending direction of the single diffusion isolation structure is perpendicular to the extending direction of the fins, and the single diffusion isolation structure spans the fins; Forming heavily doped regions in the fins located in the second region; And Forming a gate structure and a capacitor gate structure on the fins in the first region and the second region of the substrate respectively, wherein the capacitor gate structure is disposed on the single diffusion isolation structure.

7. The method of manufacturing a semiconductor device according to claim 6, wherein after forming the gate structure and the capacitor gate structure, further comprising: Forming source / drain regions and dummy source / drain regions in the fins in the first region and the second region of the substrate respectively; And Forming a first contact plug and a second contact plug on the capacitor gate structure and the dummy source / drain regions respectively.

8. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the single diffusion isolation structure comprises: Etching the fins and the substrate located in the second region to form a groove in the substrate; And Disposing a dielectric layer in the groove, wherein the top surface of the single diffusion isolation structure is lower than the top surface of the fins.

9. The method of manufacturing a semiconductor device according to claim 6, wherein the step of forming the gate structure and the capacitor gate structure comprises: Forming a dielectric layer on the substrate; Forming a gate material layer on the dielectric layer; And Remove the portion of the dielectric layer and the gate material layer to form the gate structure including a gate dielectric layer and a gate in the first region of the substrate, and form the capacitor gate structure including a capacitor dielectric layer and a capacitor gate in the second region of the substrate.

10. The method of manufacturing a semiconductor device according to claim 6, wherein an ion implantation process and a rapid thermal process are performed to form the heavily doped region in the fin located in the second region.

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