Semiconductor structure, semiconductor device and preparation method

Abstract

The invention provides a semiconductor structure, a semiconductor device and a preparation method. Comprising the steps of providing a substrate and manufacturing a functional layer according to the substrate; manufacturing a virtual gate on the surface of the functional layer; manufacturing a source electrode and a drain electrode; the virtual gate comprises a first virtual gate and a second virtual gate, and the horizontal section size of the first virtual gate is larger than that of the second virtual gate; forming an etching stop layer on the first virtual gate and the second virtual gate; manufacturing an interlayer dielectric layer; performing first chemical mechanical polishing on the interlayer dielectric layer to expose the etching stop layer; performing second chemical mechanical polishing on the etching stop layer to expose the second virtual gate; performing selective epitaxy on the second virtual gate, and forming a compensation layer on the second virtual gate; and third chemical mechanical polishing is performed on the compensation layer and the etching stop layer on the surface of the first virtual gate, so that the etching stop layer on the compensation layer and the first virtual gate is removed at the same time, and the first virtual gate and the second virtual gate are exposed. The thicknesses of the interlayer dielectric layer and the etching stop layer around the first virtual gate and the second virtual gate prepared by the preparation method of the semiconductor structure are similar.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and particularly relates to a semiconductor structure, a semiconductor device and a preparation method thereof. Background Art

[0002] As device sizes continue to shrink, HKMG (i.e., high-K metal gate) technology is widely used in the fabrication of transistors with dimensions below 45 nm.

[0003] As Figures 1 to 4 shown, a conventional process for fabricating a transistor is as follows: an isolation structure 12a is formed in a substrate 11a; a PMOS region (also the second doped region 14a) and an NMOS region (also the first doped region 13a) separated by the isolation structure 12a are fabricated in the substrate 11a, thereby forming a functional layer 1a; a dummy gate 2a (the dummy gate 2a includes a large-sized first dummy gate 21a and a small-sized second dummy gate 22a) is fabricated on the surface of the functional layer 1a; a source electrode 15a and a drain electrode 16a are formed in the functional layer 1a; an etch stop layer 3a is fabricated on the surface of the dummy gate 2a; an interlayer dielectric layer 4a (ILD) is formed between the surface of the etch stop layer 3a and the dummy gate 2a (the first dummy gate 21a, the second dummy gate 22a). For the completed interlayer dielectric layer 4a, please refer to Figure 1 ; chemical mechanical polishing is performed on the interlayer dielectric layer 4a to expose the etch stop layer 3a (for the polished interlayer dielectric layer 4a, please refer to Figure 2 ); chemical mechanical polishing is performed on the etch stop layer 3a to expose the dummy gate 2a. This process is called the ILD0 process; the dummy gate 2a is removed to form a gate trench (not shown); a high-K dielectric layer (not shown) and a metal gate (not shown) are fabricated in the gate trench to form a high-K metal gate (not shown).

[0004] However, the existing process for fabricating a transistor has the following defects: the sizes of the dummy gates 2a on the surface of the functional layer 1a (here, the size refers to the horizontal cross-sectional area of the dummy gate 2a) are inconsistent. When chemical mechanical polishing is used to polish the etch stop layer 3a, the area of the etch stop layer 3a on the surface of the small-sized second dummy gate 22a is smaller, and the area of the etch stop layer 3a on the surface of the large-sized first dummy gate 21a is larger. This will cause the etch stop layer 3a on the surface of the small-sized second dummy gate 22a to be removed faster (i.e., its polishing rate is faster) when the etch stop layer 3a is removed by chemical mechanical polishing, while the etch stop layer 3a on the surface of the large-sized first dummy gate 21a will be removed slower (i.e., its polishing efficiency is slower) (please refer to Figure 3). After the etch stop layer 3a on the surface of the small-sized second dummy gate 22a is removed, the chemical mechanical polishing process continues to remove the etch stop layer 3a on the surface of the large-sized first dummy gate 21a. This will cause the chemical mechanical polishing process to simultaneously polish the small-sized second dummy gate 22a, the interlayer dielectric layer 3a around the small-sized second dummy gate 22a, the interlayer dielectric layer 3a between the large-sized first dummy gate 21a and the small-sized second dummy gate 22a, and the etch stop layer surrounding the small-sized second dummy gate 22a (when the etch stop layer on the top of the second dummy gate 22a is removed, the remaining etch stop layer surrounding the second dummy gate 22a becomes the gate sidewall, and the height of the gate sidewall will affect the height of the finally formed gate), which will result in a reduction in the thickness of the interlayer dielectric layer 4a around the small-sized second dummy gate 22a, the interlayer dielectric layer 4a between the small-sized second dummy gate 22a and the large-sized first dummy gate 21a, and a reduction in the height of the etch stop layer 3a on the side of the small-sized second dummy gate 22a. The thickness of the interlayer dielectric layer 4a on the top of the large-sized first dummy gate 21a decreases more slowly (since the thickness of the etch stop layer 3a on the top of the large-sized first 21a dummy gate decreases more slowly, it will cause the thickness of the interlayer dielectric layer 4a around the large-sized first dummy gate 21a and the height of the etch stop layer 3a on the side of the large-sized first dummy gate 21a to be protected by the large-sized first dummy gate 21a and the etch stop layer 3a on the top of the large-sized first dummy gate 21a). Finally, when the etch stop layer 3a on the top of the large-sized first dummy gate 21a is removed, it will cause a height difference between the etch stop layer 3a on the side of the large-sized first dummy gate 21a, the interlayer dielectric layer 4a and the etch stop layer 3a on the side of the small-sized second dummy gate 22a, and the interlayer dielectric layer 4a (please refer to Figure 4 ). This height difference will cause the depth of the gate grooves formed after removing the large-sized first dummy gate and the small-sized second dummy gate to be inconsistent during the subsequent high-k metal gate preparation process. As a result, when forming the high-k metal gate in the gate grooves, the heights of the obtained high-k metal gates will be inconsistent (this height difference between the high-k metal gates may even exceed 200 angstroms), which is not conducive to the performance of the device. SUMMARY OF THE INVENTION

[0005] One object of the present invention is to provide a method for fabricating a semiconductor structure to solve the technical problem of gate height difference in the ILD0 process.

[0006] Another object of the present invention is to provide a method for fabricating a semiconductor device, which fabricates a gate structure based on the above semiconductor structure fabrication technology.

[0007] On the one hand, a method for fabricating a semiconductor structure is provided. The method for fabricating the semiconductor structure includes: Providing a substrate and fabricating a functional layer according to the substrate; Fabricate dummy gates on the surface of the functional layer; wherein, the dummy gates include a first dummy gate and a second dummy gate, and the horizontal cross-sectional dimension of the first dummy gate is larger than that of the second dummy gate; Fabricate a source electrode and a drain electrode in the functional layer; Form an etch stop layer on the first dummy gate and the second dummy gate; Fabricate an interlayer dielectric layer; Perform a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer; Perform a second chemical mechanical polishing on the etch stop layer to expose the second dummy gate; Perform selective epitaxy on the second dummy gate to form a compensation layer on the second dummy gate; Perform a third chemical mechanical polishing on the compensation layer and the etch stop layer on the surface of the first dummy gate, so that the compensation layer and the etch stop layer on the first dummy gate are removed simultaneously to expose the first dummy gate and the second dummy gate.

[0008] Optionally, the thickness of the compensation layer is 1.1 to 1.3 times the thickness of the etch stop layer.

[0009] The thickness of the compensation layer is 50 Å to 120 Å.

[0010] Optionally, the compensation layer includes a Si layer.

[0011] Optionally, when performing the third chemical mechanical polishing process, the polishing efficiency of the compensation layer is higher than that of the interlayer dielectric layer, and the polishing efficiency of the etch stop layer on the surface of the first dummy gate is higher than that of the interlayer dielectric layer.

[0012] Optionally, when performing the third chemical mechanical polishing, the polishing rate ratio of the etch stop layer to the compensation layer is ; the polishing rate ratio of the etch stop layer to the interlayer dielectric layer is greater than ; the polishing rate ratio of the compensation layer to the interlayer dielectric layer is greater than ; Wherein, The value range of is 0.5 to 1.5, The value range of is 5 to 7, The value range of is 5 to 7.

[0013] Optionally, the steps of performing the third chemical mechanical polishing are as follows: Use an acidic polishing liquid to polish the etch stop layer on the surface of the first dummy gate, the compensation layer, and the interlayer dielectric layer until the first dummy gate is exposed.

[0014] Optionally, the acidic polishing liquid includes an oxidant, a chelating agent, a surfactant, polishing particles, and a pH regulator; Among them, the oxidant includes hydrogen peroxide; the chelating agent includes citric acid; the surfactant includes sodium dodecyl sulfate; the abrasive particles include silica or cerium oxide.

[0015] Optionally, in the acidic abrasive liquid, the proportion of the oxidant is 1 wt% - 3 wt%, the proportion of the chelating agent is 0.5 wt% - 1.5 wt%, the proportion of the surfactant is 0.1 wt% - 0.5 wt%, the proportion of the abrasive particles is 5 wt% - 10 wt%, and the proportion of the pH regulator is determined according to the pH value of the abrasive liquid.

[0016] Optionally, the pH value of the acidic abrasive liquid is 4 - 6.

[0017] In a second aspect, a semiconductor structure is provided, and the semiconductor structure is prepared by the method described in any one of the above.

[0018] In a third aspect, a method for manufacturing a semiconductor device is provided, and the method for manufacturing the semiconductor device includes: Providing a substrate and fabricating a functional layer according to the substrate; Fabricating a dummy gate on the surface of the functional layer; wherein, the dummy gate includes a first dummy gate and a second dummy gate, and the horizontal cross-sectional dimension of the first dummy gate is larger than that of the second dummy gate; Fabricating a source electrode and a drain electrode in the functional layer; Forming an etch stop layer on the first dummy gate and the second dummy gate; Fabricating an interlayer dielectric layer; Performing a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer; Performing a second chemical mechanical polishing on the etch stop layer to expose the second dummy gate; Performing selective epitaxy on the second dummy gate to form a compensation layer on the second dummy gate; Performing a third chemical mechanical polishing on the compensation layer and the etch stop layer on the surface of the first dummy gate, so that the etch stop layer on the compensation layer and the first dummy gate is removed simultaneously to expose the first dummy gate and the second dummy gate; Removing the first dummy gate and the second dummy gate to obtain a first gate groove and a second gate groove; Fabricating a gate metal layer in the first gate groove and the second gate groove; Performing a fourth chemical mechanical polishing on the gate metal layer to form a first gate in the first gate groove and a second gate in the second gate groove.

[0019] In a fourth aspect, a semiconductor device is provided, and the semiconductor device is prepared by the method described above.

[0020] The unexpected technical effect achieved by the technical solution provided by the present invention is as follows: The present invention provides a method for manufacturing a semiconductor structure. After the second dummy gate is exposed by using the second chemical mechanical polishing, a selective epitaxial process is performed on the second dummy gate. After a compensation layer is formed on the surface of the second dummy gate, the third chemical mechanical polishing is performed again. The unexpected technical effect is that the second dummy gate is protected by the compensation layer to prevent the second dummy gate and the interlayer dielectric layer around the second dummy gate from being polished during the third chemical mechanical polishing, thereby protecting the height of the interlayer dielectric layer around the second dummy gate. At the same time, when performing the third chemical mechanical polishing process, by optimizing the process parameters of the third chemical mechanical polishing, different polishing efficiencies are achieved for the compensation layer, the interlayer dielectric layer, and the etch stop layer. Among them, the polishing efficiencies of the compensation layer and the etch stop layer are higher than that of the interlayer dielectric layer, so as to ensure that after the compensation layer and the etch stop layer on the surface of the first dummy gate are removed by the third chemical mechanical polishing process, the heights of the etch stop layers surrounding the first dummy gate and the second dummy gate are similar. It can also ensure that when the compensation layer and the etch stop layer on the surface of the first dummy gate are removed by the third chemical mechanical polishing process, the thickness reduction rate of the interlayer dielectric layer between the first dummy gate and the second dummy gate is slower than that of the compensation layer and the etch stop layer on the surface of the first dummy gate, which is beneficial to ensuring the overall thickness of the interlayer dielectric layer, that is, ensuring that the surface of the interlayer dielectric layer is close to a plane, and the thickness of the interlayer dielectric layer is similar to the height of the etch stop layer surrounding the dummy gate.

[0021] After removing the dummy gate subsequently to form gate trenches (the first gate trench corresponding to the first dummy gate and the second gate trench corresponding to the second dummy gate), generally, a gate metal layer is first fabricated in the gate trenches, and then the gate metal layer is planarized to form a metal gate in the gate trenches. The interlayer dielectric layer and the etch stop layer with similar heights (that is, the gate sidewalls surrounding the first gate trench, the gate sidewalls surrounding the second gate trench, and the height of the interlayer dielectric layer are similar) are beneficial to ensuring that after the gate metal layer is planarized, the heights of the metal gates formed in the gate trenches are similar, and avoiding the problem of different heights of the metal gates when the gate metal layer is planarized and polished. Description of the Drawings

[0022] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are some embodiments of the present invention. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.

[0023] Figure 1 It is a schematic structural diagram of a semiconductor device during the manufacturing process provided by the related art.

[0024] Figure 2 A structural schematic diagram of a semiconductor device in the manufacturing process provided for the related art.

[0025] Figure 3 A structural schematic diagram of a semiconductor device in the manufacturing process provided for the related art.

[0026] Figure 4 A structural schematic diagram of a semiconductor device in the manufacturing process provided for the related art.

[0027] Figure 5 A flowchart of a method for manufacturing a semiconductor structure provided by the present invention.

[0028] Figure 6 A flowchart of a method for manufacturing a semiconductor device provided by the present invention.

[0029] Figure 7 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0030] Figure 8 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0031] Figure 9 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0032] Figure 10 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0033] Figure 11 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0034] Figure 12 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0035] Figure 13 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0036] Figure 14 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0037] Figure 15 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0038] Figure 16 A structural schematic diagram of a semiconductor device in the manufacturing process provided by the present invention.

[0039] Figure 17 Schematic diagram of the structure of a semiconductor device provided by the present invention during the manufacturing process.

[0040] Figure 18 Schematic diagram of the structure of a semiconductor device provided by the present invention during the manufacturing process.

[0041] Figures 1 to 4 The reference numerals in the figure are as follows: 1a - functional layer; 11a: substrate; 12a: isolation structure; 13a: first doped region; 14a: second doped region; 15a: source electrode; 16a: drain electrode; 2a: dummy gate; 21a: first dummy gate; 22a: second dummy gate; 3a: etch stop layer; 4a: interlayer dielectric layer; Figures 7 to 18 The reference numerals in the figure are as follows: 1: functional layer; 11: substrate; 12: isolation structure; 13: first doped region; 14: second doped region; 15: source electrode; 16: drain electrode; 2: dummy gate; 21: first dummy gate; 22: second dummy gate; 3: etch stop layer; 4: interlayer dielectric layer; 5: compensation layer; 61: first gate groove; 62: second gate groove; 63: high - K dielectric layer; 64: gate metal layer; 65: first metal gate; 66: second metal gate. Detailed implementation manners

[0042] To make the objectives, technical solutions and advantages of the present invention clearer, the technical solutions in the present invention will be clearly and completely described below with reference to the accompanying drawings in the present invention. Obviously, the described embodiments are part of the embodiments of the present invention, rather than all of the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments in the present invention without making creative efforts shall fall within the protection scope of the present invention.

[0043] Figure 5 Flowchart of a method for preparing a semiconductor structure provided by the present invention. Refer to Figure 5 The method steps include: S101. Provide a substrate 11 and fabricate a functional layer 1 based on the substrate 11.

[0044] Refer to Figure 7 Figure 7 Schematic diagram of the structure of a semiconductor device provided by the present invention during the manufacturing process, in which the structure of a functional layer 1 is specifically shown. ​

[0045] In this embodiment, the functional layer 1 includes a substrate 11, an isolation structure 12 formed on the substrate, a first doped region 13, and a second doped region 14 (the first doped region 13 and the second doped region 14 are also referred to as active regions).

[0046] In this embodiment, the substrate 11 may be a Si substrate.

[0047] In other embodiments, the substrate may be composed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate may be a layered substrate including, such as Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type and thickness of the substrate should not limit the protection scope of the present disclosure.

[0048] In this embodiment, the isolation structure 12 may be a shallow trench isolation (STI) structure, that is, after forming a shallow trench in the substrate 11, an oxide layer is filled in the shallow trench to form the isolation structure 12.

[0049] In this embodiment, the functional layer 1 may include a PMOS region and an NMOS region. Among them, the NMOS region is the first doped region 13, and the PMOS region is the second doped region 14.

[0050] In another embodiment, the functional layer 1 may include a PMOS region.

[0051] In other embodiments, the functional layer 1 may include an NMOS region.

[0052] It should be noted that the PMOS region is a region formed after P-type doping in the substrate, and the NMOS region is a region formed after N-type doping in the substrate.

[0053] In this embodiment, the PMOS region refers to a region doped with trivalent impurity elements. For example, any one of elements such as boron (B), gallium (Ga), etc. may be doped.

[0054] In this embodiment, the NMOS region refers to a region doped with pentavalent impurity elements. For example, any one of elements such as phosphorus (P), arsenic (As), etc. may be doped.

[0055] Of course, the above structures of the functional layer are only examples provided by the present invention. In actual application, the functional layer should include but not be limited to the structures in the above examples.

[0056] S102. Fabricate a dummy gate 2 on the surface of the functional layer 1; wherein, the dummy gate 2 includes a first dummy gate 21 and a second dummy gate 22, and the horizontal cross-sectional dimension of the first dummy gate 21 is larger than that of the second dummy gate 22.

[0057] In this embodiment, the dummy gate can be obtained by growing a polysilicon layer and performing an etching process on the polysilicon layer.

[0058] See Figure 8 , Figure 8 which is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein the first dummy gate 21 and the second dummy gate 22 are specifically shown.

[0059] S103. Fabricate a source electrode and a drain electrode in the functional layer.

[0060] In one example, step 103 includes: Step 1. Fabricate a source electrode 15 and a drain electrode 16 in the first doping region 13.

[0061] In one example, if the first doping region 13 is a PMOS region, then step 1 includes: Inject a trivalent impurity element into the first doping region to form a source electrode 15 and a drain electrode 16 in the first doping region 13.

[0062] In another example, if the first doping region 13 is an NMOS region, then step 1 includes: Inject a pentavalent impurity element into the first doping region 13 to form a source electrode 15 and a drain electrode 16 in the first doping region 13.

[0063] Step 2. Fabricate a source electrode 15 and a drain electrode 16 in the second doping region 14.

[0064] In one example, if the second doping region 14 is a PMOS region, then step 2 includes: Inject a trivalent impurity element into the second doping region 14 to form a source electrode 15 and a drain electrode 16 in the second doping region 14.

[0065] In one example, if the second doping region 14 is an NMOS region, then step 2 includes: Inject a pentavalent impurity element into the second doping region 14 to form a source electrode 15 and a drain electrode 16 in the second doping region.

[0066] See Figure 9 , Figure 9 which is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein the source electrode 15 and the drain electrode 16 are specifically shown.

[0067] S104. Form an etch stop layer 3 on the first dummy gate 21 and the second dummy gate 22.

[0068] In one example, step S104 includes: Fabricate silicon nitride as the etch stop layer 3 on the surfaces and sides of the first dummy gate 21 and the second dummy gate 22. Of course, materials such as silicon carbonitride, silicon oxynitride, titanium nitride, tantalum nitride, high-k metal oxides (such as aluminum oxide, hafnium oxide), etc. can also be fabricated as the etch stop layer.

[0069] See Figure 10 , Figure 10 FIG.

[0070] S105. Fabricate an interlayer dielectric layer 4.

[0071] In one example, step S105 includes: See Figure 11 , Figure 11 FIG.

[0072] S106. Perform a first chemical mechanical polishing on the interlayer dielectric layer 4 to expose the etch stop layer 3.

[0073] In one example, step S106 includes: First step: Use a polishing slurry with SiO2 as the polishing particles to polish the interlayer dielectric layer 4, grind off most of the interlayer dielectric layer 4, and retain a certain thickness of the interlayer dielectric layer 4 above the etch stop layer 3.

[0074] Second step: Use a polishing slurry with CeO2 as the polishing particles to polish the interlayer dielectric layer 4 again, and stop polishing on the surface of the etch stop layer 3.

[0075] Of course, the above is only an example of the polishing slurry for the first chemical mechanical polishing provided by the present invention. The first chemical mechanical polishing can also use polishing slurries formed by other polishing particles. The above examples are not used to limit the present invention.

[0076] See Figure 12 , Figure 12 FIG.

[0077] S107. Perform a second chemical mechanical polishing on the etch stop layer 3 to expose the second dummy gate 22.

[0078] In one example, step S107 includes: Using a polishing liquid with SiO2 as the polishing particles, remove the etch stop layer 3 on the surface of the second dummy gate 22 to expose the second dummy gate 22.

[0079] Refer to Figure 13 , Figure 13 which is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein the structures of the etch stop layer 3 and the interlayer dielectric layer 4 after performing the second chemical mechanical polishing are specifically shown.

[0080] It should be noted that after the etch stop layer 3 on the top of the second dummy gate 22 is ground away, a gate sidewall is formed around the second dummy gate 22.

[0081] S108. Perform selective epitaxy on the second dummy gate 22 to form a compensation layer 5 on the second dummy gate 22.

[0082] Refer to Figure 14 , Figure 14 which is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein the structure of the compensation layer 5 is specifically shown.

[0083] In this embodiment, the compensation layer 5 may include a Si layer.

[0084] Of course, the actual function of the compensation layer is to make up for the difference in etching efficiency caused by the different areas of the etch stop layer on the surface of the first dummy gate and the etch stop layer on the surface of the second dummy gate. Therefore, as long as the material used for the compensation layer can make the polishing efficiency of the compensation layer similar to that of the etch stop layer on the surface of the first dummy gate.

[0085] When the material of the second dummy gate 22 is polysilicon, polysilicon can be selectively epitaxially grown to form the compensation layer 5, and specifically, chemical vapor deposition (CVD) or physical vapor deposition (PVD) processes can be used for epitaxy; for example, when using chemical vapor deposition (CVD) for epitaxy, silane (SiH4) or dichlorosilane (SiH2Cl2) is used to deposit polysilicon under low pressure and high temperature conditions.

[0086] In this embodiment, the thickness of the compensation layer is 1.1 to 1.3 times the thickness of the etch stop layer.

[0087] In one example, the thickness of the compensation layer is 1.2 times the thickness of the etch stop layer.

[0088] In this embodiment, the thickness of the compensation layer 5 is 50 to 120 angstroms.

[0089] Exemplarily, the thickness of the compensation layer 5 is 60 angstroms.

[0090] It should be noted that the thickness of the compensation layer 5 can be slightly thicker than the thickness of the etch stop layer 3 on the surface of the first dummy gate 21. For example, it is slightly thicker than the thickness of the etch stop layer 3 on the surface of the first dummy gate 21 by 20 angstroms.

[0091] In this embodiment, the thickness of the etch stop layer 3 is 30 angstroms to 100 angstroms.

[0092] S109. Perform a third chemical mechanical polishing on the compensation layer 5 and the etch stop layer 3 on the surface of the first dummy gate 21, so that the compensation layer 5 and the etch stop layer 3 on the first dummy gate 21 are removed simultaneously, exposing the first dummy gate 21 and the second dummy gate 22.

[0093] Among them, when performing the third chemical mechanical polishing process, the polishing efficiency of the compensation layer 5 is higher than that of the interlayer dielectric layer 4, and the polishing efficiency of the etch stop layer 3 on the surface of the first dummy gate 21 is higher than that of the interlayer dielectric layer 4.

[0094] In this embodiment, when performing the third chemical mechanical polishing, the polishing rate ratio of the etch stop layer 3 to the compensation layer 5 is ; the polishing rate ratio of the etch stop layer 3 to the interlayer dielectric layer 4 is greater than ; the polishing rate ratio of the compensation layer 5 to the interlayer dielectric layer 4 is greater than ; Among them, The value range of is 0.5 to 1.5, The value range of is 5 to 7, The value range of is 5 to 7.

[0095] Exemplarily, is 1, is 6, is 6.

[0096] In this embodiment, by adopting the above-mentioned ratio of polishing rates, it can be ensured that the thickness of the interlayer dielectric layer on the surface of the final first dummy gate, the thickness of the interlayer dielectric layer between the first dummy gate and the second dummy gate, and the thickness of the interlayer dielectric layer around the second dummy gate are similar.

[0097] Exemplarily, the average area ratio of the first dummy gate 21 to the second dummy gate 22 is , the thickness of the etch stop layer 3 is denoted as , then the thickness of the compensation layer , K is a correction coefficient. When the grinding rate of the compensation layer is the same as that of the etch stop layer, K = 1. When the grinding rate of the compensation layer is greater than that of the etch stop layer, K is greater than 1, and vice versa when it is less than 1. Generally, the grinding rates of the compensation layer and the etch stop layer are approximately the same, so K should be taken as 1. When the grinding rates are different, a separate material grinding experiment can be conducted to determine the value of K; Exemplarily, , , then the thickness of the compensation layer is calculated .

[0098] In one example, step S109 includes: Grind the etch stop layer 3, compensation layer 5, and interlayer dielectric layer 4 on the surface of the first dummy gate 21 with an acidic grinding liquid until the first dummy gate 21 is exposed.

[0099] In this embodiment, the pH value of the acidic grinding liquid is 4 - 6.

[0100] Exemplarily, the pH value of the acidic grinding liquid is 5.

[0101] In this embodiment, the acidic grinding liquid includes an oxidant, a chelating agent, a surfactant, grinding particles, and a pH regulator; wherein, the oxidant includes hydrogen peroxide; the chelating agent includes citric acid; the surfactant includes sodium dodecyl sulfate; the grinding particles include silicon dioxide or cerium oxide.

[0102] In this embodiment, in the acidic grinding liquid, the proportion of the oxidant is 1wt% - 3wt%, the proportion of the chelating agent is 0.5wt% - 1.5wt%, the proportion of the surfactant is 0.1wt% - 0.5wt%, the proportion of the grinding particles is 5wt% - 10wt%, the remaining component is water, and the proportion of the pH regulator is determined according to the pH value of the grinding liquid.

[0103] Exemplarily, in the acidic grinding liquid, the proportion of the oxidant is 1.5wt%, the proportion of the chelating agent is 1wt%, the proportion of the surfactant is 0.3wt%, the proportion of the grinding particles is 7.5wt%, the proportion of the pH regulator is determined according to the pH value of the grinding liquid, such as the proportion of the pH regulator is 2wt%.

[0104] The above proportions are only taken as an example, and during the actual implementation process, the ratio can be adjusted according to needs.

[0105] In this embodiment, the oxidant functions to oxidize the surfaces of the Si layer (compensation layer), SiN layer (etch stop layer), and SiO2 layer (interlayer dielectric layer), promoting the material removal efficiency during the chemical mechanical polishing (CMP) process. The chelating agent synergistically acts with the oxidant to chelate metal ions, prevent particle agglomeration, and regulate the surface reaction rate. The surfactant is used to reduce the surface tension, improve the wettability and dispersibility of the polishing liquid, and ensure uniform polishing. The abrasive particles provide mechanical polishing action and synergistically work with the chemical components to achieve efficient material removal. The pH regulator is used to optimize the activities of the oxidant and chelating agent to ensure the stability of the polishing liquid.

[0106] In this embodiment, by adjusting the ratio of the oxidant to the chelating agent, the surface oxidation rates of the SiN layer (etch stop layer) and the Si layer (compensation layer) are made similar, which is beneficial to ensuring that the polishing rates of the SiN layer (etch stop layer) and the Si layer (compensation layer) are similar. The SiO2 layer (interlayer dielectric layer) has a relatively low polishing efficiency under weakly acidic conditions, while the SiN layer (etch stop layer) has a relatively high polishing efficiency under the action of the oxidant and chelating agent, so that the polishing efficiency ratio of the SiN layer (etch stop layer) to the SiO2 layer (interlayer dielectric layer) is greater than 5. The Si layer (compensation layer) forms an easily removable oxide under the action of the oxidant, while the SiO2 layer (interlayer dielectric layer) has a relatively low polishing efficiency under the same conditions, so that the polishing efficiency ratio of the Si layer (compensation layer) to the SiO2 layer (interlayer dielectric layer) is greater than 5.

[0107] See Figure 15 , Figure 15 is a schematic structural diagram of a semiconductor device during the manufacturing process provided by the present invention, in which the structure after the third chemical mechanical polishing is specifically shown. Using the semiconductor structure preparation method provided by the present invention, the finally obtained semiconductor structure is as Figure 15 shown. In the finally obtained semiconductor structure, the heights of the first dummy gate 21, the second dummy gate 22, the interlayer dielectric layer 4 around the first dummy gate 21, the etch stop layer 3 around the first dummy gate 21, the interlayer dielectric layer 4 around the second dummy gate 22, and the etch stop layer 3 around the second dummy gate 22 are similar.

[0108] Figure 6 is a flowchart of a method for manufacturing a semiconductor device provided by the present invention. See Figure 6 , the method steps include: S201. Provide a substrate and fabricate a functional layer according to the substrate.

[0109] In one example, step S201 includes: Step 1. Provide a substrate 11.

[0110] For the material of the substrate, please refer to step S101.

[0111] Step 2: Form an isolation structure 12 on the substrate 11.

[0112] In one example, Step 2 includes: First step: Etch the substrate 11 to form a shallow trench in the substrate.

[0113] Second step: Form an insulating layer in the shallow trench.

[0114] Wherein, the insulating layer can be a SiO2 layer.

[0115] Third step: Perform chemical mechanical polishing on the insulating layer to planarize it and form the isolation structure 12.

[0116] Step 3: Perform a first ion implantation on the substrate 11 to form a first doped region 13 in the substrate.

[0117] Wherein, if the first doped region is a PMOS region, the element implanted by the first ion implantation can be a trivalent impurity element, such as any one of boron (B), gallium (Ga), etc.

[0118] If the first doped region is an NMOS region, the element implanted by the first ion implantation can be a pentavalent impurity element, for example, any one of phosphorus (P), arsenic (As), etc. can be doped.

[0119] Step 4: Perform a second ion implantation on the substrate 11 to form a second doped region 14 in the substrate; wherein, the first doped region 13 and the second doped region 14 are separated by the isolation structure 12.

[0120] Wherein, if the second doped region is a PMOS region, the element implanted by the first ion implantation can be a trivalent impurity element, such as any one of boron (B), gallium (Ga), etc.

[0121] If the second doped region is an NMOS region, the element implanted by the first ion implantation can be a pentavalent impurity element, for example, any one of phosphorus (P), arsenic (As), etc. can be doped.

[0122] S202: Fabricate a dummy gate 2 on the surface of the doped region; wherein, the dummy gate 2 includes a first dummy gate 21 and a second dummy gate 22, and the horizontal cross-sectional dimension of the first dummy gate 21 is larger than that of the second dummy gate 22.

[0123] Refer to Step S102.

[0124] S203: Fabricate a source electrode and a drain electrode in the functional layer.

[0125] Refer to Step S103.

[0126] S204. Form an etch stop layer 3 on the first dummy gate 21 and the second dummy gate 22.

[0127] Refer to step S104.

[0128] S205. Fabricate an interlayer dielectric layer 4.

[0129] Refer to step S105.

[0130] S206. Perform a first chemical mechanical polishing on the interlayer dielectric layer 4 to expose the etch stop layer 3.

[0131] Refer to step S106.

[0132] S207. Perform a second chemical mechanical polishing on the etch stop layer 3 to expose the second dummy gate 22.

[0133] Refer to step S107.

[0134] S208. Perform selective epitaxy on the second dummy gate 22 to form a compensation layer 5 on the second dummy gate 22.

[0135] Refer to step S108.

[0136] S209. Perform a third chemical mechanical polishing on the compensation layer 5 and the etch stop layer 3 on the surface of the first dummy gate 21, so that the compensation layer and the etch stop layer on the first dummy gate are removed simultaneously to expose the first dummy gate 21 and the second dummy gate 22.

[0137] Refer to step S109.

[0138] S210. Remove the first dummy gate 21 and the second dummy gate 22 to obtain a first gate groove 61 and a second gate groove 62.

[0139] In one example, step S210 includes: Selectively remove the dummy gate made of polysilicon using anisotropic dry etching (such as reactive ion etching, RIE).

[0140] The etching gas used in dry etching usually includes a mixture of Cl2, HBr and O2. These gases have high selectivity for polysilicon and can avoid damaging the sidewall and the interlayer dielectric layer.

[0141] Refer to Figure 16 , Figure 16 which is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, where the first gate groove 61 and the second gate groove 62 are specifically shown.

[0142] S211. Fabricate a gate metal layer in the first gate groove 61 and the second gate groove 62.

[0143] In one example, step S211 includes: First step, deposit a high-K dielectric layer 63 in the first gate groove 61 and the second gate groove 62.

[0144] Among them, the high-K dielectric layer 63 can be an HfO2 layer.

[0145] The atomic layer deposition process can be used to prepare the high-K dielectric layer.

[0146] Second step, fabricate a gate metal layer 64 on the high-K dielectric layer 63 in the first gate groove 61 and the second gate groove 62 respectively.

[0147] Among them, the gate metal layer 64 can be formed of materials such as Al, TiN, TaN, etc.

[0148] Refer to Figure 17 , Figure 17 , which is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process. Among them, the gate metal layer 64 is specifically shown.

[0149] S212. Perform a fourth chemical mechanical polishing on the gate metal layer to form a first gate in the first gate groove and a second gate in the second gate groove.

[0150] Among them, perform chemical mechanical polishing on the gate metal layer 64, and retain the gate metal layer 64 located in the first gate groove 61 and the second gate groove 62 as the first metal gate 65 and the second metal gate 66.

[0151] In this embodiment, the first metal gate 65 and the high-K dielectric layer 63 form the first gate, and the second metal gate 66 and the high-K dielectric layer 63 form the second gate.

[0152] Refer to Figure 18 , Figure 18 , which is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, where the first metal gate 65 and the second metal gate 66 are specifically shown.

[0153] The present invention also provides a semiconductor device, and the semiconductor device can be formed by using the manufacturing method of the semiconductor structure or the manufacturing method of the semiconductor device as described above.

[0154] Finally, it should be noted that the unexpected technical effect of the technical solution provided by the present invention is: The present invention provides a method for manufacturing a semiconductor structure. After exposing a second dummy gate by using a second chemical mechanical polishing, a selective epitaxial process is performed on the second dummy gate. After a compensation layer is formed on the surface of the second dummy gate, a third chemical mechanical polishing is performed again. The unexpected technical effect is that the second dummy gate is protected by the compensation layer to avoid polishing the second dummy gate and the interlayer dielectric layer around the second dummy gate during the third chemical mechanical polishing, thereby protecting the height of the interlayer dielectric layer around the second dummy gate. At the same time, when performing the third chemical mechanical polishing process, by optimizing the process parameters of the third chemical mechanical polishing, the third chemical mechanical polishing process has different polishing efficiencies for the compensation layer, the interlayer dielectric layer, and the etch stop layer. Among them, the polishing efficiencies of the compensation layer and the etch stop layer are higher than that of the interlayer dielectric layer, so as to ensure that after removing the etch stop layer on the surface of the compensation layer and the first dummy gate by the third chemical mechanical polishing process, the heights of the etch stop layers surrounding the first dummy gate and the second dummy gate are similar, and it can also ensure that when removing the etch stop layer on the surface of the compensation layer and the first dummy gate by the third chemical mechanical polishing process, the thickness reduction rate of the interlayer dielectric layer between the first dummy gate and the second dummy gate is slower than that of the compensation layer and the etch stop layer on the surface of the first dummy gate, which is beneficial to ensuring the overall thickness of the interlayer dielectric layer, that is, ensuring that the surface of the interlayer dielectric layer is close to a plane, and the thickness of the interlayer dielectric layer is similar to the height of the etch stop layer surrounding the dummy gate.

[0155] After subsequently removing the dummy gate to form gate trenches (a first gate trench corresponding to the first dummy gate and a second gate trench corresponding to the second dummy gate), when manufacturing a metal gate in the gate trenches, the etch stop layers with similar heights (that is, the heights of the etch stop layers surrounding the first gate trench and the etch stop layers surrounding the second gate trench are similar) and the interlayer dielectric layers with similar thicknesses are beneficial to ensuring that the thicknesses of the metal gates formed in the gate trenches are the same or similar.

[0156] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention and are not intended to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those of ordinary skill in the art should understand that they can still modify the technical solutions described in the foregoing embodiments, or perform equivalent replacements for some of the technical features; and these modifications or replacements do not make the essence of the corresponding technical solutions deviate from the spirit and scope of the technical solutions of the embodiments of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that, The method for preparing the semiconductor structure includes: providing a substrate and fabricating a functional layer based on the substrate; fabricating dummy gates on the surface of the functional layer; wherein, the dummy gates include a first dummy gate and a second dummy gate, and the horizontal cross-sectional dimension of the first dummy gate is larger than that of the second dummy gate; fabricating a source electrode and a drain electrode in the functional layer; forming an etch stop layer on the first dummy gate and the second dummy gate; fabricating an interlayer dielectric layer; performing a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer; performing a second chemical mechanical polishing on the etch stop layer to expose the second dummy gate; performing selective epitaxy on the second dummy gate to form a compensation layer on the second dummy gate; performing a third chemical mechanical polishing on the compensation layer and the etch stop layer on the surface of the first dummy gate, such that the etch stop layers on the compensation layer and the first dummy gate are removed simultaneously, exposing the first dummy gate and the second dummy gate.

2. The method for preparing a semiconductor structure according to claim 1, wherein The thickness of the compensation layer is 1.1 to 1.3 times the thickness of the etch stop layer.

3. The method for manufacturing a semiconductor structure according to claim 1, wherein, The compensation layer includes a Si layer.

4. The method for manufacturing a semiconductor structure according to any one of claims 1 to 3, characterized in that, When performing the third chemical mechanical polishing, the polishing rate ratio of the etch stop layer to the compensation layer is ; the polishing rate ratio of the etch stop layer to the interlayer dielectric layer is greater than ; the polishing rate ratio of the compensation layer to the interlayer dielectric layer is greater than ; Among them, ranges from 0.5 to 1.5, ranges from 5 to 7, ranges from 5 to 7.

5. The method for manufacturing a semiconductor structure according to claim 4, wherein, The steps for performing the third chemical mechanical polishing are as follows: using an acidic polishing liquid to polish the etch stop layer on the surface of the first dummy gate, the compensation layer, and the interlayer dielectric layer until the first dummy gate is exposed.

6. The method for manufacturing a semiconductor structure according to claim 5, characterized in that, The acidic polishing liquid includes an oxidant, a chelating agent, a surfactant, polishing particles, and a pH regulator; wherein, the oxidant includes hydrogen peroxide; the chelating agent includes citric acid; the surfactant includes sodium dodecyl sulfate; the polishing particles include silicon dioxide or cerium oxide.

7. The method for manufacturing a semiconductor structure according to claim 6, wherein, In the acidic polishing liquid, the proportion of the oxidant is 1 wt% to 3 wt%, the proportion of the chelating agent is 0.5 wt% to 1.5 wt%, the proportion of the surfactant is 0.1 wt% to 0.5 wt%, the proportion of the polishing particles is 5 wt% to 10 wt%, and the proportion of the pH regulator is determined according to the pH value of the polishing liquid.

8. A semiconductor structure, characterized in that, The semiconductor structure is prepared by the method according to any one of claims 1 to 7.

9. A method for manufacturing a semiconductor device, characterized in that, The method for preparing the semiconductor device includes: providing a substrate and fabricating a functional layer based on the substrate; fabricating dummy gates on the surface of the functional layer; wherein, the dummy gates include a first dummy gate and a second dummy gate, and the horizontal cross-sectional dimension of the first dummy gate is larger than that of the second dummy gate; fabricating a source electrode and a drain electrode in the functional layer; forming an etch stop layer on the first dummy gate and the second dummy gate; fabricating an interlayer dielectric layer; performing a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer; performing a second chemical mechanical polishing on the etch stop layer to expose the second dummy gate; performing selective epitaxy on the second dummy gate to form a compensation layer on the second dummy gate; performing a third chemical mechanical polishing on the compensation layer and the etch stop layer on the surface of the first dummy gate, such that the etch stop layers on the compensation layer and the first dummy gate are removed simultaneously, exposing the first dummy gate and the second dummy gate; removing the first dummy gate and the second dummy gate to obtain a first gate groove and a second gate groove; fabricating a gate metal layer in the first gate groove and the second gate groove; performing a fourth chemical mechanical polishing on the gate metal layer to form a first gate in the first gate groove and a second gate in the second gate groove.

10. A semiconductor device, characterized in that, The semiconductor device is fabricated by the method as described in Claim 9.

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