Semiconductor structure, semiconductor device and manufacturing method

Abstract

The present invention provides a semiconductor structure, a semiconductor device, and a fabrication method. The method comprises: providing a substrate and fabricating a functional layer based on the substrate; fabricating a virtual gate on the surface of the functional layer; fabricating a source electrode and a drain electrode; the virtual gate comprising a first virtual gate and a second virtual gate, wherein the horizontal cross-sectional dimension of the first virtual gate is larger than that of the second virtual gate; forming an etch stop layer on the first and second virtual gates; fabricating an interlayer dielectric layer; performing a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer; performing a second chemical mechanical polishing on the etch stop layer to expose the second virtual gate; performing selective epitaxy on the second virtual gate to form a compensation layer on the second virtual gate; and performing a third chemical mechanical polishing on the compensation layer and the etch stop layer on the surface of the first virtual gate to simultaneously remove the compensation layer and the etch stop layer on the first virtual gate, exposing the first and second virtual gates. The fabrication method of the semiconductor structure results in interlayer dielectric layers and etch stop layers having similar thicknesses around the first and second virtual gates.

Description

Technical Field

[0001] The present invention belongs to the field of semiconductors, and in particular relates to a semiconductor structure, a semiconductor device and a preparation method thereof. Background Art

[0002] As device sizes continue to shrink, HKMG (also known as high-K metal gate) technology is widely used to prepare transistors with sizes below 45nm.

[0003] like Figures 1 to 4 As shown, a conventional transistor fabrication process is as follows: forming an isolation structure 12a within a substrate 11a; forming a PMOS region (also a second doped region 14a) and an NMOS region (also a first doped region 13a) separated by the isolation structure 12a within the substrate 11a, thereby forming a functional layer 1a; forming a dummy gate 2a on the surface of the functional layer 1a (the dummy gate 2a includes a large-sized first dummy gate 21a and a small-sized second dummy gate 22a); forming a source 15a and a drain 16a within the functional layer 1a; forming an etch stop layer 3a on the surface of the dummy gate 2a; and forming an interlayer dielectric layer 4a (ILD) between the surface of the etch stop layer 3a and the dummy gates 2a (the first dummy gate 21a and the second dummy gate 22a). The fabricated interlayer dielectric layer 4a is shown in FIG. Figure 1 ; Perform chemical mechanical polishing on the interlayer dielectric layer 4a to expose the etch stop layer 3a (see the interlayer dielectric layer 4a after polishing Figure 2 ); chemical mechanical polishing is performed on the etch stop layer 3a to expose the dummy gate 2a. This process is called ILD0 process; the dummy gate 2a is removed to form a gate groove (not shown); a high-K dielectric layer (not shown) and a metal gate (not shown) are formed in the gate groove to form a high-K metal gate (not shown).

[0004] However, the existing transistor manufacturing process has the following defects: the size of the virtual gate 2a on the surface of the functional layer 1a (the size here refers to the horizontal cross-sectional area of the virtual gate 2a) is inconsistent. When the chemical mechanical polishing process is used to polish the etch stop layer 3a, the area of the etch stop layer 3a on the surface of the small-sized second virtual gate 22a is smaller, and the area of the etch stop layer 3a on the surface of the large-sized first virtual gate 21a is larger. This will result in that when the chemical mechanical polishing process is used to remove the etch stop layer 3a, the etch stop layer 3a on the surface of the small-sized second virtual gate 22a will be removed faster (that is, its polishing rate will be faster), while the etch stop layer 3a on the surface of the large-sized first virtual gate 21a will be removed slower (that is, its polishing efficiency will be slower) (see Figure 3After the etch-stop layer 3a on the surface of the small-sized second dummy gate 22a is removed, the chemical mechanical polishing process continues to remove the etch-stop layer 3a on the surface of the large-sized first dummy gate 21a. This will cause the chemical mechanical polishing process to simultaneously polish the small-sized second dummy gate 22a, the interlayer dielectric layer 3a around the small-sized second dummy gate 22a, the interlayer dielectric layer 3a between the large-sized first dummy gate 21a and the small-sized second dummy gate 22a, and the etch-stop layer surrounding the small-sized second dummy gate 22a (after the etch-stop layer on the top of the second dummy gate 22a is removed, the remaining etch-stop layer surrounding the second dummy gate 22a becomes the gate sidewall, and the height of the gate sidewall will affect the height of the gate finally formed). This will cause the thickness of the interlayer dielectric layer 4a around the small-sized second dummy gate 22a, the interlayer dielectric layer 4a between the small-sized second dummy gate 22a and the large-sized first dummy gate 21a, and the height of the etch-stop layer 3a on the side of the small-sized second dummy gate 22a to be reduced. The thickness of the interlayer dielectric layer 4a on top of the large-sized first dummy gate 21a decreases more slowly (the thickness of the etch-stop layer 3a on top of the large-sized first dummy gate 21a decreases more slowly, which results in the thickness of the interlayer dielectric layer 4a around the large-sized first dummy gate 21a and the height of the etch-stop layer 3a on the side of the large-sized first dummy gate 21a being protected by the large-sized first dummy gate 21a and the etch-stop layer 3a on top of the large-sized first dummy gate 21a). Ultimately, after the etch-stop layer 3a on top of the large-sized first dummy gate 21a is removed, a height difference will exist between the etch-stop layer 3a and the interlayer dielectric layer 4a on the side of the large-sized first dummy gate 21a and the etch-stop layer 3a and the interlayer dielectric layer 4a on the side of the small-sized second dummy gate 22a (see Figure 4 This height difference will cause inconsistent depths of the gate grooves formed after removing the large-sized first dummy gate and the small-sized second dummy gate during the subsequent high-K metal gate fabrication process. Consequently, when a high-K metal gate is formed in the gate groove, the resulting high-K metal gates will have inconsistent heights (the height difference between the high-K metal gates may even exceed 200 angstroms), which will be detrimental to device performance. Summary of the Invention

[0005] One of the objectives of the present invention is to provide a method for manufacturing a semiconductor structure to solve the technical problem of gate height difference in the ILD0 process.

[0006] Another object of the present invention is to provide a method for preparing a semiconductor device, which prepares a gate structure based on the above-mentioned semiconductor structure preparation technology.

[0007] In one aspect, a method for preparing a semiconductor structure is provided, the method comprising:

[0008] Providing a substrate and manufacturing a functional layer based on the substrate;

[0009] Fabricate a virtual gate on the surface of the functional layer; wherein the virtual gate includes a first virtual gate and a second virtual gate, and the horizontal cross-sectional size of the first virtual gate is larger than the horizontal cross-sectional size of the second virtual gate;

[0010] forming a source electrode and a drain electrode in the functional layer;

[0011] forming an etch stop layer on the first dummy gate and the second dummy gate;

[0012] fabricating an interlayer dielectric layer;

[0013] performing a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer;

[0014] performing a second chemical mechanical polishing on the etch stop layer to expose a second dummy gate;

[0015] performing selective epitaxial growth on the second virtual gate to form a compensation layer on the second virtual gate;

[0016] A third chemical mechanical polishing is performed on the compensation layer and the etch stop layer on the surface of the first dummy gate, so that the compensation layer and the etch stop layer on the first dummy gate are removed simultaneously, exposing the first dummy gate and the second dummy gate.

[0017] Optionally, the thickness of the compensation layer is 1.1 to 1.3 times the thickness of the etch stop layer.

[0018] The thickness of the compensation layer is 50 angstroms to 120 angstroms.

[0019] Optionally, the compensation layer includes a Si layer.

[0020] Optionally, when performing the third chemical mechanical polishing process, the polishing efficiency of the compensation layer is higher than that of the interlayer dielectric layer, and the polishing efficiency of the etch stop layer on the surface of the first virtual gate is higher than that of the interlayer dielectric layer.

[0021] Optionally, when performing the third chemical mechanical polishing, the ratio of the polishing rate of the etch stop layer to the polishing rate of the compensation layer is The ratio of the polishing rate of the etch stop layer to the polishing rate of the interlayer dielectric layer is greater than The ratio of the grinding rate of the compensation layer to the grinding rate of the interlayer dielectric layer is greater than ;

[0022] in, The value range is 0.5~1.5, The value range is 5~7. The value range is 5~7.

[0023] Optionally, the steps of performing the third chemical mechanical polishing are as follows:

[0024] An acidic polishing liquid is used to polish the etching stop layer, the compensation layer, and the interlayer dielectric layer on the surface of the first virtual gate until the first virtual gate is exposed.

[0025] Optionally, the acidic polishing liquid comprises an oxidant, a chelating agent, a surfactant, abrasive particles and a pH adjuster;

[0026] Wherein, the oxidant includes hydrogen peroxide; the chelating agent includes citric acid; the surfactant includes sodium lauryl sulfate; and the abrasive particles include silicon dioxide or cerium oxide.

[0027] Optionally, in the acidic polishing liquid, the proportion of the oxidant is 1wt%~3wt%, the proportion of the chelating agent is 0.5wt%~1.5wt%, the proportion of the surfactant is 0.1wt%~0.5wt%, the proportion of the abrasive particles is 5wt%~10wt%, and the proportion of the pH regulator is determined according to the pH value of the polishing liquid.

[0028] Optionally, the pH value of the acidic polishing liquid is 4-6.

[0029] In a second aspect, a semiconductor structure is provided, wherein the semiconductor structure is prepared using any of the methods described above.

[0030] In a third aspect, a method for preparing a semiconductor device is provided, the method comprising:

[0031] Providing a substrate and manufacturing a functional layer based on the substrate;

[0032] Fabricate a virtual gate on the surface of the functional layer; wherein the virtual gate includes a first virtual gate and a second virtual gate, and the horizontal cross-sectional size of the first virtual gate is larger than the horizontal cross-sectional size of the second virtual gate;

[0033] forming a source electrode and a drain electrode in the functional layer;

[0034] forming an etch stop layer on the first dummy gate and the second dummy gate;

[0035] fabricating an interlayer dielectric layer;

[0036] performing a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer;

[0037] performing a second chemical mechanical polishing on the etch stop layer to expose a second dummy gate;

[0038] performing selective epitaxial growth on the second virtual gate to form a compensation layer on the second virtual gate;

[0039] performing a third chemical mechanical polishing on the compensation layer and the etch stop layer on the surface of the first dummy gate, so that the compensation layer and the etch stop layer on the first dummy gate are removed simultaneously, exposing the first dummy gate and the second dummy gate;

[0040] removing the first dummy gate and the second dummy gate to obtain a first gate groove and a second gate groove;

[0041] forming a gate metal layer in the first gate groove and the second gate groove;

[0042] A fourth chemical mechanical polishing is performed on the gate metal layer to form a first gate in the first gate groove and a second gate in the second gate groove.

[0043] In a fourth aspect, a semiconductor device is provided, wherein the semiconductor device is manufactured using the method described above.

[0044] The technical solution provided by the present invention has the following unexpected technical effects:

[0045] The present invention provides a method for fabricating a semiconductor structure, wherein, after a second chemical mechanical polishing process is performed to expose a second virtual gate, a selective epitaxial growth process is performed on the second virtual gate to form a compensation layer on the surface of the second virtual gate, and then a third chemical mechanical polishing process is performed. An unexpected technical effect is that the compensation layer protects the second virtual gate, preventing the second virtual gate and the interlayer dielectric layer surrounding the second virtual gate from being polished during the third chemical mechanical polishing process, thereby protecting the height of the interlayer dielectric layer surrounding the second virtual gate. Furthermore, during the third chemical polishing process, by optimizing the process parameters of the third chemical mechanical polishing process, the third chemical mechanical polishing process achieves different polishing efficiencies for the compensation layer, the interlayer dielectric layer, and the etch stop layer. Among them, the grinding efficiency of the compensation layer and the etch stop layer is higher than that of the interlayer dielectric layer, thereby ensuring that after the compensation layer and the etch stop layer on the surface of the first virtual gate are removed by the third chemical mechanical polishing process, the heights of the etch stop layers surrounding the first virtual gate and the second virtual gate are similar. It can also be ensured that when the compensation layer and the etch stop layer on the surface of the first virtual gate are removed by the third chemical mechanical polishing process, the thickness decrease rate of the interlayer dielectric layer between the first virtual gate and the second virtual gate is slower than that of the etch stop layer on the surface of the compensation layer and the first virtual gate, which is beneficial to ensuring the overall thickness of the interlayer dielectric layer, that is, ensuring that the surface of the interlayer dielectric layer is close to a plane, and the thickness of the interlayer dielectric layer is similar to the height of the etch stop layer surrounding the virtual gate.

[0046] After the dummy gates are subsequently removed to form gate recesses (a first gate recess corresponding to the first dummy gate and a second gate recess corresponding to the second dummy gate), a gate metal layer is generally first fabricated in the gate recesses, and then the gate metal layer is planarized to form a metal gate in the gate recesses. Having interlayer dielectric layers and etch-stop layers of similar height (i.e., the gate sidewalls surrounding the first gate recess, the gate sidewalls surrounding the second gate recess, and the interlayer dielectric layer) helps ensure that the metal gates formed in the gate recesses are of similar height after the gate metal layer is planarized, thus avoiding the problem of varying metal gate heights during planarization and polishing of the gate metal layer. BRIEF DESCRIPTION OF THE DRAWINGS

[0047] In order to more clearly illustrate the technical solutions in the present invention or the prior art, the following briefly introduces the drawings required for use in the embodiments or the description of the prior art. Obviously, the drawings described below are some embodiments of the present invention. For ordinary technicians in this field, other drawings can be obtained based on these drawings without paying any creative work.

[0048] Figure 1 A schematic structural diagram of a semiconductor device during the manufacturing process is provided for related technology.

[0049] Figure 2 A schematic structural diagram of a semiconductor device during the manufacturing process is provided for related technology.

[0050] Figure 3 A schematic structural diagram of a semiconductor device during the manufacturing process is provided for related technology.

[0051] Figure 4 A schematic structural diagram of a semiconductor device during the manufacturing process is provided for related technology.

[0052] Figure 5 This is a flow chart of a method for manufacturing a semiconductor structure provided by the present invention.

[0053] Figure 6 This is a flow chart of a method for manufacturing a semiconductor device provided by the present invention.

[0054] Figure 7 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0055] Figure 8 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0056] Figure 9 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0057] Figure 10 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0058] Figure 11 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0059] Figure 12 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0060] Figure 13 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0061] Figure 14 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0062] Figure 15 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0063] Figure 16 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0064] Figure 17 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0065] Figure 18 The present invention provides a schematic structural diagram of a semiconductor device during its manufacturing process.

[0066] Figures 1 to 4 The accompanying drawings are numerals as follows:

[0067] 1a-functional layer; 11a: substrate; 12a: isolation structure; 13a: first doped region; 14a: second doped region; 15a: source; 16a: drain;

[0068] 2a: virtual gate; 21a: first virtual gate; 22a: second virtual gate;

[0069] 3a: etch stop layer;

[0070] 4a: interlayer dielectric layer;

[0071] Figures 7 to 18 The accompanying drawings are numerals as follows:

[0072] 1: functional layer; 11: substrate; 12: isolation structure; 13: first doped region; 14: second doped region; 15: source; 16: drain;

[0073] 2: virtual gate; 21: first virtual gate; 22: second virtual gate;

[0074] 3: Etch stop layer;

[0075] 4: interlayer dielectric layer;

[0076] 5: compensation layer;

[0077] 61: first gate groove; 62: second gate groove; 63: high-K dielectric layer; 64: gate metal layer; 65: first metal gate; 66: second metal gate. DETAILED DESCRIPTION

[0078] To make the objectives, technical solutions, and advantages of the present invention more clear, the technical solutions of the present invention will be clearly and completely described below in conjunction with the accompanying drawings. Obviously, the embodiments described are only some embodiments of the present invention, not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by ordinary technicians in this field without making creative efforts shall fall within the scope of protection of the present invention.

[0079] Figure 5 This is a flow chart of a method for preparing a semiconductor structure provided by the present invention. Figure 5 , the method steps include:

[0080] S101 , providing a substrate 11 , and manufacturing a functional layer 1 based on the substrate 11 .

[0081] See also Figure 7 , Figure 7 This is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein the structure of a functional layer 1 is specifically shown.

[0082] In this embodiment, the functional layer 1 includes a substrate 11 , an isolation structure 12 formed on the substrate, a first doping region 13 and a second doping region 14 (the first doping region 13 and the second doping region 14 are also referred to as active regions).

[0083] In this embodiment, the substrate 11 may be a Si substrate.

[0084] In other embodiments, the substrate may be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. For example, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate may be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type and thickness of the substrate should not limit the scope of protection of the present disclosure.

[0085] In this embodiment, the isolation structure 12 may be a shallow trench isolation (STI) structure, that is, after a shallow trench is formed in the substrate 11 , an oxide layer is filled in the shallow trench to form the isolation structure 12 .

[0086] In this embodiment, the functional layer 1 may include a PMOS region and an NMOS region, wherein the NMOS region is the first doping region 13 and the PMOS region is the second doping region 14 .

[0087] In another embodiment, the functional layer 1 may include a PMOS region.

[0088] In other embodiments, the functional layer 1 may include an NMOS region.

[0089] It should be noted that the PMOS region is a region formed after P-type doping is performed in the substrate, and the NMOS region is a region formed after N-type doping is performed in the substrate.

[0090] In this embodiment, the PMOS region refers to a region doped with a trivalent impurity element, and for example, may be doped with any one of boron (B), gallium (Ga), and the like.

[0091] In this embodiment, the NMOS region is doped with a pentavalent impurity element, for example, any one of phosphorus (P), arsenic (As), and the like.

[0092] Of course, the structure of the functional layer above is only an example provided by the present invention. In actual application, the functional layer should include but not be limited to the structure in the above example.

[0093] S102 , fabricating a virtual gate 2 on the surface of the functional layer 1 ; wherein the virtual gate 2 includes a first virtual gate 21 and a second virtual gate 22 , and the horizontal cross-sectional dimension of the first virtual gate 21 is larger than the horizontal cross-sectional dimension of the second virtual gate 22 .

[0094] In this embodiment, the virtual gate can be obtained by growing a polysilicon layer and etching the polysilicon layer.

[0095] See also Figure 8 , Figure 8 This is a schematic structural diagram of a semiconductor device provided by the present invention during its manufacturing process, wherein a first dummy gate 21 and a second dummy gate 22 are specifically shown.

[0096] S103 , making a source electrode and a drain electrode in the functional layer.

[0097] In one example, step 103 includes:

[0098] Step 1: forming a source 15 and a drain 16 in the first doping region 13 .

[0099] In one example, the first doped region 13 is a PMOS region, and step 1 includes:

[0100] A trivalent impurity element is implanted into the first doping region to form a source 15 and a drain 16 in the first doping region 13 .

[0101] In another example, the first doped region 13 is an NMOS region, and step 1 includes:

[0102] An impurity element with a valence of five is implanted into the first doping region 13 to form a source 15 and a drain 16 in the first doping region 13 .

[0103] Step 2: forming a source 15 and a drain 16 in the second doping region 14 .

[0104] In one example, the second doped region 14 is a PMOS region, and step 2 includes:

[0105] A trivalent impurity element is implanted into the second doping region 14 to form a source 15 and a drain 16 in the second doping region 14 .

[0106] In one example, the second doped region 14 is an NMOS region, and step 2 includes:

[0107] An impurity element with a valence of five is implanted into the second doping region 14 to form a source 15 and a drain 16 in the second doping region.

[0108] See also Figure 9 , Figure 9 This is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein a source 15 and a drain 16 are specifically shown.

[0109] S104 , forming an etch stop layer 3 on the first dummy gate 21 and the second dummy gate 22 .

[0110] In one example, step S104 includes:

[0111] Silicon nitride is formed on the surface and side of the first virtual gate 21 and the second virtual gate 22 as an etch stop layer 3. Of course, silicon carbon nitride, silicon oxynitride, titanium nitride, tantalum nitride, high-k metal oxide (such as aluminum oxide, hafnium oxide) and other materials can also be formed as the etch stop layer.

[0112] See also Figure 10 , Figure 10 This is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein the etching stop layer 3 is specifically shown.

[0113] S105 , fabricating an interlayer dielectric layer 4 .

[0114] In one example, step S105 includes:

[0115] See also Figure 11 , Figure 11 This is a schematic structural diagram of a semiconductor device provided by the present invention during its manufacturing process, wherein an interlayer dielectric layer 4 is specifically shown, which is generally made of silicon dioxide or other low-k materials.

[0116] S106 , performing a first chemical mechanical polishing on the interlayer dielectric layer 4 to expose the etch stop layer 3 .

[0117] In one example, step S106 includes:

[0118] In the first step, the interlayer dielectric layer 4 is ground with a grinding liquid containing SiO 2 grinding particles to remove most of the interlayer dielectric layer 4 and retain a certain thickness of the interlayer dielectric layer 4 above the etch stop layer 3 .

[0119] In the second step, the interlayer dielectric layer 4 is polished again using a polishing liquid containing CeO 2 polishing particles, and the polishing stops at the surface of the etch stop layer 3 .

[0120] Of course, the above is only an example of a polishing liquid for the first chemical mechanical polishing provided by the present invention. The first chemical mechanical polishing may also use a polishing liquid formed by other polishing particles. The above example is not intended to limit the present invention.

[0121] See also Figure 12 , Figure 12 This is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, specifically showing the structure of the interlayer dielectric layer 4 after the first chemical mechanical polishing is performed.

[0122] S107 , performing a second chemical mechanical polishing on the etch stop layer 3 to expose the second dummy gate 22 .

[0123] In one example, step S107 includes:

[0124] The etching stop layer 3 on the surface of the second dummy gate 22 is removed by using a polishing liquid containing SiO 2 polishing particles, thereby exposing the second dummy gate 22 .

[0125] See also Figure 13 , Figure 13 This is a schematic structural diagram of a semiconductor device during the manufacturing process provided by the present invention, which specifically shows the structure of the etch stop layer 3 and the interlayer dielectric layer 4 after the second chemical mechanical polishing is performed.

[0126] It should be noted that after the etching stop layer 3 on the top of the second dummy gate 22 is removed, a gate sidewall is formed around the second dummy gate 22 .

[0127] S108 , performing selective epitaxial growth on the second virtual gate 22 to form a compensation layer 5 on the second virtual gate 22 .

[0128] See also Figure 14 , Figure 14 This is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein the structure of the compensation layer 5 is specifically shown.

[0129] In this embodiment, the compensation layer 5 may include a Si layer.

[0130] Of course, the actual function of the compensation layer is to compensate for the difference in etching efficiency caused by the different areas of the etch-stop layer on the first and second virtual gate surfaces. Therefore, as long as the material used for the compensation layer can make the polishing efficiency of the compensation layer similar to that of the etch-stop layer on the first virtual gate surface, it can be sufficient.

[0131] When the material of the second virtual gate 22 is polysilicon, the compensation layer 5 can be formed by selective epitaxial growth of polysilicon. Specifically, the epitaxial growth can be performed using a chemical vapor deposition (CVD) or physical vapor deposition (PVD) process. For example, when using chemical vapor deposition (CVD) epitaxy, polysilicon is deposited using silane (SiH4) or dichlorosilane (SiH2Cl2) under low pressure and high temperature conditions.

[0132] In this embodiment, the thickness of the compensation layer is 1.1 to 1.3 times the thickness of the etch stop layer.

[0133] In one example, the thickness of the compensation layer is 1.2 times the thickness of the etch stop layer.

[0134] In this embodiment, the thickness of the compensation layer 5 is 50-120 angstroms.

[0135] By way of example, the thickness of the compensation layer 5 is 60 angstroms.

[0136] It is worth noting that the thickness of the compensation layer 5 can be slightly thicker than the thickness of the etch stop layer 3 on the surface of the first dummy gate 21. For example, it can be slightly thicker by 20 angstroms than the thickness of the etch stop layer 3 on the surface of the first dummy gate 21.

[0137] In this embodiment, the thickness of the etch stop layer 3 is 30 angstroms to 100 angstroms.

[0138] S109 , performing a third chemical mechanical polishing on the compensation layer 5 and the etch stop layer 3 on the surface of the first dummy gate 21 , so that the compensation layer 5 and the etch stop layer 3 on the first dummy gate 21 are removed simultaneously, exposing the first dummy gate 21 and the second dummy gate 22 .

[0139] Among them, when performing the third chemical mechanical polishing process, the polishing efficiency of the compensation layer 5 is higher than the polishing efficiency of the interlayer dielectric layer 4, and the polishing efficiency of the etch stop layer 3 on the surface of the first virtual gate 21 is higher than the polishing efficiency of the interlayer dielectric layer 4.

[0140] In this embodiment, when the third chemical mechanical polishing is performed, the ratio of the polishing rate of the etch stop layer 3 to the polishing rate of the compensation layer 5 is: The ratio of the polishing rate of the etch stop layer 3 to the polishing rate of the interlayer dielectric layer 4 is greater than The ratio of the grinding rate of the compensation layer 5 to the grinding rate of the interlayer dielectric layer 4 is greater than ;

[0141] in, The value range is 0.5~1.5, The value range is 5~7. The value range is 5~7.

[0142] For example, is 1, is 6, is 6.

[0143] In this embodiment, the above grinding rate ratio can ensure that the thickness of the interlayer dielectric layer on the surface of the first virtual gate, the thickness of the interlayer dielectric layer between the first virtual gate and the second virtual gate, and the thickness of the interlayer dielectric layer around the second virtual gate are similar.

[0144] For example, the average area ratio of the first virtual gate 21 to the second virtual gate 22 is , the thickness of the etching stop layer 3 is recorded as , then the thickness of the compensation layer , K is the correction coefficient. When the grinding rate of the compensation layer is the same as that of the etch stop layer, K=1. When the grinding rate of the compensation layer is greater than that of the etch stop layer, K is greater than 1, otherwise it is less than 1. In general, the grinding rates of the compensation layer and the etch stop layer are roughly the same, so K should be 1. When the grinding rates are different, a separate material grinding experiment can be performed to determine the K value. For example, , , then the thickness of the compensation layer is calculated .

[0145] In one example, step S109 includes:

[0146] The etch stop layer 3 , the compensation layer 5 , and the interlayer dielectric layer 4 on the surface of the first dummy gate 21 are polished with an acidic polishing liquid until the first dummy gate 21 is exposed.

[0147] In this embodiment, the pH value of the acidic polishing liquid is 4-6.

[0148] Exemplarily, the pH value of the acidic polishing liquid is 5.

[0149] In this embodiment, the acidic polishing liquid includes an oxidant, a chelating agent, a surfactant, abrasive particles and a pH regulator; wherein the oxidant includes hydrogen peroxide; the chelating agent includes citric acid; the surfactant includes sodium lauryl sulfate; and the abrasive particles include silicon dioxide or cerium oxide.

[0150] In this embodiment, in the acidic polishing liquid, the proportion of the oxidant is 1wt%~3wt%, the proportion of the chelating agent is 0.5wt%~1.5wt%, the proportion of the surfactant is 0.1wt%~0.5wt%, the proportion of the abrasive particles is 5wt%~10wt%, and the remaining component is water. The proportion of the pH adjuster is determined according to the pH value of the polishing liquid.

[0151] For example, in the acidic polishing liquid, the proportion of the oxidant is 1.5wt%, the proportion of the chelating agent is 1wt%, the proportion of the surfactant is 0.3wt%, the proportion of the abrasive particles is 7.5wt%, and the proportion of the pH regulator is determined according to the pH value of the polishing liquid, such as the proportion of the pH regulator is 2wt%.

[0152] The above ratio is only an example. In actual implementation, the ratio can be adjusted as needed.

[0153] In this embodiment, the oxidant oxidizes the surfaces of the Si layer (compensation layer), SiN layer (etch stop layer), and SiO2 layer (interlayer dielectric layer), thereby promoting material removal efficiency during chemical mechanical polishing (CMP). The chelating agent synergizes with the oxidant to integrate metal ions, prevent particle agglomeration, and regulate surface reaction rates. The surfactant is used to reduce surface tension, improve the wettability and dispersibility of the polishing fluid, and ensure uniform polishing. The abrasive particles provide mechanical polishing and work in conjunction with the chemical components to achieve efficient material removal. The pH regulator is used to optimize the activity of the oxidant and the integrator to ensure the stability of the polishing fluid.

[0154] In this embodiment, by adjusting the ratio of the oxidant and the chelating agent, the surface oxidation rates of the SiN layer (etch stop layer) and the Si layer (compensation layer) are similar, which helps ensure similar polishing rates for the SiN layer (etch stop layer) and the Si layer (compensation layer). The polishing efficiency of the SiO2 layer (interlayer dielectric layer) is low under weakly acidic conditions, while the polishing efficiency of the SiN layer (etch stop layer) is high under the action of the oxidant and the integrator. As a result, the polishing efficiency ratio of the SiN layer (etch stop layer) to the SiO2 layer (interlayer dielectric layer) is greater than 5. The Si layer (compensation layer) forms an easily removable oxide under the action of the oxidant, while the polishing efficiency of the SiO2 layer (interlayer dielectric layer) is low under the same conditions. As a result, the polishing efficiency ratio of the Si layer (compensation layer) to the SiO2 layer (interlayer dielectric layer) is greater than 5.

[0155] See also Figure 15 , Figure 15 The schematic diagram of the structure of a semiconductor device during the manufacturing process provided by the present invention specifically shows the structure after the third chemical mechanical polishing is performed. The semiconductor structure finally obtained by the method for preparing the semiconductor structure provided by the present invention is as follows: Figure 15 As shown, in the semiconductor structure finally obtained, the height of the first virtual gate 21, the height of the second virtual gate 22, the height of the interlayer dielectric layer 4 around the first virtual gate 21, the height of the etch stop layer 3 around the first virtual gate 21, the height of the interlayer dielectric layer 4 around the second virtual gate 22, and the height of the etch stop layer 3 around the second virtual gate 22 are similar.

[0156] Figure 6 This is a flow chart of a method for preparing a semiconductor device provided by the present invention. Figure 6 , the method steps include:

[0157] S201: providing a substrate, and manufacturing a functional layer based on the substrate.

[0158] In one example, step S201 includes:

[0159] Step 1: Provide a substrate 11.

[0160] The material of the substrate refers to step S101.

[0161] Step 2: forming an isolation structure 12 on the substrate 11 .

[0162] In one example, step 2 includes:

[0163] In the first step, the substrate 11 is etched to form a shallow trench in the substrate.

[0164] The second step is to form an insulating layer in the shallow trench.

[0165] The insulating layer may be a SiO2 layer.

[0166] In the third step, chemical mechanical polishing is used to planarize the insulating layer to form an isolation structure 12 .

[0167] Step 3: Perform a first ion implantation on the substrate 11 to form a first doped region 13 in the substrate.

[0168] If the first doped region is a PMOS region, the element implanted by the first ion implantation may be a trivalent impurity element, such as boron (B), gallium (Ga), or any other element.

[0169] If the first doped region is an NMOS region, the element implanted by the first ion implantation may be a pentavalent impurity element, for example, any one of phosphorus (P), arsenic (As), and the like.

[0170] Step 4: Perform a second ion implantation on the substrate 11 to form a second doping region 14 in the substrate; wherein the first doping region 13 and the second doping region 14 are separated by the isolation structure 12 .

[0171] If the second doped region is a PMOS region, the element implanted by the first ion implantation may be a trivalent impurity element, such as boron (B), gallium (Ga), or any other element.

[0172] If the second doping region is an NMOS region, the element implanted by the first ion implantation may be a pentavalent impurity element, for example, any one of phosphorus (P), arsenic (As), and the like.

[0173] S202 , forming a virtual gate 2 on the surface of the doped region; wherein the virtual gate 2 includes a first virtual gate 21 and a second virtual gate 22 , and the horizontal cross-sectional dimension of the first virtual gate 21 is larger than the horizontal cross-sectional dimension of the second virtual gate 22 .

[0174] See step S102.

[0175] S203 , making a source electrode and a drain electrode in the functional layer.

[0176] See step S103.

[0177] S204 , forming an etch stop layer 3 on the first dummy gate 21 and the second dummy gate 22 .

[0178] See step S104.

[0179] S205 , fabricating an interlayer dielectric layer 4 .

[0180] See step S105.

[0181] S206 , performing a first chemical mechanical polishing on the interlayer dielectric layer 4 to expose the etch stop layer 3 .

[0182] See step S106.

[0183] S207 , performing a second chemical mechanical polishing on the etch stop layer 3 to expose the second dummy gate 22 .

[0184] See step S107.

[0185] S208 , performing selective epitaxial growth on the second virtual gate 22 to form a compensation layer 5 on the second virtual gate 22 .

[0186] See step S108.

[0187] S209 , performing a third chemical mechanical polishing on the compensation layer 5 and the etch stop layer 3 on the surface of the first dummy gate 21 , so that the compensation layer and the etch stop layer on the first dummy gate are removed simultaneously, exposing the first dummy gate 21 and the second dummy gate 22 .

[0188] See step S109.

[0189] S210 , removing the first dummy gate 21 and the second dummy gate 22 to obtain a first gate groove 61 and a second gate groove 62 .

[0190] In one example, step S210 includes:

[0191] Anisotropic dry etching (such as reactive ion etching, RIE) is used to selectively remove the dummy gate made of polysilicon.

[0192] The etching gas used in dry etching usually includes a mixture of Cl2, HBr and O2. These gases have high selectivity for polysilicon and can avoid damage to the sidewalls and interlayer dielectric layers.

[0193] See also Figure 16 , Figure 16 This is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein a first gate groove 61 and a second gate groove 62 are specifically shown.

[0194] S211 , forming a gate metal layer in the first gate groove 61 and the second gate groove 62 .

[0195] In one example, step S211 includes:

[0196] In the first step, a high-K dielectric layer 63 is deposited in the first gate groove 61 and the second gate groove 62 .

[0197] The high-K dielectric layer 63 may be a HfO 2 layer.

[0198] The high-K dielectric layer can be prepared using an atomic layer deposition process.

[0199] In the second step, a gate metal layer 64 is formed on the high-K dielectric layer 63 in the first gate groove 61 and the second gate groove 62 .

[0200] The gate metal layer 64 can be formed of materials such as Al, TiN, and TaN.

[0201] See also Figure 17 , Figure 17 This is a schematic structural diagram of a semiconductor device provided by the present invention during its manufacturing process, wherein the gate metal layer 64 is specifically shown.

[0202] S212 , performing a fourth chemical mechanical polishing on the gate metal layer to form a first gate in the first gate groove and a second gate in the second gate groove.

[0203] The gate metal layer 64 is subjected to chemical mechanical polishing, and the gate metal layer 64 located in the first gate groove 61 and the second gate groove 62 is retained to serve as the first metal gate 65 and the second metal gate 66 .

[0204] In this embodiment, the first metal gate 65 and the high-K dielectric layer 63 form a first gate, and the second metal gate 66 and the high-K dielectric layer 63 form a second gate.

[0205] See also Figure 18 , Figure 18 This is a schematic structural diagram of a semiconductor device provided by the present invention during the manufacturing process, wherein a first metal gate 65 and a second metal gate 66 are specifically shown.

[0206] The present invention further provides a semiconductor device, which can be formed using the above-mentioned method for manufacturing a semiconductor structure or a method for manufacturing a semiconductor device.

[0207] Finally, it should be noted that the technical solution provided by the present invention has the following unexpected technical effects:

[0208] The present invention provides a method for fabricating a semiconductor structure, wherein, after a second chemical mechanical polishing process is performed to expose a second virtual gate, a selective epitaxial growth process is performed on the second virtual gate to form a compensation layer on the surface of the second virtual gate, and then a third chemical mechanical polishing process is performed. An unexpected technical effect is that the compensation layer protects the second virtual gate, preventing the second virtual gate and the interlayer dielectric layer surrounding the second virtual gate from being polished during the third chemical mechanical polishing process, thereby protecting the height of the interlayer dielectric layer surrounding the second virtual gate. Furthermore, during the third chemical polishing process, by optimizing the process parameters of the third chemical mechanical polishing process, the third chemical mechanical polishing process achieves different polishing efficiencies for the compensation layer, the interlayer dielectric layer, and the etch stop layer. Among them, the grinding efficiency of the compensation layer and the etch stop layer is higher than that of the interlayer dielectric layer, thereby ensuring that after the compensation layer and the etch stop layer on the surface of the first virtual gate are removed by the third chemical mechanical polishing process, the heights of the etch stop layers surrounding the first virtual gate and the second virtual gate are similar. It can also be ensured that when the compensation layer and the etch stop layer on the surface of the first virtual gate are removed by the third chemical mechanical polishing process, the thickness decrease rate of the interlayer dielectric layer between the first virtual gate and the second virtual gate is slower than that of the etch stop layer on the surface of the compensation layer and the first virtual gate, which is beneficial to ensuring the overall thickness of the interlayer dielectric layer, that is, ensuring that the surface of the interlayer dielectric layer is close to a plane, and the thickness of the interlayer dielectric layer is similar to the height of the etch stop layer surrounding the virtual gate.

[0209] After the dummy gate is subsequently removed to form gate grooves (a first gate groove corresponding to the first dummy gate and a second gate groove corresponding to the second dummy gate), when a metal gate is made in the gate groove, etch stop layers of similar height (that is, the etch stop layer surrounding the first gate groove and the etch stop layer surrounding the second gate groove are of similar height) and interlayer dielectric layers of similar thickness are helpful in ensuring that the thickness of the metal gate formed in the gate groove is the same or similar.

[0210] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, rather than to limit it. Although the present invention has been described in detail with reference to the aforementioned embodiments, those skilled in the art should understand that they can still modify the technical solutions described in the aforementioned embodiments, or make equivalent replacements for some of the technical features therein. However, these modifications or replacements do not deviate the essence of the corresponding technical solutions from the spirit and scope of the technical solutions of the various embodiments of the present invention.

Claims

1. A method for preparing a semiconductor structure, characterized in that: The method for preparing the semiconductor structure comprises: Providing a substrate and manufacturing a functional layer based on the substrate; Fabricate a virtual gate on the surface of the functional layer; wherein the virtual gate includes a first virtual gate and a second virtual gate, and the horizontal cross-sectional size of the first virtual gate is larger than the horizontal cross-sectional size of the second virtual gate; forming a source electrode and a drain electrode in the functional layer; forming an etch stop layer on the first dummy gate and the second dummy gate; fabricating an interlayer dielectric layer; performing a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer; performing a second chemical mechanical polishing on the etch stop layer to expose a second dummy gate; performing selective epitaxial growth on the second virtual gate to form a compensation layer on the second virtual gate; A third chemical mechanical polishing is performed on the compensation layer and the etch stop layer on the surface of the first dummy gate, so that the compensation layer and the etch stop layer on the first dummy gate are removed simultaneously, exposing the first dummy gate and the second dummy gate.

2. The method for preparing a semiconductor structure according to claim 1, wherein: The thickness of the compensation layer is 1.1 to 1.3 times the thickness of the etch stop layer.

3. The method for preparing a semiconductor structure according to claim 1, wherein: The compensation layer includes a Si layer.

4. The method for preparing a semiconductor structure according to any one of claims 1 to 3, wherein: When performing the third chemical mechanical polishing, the ratio of the polishing rate of the etch stop layer to the polishing rate of the compensation layer is The ratio of the polishing rate of the etch stop layer to the polishing rate of the interlayer dielectric layer is greater than The ratio of the grinding rate of the compensation layer to the grinding rate of the interlayer dielectric layer is greater than ; in, The value range is 0.5~1.5, The value range is 5~7. The value range is 5~7.

5. The method for preparing a semiconductor structure according to claim 4, wherein: The steps of performing the third chemical mechanical polishing are as follows: An acidic polishing liquid is used to polish the etching stop layer, the compensation layer, and the interlayer dielectric layer on the surface of the first virtual gate until the first virtual gate is exposed.

6. The method for preparing a semiconductor structure according to claim 5, wherein: The acidic polishing liquid comprises an oxidant, a chelating agent, a surfactant, abrasive particles and a pH regulator; Wherein, the oxidant includes hydrogen peroxide; the chelating agent includes citric acid; the surfactant includes sodium lauryl sulfate; and the abrasive particles include silicon dioxide or cerium oxide.

7. The method for preparing a semiconductor structure according to claim 6, wherein: In the acidic polishing liquid, the proportion of the oxidant is 1wt%~3wt%, the proportion of the chelating agent is 0.5wt%~1.5wt%, the proportion of the surfactant is 0.1wt%~0.5wt%, the proportion of the abrasive particles is 5wt%~10wt%, and the proportion of the pH regulator is determined according to the pH value of the polishing liquid.

8. A semiconductor structure, characterized in that The semiconductor structure is prepared by the method according to any one of claims 1 to 7.

9. A method for preparing a semiconductor device, characterized in that: The method for preparing the semiconductor device comprises: Providing a substrate and manufacturing a functional layer based on the substrate; Fabricate a virtual gate on the surface of the functional layer; wherein the virtual gate includes a first virtual gate and a second virtual gate, and the horizontal cross-sectional size of the first virtual gate is larger than the horizontal cross-sectional size of the second virtual gate; forming a source electrode and a drain electrode in the functional layer; forming an etch stop layer on the first dummy gate and the second dummy gate; fabricating an interlayer dielectric layer; performing a first chemical mechanical polishing on the interlayer dielectric layer to expose the etch stop layer; performing a second chemical mechanical polishing on the etch stop layer to expose a second dummy gate; performing selective epitaxial growth on the second virtual gate to form a compensation layer on the second virtual gate; performing a third chemical mechanical polishing on the compensation layer and the etch stop layer on the surface of the first dummy gate, so that the compensation layer and the etch stop layer on the first dummy gate are removed simultaneously, exposing the first dummy gate and the second dummy gate; removing the first dummy gate and the second dummy gate to obtain a first gate groove and a second gate groove; forming a gate metal layer in the first gate groove and the second gate groove; A fourth chemical mechanical polishing is performed on the gate metal layer to form a first gate in the first gate groove and a second gate in the second gate groove.

10. A semiconductor device, characterized in that: The semiconductor device is manufactured by the method according to claim 9.

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