Ring gate device structure and forming method thereof

Abstract

The invention provides a gate-all-around device structure and a forming method thereof.The gate-all-around device structure comprises a semiconductor substrate, an insulating layer, a plurality of stacking layers and a plurality of dummy gate structures are sequentially formed on the surface of the semiconductor substrate, each stacking layer comprises a plurality of channel layers and a gate-all-around structure surrounding the channel layers, and the dummy gate structures are arranged on the surface of the semiconductor substrate; the starting layers and the stopping layers of the stacking layers are channel layers, the starting layers of the stacking layers are connected, and the starting layers are used for serving as part of substrates for growth of source and drain layers; the side walls are located on the side walls of the dummy gate structures; the inner side wall is located on the side wall of the sacrificial layer; and the source and drain layers are positioned among the plurality of stack layers. The invention provides a gate-all-around device structure and a forming method thereof, which can improve the quality of source-drain epitaxy in a CFET structure, thereby improving the reliability of a device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and particularly to a gate-all-around device structure and a method for forming the same. Background Art

[0002] As device dimensions shrink, the CFET structure (Complementary FET) has attracted attention due to its good leakage control ability. In particular, to improve device isolation and reduce device capacitance and leakage, the CFET adopts a bottom isolation structure (BDI).

[0003] However, due to the introduction of the bottom isolation structure, great challenges are encountered during the source / drain epitaxy of the device, resulting in the suspension of the epitaxial structure and many stacking misalignments in the epitaxy, which greatly affects the performance of the device, especially the performance of PMOS devices.

[0004] Therefore, it is necessary to provide a more effective and reliable technical solution to improve the quality of source / drain epitaxy in the CFET structure, thereby improving device reliability. Summary of the Invention

[0005] This application provides a gate-all-around device structure and a method for forming the same, which can improve the quality of source / drain epitaxy in the CFET structure, thereby improving device reliability.

[0006] One aspect of this application provides a gate-all-around device structure, including: a semiconductor substrate, an insulating layer, a plurality of stacked layers, and a plurality of gate structures are sequentially formed on the surface of the semiconductor substrate. The stacked layers include a plurality of channel layers and a gate-all-around structure surrounding the channel layers. The starting layer and the ending layer of the stacked layers are both channel layers. The starting layers of the plurality of stacked layers are connected, and the starting layer is used as a partial substrate for the growth of the source / drain layer; sidewalls are located on the sidewalls of the plurality of gate structures; inner sidewalls are located on the sidewalls of the gate-all-around structure; and source / drain layers are located between the plurality of stacked layers.

[0007] In some embodiments of this application, the material of the channel layer includes silicon.

[0008] In some embodiments of this application, the thickness of the gate-all-around structure is 5 - 12 nanometers; the thickness of the channel layer is 5 - 12 nanometers.

[0009] In some embodiments of this application, the thickness of a part of the starting layer located between the stacked layers is 1 - 5 nanometers.

[0010] Another aspect of the present application also provides a method for forming a gate-all-around device structure, including: providing a semiconductor substrate, on the surface of which an epitaxial layer, a stacked layer, and a plurality of dummy gate structures are sequentially formed, the stacked layer including a sacrificial layer and a channel layer that are alternately stacked in sequence, and both the starting layer and the terminating layer of the stacked layer being channel layers; removing the epitaxial layer to form a hollow layer; forming an insulating layer in the hollow layer and forming a spacer layer on the sidewalls and top surface of the plurality of dummy gate structures and on the surface of the stacked layer; etching the spacer layer and the stacked layer into the starting layer of the stacked layer, removing the spacer layer on the surface of the stacked layer and on the top surface of the plurality of dummy gate structures, and forming spacers on the sidewalls of the plurality of dummy gate structures; etching the sacrificial layer to form recesses on both sides of the sacrificial layer and forming inner spacers in the recesses; epitaxially growing source and drain layers using the starting layer of the stacked layer and the channel layer as substrates.

[0011] In some embodiments of the present application, the material of the epitaxial layer includes silicon germanium, the material of the sacrificial layer includes silicon germanium, and the material of the channel layer includes silicon. Among them, the atomic proportion of germanium in the material of the epitaxial layer is greater than the atomic proportion of germanium in the sacrificial layer.

[0012] In some embodiments of the present application, the atomic proportion of germanium in the material of the epitaxial layer is greater than 45%.

[0013] In some embodiments of the present application, the thickness of the sacrificial layer is 5 - 12 nanometers; the thickness of the channel layer is 5 - 12 nanometers.

[0014] In some embodiments of the present application, after etching the spacer layer and the stacked layer into the starting layer of the stacked layer, the remaining thickness of the starting layer of the stacked layer is 1 - 5 nanometers.

[0015] In some embodiments of the present application, the method for forming the gate-all-around device structure further includes: removing the dummy gate structures and the sacrificial layer, forming gate structures at the positions of the dummy gate structures, and forming gate-all-around structures surrounding the channel layer at the positions of the sacrificial layer.

[0016] Another aspect of the present application also provides a method for forming a gate-all-around device structure, including: providing a semiconductor substrate, on the surface of which an epitaxial layer, a stacked layer, and a plurality of dummy gate structures are sequentially formed, the stacked layer includes a sacrificial layer and a channel layer stacked alternately in sequence, and the starting layer and the ending layer of the stacked layer are both channel layers; forming a spacer layer on the sidewalls and the top surface of the plurality of dummy gate structures and on the surface of the stacked layer; etching the spacer layer and the stacked layer to the starting layer of the stacked layer, removing the spacer layer on the surface of the stacked layer and the top surfaces of the plurality of dummy gate structures, and forming spacers on the sidewalls of the plurality of dummy gate structures; etching the sacrificial layer to form recesses on both sides of the sacrificial layer and removing the epitaxial layer to form a hollow layer; forming an insulating layer in the hollow layer and forming inner spacers in the recesses; epitaxially growing source / drain layers using the starting layer of the stacked layer and the channel layer as a substrate.

[0017] In some embodiments of the present application, the material of the epitaxial layer includes silicon germanium, the material of the sacrificial layer includes silicon germanium, and the material of the channel layer includes silicon. Among them, the atomic number ratio of germanium in the material of the epitaxial layer is greater than the atomic number ratio of germanium in the sacrificial layer.

[0018] In some embodiments of the present application, the atomic number ratio of germanium in the material of the epitaxial layer is greater than 45%.

[0019] In some embodiments of the present application, the thickness of the sacrificial layer is 5 - 12 nanometers; the thickness of the channel layer is 5 - 12 nanometers.

[0020] In some embodiments of the present application, after etching the spacer layer and the stacked layer to the starting layer of the stacked layer, the remaining thickness of the starting layer of the stacked layer is 1 - 5 nanometers.

[0021] In some embodiments of the present application, the method for forming the gate-all-around device structure further includes: removing the dummy gate structures and the sacrificial layer, and forming a gate structure at the position of the dummy gate structures and forming a gate-all-around structure surrounding the channel layer at the position of the sacrificial layer.

[0022] The present application provides a gate-all-around device structure and a method for forming the same, which can improve the quality of source / drain epitaxy in the CFET structure, thereby improving device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] The following drawings detail the exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non-limiting, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale.

[0024] Wherein:

[0025] Figures 1 to 10 are schematic structural diagrams of the steps in the method for forming a gate-all-around device structure according to some embodiments of the present application;

[0026] Figures 11 to 19 are schematic structural diagrams of the steps in the method for forming a gate-all-around device structure according to other embodiments of the present application. Detailed Description of the Invention

[0027] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content of the present application. For those skilled in the art, various local modifications to the disclosed embodiments are obvious, and the general principles defined herein can be applied to other embodiments and applications without departing from the spirit and scope of the present application. Therefore, the present application is not limited to the illustrated embodiments, but has the broadest scope consistent with the claims.

[0028] The technical solution of the present invention will be described in detail below with reference to the embodiments and the accompanying drawings.

[0029] Figures 1 to 10 are schematic structural diagrams of the steps in the method for forming a gate-all-around device structure according to some embodiments of the present application. It should be noted that the accompanying drawings of the present application only show partial cross-sectional views of the gate-all-around device structure, and some structures are not shown.

[0030] Refer to Figure 1 、 Figure 2 and Figure 3 as shown, wherein, Figure 1 is a top view, Figure 2 is a longitudinal cross-sectional view along the dashed line X-X in Figure 1 , Figure 3 is a longitudinal cross-sectional view along the dashed line Y-Y in Figure 1 . A semiconductor substrate 100 is provided, and an epitaxial layer 110, a stacked layer 120, and a plurality of dummy gate structures 130 are sequentially formed on the surface of the semiconductor substrate 100. The stacked layer 120 includes a sacrificial layer 122 and a channel layer 121 that are alternately stacked in sequence, and both the starting layer and the ending layer of the stacked layer 120 are channel layers 121.

[0031] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide; or (iv) a combination of the above.

[0032] Specifically, refer toFigure 1 As shown, the semiconductor substrate 100 includes an x-direction and a y-direction that are perpendicular to each other. Among them, the epitaxial layer 110 and the stacked layer 120 extend in the x-direction, and the pseudo-gate structure 130 extends in the y-direction.

[0033] In some embodiments of the present application, the material of the epitaxial layer 110 includes silicon germanium, the material of the sacrificial layer 122 includes silicon germanium, and the material of the channel layer 121 includes silicon. Among them, the proportion of germanium atoms in the material of the epitaxial layer 110 is greater than the proportion of germanium atoms in the sacrificial layer 122. The proportion of germanium atoms refers to the proportion of germanium atoms in silicon germanium to the total number of silicon atoms and germanium atoms. The higher the proportion of germanium atoms, the easier it is to etch and remove the silicon germanium material. Here in the present application, the epitaxial layer 110 needs to be removed later, but the sacrificial layer 122 is not removed at the same time. Therefore, the proportion of germanium atoms in the material of the epitaxial layer 110 needs to be much greater than the proportion of germanium atoms in the sacrificial layer 122.

[0034] Specifically, in some embodiments of the present application, the proportion of germanium atoms in the material of the epitaxial layer 110 is greater than 45%, such as 50%, 55%, 60% or 65%, etc.

[0035] In some embodiments of the present application, the thickness of the epitaxial layer 110 is 5 - 15 nanometers. The epitaxial layer 110 is used to first form the starting layer channel layer 121 when forming the stacked layer 120. Subsequently, the epitaxial layer 110 needs to be replaced with an insulating layer, and the channel layer 121 cannot be directly formed on the insulating layer. Therefore, in the technical solution of the present application, after using the epitaxial layer 110 to form the starting layer channel layer, the epitaxial layer 110 is then replaced with an insulating layer. Therefore, the thickness of the epitaxial layer 110 is the same as the thickness of the insulating layer.

[0036] In some embodiments of the present application, the stacking number of the stacked layer 120 can be any suitable number. Here in the present application, only a five-layer stacked layer is used as an example. Among them, both the starting layer and the ending layer of the stacked layer 120 are channel layers 121, which is required to use the starting layer as an epitaxial growth matrix to grow the source-drain layer later.

[0037] In some embodiments of the present application, the thickness of the sacrificial layer 122 is 5 - 12 nanometers; the thickness of the channel layer 121 is 5 - 12 nanometers.

[0038] In a gate all around (GAA) device structure described in the present application, the sacrificial layer 122 needs to be removed later and replaced with a gate all around structure to achieve a gate surrounding structure for the channel layer 121.

[0039] In some embodiments of the present application, the material of the pseudo-gate structure 130 includes polysilicon.

[0040] Reference Figure 4 and Figure 5 as shown, wherein, Figure 4 is a longitudinal sectional view along the dashed line X-X in Figure 1 , and Figure 5 is a longitudinal sectional view along the dashed line Y-Y in Figure 1 . The epitaxial layer 110 is removed to form a hollow layer 141. The hollow layer 141 is filled with air and is an air-gap structure.

[0041] In some embodiments of the present application, the method for removing the epitaxial layer 110 is wet etching. As described above, since the proportion of germanium atoms in the material of the epitaxial layer 110 is much larger than the proportion of germanium atoms in the sacrificial layer 122, the sacrificial layer 122 is basically not damaged when the epitaxial layer 110 is removed.

[0042] Reference Figure 6 as shown, Figure 6 is a longitudinal sectional view along the dashed line X-X in Figure 1 . An insulating layer 140 is formed in the hollow layer 141, and a sidewall layer 151 is formed on the sidewalls and top surface of the plurality of dummy gate structures 130 and on the surface of the stacked layer 120. The insulating layer 140 is a bottom dielectric isolation (BDI) structure.

[0043] In some embodiments of the present application, the sidewall layer 151 and the insulating layer 140 are formed synchronously and have the same material, such as silicon oxide.

[0044] Reference Figure 7 as shown, Figure 7 is a longitudinal sectional view along the dashed line X-X in Figure 1 . The sidewall layer 151 and the stacked layer 120 are etched into the starting layer of the stacked layer 120, and the sidewall layer 151 on the surface of the stacked layer 120 and on the top surfaces of the plurality of dummy gate structures 130 is removed to form sidewalls 150 on the sidewalls of the plurality of dummy gate structures 130.

[0045] The starting layer channel layer 121 is subsequently used for epitaxial growth to form source / drain layers. Therefore, the starting layer channel layer 121 cannot be etched to expose the insulating layer 140, and the etching needs to stop in this starting layer channel layer 121. Of course, theoretically, the etching can just stop on the surface of this starting layer channel layer 121. However, in practice, this requires a very high control accuracy of the etching process. To avoid the etching accuracy fluctuation causing the etching to stop above the starting layer channel layer 121, a moderate over-etching is allowed so that the etching stops below the surface of the starting layer channel layer 121 and above the insulating layer 140.

[0046] In some embodiments of the present application, after etching the sidewall layer 151 and the stacked layer 120 to the starting layer of the stacked layer 120, the remaining thickness of the starting layer of the stacked layer 120 is 1-5 nanometers.

[0047] Reference Figure 8 shown, Figure 8 is a longitudinal sectional view along the Figure 1 dotted line X-X in. After etching the sacrificial layer 122, recesses are formed on both sides of the sacrificial layer 122, and inner sidewalls 160 are formed in the recesses. The material of the inner sidewalls 160 includes silicon oxide or silicon nitride, etc.

[0048] Reference Figure 9 shown, Figure 9 is a longitudinal sectional view along the Figure 1 dotted line X-X in. The source-drain layer 170 is epitaxially grown with the starting layer of the stacked layer 120 and the channel layer 121 as the substrate. The source-drain layer 170 adaptively serves as the source or drain of the CFET device described in the embodiments of the present application according to the type of voltage applied subsequently.

[0049] In some embodiments of the present application, the material of the source-drain layer 170 includes silicon or germanium.

[0050] Reference Figure 10 shown, in some embodiments of the present application, the method for forming the gate-all-around device structure further includes: removing the dummy gate structure 130 and the sacrificial layer 122, forming a gate structure 131 at the original position of the dummy gate structure 130, and forming a gate-all-around structure 132 surrounding the channel layer 121 at the original position of the sacrificial layer 122.

[0051] In the technical solution of the present application, using the starting layer of the stacked layer and the channel layer as the seed layer for epitaxial growth can effectively improve the quality of epitaxial growth, reduce epitaxial growth defects, and thus improve device reliability and device performance.

[0052] In the technical solution of the present application, in order to make the starting layer of the stacked layer be the channel layer instead of the sacrificial layer, an epitaxial layer is first used to form the starting layer channel layer, and then the epitaxial layer is replaced with an insulating layer.

[0053] The technical solution of the present application has a BDI structure, and the device capacitance is greatly reduced compared with the device without the BDI structure.

[0054] Some embodiments of the present application provide a method for forming a gate-all-around device structure, which can improve the quality of source-drain epitaxy in the CFET structure, thereby improving device reliability.

[0055] Figures 11 to 19 is a schematic structural diagram of each step in the method for forming the gate-all-around device structure described in other embodiments of the present application.

[0056] Reference Figure 10 、 Figure 11 and Figure 12 as shown, wherein, Figure 10 is a top view, Figure 11 is a longitudinal sectional view along the dashed line X-X in Figure 10 , and Figure 12 is a longitudinal sectional view along the dashed line Y-Y in Figure 10 . A semiconductor substrate 200 is provided, on the surface of which an epitaxial layer 210, a stacked layer 220 and a plurality of dummy gate structures 230 are sequentially formed. The stacked layer 220 includes a sacrificial layer 222 and a channel layer 221 that are alternately stacked in sequence, and both the starting layer and the ending layer of the stacked layer 220 are channel layers 221.

[0057] In some embodiments of the present application, the material of the semiconductor substrate 200 includes (i) elemental semiconductors, such as silicon or germanium; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide or indium phosphide; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide or gallium indium phosphide; or (iv) a combination of the above.

[0058] Specifically, referring to Figure 10 as shown, the semiconductor substrate 200 includes an x direction and a y direction that are perpendicular to each other. Among them, the epitaxial layer 210 and the stacked layer 220 extend in the x direction, and the dummy gate structures 230 extend in the y direction.

[0059] In some embodiments of the present application, the material of the epitaxial layer 210 includes silicon germanium, the material of the sacrificial layer 222 includes silicon germanium, and the material of the channel layer 221 includes silicon. Among them, the atomic number ratio of germanium in the material of the epitaxial layer 210 is greater than the atomic number ratio of germanium in the sacrificial layer 222. The atomic number ratio of germanium refers to the ratio of the number of germanium atoms in silicon germanium to the total number of silicon atoms and germanium atoms. The higher the atomic number ratio of germanium, the easier it is to etch and remove the silicon germanium material. In the present application, the epitaxial layer 210 needs to be removed later, but the sacrificial layer 222 is not removed at the same time. Therefore, the atomic number ratio of germanium in the material of the epitaxial layer 210 needs to be much greater than the atomic number ratio of germanium in the sacrificial layer 222.

[0060] Specifically, in some embodiments of the present application, the atomic number ratio of germanium in the material of the epitaxial layer 210 is greater than 45%, such as 50%, 55%, 60% or 65%, etc.

[0061] In some embodiments of the present application, the thickness of the epitaxial layer 210 is 5 - 15 nanometers. The epitaxial layer 210 is used to form the starting layer channel layer 221 when forming the stacked layer 220. Subsequently, the epitaxial layer 210 needs to be replaced with an insulating layer, and the channel layer 221 cannot be directly formed on the insulating layer. Therefore, in the technical solution of the present application, after using the epitaxial layer 210 to form the starting layer channel layer, the epitaxial layer 210 is then replaced with an insulating layer. Therefore, the thickness of the epitaxial layer 210 is the same as that of the insulating layer.

[0062] In some embodiments of the present application, the stacking number of the stacked layer 220 can be any suitable number, and here in the present application, a five-layer stacked layer is only taken as an example. Among them, both the starting layer and the ending layer of the stacked layer 220 are channel layers 221, which is for subsequently using the starting layer as an epitaxial growth substrate to grow source / drain layers.

[0063] In some embodiments of the present application, the thickness of the sacrificial layer 222 is 5 - 12 nanometers; the thickness of the channel layer 221 is 5 - 12 nanometers.

[0064] In a gate-all-around (GAA) device structure described in the present application, the sacrificial layer 222 needs to be removed subsequently and replaced with a gate-all-around structure to achieve a gate surrounding structure for the channel layer 221.

[0065] In some embodiments of the present application, the material of the dummy gate structure 230 includes polysilicon.

[0066] Reference Figure 13 as shown, wherein, Figure 13 is a longitudinal sectional view along the dashed line X-X in Figure 10 . A spacer layer 251 is formed on the sidewalls and the top surface of the plurality of dummy gate structures 230 and on the surface of the stacked layer 220. The material of the spacer layer 251 includes silicon oxide or silicon nitride, etc.

[0067] Reference Figure 14 as shown, wherein, Figure 14 is a longitudinal sectional view along the dashed line X-X in Figure 10 . The spacer layer 251 and the stacked layer 220 are etched into the starting layer channel layer 221 of the stacked layer 220, and the spacer layer 251 on the surface of the stacked layer 220 and on the top surfaces of the plurality of dummy gate structures 230 is removed to form spacers 250 on the sidewalls of the plurality of dummy gate structures 230.

[0068] The starting layer channel layer 221 is subsequently used for epitaxial growth to form source and drain layers. Therefore, the starting layer channel layer 221 cannot be etched to expose the epitaxial layer 210, and the etching needs to stop within this starting layer channel layer 221. Of course, in theory, the etching can exactly stop on the surface of this starting layer channel layer 221. However, in practice, this requires a very high control precision for the etching process. To avoid the etching precision fluctuation causing the etching to stop above the starting layer channel layer 221, a moderate over-etching can be allowed to make the etching stop below the surface of the starting layer channel layer 221 and above the epitaxial layer 210.

[0069] In some embodiments of the present application, after etching the sidewall layer 251 and the stacked layer 220 to the starting layer of the stacked layer 220, the remaining thickness of the starting layer of the stacked layer 220 is 1 - 5 nanometers.

[0070] Reference Figure 15 shown, wherein, Figure 15 is a longitudinal sectional view along Figure 10 the dashed line X-X in. Etching the sacrificial layer 222 forms recesses 261 on both sides of the sacrificial layer 222 and removes the epitaxial layer 210 to form a hollow layer 241. The hollow layer 241 is filled with air and is an air-gap structure.

[0071] In some embodiments of the present application, the method for removing the epitaxial layer 210 is wet etching.

[0072] Reference Figure 16 shown, wherein, Figure 16 is a longitudinal sectional view along Figure 10 the dashed line X-X in. An insulating layer 240 is formed in the hollow layer 241 and an inner sidewall 150 is formed in the recess 261. The insulating layer 240 is a bottom dielectric isolation (BDI) structure.

[0073] In some embodiments of the present application, the inner sidewall 260 and the insulating layer 240 are formed synchronously and have the same material, such as silicon oxide.

[0074] Reference Figure 17 shown, wherein, Figure 17 is a longitudinal sectional view along Figure 10 the dashed line X-X in. Using the starting layer of the stacked layer 220 and the channel layer 221 as a substrate for epitaxial growth to form a source and drain layer 270.

[0075] The source and drain layer 170 adaptively serves as the source or drain of the CFET device described in the embodiments of the present application according to the type of voltage applied subsequently.

[0076] In some embodiments of the present application, the material of the source and drain layer 170 includes silicon or germanium.

[0077] Reference Figure 19 As shown, in some embodiments of the present application, the method for forming the gate-all-around device structure further includes: removing the dummy gate structure 230 and the sacrificial layer 222, forming a gate structure 231 at the original position of the dummy gate structure 230, and forming a gate-all-around structure 232 surrounding the channel layer 221 at the original position of the sacrificial layer 222.

[0078] In the technical solution of the present application, using the starting layer channel layer of the stacked layer as the seed layer for epitaxial growth can effectively improve the quality of epitaxial growth, reduce epitaxial growth defects, and thus improve device reliability and device performance.

[0079] In the technical solution of the present application, in order to make the starting layer of the stacked layer be the channel layer instead of the sacrificial layer, an epitaxial layer is first used to form the starting layer channel layer, and then the epitaxial layer is replaced with an insulating layer.

[0080] The technical solution of the present application has a BDI structure, and the device capacitance is greatly reduced compared with the device without the BDI structure.

[0081] Some embodiments of the present application provide a method for forming a gate-all-around device structure, which can improve the quality of source / drain epitaxy in the CFET structure, thereby improving device reliability.

[0082] It should be noted that Figures 1 to 10 the described embodiments and Figures 11 to 19 the described embodiments are two different embodiments of the technical solution of the present application. Their basic technical solutions are all to use an epitaxial layer to form the starting layer channel layer, then remove the epitaxial layer and replace it with an insulating layer, and then epitaxially grow the source / drain layer with the starting layer channel layer as the substrate. Such a CFET device can not only have a BDI insulating layer structure but also have a high-quality source / drain layer. The difference between these two different embodiments lies only in the different step sequence positions of the step of removing the epitaxial layer and replacing it with an insulating layer. Figures 1 to 10 In the described embodiment, the epitaxial layer is removed before forming the sidewall, and the insulating layer and the sidewall are formed simultaneously. Figures 10 to 19 In the described embodiment, the epitaxial layer is removed before forming the inner sidewall, and the insulating layer and the inner sidewall are formed simultaneously.

[0083] Embodiments of the present application also provide a gate-all-around device structure. Reference Figure 10As shown, it includes: a semiconductor substrate 100, on the surface of the semiconductor substrate 100, an insulating layer 140, a plurality of stacked layers 120, and a plurality of gate structures 131 are sequentially formed. The stacked layer 120 includes a channel layer 121 and a gate-all-around structure 132 surrounding the channel layer 121. The starting layer and the ending layer of the stacked layer 120 are both the channel layer 121. The starting layers of the plurality of stacked layers 120 are connected, and the starting layer is used as a part of the substrate during the growth of the source / drain layer; sidewalls 150 are located on the sidewalls of the plurality of gate structures 131; inner sidewalls 160 are located on the sidewalls of the gate-all-around structure 132; and source / drain layers 170 are located between the plurality of stacked layers 120.

[0084] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide, etc.; or (iv) a combination of the above.

[0085] Specifically, referring to Figure 1 As shown, the semiconductor substrate 100 includes an x-direction and a y-direction that are perpendicular to each other. Among them, the epitaxial layer 110 and the stacked layer 120 extend along the x-direction, and the gate structure 131 extends along the y-direction.

[0086] In some embodiments of the present application, the material of the channel layer 121 includes silicon.

[0087] In some embodiments of the present application, the stacking number of the stacked layer 120 can be any suitable number. Here, the present application only takes five stacked layers as an example. Among them, the starting layer and the ending layer of the stacked layer 120 are both the channel layer 121.

[0088] In some embodiments of the present application, the thickness of the insulating layer 140 is 5 - 15 nanometers. The material of the insulating layer 140 is, for example, silicon oxide. The insulating layer 140 is a bottom dielectric isolation (BDI) structure.

[0089] In some embodiments of the present application, the thickness of the gate-all-around structure 132 is 5 - 12 nanometers; the thickness of the channel layer 121 is 5 - 12 nanometers.

[0090] The gate-all-around device structure described in the present application is, for example, a gate-all-around (GAA) device structure. The gate-all-around structure 132 surrounds the channel layer 121.

[0091] In some embodiments of the present application, the thickness of a part of the starting layer located between the stacked layers 120 is 1 - 5 nanometers.

[0092] In some embodiments of the present application, the material of the inner sidewall 160 includes silicon oxide, silicon nitride, etc.

[0093] In some embodiments of the present application, the material of the source-drain layer 170 includes silicon or germanium. The source-drain layer 170 adaptively serves as the source or drain of the CFET device described in the embodiments of the present application according to the type of voltage applied subsequently.

[0094] In the technical solution of the present application, using the starting layer channel layer of the stacked layer as the seed layer for epitaxial growth can effectively improve the quality of epitaxial growth, reduce epitaxial growth defects, and thus improve device reliability and device performance.

[0095] The technical solution of the present application has a BDI structure, and the device capacitance is greatly reduced compared to the device without the BDI structure.

[0096] The present application provides a gate-all-around device structure and a method for forming the same, which can improve the quality of source-drain epitaxy in the CFET structure, thereby improving device reliability.

[0097] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content can be presented only by way of example and may not be restrictive. Although not explicitly stated herein, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are all within the spirit and scope of the exemplary embodiments of the present application.

[0098] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.

[0099] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be an intermediate element. In contrast, the term "directly" means without an intermediate element. It should also be understood that the terms "comprise", "comprising", "include", or "including", when used in this application document, indicate the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not exclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups.

[0100] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, a first element in some embodiments may be referred to as a second element in other embodiments without departing from the teachings of this application. The same reference numerals or the same reference designators represent the same elements throughout the specification.

[0101] In addition, the present application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or three-dimensional views. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Accordingly, exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in the shapes resulting from, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Thus, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A gate-all-around device structure, characterized in that, Comprising: A semiconductor substrate, on the surface of which an insulating layer, a plurality of stacked layers, and a plurality of gate structures are sequentially formed. The stacked layers include a plurality of channel layers and a gate-all-around structure surrounding the channel layers. The starting layer and the ending layer of the stacked layers are both channel layers. The starting layers of the plurality of stacked layers are connected, and the starting layer is used as a partial substrate for the growth of the source-drain layer; Sidewalls, located on the sidewalls of the plurality of gate structures; Inner sidewalls, located on the sidewalls of the gate-all-around structure; Source-drain layers, located between the plurality of stacked layers.

2. The gate-all-around device structure according to claim 1, wherein The material of the channel layer includes silicon.

3. The gate-all-around device structure according to claim 1, characterized in that, The thickness of the gate-all-around structure is 5 - 12 nanometers; the thickness of the channel layer is 5 - 12 nanometers.

4. The gate-all-around device structure according to claim 3, wherein The thickness of a part of the starting layer located between the stacked layers is 1 - 5 nanometers.

5. A method for forming a gate-all-around device structure, characterized in that, Comprising: Providing a semiconductor substrate, on the surface of which an epitaxial layer, stacked layers, and a plurality of dummy gate structures are sequentially formed. The stacked layers include sacrificial layers and channel layers stacked alternately in sequence. The starting layer and the ending layer of the stacked layers are both channel layers; Removing the epitaxial layer to form a hollow layer; Forming an insulating layer in the hollow layer and forming sidewall layers on the sidewalls and top surfaces of the plurality of dummy gate structures and on the surface of the stacked layers; Etching the sidewall layers and the stacked layers into the starting layer of the stacked layers, removing the sidewall layers on the surface of the stacked layers and the top surfaces of the plurality of dummy gate structures, and forming sidewalls on the sidewalls of the plurality of dummy gate structures; Etching the sacrificial layers to form recesses on both sides of the sacrificial layers and forming inner sidewalls in the recesses; Epitaxially growing source-drain layers using the starting layer of the stacked layers and the channel layers as substrates.

6. The forming method of the gate-all-around device structure according to claim 5, wherein The material of the epitaxial layer includes silicon germanium, the material of the sacrificial layer includes silicon germanium, and the material of the channel layer includes silicon. Among them, the atomic number ratio of germanium in the material of the epitaxial layer is greater than the atomic number ratio of germanium in the sacrificial layer.

7. The forming method of the gate-all-around device structure according to claim 6, wherein, The atomic number ratio of germanium in the material of the epitaxial layer is greater than 45%.

8. The forming method of the gate-all-around device structure according to claim 5, characterized in that, The thickness of the sacrificial layer is 5 - 12 nanometers; the thickness of the channel layer is 5 - 12 nanometers.

9. The method for forming the gate-all-around device structure according to claim 8, wherein, After etching the sidewall layers and the stacked layers into the starting layer of the stacked layers, the remaining thickness of the starting layer of the stacked layers is 1 - 5 nanometers.

10. The forming method of the gate-all-around device structure according to claim 5, wherein, Further comprising: Removing the dummy gate structures and the sacrificial layers, forming gate structures at the positions of the dummy gate structures, and forming gate-all-around structures surrounding the channel layers at the positions of the sacrificial layers.

11. A method for forming a gate-all-around device structure, characterized in that, Comprising: Providing a semiconductor substrate, on the surface of which an epitaxial layer, stacked layers, and a plurality of dummy gate structures are sequentially formed. The stacked layers include sacrificial layers and channel layers stacked alternately in sequence. The starting layer and the ending layer of the stacked layers are both channel layers; Forming sidewall layers on the sidewalls and top surfaces of the plurality of dummy gate structures and on the surface of the stacked layers; Etching the sidewall layers and the stacked layers into the starting layer of the stacked layers, removing the sidewall layers on the surface of the stacked layers and the top surfaces of the plurality of dummy gate structures, and forming sidewalls on the sidewalls of the plurality of dummy gate structures; Etching the sacrificial layers to form recesses on both sides of the sacrificial layers and removing the epitaxial layer to form a hollow layer; Forming an insulating layer in the hollow layer and forming inner sidewalls in the recesses; Epitaxially growing source-drain layers using the starting layer of the stacked layers and the channel layers as substrates.

12. The method for forming the gate-all-around device structure according to claim 11, wherein The material of the epitaxial layer includes silicon germanium, the material of the sacrificial layer includes silicon germanium, and the material of the channel layer includes silicon. Among them, the proportion of germanium atoms in the material of the epitaxial layer is greater than the proportion of germanium atoms in the sacrificial layer.

13. The method for forming the gate-all-around device structure according to claim 12, wherein The proportion of germanium atoms in the material of the epitaxial layer is greater than 45%.

14. The method for forming the gate-all-around device structure according to claim 11, wherein The thickness of the sacrificial layer is 5 - 12 nanometers; the thickness of the channel layer is 5 - 12 nanometers.

15. The method for forming the gate-all-around device structure according to claim 14, wherein, After etching the sidewall layer and the stacked layer into the starting layer of the stacked layer, the remaining thickness of the starting layer of the stacked layer is 1 - 5 nanometers.

16. The method for forming the gate-all-around device structure according to claim 11, wherein, It further includes: Removing the dummy gate structure and the sacrificial layer, forming a gate structure at the position of the dummy gate structure, and forming a gate-all-around structure surrounding the channel layer at the position of the sacrificial layer.

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