Heat dissipation cover, chip packaging structure and electronic equipment

Abstract

The embodiment of the invention provides a heat dissipation cover, a chip packaging structure and electronic equipment, relates to the technical field of heat dissipation, and is beneficial to heat dissipation of a chip. The heat dissipation cover comprises a first surface used for being connected with the chip and a groove located in the first surface, the first surface comprises a first contact area, and in the chip packaging structure, the boundary of the orthographic projection of the chip on the first surface coincides with the boundary of the first contact area. The groove is located outside the first contact area and connected with the first contact area, and the groove extends along at least part of the boundary of the first contact area. The heat dissipation cover can be applied to a chip packaging structure and is used for dissipating heat of a chip.

Description

Heat dissipation cover, chip packaging structure and electronic equipment Technical Field

[0001] The present application relates to the field of heat dissipation technology, and in particular to a heat dissipation cover, a chip packaging structure, and an electronic device. Background Art

[0002] With the development of chip technology, the power and density of chips continue to increase. During operation, chips will generate more heat, which will affect the performance and life of the chips.

[0003] Typically, a heat dissipating lid (HDL) covers the chip, and a thermal interface material (TIM) is placed between the chip and the HDL to dissipate heat from the chip. Solder Thermal Interface Material (S-TIM) is often used as the TIM.

[0004] However, the use of soldering type thermal interface materials has the problem of relatively large thermal resistance at the contact surface between the soldering type thermal interface material and the chip, which is not conducive to heat dissipation of the chip.

[0005] Summary of the Invention

[0006] The embodiments of the present application provide a heat dissipation cover, a chip packaging structure, and an electronic device, which are beneficial to the heat dissipation of the chip.

[0007] To achieve the above objectives, the embodiments of the present application adopt the following technical solutions:

[0008] In a first aspect, a heat dissipation cover is provided. The heat dissipation cover can be used in a chip packaging structure to dissipate heat from the chip. The heat dissipation cover includes a first surface for connecting to the chip, and a groove located on the first surface. The first surface includes a first contact area. In the chip packaging structure, the boundary of the chip's orthographic projection on the first surface coincides with the boundary of the first contact area. The groove is located outside the first contact area and is connected to the first contact area. The groove extends along at least a portion of the boundary of the first contact area.

[0009] The heat sink provided in the above-mentioned embodiment of the present application includes a first surface for connecting to a chip, the first surface including a first contact area corresponding to the chip. A groove is formed on the first surface, the groove being located outside and connected to the first contact area, and the groove extending along at least a portion of the boundary of the first contact area. During the process of preparing the chip packaging structure, a sheet of solderable thermal interface material and a heat sink are sequentially arranged above the chip. During the soldering process, the sheet of solderable thermal interface material melts, and a portion of the liquid solderable thermal interface material flows into the groove and is stored due to capillary flow.

[0010] During subsequent manufacturing processes, high temperatures cause the chip's corners to warp, raising their surface area and causing the solidified solder thermal interface material to melt again, causing the liquid solder thermal interface material to drain from the chip's corners. Because the grooves connect to the first contact area, the solder thermal interface material stored in the grooves flows toward the first contact area under capillary flow, then onto the chip's surface and fills the chip's corners. Once the liquid solder thermal interface material solidifies, it completely covers the chip, reducing the thermal resistance between the contact surface of the solder thermal interface material and the chip, facilitating heat dissipation from the chip.

[0011] In some embodiments, the groove is an annular groove that surrounds the first contact area. In this way, the groove can be used to store more welding type thermal interface material. The welding type thermal interface material stored in the groove will flow to the chip surface under the action of capillary flow, which is beneficial to fill all corner areas of the chip with welding type thermal interface material.

[0012] Alternatively, the groove may be designed as a segmented groove, including at least one groove segment. The first contact area includes a corner region, and each groove segment is located outside a corner region and arranged along the boundary of the corner region. In the corner region of the chip, where warping is more severe, the solderable thermal interface material stored in the groove segment will flow toward the chip corner due to capillary flow, and after the solderable thermal interface material solidifies, it will cover the chip corner.

[0013] In some embodiments, the orthographic projection of the groove segment on the first surface is L-shaped or fan-shaped.

[0014] In some embodiments, the groove includes a side surface connected to the first contact area, and the minimum angle between the side surface of the groove and the first surface is a right angle. For example, the first surface is horizontally arranged and the side surface of the groove is vertically arranged, which is conducive to the welding type thermal interface material melted into liquid to flow out along the side surface of the groove under the action of capillary flow and gravity, and flow to the first contact area to fill the edge and corner area of ​​the chip. After the liquid welding type thermal interface material is solidified, it is ensured that the first thermal interface material layer can completely cover the chip.

[0015] Alternatively, the minimum angle between the side surface of the groove and the first surface is an obtuse angle, that is, the side surface of the groove is inclined toward the first contact area.

[0016] During the manufacturing process of the chip packaging structure, the inclined side surface can guide the soldering thermal interface material to flow toward the first contact area and fill the edge and corner areas of the chip. When the liquid soldering thermal interface material solidifies, it can completely cover the chip.

[0017] In some embodiments, the cross-section of the groove along the reference plane is in any one of rectangular, trapezoidal, semicircular, and triangular shapes, and the reference plane is perpendicular to the first surface and perpendicular to the longitudinal extension direction of the groove.

[0018] In some embodiments, the width of the groove ranges from 0.1 mm to 5 mm, and the depth ranges from 100 μm to 500 μm.

[0019] In a second aspect, a chip packaging structure is provided, which includes a chip, a thermal interface material layer and a heat dissipation cover in any of the above embodiments, wherein the thermal interface material layer is arranged on the chip, and the heat dissipation cover is arranged on the side of the thermal interface material layer away from the chip.

[0020] In the chip packaging structure provided in the above-described embodiments of the present application, the heat dissipation cover includes a first surface proximal to the chip, the first surface being connected to the chip via a thermal interface material layer. The first surface includes a first contact area, and the boundary of the chip's orthographic projection on the first surface coincides with the boundary of the first contact area. In other words, the first surface includes a first contact area corresponding to the chip.

[0021] A groove is formed on the first surface of the heat dissipation cover, and the groove is located outside the first contact area and extends along at least a portion of the boundary of the first contact area. During the preparation of the chip packaging structure, the groove is used to store excess soldering thermal interface material.

[0022] In the subsequent manufacturing process, high temperature causes the corner areas of the chip to warp, making the surface of the corner areas higher. High temperature will also melt the welding type thermal interface material, and the liquid welding type thermal interface material will flow out from the corner areas of the chip. The welding type thermal interface material stored in the groove will flow to the chip surface under the action of capillary flow and fill the corner areas of the chip. After the welding type thermal interface material is solidified, it is ensured that the thermal interface material layer can completely cover the chip to reduce the thermal resistance of the contact surface between the thermal interface material layer and the chip, which is beneficial to the heat dissipation of the chip.

[0023] In some embodiments, the chip packaging structure further includes a metal connection layer, which is located between the heat dissipation cover and the thermal interface material layer and covers the surface of the first contact area and the groove.

[0024] In the above embodiment, the metal connection layer has good wettability, that is, the liquid welding type thermal interface material has a strong spreading ability on the surface of the metal connection layer, and the liquid welding type thermal interface material flows in the area corresponding to the first contact area and the groove on the metal connection layer, which is conducive to the liquid welding type thermal interface material flowing into the groove for storage, or flowing to the chip surface, so as to fill the edge and corner areas of the chip and form a thermal interface material layer covering the chip.

[0025] In some embodiments, the metal connection layer includes a first portion and a plurality of second portions, the first portion includes a plurality of corners, and each second portion is connected to a corner of the first portion, so that the metal connection layer has an unconventional shape.

[0026] The shape of the orthographic projection of the first portion on the first surface is the same as the shape of the first contact area, and the first portion covers the first contact area, which is conducive to the flow of liquid soldering thermal interface material in the area corresponding to the first contact area on the first portion, thereby facilitating the liquid soldering thermal interface material to flow to the chip surface and fill the edge and corner areas of the chip.

[0027] The groove includes multiple groove segments, and the multiple second parts correspond to the multiple groove segments one by one. The shape of the orthographic projection of the second part on the first surface is the same as the shape of the orthographic projection of the groove segment on the first surface, and the second part covers the surface of the corresponding groove segment, which is conducive to the flow of liquid welding type thermal interface material in the area corresponding to the groove segment on the second part, thereby facilitating the liquid welding type thermal interface material to flow into the groove segment and be stored.

[0028] In some embodiments, the orthographic projections of the second portion and the groove segment on the first surface are both L-shaped, or the orthographic projections of the second portion and the groove segment on the first surface are both fan-shaped.

[0029] In some embodiments, the material of the metal connection layer includes at least one of copper, aluminum, titanium, or nickel-vanadium alloy.

[0030] In some embodiments, the orthographic projection of the chip on the first surface is within the range of the orthographic projection of the thermal interface material layer on the first surface. In other words, the orthographic projection of the thermal interface material layer on the first surface covers the orthographic projection of the chip on the first surface.

[0031] It can be understood that when the welding type thermal interface material stored in the groove is melted, a portion will flow to the chip surface under the action of capillary flow and fill the edge and corner areas of the chip, and the other portion will flow to the side of the chip under the action of gravity. After the welding type thermal interface material is solidified to form a thermal interface material layer, the orthographic projection of the chip on the first surface is located within the range of the orthographic projection of the thermal interface material layer on the first surface.

[0032] In some embodiments, the thermal interface material layer covers a portion of the side surface of the chip close to the first surface.

[0033] In some embodiments, the material of the thermal interface material layer includes at least one of indium, indium-silver alloy, tin-silver-copper alloy, or tin-bismuth-silver alloy.

[0034] According to a third aspect, an electronic device is provided. The electronic device includes a chip packaging structure and a circuit board, wherein the chip packaging structure is electrically connected to the circuit board.

[0035] It can be understood that the beneficial effects that can be achieved by the electronic device provided by the above embodiments of the present application can refer to the beneficial effects of the heat dissipation cover mentioned above, and will not be repeated here. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] To more clearly illustrate the technical solutions of this application, the following briefly introduces the drawings required for use in some embodiments of this application. Obviously, the drawings described below are only drawings of some embodiments of this application, and those skilled in the art can also derive other drawings based on these drawings. Furthermore, the drawings described below are schematic diagrams and are not intended to limit the actual dimensions of the products, actual processes of the methods, actual timing of signals, and the like involved in the embodiments of this application.

[0037] FIG1 is a schematic diagram of the structure of a server provided in an embodiment of the present application;

[0038] FIG2 is a schematic structural diagram of a chip heat dissipation system provided in an embodiment of the present application;

[0039] FIG3 is a bottom view of a heat dissipation cover provided in an embodiment of the present application;

[0040] FIG4 is a cross-sectional view of the heat dissipation cover along section line AA′ in FIG3 ;

[0041] FIG5 is a partial enlarged view of the heat dissipation cover at position M in FIG4 ;

[0042] FIG6 is a schematic structural diagram of a chip packaging structure provided in an embodiment of the present application;

[0043] FIG7 is a bottom view of another heat dissipation cover provided in an embodiment of the present application;

[0044] FIG8 is a cross-sectional view of the heat dissipation cover along section line BB′ in FIG7 ;

[0045] FIG9 is a partial enlarged view of the heat dissipation cover at position N in FIG8 ;

[0046] 10 to 12 are cross-sectional views of grooves of various heat dissipation covers provided in embodiments of the present application;

[0047] 13 to 16 are bottom views of various heat dissipation covers provided in embodiments of the present application. DETAILED DESCRIPTION

[0048] The following will be combined with the accompanying drawings to clearly and completely describe the technical solutions in some embodiments of the present application. Obviously, the embodiments described are only some embodiments of the present application, not all embodiments. Based on the embodiments provided in this application, all other embodiments obtained by ordinary technicians in this field are within the scope of protection of this application.

[0049] In the description of this application, it should be understood that the terms "center", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, and are only for the convenience of describing this application and simplifying the description, rather than indicating or implying that the device or element referred to has a specific orientation, is constructed and operated in a specific orientation, and therefore cannot be understood as a limitation on this application.

[0050] Unless the context requires otherwise, throughout the specification and claims, the term "including" is to be interpreted as having an open, inclusive meaning, that is, "including, but not limited to." In the description of the specification, the terms "one embodiment," "some embodiments," "exemplary embodiments," "exemplarily," or "some examples" are intended to indicate that specific features, structures, materials, or characteristics associated with the embodiment or example are included in at least one embodiment or example of the present application. The schematic representations of the above terms do not necessarily refer to the same embodiment or example. In addition, the specific features, structures, materials, or characteristics may be included in any one or more embodiments or examples in any appropriate manner.

[0051] In the following, the terms "first" and "second" are used for descriptive purposes only and should not be understood as indicating or implying relative importance or implicitly indicating the number of the technical features indicated. Therefore, a feature defined as "first" or "second" may explicitly or implicitly include one or more of the features. In the description of the embodiments of this application, unless otherwise specified, "plurality" means two or more.

[0052] When describing some embodiments, the term "connected" and its derivatives may be used. For example, when describing some embodiments, the term "connected" may be used to indicate that two or more components are in direct physical or electrical contact with each other. The embodiments claimed herein are not necessarily limited to the contents herein.

[0053] “A and / or B” includes the following three combinations: A only, B only, and a combination of A and B.

[0054] The use of "configured to" herein is intended to be open and inclusive language that does not exclude devices adapted or configured to perform additional tasks or steps.

[0055] Additionally, the use of “based on” is meant to be open and inclusive, as a process, step, calculation, or other action “based on” one or more stated conditions or values ​​may, in practice, be based on additional conditions or values ​​beyond those stated.

[0056] Exemplary embodiments are described herein with reference to cross-sectional and / or plan views that are idealized exemplary drawings. In the drawings, the thicknesses of layers and regions are exaggerated for clarity. Therefore, variations in shape relative to the drawings due to, for example, manufacturing techniques and / or tolerances are contemplated. Therefore, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but rather include deviations in shape due to, for example, manufacturing. For example, an etched region shown as a rectangle will typically have curved features. Therefore, the regions shown in the drawings are schematic in nature, and their shapes are not intended to illustrate the actual shape of regions of the device and are not intended to limit the scope of the exemplary embodiments.

[0057] Some embodiments of the present application provide an electronic device, which may be a supercomputer, a vehicle-mounted device, a smart home device and / or a smart city device, a server, a workstation, a data center, etc. The embodiments of the present application do not impose any special restrictions on the specific type of the electronic device.

[0058] For the convenience of explanation, the following description will be given by taking the electronic device as a server as an example, but the embodiments of the present application are not limited to this.

[0059] FIG1 is a schematic diagram of the structure of a server provided in an embodiment of the present application.

[0060] Referring to Figure 1 , a server 1 includes a cabinet 2, a circuit board 3 disposed within the cabinet 2, and a chip packaging structure 4. The chip packaging structure 4 includes a chip and a structure for packaging the chip. The chip packaging structure 4 is disposed on the circuit board 3 and is electrically connected to the circuit board 3. The circuit board 3 includes, but is not limited to, a printed circuit board (PCB).

[0061] With the development of chip technology, the power and density of chips continue to increase. During operation, chips generate a lot of heat, which affects the performance and lifespan of the chips. To achieve chip heat dissipation, the server 1 is generally provided with a structure for dissipating heat from the chips. This structure, together with the chips and circuit boards, forms a chip heat dissipation system. Figure 2 is a schematic diagram of the structure of the chip heat dissipation system provided in an embodiment of the present application.

[0062] 2 , the chip heat dissipation system 10 includes a circuit board 3 and a chip packaging structure 4 . The chip packaging structure 4 is connected to the circuit board 3 via a bonding structure.

[0063] For example, the bonding structure generally includes a solder bump, a solder ball, or a copper pillar. For example, the chip package structure 4 is connected to the circuit board 3 via a solder ball.

[0064] The chip packaging structure 4 may adopt a flip chip ball grid array (FC-BGA) packaging design. The chip packaging structure 4 includes a packaging substrate 41 and a chip 42. The chip 42 is disposed on the packaging substrate 41 and connected to the packaging substrate 41 via a bonding structure.

[0065] Exemplarily, the chip 42 is connected to the package substrate 41 via solder bumps. A filling layer 43 is also provided at the bottom of the chip 42. The filling layer 43 is located between the chip 42 and the package substrate 41 and wraps the solder bumps to improve the connection strength between the chip 42 and the package substrate 41.

[0066] The chip packaging structure 4 provided in the embodiment of the present application is not limited to the above-mentioned design.

[0067] Continuing with FIG2 , the chip package structure 4 further includes a first thermal interface material layer 44 and a heat dissipating lid (HDL) 45. The first thermal interface material layer 44 is disposed on the chip 42, and the heat dissipating lid 45 is disposed on a side of the first thermal interface material layer 44 away from the chip 42. During operation, the chip 42 generates a significant amount of heat, which is conducted away through the first thermal interface material layer 44 and the heat dissipating lid 45 to dissipate heat from the chip 42.

[0068] Exemplarily, the heat dissipation cover 45 may be a copper lid, a micro-fluidic channel lid (MCL), a vapor chamber lid (VCL), or the like.

[0069] Exemplarily, the material of the heat dissipation cover 45 may include copper.

[0070] For example, the heat dissipation cover 45 may be bonded to the package substrate 41 by an adhesive.

[0071] In addition, referring to FIG2 , the chip heat dissipation system 10 further includes a second thermal interface material layer 5 and a heat sink 6. The second thermal interface material layer 5 is disposed on the heat dissipation cover 45, and the heat sink 6 is disposed on a side of the second thermal interface material layer 5 away from the heat dissipation cover 45. The second thermal interface material layer 5 and the heat sink 6 can conduct heat away from the heat dissipation cover 45, further improving the heat dissipation efficiency of the chip 42.

[0072] Both the first thermal interface material layer 44 and the second thermal interface material layer 5 comprise a thermal interface material (TIM). Compared to carbon-based and silicon-based TIMs, solderable thermal interface materials (S-TIMs) offer superior thermal conductivity and mechanical properties. For example, S-TIMs comprise at least one of indium (chemical formula: In), indium-silver alloy (chemical formula: InAg), tin-silver-copper alloy (chemical formula: SnAgCu), or tin-bismuth-silver alloy (chemical formula: SnBiAg). Therefore, the first and second thermal interface material layers 44 and 5 can be made of solderable TIMs, which improves the heat dissipation efficiency of the chip 42 and enhances the structural connection strength.

[0073] However, during the preparation of the chip heat dissipation system 10, some process steps need to be performed in a high-temperature environment. High temperatures can cause the chip 42 to warp, typically severely warping the corners of the chip 42. Furthermore, high temperatures can cause the first thermal interface material layer 44 to melt into liquid solder-type thermal interface material. Since the corners of the chip 42 are severely warped, the surface of the corners is higher, and the liquid solder-type thermal interface material can flow from the corners of the chip 42. After the solder-type thermal interface material solidifies again, the formed first thermal interface material layer 44 cannot completely cover the chip 42, thereby increasing the thermal resistance of the contact surface between the first thermal interface material layer 44 and the chip 42, which is not conducive to the heat dissipation of the chip 42.

[0074] To solve the above problems, some embodiments of the present application provide a heat dissipation cover. Figure 3 is a bottom view of a heat dissipation cover provided in an embodiment of the present application; Figure 4 is a cross-sectional view of the heat dissipation cover along section line AA' in Figure 3; Figure 5 is a partial enlarged view of the heat dissipation cover at point M in Figure 4; and Figure 6 is a structural schematic diagram of the chip packaging structure provided in an embodiment of the present application.

[0075] 3 to 6 , the chip packaging structure 4 includes a chip 42, a first thermal interface material layer 44, and a heat dissipation cover 45. The first thermal interface material layer 44 is disposed on the chip 42, and the heat dissipation cover 45 is disposed on a side of the first thermal interface material layer 44 away from the chip 42. The heat dissipation cover 45 includes a first surface P1 close to the chip 42 and a groove 7 located on the first surface P1.

[0076] It can be understood that the first surface P1 of the heat dissipation cover 45 is the bottom surface of the heat dissipation cover 45. The bottom surface of the heat dissipation cover 45 is provided with a groove 7. The bottom surface of the heat dissipation cover 45 is used to connect with the chip 42. For example, the bottom surface of the heat dissipation cover 45 is connected to the chip 42 through the first thermal interface material layer 44.

[0077] There may be multiple methods for preparing the groove 7. For example, in an embodiment of the present application, a photolithography process may be used. First, a photoresist layer is formed on the bottom surface of the heat dissipation cover 45. Then, the photoresist layer is exposed and developed so that the photoresist layer only exposes the area where the groove 7 is located. Finally, the photoresist layer is used as a mask to etch the bottom surface of the heat dissipation cover 45 to form the groove 7.

[0078] Exemplarily, the width of the groove 7 ranges from 0.1 mm to 5 mm, for example, the width of the groove 7 is 0.1 mm, 1 mm, 2.5 mm, 4 mm or 5 mm.

[0079] Exemplarily, the depth of the groove 7 ranges from 100 μm to 500 μm, for example, the depth of the groove 7 is 100 μm, 200 μm, 300 μm, 400 μm or 500 μm.

[0080] Referring to Figures 3 to 6 , first surface P1 of heat dissipation cover 45 includes a first contact region P2. In chip package structure 4, the boundary of the orthographic projection of chip 42 on first surface P1 coincides with the boundary of first contact region P2. That is, along the thickness direction Z of chip package structure 4, chip 42 corresponds to first contact region P2 of heat dissipation cover 45.

[0081] It can be understood that the shape of the orthographic projection of the chip 42 on the first surface P1 is the same as the shape of the first contact region P2 , and the areas of the two are equal.

[0082] Exemplarily, the shape of the orthographic projection of the chip 42 on the first surface P1 is a rectangle, and the shape of the first contact area P2 is also a rectangle. Figure 3 shows the case where the first contact area P2 is a rectangle. The embodiments of the present application are not limited to this. The shape of the first contact area P2 can be adjusted according to the shape of the orthographic projection of the chip 42 on the first surface P1 so that the first contact area P2 has the same shape as the chip 42.

[0083] 3 to 6 , on the first surface P1 of the heat dissipation cover 45 , the groove 7 is located outside the first contact area P2 and is connected to the first contact area P2 . The groove 7 extends along at least a portion of the boundary of the first contact area P2 .

[0084] 3 , the trench 7 has an edge close to the first contact region P2 and an edge away from the first contact region P2 , and the edge of the trench 7 close to the first contact region P2 coincides with at least a portion of the boundary of the first contact region P2 .

[0085] Exemplarily, referring to FIG3 , the groove 7 is an annular groove, which surrounds the first contact area P2 and is arranged along the entire boundary of the first contact area P2 . The edge of the groove 7 close to the first contact area P2 coincides with the entire boundary of the first contact area P2 .

[0086] In the chip package structure 4 provided in the above-described embodiment of the present application, the heat dissipation cover 45 includes a first surface P1 proximate to the chip 42. The first surface P1 is connected to the chip 42 via the first thermal interface material layer 44. The first surface P1 includes a first contact area P2. The boundary of the orthographic projection of the chip 42 on the first surface P1 coincides with the boundary of the first contact area P2. That is, the bottom surface of the heat dissipation cover 45 has a first contact area P2 corresponding to the chip 42.

[0087] A groove 7 is formed on the first surface P1 of the heat dissipation cover 45. The groove 7 is located outside the first contact area P2 and is connected to the first contact area P2. The groove 7 extends along at least a portion of the boundary of the first contact area P2. During the preparation of the chip packaging structure 4, a sheet-like welding type thermal interface material and a heat dissipation cover 45 are sequentially arranged above the chip 42. During the welding process, the sheet-like welding type thermal interface material melts, and the liquid welding type thermal interface material partially flows into the groove 7 and is stored under the action of capillary flow. After the liquid welding type thermal interface material solidifies, a first thermal interface material layer 44 surrounding the chip 42 is formed.

[0088] In subsequent manufacturing processes, such as during the ball mounting (BM) of the bottom of the package substrate 41 in the chip package structure 4, or during the process of bonding the package substrate 41 of the chip package structure 4 to the circuit board 3 using surface mounting technology (SMT), high temperatures cause the corner areas of the chip 42 to warp, resulting in a higher surface area in the corner areas. Furthermore, high temperatures can melt the first thermal interface material layer 44, causing the liquid solder-type thermal interface material to flow from the corner areas of the chip 42. Because the groove 7 is connected to the first contact area P2, the solder-type thermal interface material stored in the groove 7 flows toward the first contact area P2 under capillary flow, flows to the surface of the chip 42, and fills the corner areas of the chip 42. After the liquid solder-type thermal interface material solidifies, the first thermal interface material layer 44 is ensured to completely cover the chip 42, thereby reducing the thermal resistance of the contact surface between the first thermal interface material layer 44 and the chip 42, which is beneficial to heat dissipation of the chip 42.

[0089] Furthermore, by setting the groove 7 around the first contact area P2, that is, the groove 7 is set along the entire boundary of the first contact area P2, the groove 7 can be used to store more welding type thermal interface material, which is beneficial to fill all corner areas of the chip 42 with welding type thermal interface material.

[0090] In some embodiments, referring to FIG. 6 , the orthographic projection of the chip 42 on the first surface P1 is within the range of the orthographic projection of the first thermal interface material layer 44 on the first surface P1. In other words, the orthographic projection of the first thermal interface material layer 44 on the first surface P1 covers the orthographic projection of the chip 42 on the first surface P1.

[0091] It can be understood that when the welding type thermal interface material stored in the groove 7 is melted, a portion will flow to the surface of the chip 42 under the action of capillary flow, filling the edge and corner areas of the chip 42, and the other portion will flow to the side of the chip 42 under the action of gravity. After the welding type thermal interface material is solidified to form the first thermal interface material layer 44, the orthographic projection of the chip 42 on the first surface P1 is located within the range of the orthographic projection of the first thermal interface material layer 44 on the first surface P1.

[0092] Exemplarily, a boundary of the orthographic projection of the first thermal interface material layer 44 on the first surface P1 exceeds a boundary of the orthographic projection of the chip 42 on the first surface P1 .

[0093] For example, the first thermal interface material layer 44 includes a middle portion located between the chip 42 and the heat dissipation cover 45, and an edge portion surrounding the middle portion. The middle portion corresponds to the chip 42 and the first contact area P2 and is used to conduct heat generated by the chip 42 to the heat dissipation cover 45. The edge portion of the first thermal interface material layer 44 covers the side surfaces of the chip 42 (the portion of the side surfaces close to the first surface P1, i.e., the portion of the side surfaces close to the top of the chip 42), protecting the middle portion and slowing down the oxidation rate of the middle portion to ensure the thermal conductivity of the middle portion, thereby ensuring the long-term heat dissipation reliability of the chip 42.

[0094] In some embodiments, referring to FIG. 3 to FIG. 6 , the chip package structure 4 further includes a metal connection layer 46 , which is located between the heat dissipation cover 45 and the first thermal interface material layer 44 and covers the first contact area P2 of the heat dissipation cover 45 and the surface of the groove 7 .

[0095] Exemplarily, the material of the metal connection layer 46 includes at least one of copper (chemical formula: Au), aluminum (chemical formula: Al), titanium (chemical formula: Ti) or nickel-vanadium alloy (chemical formula: NiV), and an electroplating process can be used to form a metal connection layer 46 with uniform thickness on the surface of the first contact area P2 of the heat dissipation cover 45 and the groove 7.

[0096] 3 , the boundary of the orthographic projection of the metal connection layer 46 on the first surface P1 exceeds the outer boundary of the trench 7. In other examples, the boundary of the orthographic projection of the metal connection layer 46 on the first surface P1 may also coincide with the outer boundary of the trench 7.

[0097] During the preparation of the chip packaging structure 4, a sheet-like welding type thermal interface material is arranged above the chip 42. Usually, the orthographic projection of the metal connection layer 46 on the first surface P1 is located within the range of the orthographic projection of the sheet-like welding type thermal interface material on the first surface P1. In other words, the sheet-like welding type thermal interface material covers the metal connection layer 46. During the welding process, the sheet-like welding type thermal interface material melts, which is conducive to the liquid welding type thermal interface material covering the surface of the metal connection layer 46.

[0098] The metal connection layer 46 has good wettability, meaning that the liquid soldering thermal interface material has a strong ability to spread on the surface of the metal connection layer 46. Providing the metal connection layer 46 to cover the first contact area P2 and the surface of the groove 7 facilitates the flow of the liquid soldering thermal interface material in the area of ​​the metal connection layer 46 corresponding to the first contact area P2 and the groove 7. This facilitates the liquid soldering thermal interface material to flow into the groove 7 for storage, or to flow to the surface of the chip 42 and fill the corner areas of the chip 42, forming a first thermal interface material layer 44 covering the chip 42.

[0099] In some embodiments, referring to FIG. 5 and FIG. 6 , the trench 7 includes a side surface 71 connected to the first contact region P2 , and a minimum angle α between the side surface 71 of the trench 7 and the first surface P1 is a right angle (α=90°).

[0100] Exemplarily, the first surface P1 is parallel to the plane XY, and the side surface 71 of the groove 7 is parallel to the direction Z and perpendicular to the first surface P1.

[0101] For example, in the manufacturing process of the chip packaging structure 4, by setting the first surface P1 horizontally and the side 71 of the groove 7 vertically, it is beneficial for the welding type thermal interface material melted into liquid to flow out along the side 71 of the groove 7 under the action of capillary flow and gravity, and flow along the surface of the metal connection layer 46 to the first contact area P2 to fill the edge and corner areas of the chip 42. After the liquid welding type thermal interface material is solidified, it is ensured that the first thermal interface material layer 44 can completely cover the chip 42.

[0102] Exemplarily, the cross-section of the trench 7 along the reference plane R is rectangular. Referring to FIG. 3 , the reference plane R is perpendicular to the first surface P1 and perpendicular to the longitudinal extension direction L of the trench 7 .

[0103] 7 is a bottom view of another heat dissipation cover provided in an embodiment of the present application; FIG8 is a cross-sectional view of the heat dissipation cover in FIG7 along section line BB′; and FIG9 is a partial enlarged view of the heat dissipation cover in FIG8 at position N.

[0104] 7 to 9 , the minimum angle β between the side surface 71 of the groove 7 and the first surface P1 is an obtuse angle (90°<β<180°), that is, the side surface 71 of the groove 7 is inclined toward the first contact area P2. The inclined side surface 71 can guide the welding type thermal interface material to flow toward the first contact area P2 (flowing on the surface of the metal connection layer 46) and fill the edge and corner areas of the chip 42. After the liquid welding type thermal interface material is solidified, it is ensured that the first thermal interface material layer 44 can completely cover the chip 42.

[0105] Exemplarily, referring to FIG. 9 , the shape of the cross section of the groove 7 along the reference plane R is a trapezoid, for example, the shape of the cross section of the groove 7 is an isosceles trapezoid.

[0106] 10 to 12 are cross-sectional views of grooves of various heat dissipation covers provided in embodiments of the present application.

[0107] 10 , the cross-section of the groove 7 along the reference plane R is in the shape of a right-angled trapezoid.

[0108] 11 , the cross-section of the groove 7 along the reference plane R is in the shape of a triangle.

[0109] 12 , the cross-section of the groove 7 along the reference plane R is in the shape of a semicircle.

[0110] In the embodiment of the present application, the cross-sectional shape of the groove 7 is not limited thereto.

[0111] 13 to 16 are bottom views of various heat dissipation covers provided in embodiments of the present application.

[0112] 13 and 14 , the first contact region P2 includes a corner region P3 . For ease of illustration, the corner region P3 is exemplarily enclosed by a dotted line in the figures, but the contour of the corner region P3 is not limited thereto.

[0113] As described above, the chip 42 corresponds to the first contact area P2 of the heat dissipation cover 45 . Therefore, the corner portion of the chip 42 corresponds to the corner area P3 of the first contact area P2 .

[0114] Continuing with Figures 13 and 14 , the groove 7 includes multiple groove segments 72. Each groove segment 72 is located outside each corner region P3 of the first contact region P2, and each groove segment 72 is arranged along the boundary of the corner region P3. The groove 7 is designed in a segmented manner and does not surround the first contact region P2.

[0115] Exemplarily, the shape of the positive projection of the chip 42 on the first surface P1 is a rectangle, the shape of the first contact area P2 is also a rectangle, and the first contact area P2 has four corner areas P3. In this case, the groove 7 includes four groove segments 72, and each groove segment 72 corresponds to a corner area P3.

[0116] Exemplarily, referring to FIG. 13 , the orthographic projection of the groove segment 72 on the first surface P1 is in an L-shape.

[0117] Exemplarily, referring to FIG. 14 , the orthographic projection of the groove segment 72 on the first surface P1 is in the shape of a sector.

[0118] It is understandable that in the corner areas of the chip 42, the warping is more serious at the corners. When the first thermal interface material layer 44 is melted, the liquid welding type thermal interface material is easy to flow away from the corners of the chip 42 under the action of gravity. After the liquid welding type thermal interface material solidifies, the first thermal interface material layer 44 will not be able to cover the corners of the chip 42.

[0119] Based on this, grooves 72 are formed in the first surface P1 of the heat dissipation cover 45. Each groove 72 is located outside each corner region P3 of the first contact region P2 and along the boundary of each corner region P3. During the preparation of the chip package structure 4 and the soldering process, the liquid soldering thermal interface material will partially flow into the grooves 72 due to capillary flow and be stored.

[0120] In the subsequent manufacturing process, the corners of the chip 42 warp, and the liquid welding type thermal interface material flows away from the corners of the chip 42. The welding type thermal interface material stored in the groove section 72 will flow to the corners of the chip 42 under the action of capillary flow. After the liquid welding type thermal interface material solidifies, it is ensured that the first thermal interface material layer 44 can cover the corners of the chip 42.

[0121] From the above, it can be seen that in the embodiment of the present application, the groove 7 can be designed as an annular groove or a segmented groove.

[0122] In addition, the metal connection layer 46 may also have various pattern designs.

[0123] 13 and 14 , the metal connection layer 46 may have a conventional shape, for example, the metal connection layer 46 may be rectangular, circular, or the like.

[0124] The metal connection layer 46 may also have unconventional shapes.

[0125] 15 and 16 , the metal connection layer 46 includes a first portion S1 and a plurality of second portions S2 . The first portion S1 includes a plurality of corners S3 , and each second portion S2 is connected to a corner S3 of the first portion S1 .

[0126] The orthographic projection of the first portion S1 on the first surface P1 of the heat dissipation cover 45 has the same shape as the first contact area P2 , and the first portion S1 covers the first contact area P2 .

[0127] Since the shape of the orthographic projection of the chip 42 on the first surface P1 is the same as the shape of the first contact area P2, and the areas of the two are equal, the shape of the orthographic projection of the first portion S1 on the first surface P1 is the same as the shape of the orthographic projection of the chip 42 on the first surface P1, and the orthographic projection of the first portion S1 on the first surface P1 covers the orthographic projection of the chip 42 on the first surface P1.

[0128] Exemplarily, the orthographic projection of the chip 42 on the first surface P1 is a rectangle, the shape of the first contact region P2 is a rectangle, and the orthographic projection of the first portion S1 on the first surface P1 is also a rectangle.

[0129] By setting the first portion S1 of the metal connection layer 46 to cover the first contact area P2, the liquid soldering thermal interface material is facilitated to flow in the area corresponding to the first contact area P2 on the first portion S1, thereby facilitating the liquid soldering thermal interface material to flow to the surface of the chip 42 and fill the edge and corner areas of the chip 42.

[0130] Continuing with FIG. 15 and FIG. 16 , when the trench 7 adopts a segmented trench design, the plurality of second portions S2 of the metal connection layer 46 correspond one-to-one with the plurality of trench segments 72 of the trench 7. The orthographic projection of the second portion S2 on the first surface P1 is identical to the orthographic projection of the trench segment 72 on the first surface P1. Furthermore, the second portion S2 covers the surface of the corresponding trench segment 72.

[0131] Exemplarily, referring to FIG. 15 , the orthographic projection of the groove segment 72 on the first surface P1 is in an L-shape, and the orthographic projection of the second portion S2 on the first surface P1 is also in an L-shape.

[0132] Exemplarily, referring to FIG. 16 , the orthographic projection of the groove segment 72 on the first surface P1 is in the shape of a sector, and the orthographic projection of the second portion S2 on the first surface P1 is also in the shape of a sector.

[0133] By providing the second portion S2 of the metal connection layer 46 to cover the surface of the groove section 72 , the liquid welding type thermal interface material is facilitated to flow in the area corresponding to the groove section 72 on the second portion S2 , thereby facilitating the liquid welding type thermal interface material to flow into the groove section 72 for storage.

[0134] The heat sink provided in an embodiment of the present application includes a first surface (bottom surface) for connecting to a chip, the first surface of the heat sink having a first contact area corresponding to the chip. A groove is formed in the first surface of the heat sink, the groove being located outside the first contact area and extending along at least a portion of the boundary of the first contact area. During the preparation of the chip packaging structure, the groove is used to store excess solder-type thermal interface material.

[0135] In the subsequent manufacturing process, high temperature causes the corner areas of the chip to warp, making the surface of the corner areas higher. High temperature also causes the soldering thermal interface material to melt, and the liquid soldering thermal interface material will flow out from the corner areas of the chip. The soldering thermal interface material stored in the groove will flow to the chip surface under the action of capillary flow and fill the corner areas of the chip. After the soldering thermal interface material is solidified, it can completely cover the chip to reduce the thermal resistance of the contact surface between the soldering thermal interface material and the chip, which is beneficial to the heat dissipation of the chip.

[0136] Furthermore, the groove can be designed as an annular groove or divided into segments. In the case of an annular groove, the groove is arranged around the first contact area, and the groove can be used to store a large amount of solder-type thermal interface material, which is conducive to filling all corner areas of the chip with solder-type thermal interface material. In the case of a segmented groove, each groove segment is arranged at each corner area of ​​the first contact area. The corner areas of the chip are more prone to warping. The solder-type thermal interface material stored in the groove segment will flow to the corner areas of the chip due to capillary flow. After the solder-type thermal interface material solidifies, it can cover the corner areas of the chip.

[0137] In addition, the groove includes a side surface connected to the first contact area, and the minimum angle between the side surface of the groove and the first surface is an obtuse angle. For example, the cross-sectional shape of the groove can be a trapezoid, a semicircle or a triangle, and the side surface of the groove is inclined toward the first contact area. The inclined side surface can guide the welding type thermal interface material to flow toward the first contact area, and the welding type thermal interface material can completely cover the chip after solidification.

[0138] The beneficial effects achieved by the chip packaging structure and electronic device provided in the embodiments of the present application can be referred to the beneficial effects of the heat dissipation cover, which will not be repeated here.

[0139] The above description is merely a specific embodiment of the present application, but the scope of protection of the present application is not limited thereto. Any changes or substitutions that a person skilled in the art can conceive within the technical scope disclosed in this application should be included within the scope of protection of the present application. Therefore, the scope of protection of the present application should be based on the scope of protection of the claims.

Claims

1. A chip packaging structure, characterized in that: include: chip; A thermal interface material layer is disposed on the chip; A heat dissipation cover, arranged on a side of the thermal interface material layer away from the chip; Wherein, the heat dissipation cover comprises a first surface close to one side of the chip, and a groove located on the first surface; The first surface comprises a first contact area, and a boundary of an orthographic projection of the chip on the first surface coincides with a boundary of the first contact area; The groove is located outside the first contact area and connected to the first contact area, and the groove is extended along at least a portion of a boundary of the first contact area.

2. The chip packaging structure according to claim 1, characterized in that: The groove surrounds the first contact region; or, The first contact area includes a corner area, and the groove includes at least one groove segment; the groove segment is located outside the corner area and is arranged along a boundary of the corner area.

3. The chip packaging structure according to claim 1 or 2, characterized in that: The groove includes a side surface connected to the first contact area, and the minimum angle between the side surface of the groove and the first surface is a right angle or an obtuse angle.

4. The chip packaging structure according to claim 3, characterized in that: The cross-section of the groove along the reference surface is in any one of a rectangular, a trapezoidal, a semicircular or a triangular shape; The reference plane is perpendicular to the first surface and perpendicular to the length extension direction of the groove.

5. The chip packaging structure according to any one of claims 1 to 4, characterized in that: The chip packaging structure further comprises a metal connection layer, which is located between the heat dissipation cover and the thermal interface material layer; The metal connection layer covers surfaces of the first contact region and the trench.

6. The chip packaging structure according to claim 5, characterized in that: The metal connection layer includes a first portion and a plurality of second portions, the first portion includes a plurality of corners, and each of the second portions is connected to a corner of the first portion; The shape of the orthographic projection of the first portion on the first surface is the same as the shape of the first contact area; The first portion covers the first contact area; The groove includes a plurality of groove segments, and the plurality of second portions correspond one-to-one to the plurality of groove segments; The shape of the orthographic projection of the second portion on the first surface is the same as the shape of the orthographic projection of the groove segment on the first surface; the second portion covers the surface of the corresponding groove segment.

7. The chip packaging structure according to claim 6, characterized in that: The orthographic projections of the second portion and the groove segment on the first surface are both L-shaped; or, The orthographic projections of the second portion and the groove segment on the first surface are both fan-shaped.

8. The chip packaging structure according to any one of claims 5 to 7, characterized in that: The material of the metal connection layer includes at least one of copper, aluminum, titanium or nickel-vanadium alloy.

9. The chip packaging structure according to any one of claims 1 to 8, characterized in that: The orthographic projection of the chip on the first surface is located within the range of the orthographic projection of the thermal interface material layer on the first surface.

10. The chip packaging structure according to claim 9, characterized in that: The thermal interface material layer covers a portion of the side surface of the chip close to the first surface.

11. The chip packaging structure according to any one of claims 1 to 10, characterized in that: The material of the thermal interface material layer includes at least one of indium, indium silver alloy, tin-silver-copper alloy or tin-bismuth-silver alloy.

12. The chip packaging structure according to any one of claims 1 to 11, characterized in that: The width of the groove ranges from 0.1 mm to 5 mm; The depth of the groove ranges from 100 μm to 500 μm.

13. A heat dissipation cover, characterized in that: The heat dissipation cover comprises a first surface and a groove located on the first surface, wherein the first surface is configured to be connected to the chip; The first surface comprises a first contact area, and a boundary of an orthographic projection of the chip on the first surface coincides with a boundary of the first contact area; The groove is located outside the first contact region and extends along at least a portion of a boundary of the first contact region.

14. The heat dissipation cover according to claim 13, characterized in that: The groove surrounds the first contact region; or, The first contact area includes a corner area, and the groove includes at least one groove segment; the groove segment is located outside the corner area and is arranged along a boundary of the corner area.

15. The heat dissipation cover according to claim 14, characterized in that: The orthographic projection of the groove segment on the first surface is in an L-shape or a fan-shape.

16. The heat dissipation cover according to any one of claims 13 to 15, characterized in that: The groove includes a side surface connected to the first contact area, and the minimum angle between the side surface of the groove and the first surface is a right angle or an obtuse angle.

17. The heat dissipation cover according to claim 16, characterized in that: The cross-section of the groove along the reference surface is in any one of a rectangular, a trapezoidal, a semicircular or a triangular shape; The reference plane is perpendicular to the first surface and perpendicular to the length extension direction of the groove.

18. The heat dissipation cover according to any one of claims 13 to 17, characterized in that: The width of the groove ranges from 0.1 mm to 5 mm; The depth of the groove ranges from 100 μm to 500 μm.

19. An electronic device, characterized in that: include: The chip packaging structure according to any one of claims 1 to 12; A circuit board, the chip packaging structure is electrically connected to the circuit board.

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