Operating mode conversion options for boost converter

Abstract

A controller (140A) includes a ramp circuit (220) and control logic (260). The ramp circuit (220) includes: ramp generation circuitry having a first control input and a first current output; a ramp adjustment circuitry having a second control input and a second current output; current scaling circuitry having a first current input, a current sense output, and an offset current output, the first current input coupled to the first current output and the second current output; and ramp completion circuitry having a current sense input and a completion output, the current sense input coupled to the current sense output. The control logic (260) has a third control input (263) and first and second control outputs (266 and 267). The third control input (263) is coupled to the completion output. The first control output (266) is coupled to the first control input. The second control output (267) is coupled to the second control input.

Description

Background Art

[0001] A boost converter supplies a higher output voltage (V IN ) to a load based on a lower input voltage (V OUT ). An example system may include: a power supply configured to provide V IN ; a boost converter; an output capacitor (C OUT ); and a load. In many systems, the power consumption of the load may vary over time. Properly managing reverse current (current flow from the output node of the boost converter to the input node) and mode of operation transitions (e.g., transitions between power-off / power-on of the system or transitions between varying load states) are ongoing challenges in boost converter applications.

[0002] In a conventional approach, C OUT may be charged by an additional backup battery before being regulated by the boost converter. To avoid reverse current at startup (and associated reduced lifetime of the backup battery), forced discontinuous conduction mode (DCM), also known as pulse frequency modulation (PFM) in this context, may be used. After startup, continuous conduction mode (CCM) may be preferred (e.g., to mitigate electromagnetic interference (EMI) issues). In a conventional approach, a dual-loop control scheme uses a voltage loop to regulate V OUT , and uses a current loop to control the inductor current. In addition to the current loop, valley current sensing may be used to control the inductor current. To support reverse current (which may be desirable for some applications), an offset current (I OFFSET ) may be used to modify the sensed current (I SNS ) of the boost converter. Even during a soft-start interval, a conventional boost converter controller may apply I OFFSET to CCM operation. However, as shown in Equation 1, I OFFSET reduces I SNS , and thus affects the valley control operation of the boost converter controller.

[0003]

[0004] The result of applying I OFFSET is that the average inductor current of the boost converter decreases due to I SNS being lower. If I OFFSET suddenly increases, then I SNS suddenly decreases, and even if the load has not changed, V OUT will drop. This is because less power is transferred in subsequent cycles. Eventually, the voltage loop will regulate V REF with a higher reference current (I OUT ). Such a drop in V OUT results in an undesired less monotonic output waveform.

[0005] There are two conventional solutions to reduce V OUT drop. The first solution divides I OFFSET into smaller parts and injects each part at corresponding time intervals. With the first solution, V OUT drops less, but the V OUT waveform is not smooth and has multiple smaller drops. The second solution uses a load transient enhancement function in the boost converter control loop to reduce V OUT drop. However, the load transient enhancement function is limited and may not result in the target V OUT stability of the system. SUMMARY OF THE INVENTION

[0006] In an example, a controller includes a ramp circuit and control logic. The ramp circuit includes: a ramp generation circuitry having a first control input and a first current output; a ramp adjustment circuitry having a second control input and a second current output; a current scaling circuitry having a first current input, a current sense output, and an offset current output, the first current input being coupled to the first current output and the second current output; and a ramp completion circuitry having a current sense input and a completion output, the current sense input being coupled to the current sense output. The control logic has a third control input and a first control output and a second control output. The third control input is coupled to the completion output. The first control output is coupled to the first control input. The second control output is coupled to the second control input.

[0007] A system includes a power stage having a power input, a first ground terminal, a first control input and a second control input, and a power output. The system further includes a controller having a sense input, a second ground terminal, and a first control output and a second control output. The sense input is coupled to the power output. The first control output is coupled to the first control input. The second control output is coupled to the second control input. The controller includes a ramp circuit and control logic. The ramp circuit includes: a ramp generation circuitry having a third control input and a first current output; a ramp adjustment circuitry having a fourth control input and a second current output; a current scaling circuitry having a first current input, a current sense output, and an offset current output, the first current input being coupled to the first current output and the second current output; and a ramp completion circuitry having a current sense input and a completion output, the current sense input being coupled to the current sense output. The control logic has a fifth control input and a third control output and a fourth control output. The fifth control input is coupled to the completion output. The third control output is coupled to the third control input. The fourth control output is coupled to the fourth control input. BRIEF DESCRIPTION OF THE DRAWINGS

[0008] Figure 1Block diagram showing the system in an example.

[0009] Figure 2 Another block diagram showing the system in an example.

[0010] Figure 3 Schematic diagram showing the boost converter power stage and valley current sensing circuit in an example.

[0011] Figure 4 To show the offset current (I OFFSET ) ramp circuit schematic.

[0012] Figure 5 Schematic diagram showing the discharge circuit in an example.

[0013] Figure 6 Schematic diagram showing the one-time compensation circuit in an example.

[0014] Figure 7 Schematic diagram showing the error amplifier and compensation network circuit in an example.

[0015] Figure 8 Schematic diagram showing the switch control circuit in an example.

[0016] Figure 9 and 10 Graph showing signals related to the boost converter controller options in an example.

[0017] Figure 11 Graph showing the output voltage and inductor current signals with and without the boost converter controller option in an example.

[0018] Figure 12 Flowchart showing the boost converter controller method in an example. Detailed Description

[0019] The same reference numerals or other drawing indicators are used in the drawings to indicate the same or similar (functionally and / or structurally) features.

[0020] Figure 1 Block diagram showing system 100 in an example. As shown, in the illustrated arrangement, system 100 includes a power supply 102, a boost converter power stage 110, a controller 140 for the boost converter power stage 110, a load 160, and an output capacitor (C OUT ). In some examples, system 100 may include additional components, such as: a backup battery 170 coupled to C OUT and load 160; and / or an input capacitor (C IN) Using the backup battery 170, C OUT can maintain the output voltage (V OUT ) of the load 160, even if the boost converter power stage 110 is turned off or otherwise unable to maintain V OUT at the target level.

[0021] In Figure 1 the example, the power supply 102 has a power output 104. The boost converter power stage 110 has a power input 112, a power output 114, a first control input 116, a second control input 118, a sense output 120, and a ground terminal 122. The boost converter includes an inductor 124, a high-side (HS) switch 126, and a low-side (LS) switch 130. In Figure 1 the example, the HS switch 126 includes a control terminal 128 coupled to the first control input 116, and the LS switch 130 includes a control terminal 132 coupled to the second control input 118. Between the HS switch 126 and the LS switch 130 is a switch node 134 coupled to the sense output 120. During operation of the boost converter power stage 110, the sense output 120 provides a switch node voltage (V SW ) at the switch node 134.

[0022] In different examples, the topology of the boost converter power stage 110 (e.g., the arrangement of the inductor 124, the HS switch 126, and the LS switch 130) can vary. Regardless of the topology, the boost converter power stage 110 is configured to regulate the power to the load 160 based on the input voltage (V IN ) provided by the power supply 102, the target V OUT (not shown), and the operation of the controller 140. To improve the efficiency of the boost converter power stage 110, the controller 140 is configured to support different operating modes. Example operating modes supported by the controller 140 include discontinuous conduction mode (DCM) and forced continuous conduction mode (FCCM). For different operating modes, the minimum current in the inductor 124 is limited. In the case where the inductor 124 has a non-zero average current, if the load consumes less energy than the energy provided by the average inductor current, then V OUT rises. If the controller 140 pauses to avoid further rise of V OUT , the inductor current may drop to zero, resulting in a DCM scenario. If the load is heavy enough, the inductor current will not reach the minimum limit. To avoid the zero inductor current condition and DCM, FCCM can be used. With FCCM, the minimum current limit is reduced, such that the controller 140 can regulate V OUT based on non-zero average current and not non-switching.

[0023] In some scenarios, FCCM is superior to DCM to improve electromagnetic interference (EMI) or related switching noise issues. However, FCCM does sometimes cause reverse current in inductor 124, which can be considered by the control system. For each of the operating modes, the HS switch 126 is controlled by the high-side control signal (HS_CS) provided by the controller 140, while the LS switch 130 is controlled by the low-side control signal (LS_CS) provided by the controller 140.

[0024] In some instances, the controller 140 has a first sensing input 142, a second sensing input 144, a first control output 146, a second control output 148, and a ground terminal 150. The first sensing input 142 is coupled to the power output 114 of the boost converter power stage 110 and receives V OUT . The second sensing input 144 is coupled to the sensing output 120 of the boost converter power stage 110 and receives V SW . The first control output 146 provides HS_CS in response to the operation of the controller 140 and is coupled to the first control input 116 of the boost converter power stage 110. The second control output 148 provides LS_CS in response to the operation of the controller 140 and is coupled to the second control input 118 of the boost converter power stage 110.

[0025] In operation, the controller 140 is configured to adjust the parameters (e.g., on-time, off-time, on-trigger, off-trigger, frequency, etc.) of HS_CS at the first controller output 146 and LS_CS at the second controller output 148 based on various control options and related circuitry. In some instances, the controller 140 uses a valley current sensing circuit, a switching control circuit, an offset current (I OFFSET ) ramp circuit, a discharge circuit, a charge circuit, an error amplifier, a compensation network, control logic, and a signal generator to control HS_CS and LS_CS. Without limitation, these circuits of the controller 140 achieve smoother operating mode transitions (e.g., from light-load DCM to light-load FCCM) compared to conventional methods. In some instances, light-load DCM means that the load current is less than a threshold during DCM. Similarly, light-load FCCM means that the load current is less than a threshold during FCCM.

[0026] In some instances, the controller 140 is configured to control the drive signals HS_CS (for HS switch 126) and LS_CS (for LS switch 130) based on: detecting an operating mode transition; and during the operating mode transition, increasing I OFFSET at a target ramp rate and selectively injecting charge into the compensation network. In some instances, the target ramp rate varies with the transconductance of the error amplifier of the controller 140 and the target V OUT drop.

[0027] In some examples, controller 140 is configured to respond to V OUT Greater than the target V OUT The controller 140 is also configured to inject charge into the compensation network in response to detecting a condition indicating that there will no longer be a pause switching interval during the operating mode change. The condition includes, for example, V OUT falls below the first threshold with the target V OUT In some examples, the controller 140 is configured to stop injecting charge into the compensation network after a predetermined amount of charge is injected into the compensation network. In other examples, the controller 140 is configured to stop injecting charge into the compensation network after a predetermined amount of charge injection time.

[0028] In some examples, the controller 140 is configured to increase the target ramp rate by I relative to the target ramp rate in response to initiating the pause switching interval. OFFSET If the pause switching interface is not initiated, then I OFFSET The ramp rate is based on the target ramp rate. In some examples, the controller 140 includes a discharge circuit coupled to the power output 114. In such examples, the controller 140 is configured to selectively activate the discharge circuit to shorten a given pause switching interval.

[0029] Using the controller 140, V OUT Stability (relative to target V OUT ) is based on: I OFFSET Ramp rate control (part of valley current sensing); suspend switching control to prevent V OUT Exceed target V OUT exceeds the threshold; discharge control to selectively accelerate V OUT and charge control to selectively reduce V OUT decline.

[0030] For I OFFSET The controller 140 controls the ramp rate so that the reference current (I REF ) (one of the error amplifier inputs) can be controlled by the V OUT Adjustments to increase and eliminate I OFFSET The rate of influence increases I OFFSET For suspending switching control, the controller 140 selectively stops the switching operation (eg, controls HS_CS and LS_CS so that the HS switch 126 and the LS switch 130 are turned off). In some examples, when V OUTHigher than target V OUT When it is higher than a predetermined amount, the pause switching control stops the switching operation. In this way, when the offset current is small and the load is light, V OUT remains close to the target V OUT so as not to get out of control. For the discharge control, the controller 140 selectively activates the discharge at the power output 114 to ensure that the duration of the pause switching interval enables the loop to respond to the I OFFSET ramp. For the variation control, the controller 140 selectively applies charge to the charging input (e.g., the integration node) of the compensation network. In some instances, the charging operation is applied after the pause switching interval and after determining that there will be no pause switching interval during the operation mode transition. A one-time compensation is needed because when the switching pauses, the transconductance (G m ) stage (i.e., the error amplifier) of the controller 140 operates in a low clamp state. Therefore, the integration node of the compensation network stabilizes to a low clamp value due to the decrease in I REF (used to trigger the low clamp) during the low power condition. When applied, the one-time compensation helps the G m stage to recover the integration node voltage and reduce the V OUT drop.

[0031] Figure 2 Another block diagram showing the system 200 in the example. In the system 200, the boost converter power stage 110 regulates the power to the load 160 based on the V IN from the power supply 102. In operation, the boost converter power stage 110 is configured to: receive V IN at the power input 112; receive HS_CS at the first control input 116; receive LS_CS at the second control input 118; and regulate the V OUT at the power output 114 relative to the target V OUT in response to HS_CS, LS_CS, and the demand of the load 160. In the Figure 2 example, the boost converter power stage 110 is also configured to provide V SW to the sense output 120.

[0032] In the Figure 2 example, HS_CS and LS_CS are provided by the controller 140A ( Figure 1 an example of the controller 140 in OFFSET ) based on the operation of various circuits, which include: valley current sensing circuit 201; switch control circuit 210; I

[0033] In the Figure 2In an example, the valley current sensing circuit 201 includes an I OFFSET input 202. In other examples, the I OFFSET ramp circuit 220 is part of the valley current sensing circuit 201. In such examples, the internal I OFFSET and I OFFSET inputs 202 are omitted. As shown, Figure 2 the valley current sensing circuit 201 of also includes an I REF control signal (I REF_ CS) input 203, a first sensing circuit input 204, a control input 205, a second sensing circuit input 206, a ground terminal 207, and a sensing circuit output 208. In operation, the valley current sensing circuit 201 is configured to enable valley current sensing in response to HS_CS received at the control input 205. Once sensing is enabled, the valley current sensing circuit 201 is configured to provide a valley detection signal (Valley_Detect) at the sensing circuit output 208 in response to each of the following: an I OFFSET received or internally generated at the I OFFSET input 202; an I REF received at the I REF_CS control signal input 203; a V OUT received at the first sensing circuit input 204; and a V SW received at the second sensing circuit input 206.

[0034] The I OFFSET ramp circuit 220 includes an adjustment input 221, a ramp generation input 222, a power input 223, a first signal input 224, a second signal input 225, a third signal input 226, a fourth signal input 227, a completion output 228, an I OFFSET output 229, and a ground terminal 230. In operation, the I OFFSET ramp circuit 220 is configured to increase the I OFFSET from an initial I OFFSET value to a target I OFFSET in response to each of the following: receiving a power supply (V CC ) at the power input 223; and receiving an enable signal (EN_MTz) at the ramp generation input 222. In response to receiving an acceleration signal (SPEEDUPZ) at the adjustment input 221, the I OFFSET ramp circuit 220 is configured to accelerate the I OFFSET to reach the target I OFFSET . In some examples, the I OFFSET ramp circuit 220 is configured to increase the initial I OFFSET value in response to receiving SPEEDUPZ at the adjustment input 221. In other examples, the I OFFSETThe ramp circuit 220 can be configured to increase I in response to receiving SPEEDUPZ at the adjustment input 221 OFFSET ramp rate. I OFFSET The bias value of the ramp circuit 220 is selectively based on: a first signal (SEL_CTRL_BIAS) received at the first signal input 224; a second signal (SEL_CTRL_BIASz) received at the second signal input 225; a third signal (SEL_CONST_BIAS) received at the third signal input 226; and a fourth signal (SEL_CONST_BIASz) received at the fourth signal input 227. In some instances, I OFFSET The ramp circuit 220 is configured to: use SEL_CTRL_BIAS and SEL_CTRL_BIASz to set the bias value during an operation mode transition; and use SEL_CONST_BIAS and SEL_CONST_BIASz to set the bias value during normal operation (e.g., when the load current is greater than a threshold).

[0035] In some instances, I OFFSET The ramp circuit 220 is configured to ramp I at a target ramp rate OFFSET from an initial I OFFSET level to a target I OFFSET level. The target ramp rate can depend on the transconductance of the error amplifier of the controller 140A and the target V OUT drop. Once I OFFSET reaches the target I OFFSET level, I OFFSET The ramp circuit 220 is configured to assert a done signal (DONE) at the completion output 228.

[0036] The discharge circuit 232 has a power input 234, an enable input 236, and a ground terminal 238. In response to receiving an enable signal (EN_DISCHG) at the enable input 236, the discharge circuit 232 is configured to couple the power output 114 of the boost converter power stage 110 to the ground terminal 238, which reduces V OUT .

[0037] The charging circuit 240 includes an enable input 242, a power input 244, and a charging output 246. In response to receiving an enable signal (EN_COMP) at the enable input 242, the charging circuit 240 is configured to provide a charging signal (COMP_C) at the charging output 246 based on the V at the power input 244 CC In different instances, COMP_C is provided for a predetermined duration or until a predetermined amount of charge is provided to the charging output 246.

[0038] The error amplifier 250 includes a first amplifier input 251, a second amplifier input 252, and an error output 253. In operation, the error amplifier 250 is configured to respond to V received at the first amplifier input 251 OUT sense signal (V OUT *) and the reference voltage (V REF ) received at the second amplifier input 252 to provide an error result 254.

[0039] The compensation network 255 includes an error input 256, a charge input 257, an I REF control output 258, and a ground terminal 259. In operation, the compensation network 255 is configured to respond to the error result 254 received at the error input 256 and COMP_C received at the charge input 257 to provide I REF at the I REF_CS control output 258. In some instances, I REF_CS is provided to a voltage-to-current (V2I) converter to generate I REF . In some instances, one or more of such V2I converters and the valley current sensing circuit 201 are included. In some instances, I REF_CS is provided to a voltage-to-current (V2I) converter to generate I REF .

[0040] The signal generator 272 includes a control input 274, a first non-overlapping signal output 276, and a second non-overlapping signal output 278. In operation, the signal generator 272 is configured to respond to a signal generator control signal (SG_CS) received at the control input 274 to provide a first signal (SEL_CONST_BIAS) at the first non-overlapping signal output 276 and a second signal (SEL_CTRL_BIAS) at the second non-overlapping signal output 278.

[0041] As shown, the controller 140A also includes a first inverter 280 and a second inverter 286. The first inverter 280 has a first inverter input 282 and a first inverter output 284. In Figure 2In an example, the first inverter input 282 is coupled to the first non-overlapping signal output 276. In operation, the first inverter 280 is configured to receive SEL_CONST_BIAS at the first inverter input 282 and provide an inverted signal (SEL_CONST_BIASz) at the first inverter output 284. The second inverter 286 has a second inverter input 288 and a second inverter output 290. In operation, the second inverter 286 is configured to receive SEL_CTRL_BIAS at the second inverter input 288 and provide an inverted signal (SEL_CTRL_BIASz) at the second inverter output 290.

[0042] The control logic 260 includes a first control input 261, a second control input 262, a third control input 263, a fourth control input 264, a fifth control input 265, a first control output 266, a second control output 267, a third control output 268, a fourth control output 269, a fifth control output 270, and a sixth control output 271. In operation, the control logic 260 is configured to: provide an enable I OFFSET ramp signal (e.g., EN_MTz) at the first control output 266; provide an acceleration signal (e.g., SPEEDUPZ) at the second control output 267; provide an enable discharge signal (e.g., EN_DISCHG) at the third control output 268; provide an enable charge signal (e.g., EN_COMP) at the fourth control output 269; provide an enable pause signal (e.g., EN_PAUSE) at the fifth control output 270; and provide a signal generator control signal (e.g., SG_CS) at the sixth control output 271. The signals provided by the control logic 260 are provided as needed to perform the operations described herein in response to: an I OFFSET ramp completion signal (e.g., DONE) received at the first control input 261; a first V OUT high threshold (e.g., VOUT_HIGH) received at the second control input 262; a second V OUT high threshold (e.g., VOUT_HIGH_II) received at the third control input 263; a soft start completion signal (e.g., SSdone) received at the fourth control input 264; and / or a mode signal (e.g., MODE) received at the fifth control input 265.

[0043] In some instances, control logic 260 is configured to provide EN_MTz at a first control output 266 in response to detecting an operating mode transition (e.g., assertion of an S S done signal). In some instances, control logic 260 is configured to provide SPEEDUPZ at a second control output 267 in response to initiating a pause switching interval during an operating mode transition. In some instances, control logic 260 is configured to provide EN_DISCHG at a third control output 268 in response to providing EN_PAUSE at a fifth control output 270. In some instances, control logic 260 is configured to provide EN_COMP at a fourth control output 269 in response to a condition indicating that there will no longer be a pause switching interval during an operating mode transition. In some instances, the condition is V OUT drops from VOUT_HIGH_II to below VOUT_HIGH. In some instances, control logic 260 is configured to provide EN_PAUSE at a fifth control output 270 in response to V OUT reaching VOUT_HIGH_II. In some instances, control logic 260 is configured to provide SG_CS at a sixth control output 271 in response to a DONE signal received at a first control input 261.

[0044] As previously described, signal generator 272 is configured to generate SEL_CONST_BIAS and SEL_CTRL_BIAS in response to SG_CS. Most of the time (during normal operation with normal load demands), SEL_CONST_BIAS and SEL_CONST_BIASz are used by I OFFSET ramp circuit 220. During a given operating mode transition (e.g., from light load DCM to light load FCCM), SEL_CTRL_BIAS and SEL_CTRL_BIAS are used by I OFFSET ramp circuit 220 to ramp up I OFFSET .

[0045] Switch control circuit 210 includes a control input 212, a sense input 214, a first control output 216, and a second control output 218. In operation, switch control circuit 210 is configured to: receive a Valley_Detect signal at control input 212; receive V OUT at sense input 214; provide HS_CS at a first control output 216 in response to the Valley_Detect signal and V OUT ; and provide HS_CS at a second control output 218 in response to the Valley_Detect signal and V OUTThe LS_CS is provided at the second control output 218. In some examples, the switch control circuit 210 includes circuitry for determining the on-time and off-time of the HS_CS and the associated HS switch 126. The switch control circuit 210 controls the LS_CS to be complementary to the HS_CS (i.e., when the HS_CS is high, the LS_CS is low; and when the HS_CS is low, the LS_CS is high), unless switching is paused. With the controller 140A and associated operations, the V OUT drop remains within the target tolerance during a given mode of operation transition (e.g., from light load DCM to light load FCCM).

[0046] Figure 3 To illustrate an example of the boost converter power stage 110A ( Figure 1 and 2 an example of the boost converter power stage 110 in) and the valley current sensing circuit 201A ( Figure 2 an example of the valley current sensing circuit 201 in). In some examples, in the arrangement shown in Figure 3 , the boost converter power stage 110A includes: an inductor (labeled L); a transistor (M1) operating as the HS switch of the boost converter power stage 110A (e.g., Figure 1 the HS switch 126 in); and the LS switch of the boost converter power stage 110A (e.g., Figure 1 the LS switch 130 in). Specifically, a first side 320 of L is coupled to the power input 112. A second side 322 of L is coupled to the switch node 134. A first current terminal 324 of the LS switch is also coupled to the switch node 134. A second current terminal 326 of the LS switch is coupled to the ground terminal 122. A control terminal 132 of the LS switch is coupled to the second control input 118. In operation, the boost converter power stage 110A is configured to receive the LS_CS at the second control input 118. A first current terminal 328 ( Figure 3 the HS switch in) of M1 is coupled to the switch node 134. A second current terminal 330 of M1 is coupled to the power output 114. A control terminal 128 of M1 is coupled to the first control input 116. In operation, the boost converter power stage 110A is configured to receive the HS_CS at the first control input 116. The sense output 120 is coupled to the switch node 134. In operation, the boost converter power stage 110A is configured to provide V SW .

[0047] In some examples, in the arrangement shown in Figure 3 , the valley current sensing circuit 201A includes: transistors M2, M3, M4; I REF sources 304 and 306; I OFFSET ramp circuit 220A (Figure 2 the I in OFFSET an example of the ramp circuit 220); and a current comparator 302. Specifically, the first current terminal of M2 (note: M2 has a resistance Rsns when turned on) is coupled to the second sense circuit input 206. The second current terminal of M2 is coupled to the first current terminal of M3 (note: M3 has a resistance R when turned on). The control terminal of M2 is coupled to the control input 205. The second current terminal of M3 is coupled to the first side of the I REF source 304. REF The second side of the I source 304 is coupled to the ground terminal 207. The first current terminal of M4 is coupled to the first sense circuit input 204. The second current terminal of M4 is coupled to the first side of the I REF source 306. In Figure 3 an example, the control terminals of M3 and M4 receive a control signal (CS2), which may be provided in response to the HS switch being turned on (or the relevant current being available). REF The second side of the I source 306 is coupled to the ground terminal 207. The second current terminal of M4 is also coupled to the I OFFSET first side of the ramp circuit 220A. OFFSET The second side of the ramp circuit 220A is coupled to the ground terminal 207. In Figure 3 an example, the current comparator 302 includes a non-inverting (“+”) input, an inverting (“-”) input, and a comparator output. The non-inverting (“+”) input of the current comparator 302 is coupled to the second current terminal of M4. The inverting (“-”) input of the current comparator 302 is coupled to the second current terminal of M3. The output of the current comparator 302 is coupled to the sense circuit output 208. In operation, the current comparator 302 provides a Valley_Detect signal in response to the sense current (Isns) reaching a valley level threshold. In some examples, the valley level threshold varies with the I OFFSET and in some examples, Isns can be adjusted based on the I REF and the I OFFSET where the I OFFSET is constant, except during the ramp-up period, and the I REF is controlled based on the error amplifier operation (i.e., the I REF varies as the load changes).

[0048] In some examples, the valley current sense circuit 201A is configured to enable valley current sensing in response to receiving HS_CS at the control input 205. Once sensing is enabled, the valley current sense circuit 201A is configured to provide Valley_Detect at the sense circuit output 208 in response to each of the following: the I OFFSET provided by the ramp circuit 220A; the I OFFSET ; in the I REFI received at the control signal input 203 REF CS ; V received at the first sensing circuit input 204 OUT ; and V received at the second sensing circuit input 206 SW . Figure 4 To show I in the example OFFSET Ramp circuit 220B( Figure 2 I in OFFSET Ramp circuit 220 or Figure 3 I in OFFSET Example of ramp circuit 220A). In some examples, in the arrangement shown in Figure 4 , I OFFSET Ramp circuit 220B includes transistors M5 to M15 (each having a corresponding first current terminal, a corresponding second current terminal, and a corresponding control terminal), operational amplifier 402, capacitor (C1), resistor (R1), current source 404, Schmitt trigger 406, and first transmission gate 408 and second transmission gate 418.

[0049] In Figure 2 's example, the first transmission gate 408 has a first control input 410, a second control input 412, a transmission input 414, and a transmission output 416. The second transmission gate 418 has a first control input 420, a second control input 422, a transmission input 424, and a transmission output 426. In some examples, each of the first transmission gate 408 and the second transmission gate 418 includes a p-channel FET (PFET) and an n-channel FET (NFET), where one of the PFET and the NFET is always on. When there is not enough gate-to-source voltage (V GS ) for FET operation, each of the first transmission gate 408 and the second transmission gate 418 provides a relatively low resistance.

[0050] In Figure 4 's example, the first current terminal of M5 is coupled to the power input 223. The second current terminal of M5 is coupled to the first current terminal of M6. The second current terminal of M6 is coupled to the first current terminal of M7 and the first side of C1. The second current terminal of M7 and the second side of C1 are coupled to the ground terminal 230.

[0051] The first current terminal of M16 is coupled to the power input 223 (e.g., to receive V CC)。The second current terminal of M16 is coupled to the first side of R1. The second side of R1 is coupled to the ground terminal 230. The first current terminal of M8 is coupled to the power input 223. The second current terminal of M8 is coupled to the first current terminal of M11. The second current terminal of M11 is coupled to the ground terminal 230. The first current terminal of M10 is coupled to the power input 223. The second current terminal of M10 is coupled to the first current terminal of M9. The second current terminal of M9 is coupled to the first current terminal of M11. The first current terminal of M13 is coupled to the power input 223. The second current terminal of M13 is coupled to the first current terminal of M12. The first current terminal of M14 is coupled to the current source 404. The second current terminal of M14 is coupled to the ground terminal 230. The first current terminal of M15 is coupled to I OFFSET output 229. The second current terminal of M15 is coupled to the ground terminal (e.g., the ground terminal 230). The control terminal of M15 is coupled to the transfer output 416 of the first transfer gate 408 and the transfer output 426 of the second transfer gate 418. During normal operation (e.g., when the load current is greater than the threshold), I OFFSET is constant and based on the current from the current source 404 and the bias provided by the second transfer gate 418. During the operation mode transition (e.g., from light load DCM to light load FCCM), I OFFSET ramp up and is based on the current from the current mirror using M11 and M12 and the bias provided by the first transfer gate 408.

[0052] As Figure 4 shown, the inverting (“-”) input of the operational amplifier 402 is coupled to the second current terminal of M6. The non-inverting (“+”) input of the operational amplifier 402 is coupled to the second current terminal of M16. The output of the operational amplifier 402 is coupled to the control terminals of M16 and M8. The control terminals of M5 and M7 are coupled to the ramp generation input 222. In operation, I OFFSET The ramp circuit 220B is configured to receive EN_MTz at the ramp generation input 222. The control terminals of M6, M9, and M13 are coupled to the power input 223. The control terminals of M7 and M8 are coupled to the output of the operational amplifier 402. The control terminal of M10 is coupled to the adjustment input 221. In operation, I OFFSET The ramp circuit 220B is configured to receive SPEEDUPz at the adjustment input 221. The control terminals of M11 and M12 are coupled to each other and to the second current terminals of M8 and M9. The control terminals of M11 and M12 are also coupled to the transfer input 414 of the first transfer gate 408. The first control input 410 of the first transfer gate 408 is coupled to the first signal input 224. In operation, I OFFSETThe ramp circuit 220B is configured to receive SEL_CTRL_BIAS at the first signal input 224. The second control input 412 of the first transmission gate 408 is coupled to the second signal input 225. In operation, I OFFSET The ramp circuit 220B is configured to receive SEL_CTRL_BIASz at the second signal input 225. The control terminal of M14 is coupled to the transmission input 424 of the second transmission gate 418 and the first current terminal of M14. The first control input 420 of the second transmission gate 418 is coupled to the third signal input 226. In operation, I OFFSET The ramp circuit 220B is configured to receive SEL_CONST_BIAS at the third signal input 226. The second control input 422 of the second transmission gate 418 is coupled to the fourth signal input 227. In operation, I OFFSET The ramp circuit 220B is configured to receive SEL_CONST_BIASz at the fourth signal input 227.

[0053] When enabled by receiving EN_MTz at the ramp generation input 222, I OFFSET The ramp circuit 220B is configured to cause the I OFFSET at the output 229 to OFFSET ramp up in response to a set of bias control signals (e.g., SEL_CTRL_BIAS and SEL_CTRL_BIASz during an operation mode transition). If desired, SPEEDUPZ is used to accelerate the I OFFSET to reach the target I OFFSET .

[0054] In some instances, I OFFSET the ramp circuit 220B is only enabled when there is a target operation mode transition (e.g., EN_MTz is high). For example, the MODE signal provided by the control logic 260 can indicate when there is a target operation mode transition. As described herein, I OFFSET the operation of the ramp circuit 220B involves several signals, including: EN_MTz; DONE; and SPEEDUPZ. Similarly, EN_MTz is the I OFFSET enable signal for the ramp circuit 220B. When there is sufficient bias current (varying with the total I OFFSET and the current mirror ratio formed using M12 to M15) and the operation mode transition is complete, I OFFSET the ramp circuit 220B provides DONE to the completion output 228. In Figure 4 the instance of, current comparison performed by the Schmitt trigger 406 (between the second current terminal of M13 and the completion output 228) is used to determine when there is sufficient bias current and the operation mode transition is complete.

[0055] In some instances, I OFFSET ramp circuit 220B is configured to ramp up faster in response to receiving SPEEDUPz at adjustment input 221 OFFSET . As an example, control logic (e.g., Figure 2 control logic 260 in OFFSET ) can be configured to provide SPEEDUPz in response to a pause switching interval during a given mode of operation transition. When SPEEDUPz is de-asserted, I OFFSET ramps up from an initial OFFSET value to a target OFFSET value during a given mode of operation transition. When SPEEDUPz is asserted, I OFFSET ramps up faster (e.g., by increasing the initial OFFSET value, increasing the ramp rate, or adding in a step-up fashion to I speedup ). In some instances, when I m is low-clamped, it has a boundary defined by the I REF of the G

[0056] stage (error amplifier 250). This boundary can be calculated, for example, using Equation 2. where when low-clamped, REF (2)

[0057] For Equation 2, Rsns is the resistance of M2 in Figure 3 , R is the resistance of M3 and M4 in Figure 3 , and is the I sns of R REF . When SPEEDUPz is asserted, the amount of discharge time is reduced, which improves the thermal behavior.

[0058] In some instances, I OFFSET ramp circuit 220B includes: a ramp generation circuitry having a first control input and a first current output; a ramp adjustment circuitry having a second control input and a second current output; a current scaling circuitry having a first current input, a current sense output, and an offset current output; and a ramp completion circuitry having an offset current input and a completion output. Regarding Figure 4 , an example ramp generation circuitry includes M5, M6, M7, M8, M16, and operational amplifier 402. In this example, the control terminal of M5 and / or the control terminal of M7 is the example first control input of the ramp generation circuitry. The second current terminal of M8 is the example first current output of the ramp generation circuitry. Figure 4The example ramp adjustment circuit system in contains M10. In this example, the control terminal of M10 is the example second control input of the ramp adjustment circuit system. The second current terminal of M10 is the example second current output of the ramp adjustment circuit system. Figure 4 The example current scaling circuit system in contains M11, M12, and M15. In this example, the control terminals of M11, M12, and M15 together with the first current terminal of M11 are the example first current input of the current scaling circuit system. The first current terminal of M12 is the example current sense output of the current scaling circuit system. The first current terminal of M15 is the example offset current output of the current scaling circuit system. Figure 4 The example ramp completion circuit system in contains M13 and Schmitt trigger 406. In this example, the Schmitt trigger input is the example offset current input of the ramp completion circuit system. The Schmitt trigger output is the example completion output of the ramp completion circuit system.

[0059] In Figure 4 the example, the first control output 266 of the control logic 260 is coupled to the first control input of the ramp generation circuit system via the ramp generation input 222. The second control output 267 of the control logic 260 is coupled to the second control input of the ramp adjustment circuit system via the adjustment input 221. The first current output of the ramp generation circuit system is coupled to the first current input of the current scaling circuit system. The second current output of the ramp adjustment circuit system is also coupled to the first current input of the current scaling circuit system. The current sense output of the current scaling circuit system is coupled to the current sense input of the ramp completion circuit system. The offset current output of the current scaling circuit system is coupled to I OFFSET output 229. The completion output of the ramp completion circuit system is coupled to the first control input 261 of the control logic 260 via the completion output 228.

[0060] Figure 5 To show a schematic diagram of the discharge circuit 232A ( Figure 2 an example of the discharge circuit 232 in Figure 5 the example). In the example, the discharge circuit 232A includes a resistor (R2) and a switch (S2) connected in series between the power input 234 and the ground terminal 238. The control terminal of S2 is coupled to the enable input 236 of the discharge circuit 232A. In operation, the discharge circuit 232A is configured to couple the power output 114 associated with V OUT to the ground terminal 238 in response to receiving EN_DISCHG at the enable input 236. Specifically, when EN_DISCHG is asserted, S2 closes to activate the discharge at the power output 114, which reduces V OUT . In some examples, the control logic (e.g., Figure 2The control logic 260) is configured to provide EN_DISCHG in response to EN_PAUSE being provided (e.g., to reduce the pause switching interval or the duration of a related operating mode transition).

[0061] Figure 6 Schematic diagram showing an example of the charging circuit 240A ( Figure 2 an example of the charging circuit 240 in). In Figure 6 In the example, in the illustrated arrangement, the charging circuit 240A includes: M16; M17; a delay circuit 602; and a NAND gate 604. Specifically, the delay circuit 602 is coupled to the enable input 242. In operation, the charging circuit 240A is configured to receive EN_COMP at the enable input 242. The output of the delay circuit 602 is coupled to the first input of the NAND gate 604. The second input of the NAND gate 604 is coupled to the enable input 242. In addition, the first current terminal of M16 is coupled to the power input 244. The second current terminal of M16 is coupled to the first current terminal of M17. The second current terminal of M17 is coupled to the charging output 246.

[0062] As shown, the control terminal of M16 is coupled to the output of the NAND gate 604, while the control terminal of M17 is coupled to the power input 244. In operation, the charging circuit 240A is configured to provide COMP_C at the charging output 246 in response to EN_COMP and a delay (e.g., based on the delay of the delay circuit 602). In some examples, the control logic (e.g., Figure 2 the control logic 260 in) is configured to provide EN_COMP in response to a detectable condition indicating that there will no longer be a pause switching interval during a given operating mode transition. In some examples, the detectable condition is that V OUT drops from VOUT_HIGH_II to VOUT_HIGH. In some examples, VOUT_HIGH_II is below the pulse frequency modulation (PFM) threshold, and a de-short pulse interference time greater than 10 us is used (varies with the switching frequency of the HS switch 126 and the LS switch 130), such that V OUT returns to the target V OUT value. The purpose of the charging circuit 240A is to inject a target amount of charge into a compensation capacitor (e.g., Figure 7 the C in C ). In some examples, the target charge amount is defined by an expected voltage change ΔV comp . In such example embodiments, the current I comp and the pulse time ΔT comp can be used to provide the compensation charge, where I comp varies with V CC and the resistance of M16 and M17 when turned on. At the same time, ΔTcomp based on I comp and the target charge amount.

[0063] Figure 7 To show the error amplifier 250A in the example ( Figure 2 the example of the error amplifier 250 in ) and the compensation network 255A ( Figure 2 the example of the compensation network 255 in ) of the schematic diagram. In Figure 7 the example, the error amplifier 250A is an operational transconductance amplifier, which has a first amplifier input 251 (for example, an inverting (“-”) input), a second amplifier input 252 (for example, a non-inverting (“+”) input) and an error output 253. In operation, the error amplifier 250A is configured to respond to V received at the first amplifier input 251 OUT * and V received at the second amplifier input 252 REF and provide an error result 254. In Figure 7 the example, V REF is provided to V REF source 704. In Figure 7 the example, a voltage divider with resistors R3 and R4 connected in series between the power output 114 and the ground terminal 708 is used to obtain V OUT *. In this example, V OUT * is a scaled version of V OUT .

[0064] As shown, the compensation network 255A includes an operational transconductance amplifier 706 and a compensation circuit system formed by resistors (Rc), Cc and another capacitor (C2) in the shown arrangement. In some examples, the operational transconductance amplifier 706 operates as a V2I converter with a low clamping threshold. In Figure 7 the example, the error amplifier 250A has a first voltage-current ratio (g m1 ), while the operational transconductance amplifier 706 has a second voltage-current ratio (g m2 ).

[0065] In Figure 7 the example, the non-inverting (“+”) input of the operational transconductance amplifier 706 is configured to receive the maximum clamping threshold (max_Level), where max_Level is the maximum inductor current. As mentioned before, I REF is used for valley current sensing, and a V2I converter can be used to generate based on I REF_ CS. For the maximum inductor current, there will be a maximum V2I current and a related scaled V2I value (for example, related to the operational transconductance amplifier 706). In some examples, max_Level is a scaled value determined based on the maximum inductor current.

[0066] In the example of Figure 7 , the inverting (“-”) input of the operational transconductance amplifier 706 is coupled to the error input and the I REF control output 258. The output of the operational transconductance amplifier 706 is also coupled to the error input 256 and the I REF control output 258. As shown, the first side of Rc is coupled to the error input 256 and the I REF control output 258. The second side of Rc is coupled to the charge input 257 and the first side of Cc. The second side of Cc is coupled to the ground terminal 259. The first side of C2 is coupled to the error input 256 and the I REF control output 258. The second side of C2 is coupled to the ground terminal 259.

[0067] In operation, the error amplifier 250A is configured to compare V OUT * with V REF to detect whether V OUT has dropped below a threshold (e.g., below the target V OUT ). The error result 254 provided at the error output 253 is used to adjust the inductor current. When the feedback loop is stable, V OUT * can approach V REF . Otherwise, the comparison result of the error amplifier 250A increases, which causes more energy to be supplied (to increase V OUT ) or less energy to be supplied (to decrease V OUT ). During an operation mode transition, the control logic (e.g., the control logic 260 in Figure 2 ) is configured to provide COMP_C to the charge input 257 in response to an indication that there will no longer be a pause switching interval during the operation mode transition. In the example of Figure 7 , COMP_C is used to charge Cc, which enables the control loop associated with the error amplifier 250A and the compensation network 255A to recover from a low load condition, thereby reducing the charge on Cc.

[0068] Using the error amplifier 250A (associated with g m1 ) and the operational transconductance amplifier 706, the following sensing equation applies:

[0069]

[0070] When the controller 140 is stable, there is a ΔV between the target value and the current output. To select the target ΔV, I offset can be adjusted according to the following equation:

[0071]

[0072] In Equation 4, g m2 is the transconductance of the V2I converter configured to generate I REF_ based on I REF CS. Based on Equation 4, the expected slew rate of I offset is:

[0073]

[0074] To achieve a slower I offset ramp, a larger C1 can be used (see Figure 4 ). In different instances, the optimization of the I offset ramp is based on the target V OUT drop, the target IC area, the target g m1 (or related resistance), the target g m2 (or related resistance), or other design parameters.

[0075] In some instances, I comp (the current used to charge Cc) is given by:

[0076]

[0077] If the low clamp value of COMP_C is specified as V low_pow (when the controller 140A is operating in the low power mode) and the normal value is specified as V normal (when the controller 140A is operating in the normal mode other than the low power mode), then ΔV comp is limited by V normal - V low_pow . In some instances, ΔV comp is not adaptive and can be carefully selected. For example, if ΔV comp is too high, then the V OUT drop decreases under light load conditions, but COMP_C is slightly overcompensated under light to medium load conditions. Under heavy load conditions, the charging operation is not enabled (e.g., provided by the charging circuit 240 in Figure 2 or the charging circuit 240A in Figure 6 ).

[0078] Figure 8 FIG. is a schematic diagram showing the switch control circuit 210A (an example of the switch control circuit 210 in Figure 2 ) in an example. In Figure 8In an example, in the illustrated arrangement, the switch control circuit 210A includes: a current generator 802, resistors (R5 and R6), a capacitor (C3), a switch (S3), a comparator 808, an SR latch 810, and an inverter 812. The current generator 802 has a current generator input 804 and a current generator output 806. Specifically, a first side of R5 is coupled to the sense input 214. In operation, the switch control circuit 210A is configured to receive V at the sense input 214 OUT . A second side of R5 is coupled to the current generator input 804 of the current generator 802. In operation, the current generator 802 is configured to generate a current proportional to V OUT _ (e.g., V OUT / R5), and then amplify this current by a factor of 4 (1:4 ratio). The amplified current is used to discharge the capacitor C3.

[0079] As shown, the second side of R5 is also coupled to the non-inverting (“+”) input of the comparator 808. A first side of R6 is coupled to the sense input 214. A second side of R6 is coupled to a first side of C3. A second side of C3 is coupled to the current generator output 806 and the inverting (“-”) input of the comparator 808. A first side of S3 is coupled to the sense input 214. A second side of S3 is coupled to the inverting (“-”) input of the comparator 808. The output of the comparator 808 is coupled to the reset (R) input of the SR latch 810. The set (S) input of the SR latch 810 is coupled to the control input 212. The Q output of the SR latch 810 is coupled to the second control output 218 and provides LS_CS. The Q output of the SR latch 810 is also coupled to the input of the inverter 812. The output of the inverter 812 is provided to the control terminal of S3. The QZ output of the SR latch 810 is coupled to the first control output 216 and provides HS_CS. In operation, the switch control circuit 210A is configured to provide HS_CS and LS_CS in response to the Valley_Detect signal, V OUT , the on-time (TON) control option, and the off-time (TOFF) control option. In some examples, the TON can be determined using the target duty cycle of a known inductor turns ratio and switching frequency. In some examples, the TOFF can be based on the voltage-second balance of the inductor current.

[0080] Figure 9 And 10 Graphs 900 and 1000 are graphs showing signals related to boost converter controller options in the example. In Figure 9 graph 900, V OUT and the EN_COMP signal are shown as varying over time (e.g., during an operating mode transition). Additionally, V OUT _HIGH, VOUT _HIGH_II and target V OUT The instance threshold. As shown, V OUT has an initial value between V OUT _HIGH and V OUT _HIGH_II threshold. Once V OUT exceeds V OUT _HIGH_II, a pause switching interval is initiated (e.g., after the next HS switch - on cycle). The pause switching interval causes V OUT to eventually drop below V OUT _HIGH_II, which ends the pause switching interval. If there is a light load, then V OUT will increase due to the switching operation. In the Figure 9 instance, V OUT exceeds V OUT _HIGH_II again, thus causing another pause switching interval to be initiated. The pause switching interval causes V OUT to drop below V OUT _HIGH_II again. If V OUT drops below VOUT_HIGH (an indication that there will be no more pause switching intervals during the operation mode transition), then EN_COMP is asserted. In the case of the assertion of EN_COMP, compensating charge is applied to Cc of the compensation network (see for example Figure 7 ). After the de - assertion of EN_COMP, the operation mode transition is completed. Even after the de - assertion of EN_COMP, the transition continues and I OFFSET ramps up until it reaches the target value. The effect of the ramp - up of I OFFSET is similar to an increase in the load. This is because I OFFSET lowers V SW when Valley_Detect is asserted (a lower V SW is equivalent to pulling current from V OUT ).

[0081] In Figure 10 graph 1000, V OUT , I L , Ssdone, EN_MT, I OFFSET , SPEEDUPZ, EN_PAUSE, EN_DISCH, EN_COMP, COMP_C, COMP_IN, DONE, SEL_BIAS_CONST, and SEL_BIAS_CTRL signals are shown as varying with time (e.g., during the operation mode transition). At point 1, the operation mode transition is triggered by Ssdone, causing EN_MT to be asserted to initiate the ramp - up of I OFFSET . At the start of the operation mode transition, VOUT Reach the Pulse Frequency Modulation (PFM) threshold (e.g., VOUT_HIGH_II), which causes EN_PAUSE to be asserted to initiate a pause switching interval. Enable the discharge operation using EN_DISCHG to prevent the pause switching interval from lasting too long. Due to the pause switching interval, COMP_C reaches a lower level because the low clamp value of COMP_IN is selected to save power. At point 2, V OUT returns to the target V OUT . In response, enable one-time compensation by asserting EN_COMP. At point 3, the DONE signal is triggered, and I OFFSET 's current mirror is connected to M14, which is biased by a constant current. The DONE signal coincides with the end of the operation mode transformation. At point 3, I L is controlled by the controller 140, and SPEEDUPZ is not cleared, which does not affect I OFFSET . Before the DONE signal is asserted, M15 is connected to M11. After the DONE signal is asserted, M15 is connected to M14, and SPEEDUPZ only affects M11 (and thus does not need to be cleared after the DONE signal is asserted).

[0082] Figure 11 To show V OUT and I L signals in the example with and without the boost converter controller option. In graph 1100, V OUT BEFORE , V OUT AFTER , I L BEFORE and I L AFTER signals are shown as varying with time (e.g., during the operation mode transformation). Without the boost converter controller option described herein, V OUT_BEFORE drops from 5V to 4.55V, which may be greater than the target V OUT drop. With the boost converter controller option described herein (e.g., I OFFSET ramp, discharge, one-time compensation, and control features), V OUT_AFTER drops from 5V to 4.90V, which is a much smaller V OUT_BEFORE drop compared to V OUT . I L_BEFORE and I L_AFTER show the effect of the I OFFSET ramp as described herein. Compared to I L_BEFORE , I L_AFTER has a smaller inductor current valley envelope. This is because I OFFSET ramps and results in a smaller V OUTDecrease.

[0083] Figure 12 FIG. 12 is a flowchart illustrating a boost converter controller method 1200 in an example. The boost converter controller method 1200 is performed, for example, by a boost converter controller (e.g., Figure 2 controller 140A in FIG. 14), the boost converter controller having a valley current sensing circuit (e.g., Figure 2 valley current sensing circuit 201 in FIG. 20 or Figure 3 valley current sensing circuit 201A in FIG. 20A), an error amplifier (e.g., Figure 2 error amplifier 250 in FIG. 25 or Figure 7 error amplifier 250A in FIG. 25A), and a compensation network circuit (e.g., Figure 2 compensation network 255 in FIG. 25 or Figure 7 compensation network 255A in FIG. 25A). As shown, the boost converter controller method 1200 includes detecting an operating mode transition at block 1202. In response to detecting an operating mode transition at block 1202, increasing I OFFSET at a target ramp rate at block 1204. At block 1206, selectively injecting charge into the compensation network during the operating mode transition. In some examples, charge is injected into the compensation network in response to a pause switching interval (e.g., a pause switching internal initiated by EN_PAUSE) starting at a point during the operating mode transition and a condition indicating that there will no longer be a pause switching interval during the operating mode transition. In some examples, the condition includes V OUT decreasing below a threshold (e.g., VOUT_HIGH) between a first threshold (VOUT_HIGH_II) and a target output voltage (target V OUT ).

[0084] In this specification, the term “coupled” may cover a connection, communication, or signal path that enables a functional relationship consistent with this specification. For example, if device A generates a signal to control device B to perform an action, then: (a) in a first example, device A is coupled to device B by a direct connection; or (b) in a second example, device A is coupled to device B through an intermediate component C, provided that the intermediate component C does not change the functional relationship between device A and device B such that device B is controlled by device A via a control signal generated by device A.

[0085] Additionally, in this specification, the statement “based on” means “at least partially based on”. Thus, if X is based on Y, then X may vary with Y and any number of other factors.

[0086] A device “configured to” perform a task or function can be configured (e.g., programmed and / or hardwired) by a manufacturer at the time of manufacture to perform the function, and / or can be configured (or reconfigured) by a user after manufacture to perform the function and / or other additional or alternative functions. The configuration can be performed by programming the device's firmware and / or software, by the construction and / or layout of the device's hardware components and interconnections, or a combination thereof.

[0087] As used herein, the terms “terminal,” “node,” “interconnection,” “pin,” and “lead” may be used interchangeably. Unless specifically stated to the contrary, these terms are generally used to mean the interconnection between or the ends of device elements, circuit elements, integrated circuits, devices, or other electronic devices or semiconductor components.

[0088] A circuit or device described herein as including certain components may actually be adapted to be coupled to those components for forming the described circuitry or device. For example, a structure described as including one or more semiconductor elements (e.g., transistors), one or more passive elements (e.g., resistors, capacitors, and / or inductors), and / or one or more sources (e.g., voltage and / or current sources) may actually include only semiconductor elements within a single physical device (e.g., a semiconductor die and / or an integrated circuit (IC) package), and may be adapted to be coupled to at least some of the passive elements and / or sources to form the described structure at the time of manufacture or after manufacture, e.g., by a final user and / or a third party.

[0089] Although the use of specific transistors is described herein, other transistors (or equivalent devices) may be used with little or no change to the rest of the circuitry. For example, a field effect transistor (“FET”) (e.g., an n-channel FET (NFET) or a p-channel FET (PFET)), a bipolar junction transistor (BJT - e.g., an NPN transistor or a PNP transistor), an insulated gate bipolar transistor (IGBT), and / or a junction field effect transistor (JFET) may be used in place of or in combination with the devices described herein. The transistor can be a depletion-type device, a drain extension device, an enhancement-type device, a natural transistor, or other types of device structure transistors. Additionally, the device can be implemented in or on a silicon substrate (Si), a silicon carbide substrate (SiC), a gallium nitride substrate (GaN), or a gallium arsenide substrate (GaAs).

[0090] In the claims, reference may be made to the control input of a transistor and its current terminals. In the context of an FET, the control input is the gate, and the current terminals are the drain and source. In the context of a BJT, the control input is the base, and the current terminals are the collector and emitter.

[0091] As used herein, "turning on" an FET means that a conductive channel of the FET exists and a drain current can flow through the FET. As used herein, "turning off" an FET means that a conductive channel of the FET does not exist and a drain current does not flow through the FET. However, a "turned off" FET may have a current flowing through the body diode of the transistor.

[0092] The circuits described herein are reconfigurable to include additional or different components to provide functionality that is at least partially similar to the functionality available prior to component replacement. Unless otherwise stated, a component shown as a resistor generally represents any one or more elements coupled in series and / or in parallel to provide the amount of impedance represented by the shown resistor. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in parallel between the same nodes. For example, a resistor or capacitor shown and described herein as a single component may actually be multiple resistors or capacitors coupled in series between the same two nodes as a single resistor or capacitor.

[0093] Although some elements of the described examples are included in an integrated circuit and other elements are external to the integrated circuit, in other examples, additional or fewer features may be incorporated into the integrated circuit. Additionally, some or all of the features described as external to the integrated circuit may be included in the integrated circuit, and / or some features described as internal to the integrated circuit may be incorporated external to the integrated circuit. As used herein, the term "integrated circuit" means one or more circuits that: (i) are incorporated in / above a semiconductor substrate; (ii) are incorporated in a single semiconductor package; (iii) are incorporated into the same module; and / or (iv) are incorporated in / on the same printed circuit board.

[0094] The use of the phrase "ground" in the foregoing description includes chassis ground, earth ground, floating ground, virtual ground, digital ground, common ground, and / or any other form of ground connection applicable to or suitable for the teachings of this specification. In this specification, unless otherwise stated, "about", "substantially", or "essentially" before a parameter means within + / - 10% of the parameter.

[0095] Within the scope of the claims, modifications are possible in the described examples, and other examples are possible.

Claims

1. A controller, comprising: A ramp circuit, comprising: A ramp generation circuit system having a first control input and a first current output; A ramp adjustment circuit system having a second control input and a second current output; A current scaling circuit system having a first current input, a current sense output, and an offset current output, the first current input being coupled to the first current output and the second current output; And A ramp completion circuit system having a current sense input and a completion output, the current sense input being coupled to the current sense output; And Control logic having a third control input and first and second control outputs, the third control input being coupled to the completion output, the first control output being coupled to the first control input, and the second control output being coupled to the second control input.

2. The controller according to claim 1, wherein the control logic has a third control output, and the controller further comprises a charging circuit having an enable input and a charging output, the enable input being coupled to the third control output.

3. The controller according to claim 2, further comprising an error amplifier and a compensation network, the error amplifier having an error output and first and second amplifier inputs, the compensation network having an error input, a charging input, and a reference current control output, the error input being coupled to the error output, and the charging input being coupled to the charging output.

4. The controller according to claim 2, wherein the control logic has a fourth control output, the controller comprises a signal generator and first and second inverters, the signal generator having a fourth control input and first and second non-overlapping signal outputs, the fourth control input being coupled to the fourth control output, the first inverter having a first inverter input and a first inverter output, the first inverter input being coupled to the first non-overlapping signal output, the second inverter having a second inverter input and a second inverter output, and the second inverter input being coupled to the second non-overlapping signal output.

5. The controller according to claim 4, wherein the ramp circuit has first, second, third, and fourth signal inputs, the first signal input being coupled to the second non-overlapping signal output, the second signal input being coupled to the second inverter output, the third signal input being coupled to the first non-overlapping signal output, and the fourth signal input being coupled to the first inverter output.

6. The controller according to claim 5, wherein the ramp circuit comprises a first transmission gate and a second transmission gate, the first transmission gate having fifth and sixth control inputs, the fifth control input being coupled to the first signal input, the sixth control input being coupled to the second signal input, the second transmission gate having seventh and eighth control inputs, the seventh control input being coupled to the third signal input, and the eighth control input being coupled to the fourth signal input.

7. The controller according to claim 4, wherein the enable input is a first enable input, the control logic has a fifth control output, and the controller further includes a discharge circuit having a second enable input, a power input, and a ground terminal, the second enable input being coupled to the fifth control output.

8. The controller according to claim 3, further including a valley current sensing circuit having a sensing circuit input and a sensing circuit output, the sensing circuit input being coupled to the reference current control output.

9. The controller according to claim 8, wherein the sensing circuit input is a first sensing circuit input, and the valley current sensing circuit has a second sensing circuit input, a third sensing circuit input, and a fourth sensing circuit input.

10. The controller according to claim 9, wherein the valley current sensing circuit includes the ramp circuit, a voltage-to-current (V2I) converter, and a current comparator, the V2I converter having a V2I input and a V2I output, the V2I input being coupled to the first sensing circuit input, the current comparator having a comparator output and a first comparator input and a second comparator input, the first comparator input being coupled to the V2I output, the second comparator input being coupled to the V2I output and the offset current output, and the comparator output being coupled to the sensing circuit output.

11. A system, comprising: A power stage having a first power input, a first ground terminal, a first control input, a second control input, and a power output; And A controller having a sensing input, a second ground terminal, and a first control output and a second control output, the sensing input being coupled to the power output, the first control output being coupled to the first control input, the second control output being coupled to the second control input, the controller including a ramp circuit and control logic, The ramp circuit includes: A ramp generation circuitry having a third control input and a first current output; A ramp adjustment circuitry having a fourth control input and a second current output; A current scaling circuitry having a first current input, a current sensing output, and an offset current output, the first current input being coupled to the first current output and the second current output; A ramp completion circuitry having a current sensing input and a completion output, the current sensing input being coupled to the current sensing output; And The control logic having a fifth control input and a third control output and a fourth control output, the fifth control input being coupled to the completion output, the third control output being coupled to the third control input, and the fourth control output being coupled to the fourth control input.

12. The system according to claim 11, wherein the ramp generation circuitry is configured to initiate an offset current ramp in response to an enable signal received at the third control input, the ramp adjustment circuitry is configured to adjust a rate of the offset current ramp in response to an acceleration signal received at the fourth control input, the ramp completion circuitry is configured to provide a completion signal at the completion output in response to an offset current at the offset current output reaching a target threshold, and the control logic is configured to: provide the enable signal; provide the acceleration signal; and receive the completion signal.

13. The system according to claim 12, wherein the control logic is configured to provide the enable signal in response to an operation mode transition.

14. The system according to claim 13, wherein the operation mode transition involves a transition from a light load discontinuous conduction mode (DCM) to a light load forced continuous conduction mode (FCCM).

15. The system according to claim 13, wherein the control logic is configured to provide the acceleration signal in response to initiating a pause switching interval during the operation mode transition.

16. The system according to claim 13, wherein the enable signal is a first enable signal, the controller includes a compensation network and a charging circuit, and the charging circuit is configured to provide charge to a capacitor of the compensation network in response to a second enable signal provided by the control logic during the operation mode transition.

17. The system according to claim 16, wherein the second enable signal is provided in response to a pause switching signal.

18. The system according to claim 17, wherein the pause switching signal is provided in response to a voltage at the power output being greater than a threshold during the operation mode transition.

19. The system according to claim 18, wherein the controller includes a discharge circuit coupled to the power output, the discharge circuit being configured to couple the power output to a ground terminal in response to a condition indicating that there will no longer be a pause switching interval during the operation mode transition.

20. The system according to claim 19, wherein the threshold is a first threshold, and the condition includes the voltage at the power output dropping below a second threshold between the first threshold and a target output voltage.

21. The system according to claim 13, wherein the ramp adjustment circuitry adjusts an initial offset current in response to receiving the acceleration signal at the fourth control input.

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