Railway signal interlocking device fault detection method and system

Abstract

The application provides a railway signal interlocking equipment fault detection method and system, and relates to the technical field of railway power grids.The method comprises the following steps: acquiring a wiring drawing at the starting moment of a detection period; acquiring drawing information according to the wiring drawing; determining a terminal wiring fault detection score according to the drawing information; acquiring hardware state parameters at multiple moments in the detection period; determining an equipment hardware fault detection score according to the hardware state parameters; acquiring logic communication parameters at multiple moments in the detection period; determining a logic communication fault detection score according to the logic communication parameters; and producing an equipment fault detection report according to the terminal wiring fault detection score, the equipment hardware fault detection score and the logic communication fault detection score.According to the application, the terminal wiring fault condition, the hardware fault condition and the logic communication fault condition can be detected, and the comprehensiveness and accuracy of the signal interlocking equipment fault detection are improved.

Description

TECHNICAL FIELD

[0001] The present application relates to the technical field of railway power grid, and particularly relates to a railway signal interlocking equipment fault detection method and system. BACKGROUND

[0002] In the related art, the fault detection of the railway signal interlocking equipment mainly relies on manual detection by security personnel, that is, mainly depends on human factors, and the workload of the security work is very large, therefore, excessive dependence on human factors may be difficult to accurately investigate potential safety hazards, causing the problem of low efficiency of railway signal interlocking equipment fault detection.

[0003] The information disclosed in the background section of this application is only intended to deepen the understanding of the general background of the application and should not be regarded as acknowledging or implying in any form that this information constitutes prior art known to those skilled in the art. SUMMARY

[0004] The present application provides a railway signal interlocking equipment fault detection method and system, which can solve the technical problem of low efficiency of railway signal interlocking equipment fault detection caused by excessive dependence on human factors.

[0005] According to a first aspect of the present application, a railway signal interlocking equipment fault detection method is provided, comprising:

[0006] At the beginning of the detection period, the wiring drawing is acquired;

[0007] According to the wiring drawing, drawing information is acquired;

[0008] According to the drawing information, a terminal wiring fault detection score is determined;

[0009] At multiple moments in the detection period, hardware state parameters are acquired;

[0010] According to the hardware state parameters, a device hardware fault detection score is determined;

[0011] At multiple moments in the detection period, logic communication parameters are acquired;

[0012] According to the logic communication parameters, a logic communication fault detection score is determined;

[0013] According to the terminal wiring fault detection score, the device hardware fault detection score and the logic communication fault detection score, a device fault detection report is produced.

[0014] According to the present application, according to the wiring drawing, drawing information is acquired, comprising:

[0015] determining identifiable formatted data from the wiring diagram;

[0016] determining a cable ID from the identifiable formatted data;

[0017] determining a cable start terminal number and a cable end terminal number from the identifiable formatted data;

[0018] determining a list of legal terminal numbers from the identifiable formatted data.

[0019] According to the present application, determining a terminal wiring fault detection score from the diagram information, comprising:

[0020] determining a missing terminal number from the cable start terminal number, the cable end terminal number and the list of legal terminal numbers;

[0021] determining a number of the missing terminal number;

[0022] determining a single-ended error fault detection score from the number of the missing terminal number;

[0023] determining a double-ended error fault detection score from the cable ID, the cable start terminal number and the cable end terminal number;

[0024] determining a terminal wiring fault detection score from the single-ended error fault detection score and the double-ended error fault detection score.

[0025] According to the present application, determining a double-ended error fault detection score from the cable ID, the cable start terminal number and the cable end terminal number, comprising:

[0026] determining a same cable from the cable ID;

[0027] determining a cable start terminal number and a cable end terminal number of the same cable;

[0028] determining a double-ended error fault detection score from the cable start terminal number and the cable end terminal number of the same cable.

[0029] According to the present application, determining a device hardware fault detection score from the hardware status parameter, comprising:

[0030] determining a track circuit frequency, a track circuit impedance value, a power supply voltage and a device current from the hardware status parameter;

[0031] obtaining maintenance information, wherein the maintenance information comprises: a number of maintenance and a latest maintenance time;

[0032] inputting the track circuit frequency, the track circuit impedance value, the power supply voltage, the device current, the maintenance frequency and the latest maintenance time into a trained fault occurrence prediction model to determine a predicted fault occurrence time;

[0033] According to the predicted fault occurrence time, a device hardware fault detection score is determined.

[0034] According to the present application, the training step of the fault occurrence prediction model comprises:

[0035] Obtaining historical hardware state parameters and historical maintenance information of other signal interlocking devices in a historical detection period, wherein the historical hardware state parameters comprise historical track circuit frequency, historical track circuit impedance value, historical power supply voltage and historical device current, and the historical maintenance information comprises historical maintenance frequency and historical latest maintenance time;

[0036] Inputting the historical hardware state parameters and the historical maintenance information into a fault occurrence prediction model to determine a sample predicted fault occurrence time;

[0037] Obtaining historical fault occurrence times of other signal interlocking devices in a historical detection period;

[0038] According to the sample predicted fault occurrence time, the historical fault occurrence time, the historical hardware state parameters and the historical maintenance information, a training loss function of the fault occurrence prediction model is determined;

[0039] According to the training loss function of the fault occurrence prediction model, the fault occurrence prediction model is trained to obtain a trained fault occurrence prediction model.

[0040] According to the present application, according to the sample predicted fault occurrence time, the historical fault occurrence time, the historical hardware state parameters and the historical maintenance information, a training loss function of the fault occurrence prediction model is determined, comprising:

[0041] According to the formula

[0042]

[0043] determining a training loss function of the fault occurrence prediction model wherein, is a sample predicted fault occurrence time of the kth other signal interlocking device in the i th historical detection period, is a historical fault occurrence time of the kth other signal interlocking device in the i th historical detection period, is a historical track circuit frequency of the kth other signal interlocking device in the i th historical detection period, is a preset track circuit frequency threshold,​ is a historical track circuit impedance value of the kth other signal interlocking device in the ith historical detection period, is a preset track circuit impedance threshold value, is a historical power supply voltage of the kth other signal interlocking device in the ith historical detection period, is a preset power supply voltage threshold value, is a historical device current of the kth other signal interlocking device in the ith historical detection period, is a preset device current threshold value, is a historical maintenance frequency of the kth other signal interlocking device, is a preset maintenance frequency threshold value, is a historical recent maintenance time of the kth other signal interlocking device, is a preset maintenance time threshold value, K is the number of other signal interlocking devices, n is the number of historical detection periods, k≤K, i≤n, k, K, i and n are all positive integers.

[0044] According to the present application, the device hardware fault detection score is determined according to the predicted fault occurrence time, comprising:

[0045] According to the formula

[0046] ,

[0047] determining the device hardware fault detection score wherein if is a conditional function, is a predicted fault occurrence time, is a preset fault occurrence time threshold value.

[0048] According to the present application, the logical communication fault detection score is determined according to the logical communication parameters, comprising:

[0049] According to the logical communication parameters, the log information and the communication parameters are determined;

[0050] According to the log information, the locking event trigger record and the unlocking event trigger record are determined;

[0051] According to the locking event trigger record and the unlocking event trigger record, the logical fault detection result is determined;

[0052] According to the communication parameters, the transmission delay and the bit error rate are determined;

[0053] According to the transmission delay and the bit error rate, the communication fault detection result is determined;

[0054] According to the logical fault detection result and the communication fault detection result, the logical communication fault detection score is determined.

[0055] According to a second aspect of the present application, there is provided a railway signal interlocking equipment fault detection system, comprising:

[0056] a wiring diagram module configured to acquire a wiring diagram at a start time of a detection period;

[0057] a diagram information module configured to acquire diagram information according to the wiring diagram;

[0058] a wiring fault module configured to determine a terminal wiring fault detection score according to the diagram information;

[0059] a hardware parameter module configured to acquire hardware state parameters at multiple times in the detection period;

[0060] a hardware fault module configured to determine an equipment hardware fault detection score according to the hardware state parameters;

[0061] a software parameter module configured to acquire logic communication parameters at multiple times in the detection period;

[0062] a software fault module configured to determine a logic communication fault detection score according to the logic communication parameters;

[0063] a detection report module configured to produce an equipment fault detection report according to the terminal wiring fault detection score, the equipment hardware fault detection score, and the logic communication fault detection score.

[0064] Technical effects: According to the present application, the wiring drawing of the railway can be accurately obtained, and the hardware state parameters and logic communication parameters of the signal interlocking equipment are monitored. Further, the terminal wiring fault condition is detected according to the wiring drawing, the hardware fault condition is detected according to the hardware state parameters, and the logic communication fault condition is detected according to the logic communication parameters. The comprehensiveness and accuracy of the signal interlocking equipment fault detection are improved. In the process of obtaining the wiring drawing, the railway signal interlocking drawing resources are re-integrated, all related drawings are integrated into a unified and standard electronic document or system, the drawing management system construction from individual functional nodes to advantage functional nodes to full functional nodes is realized, the integrated management of drawing resources is formed, the structural innovation is realized, the transformation from paper resources to digital resources is realized, the single to big data direction is promoted, the data innovation is completed, the accuracy and efficiency of work are improved, the efficiency of drawing integration and checking can be greatly improved, the errors of manual operation are reduced, and strong technical support is provided for the maintenance and management of railway signal equipment. When determining the training loss function of the fault occurrence prediction model, the sample prediction fault occurrence time, historical fault occurrence time, historical hardware state parameters and historical maintenance information can be used to determine the training loss function of the fault occurrence prediction model. In the calculation process, the influence of track circuit frequency, track circuit impedance value, power supply voltage, equipment current, maintenance frequency and recent maintenance time on the possibility of signal interlocking equipment failure can be determined, and the influence of the above data on the error of the sample prediction fault occurrence time is determined. Based on the influence and the relative error of the sample prediction fault occurrence time, the training loss function is set, so that the fault occurrence prediction model reduces the training loss function in the training process, and more accurately improves the precision of the fault occurrence prediction model. When determining the equipment hardware fault detection score, the equipment hardware fault detection score can be determined according to the prediction fault occurrence time. In the calculation process, the running condition of the hardware equipment can be evaluated according to the prediction fault occurrence time, and the accuracy of the equipment hardware fault detection score is improved.

[0065] It should be understood that the above general description and the following detailed description are only exemplary and explanatory, but not limiting the present application. Other features and aspects of the present application will be more apparent from the following detailed description of exemplary embodiments with reference to the accompanying drawings. BRIEF DESCRIPTION OF DRAWINGS

[0066] In order to more clearly illustrate the technical solutions in the embodiments of the present application or the prior art, the drawings needed in the embodiment or prior art description will be briefly introduced below. Obviously, the drawings in the following description are only some embodiments of the present application, and those skilled in the art can also obtain other embodiments from these drawings without creative labor;

[0067] Figure 1 Fig. 1 shows a flowchart of a method for detecting faults of a railway signal interlocking device according to an embodiment of the present application;

[0068] Figure 2 Fig. 2 shows a flowchart of a process for obtaining drawing information according to an embodiment of the present application;

[0069] Figure 3 Fig. 3 shows a flowchart of a process for calculating a terminal wiring fault detection score according to an embodiment of the present application;

[0070] Figure 4 Fig. 4 shows a flowchart of a process for calculating a device hardware fault detection score according to an embodiment of the present application;

[0071] Figure 5 Fig. 5 shows a flowchart of a process for calculating a logic communication fault detection score according to an embodiment of the present application;

[0072] Figure 6 Fig. 6 shows a block diagram of a system for detecting faults of a railway signal interlocking device according to an embodiment of the present application. DETAILED DESCRIPTION

[0073] In order to make the objects, technical solutions and advantages of embodiments of the present application clearer, the following will be combined with the accompanying drawings for the embodiments of the present application to clearly and completely describe the technical solutions of the embodiments of the present application. Obviously, the described embodiments are only a part but not all of the embodiments of the present application. Based on the embodiments in the present application, all other embodiments obtained by a person of ordinary skill in the art without creative work fall within the protection scope of the present application.

[0074] The technical solutions of the present application will be described in detail in the following specific embodiments. The following specific embodiments can be combined with each other, and some embodiments can not be described again for the same or similar concepts or processes.

[0075] Figure 1 Fig. 1 shows a flowchart of a method for detecting faults of a railway signal interlocking device according to an embodiment of the present application, and the method comprises:

[0076] Step S1, obtaining a wiring drawing at a starting moment of a detection period;

[0077] Step S2, obtaining drawing information according to the wiring drawing;

[0078] Step S3, determining a terminal wiring fault detection score according to the drawing information;

[0079] Step S4, obtaining hardware state parameters at multiple moments in the detection period;

[0080] Step S5, determining a device hardware fault detection score according to the hardware state parameter;

[0081] Step S6, acquiring a logical communication parameter at multiple time points in a detection period;

[0082] Step S7, determining a logical communication fault detection score according to the logical communication parameter;

[0083] Step S8, producing a device fault detection report according to the terminal wiring fault detection score, the device hardware fault detection score and the logical communication fault detection score.

[0084] The railway signal interlocking device fault detection method according to the embodiment of the present application can accurately acquire the wiring drawing of the railway, and monitor the hardware state parameter and the logical communication parameter of the signal interlocking device. Further, the terminal wiring fault condition is detected according to the wiring drawing, the hardware fault condition is detected according to the hardware state parameter, and the logical communication fault condition is detected according to the logical communication parameter. The comprehensiveness and accuracy of the signal interlocking device fault detection are improved. In the process of acquiring the wiring drawing, the railway signal interlocking drawing resource is re-integrated, all related drawings are integrated into a unified and standard electronic document or system, the drawing management system construction from individual functional nodes to advantage functional nodes to full-process functional nodes is realized, the integrated management of drawing resources is formed, the structural innovation is realized, the transformation from paper resources to digital resources is realized, the single to big data direction is promoted, the data innovation is completed, the accuracy and efficiency of work are improved, the efficiency of drawing integration and checking can be greatly improved, the error of manual operation is reduced, and strong technical support is provided for the maintenance and management of railway signal equipment.

[0085] According to one embodiment of the present application, in step S1, the wiring drawing is acquired at the starting time point of the detection period.

[0086] For example, in order to quickly obtain the corresponding wiring drawing and ensure the information security of the wiring drawing, fine management of the access rights of internal users of the railway signal and establishment of a centralized drawing management platform of the railway signal equipment, wherein the specific measures of the fine management are to effectively control the access of the users to the functions and data of the system by setting different levels of user roles and corresponding permissions, which not only ensures the security of sensitive information and key operations, but also enables the users of various departments of the railway to focus on the work within their own scope of responsibility, thereby improving the work efficiency, the drawing management platform can effectively integrate and store various wiring drawings, including but not limited to zero-layer wiring drawings, side wiring drawings and distribution panel wiring drawings, and can use keyword search and drawing type screening functions to enable the users to quickly and accurately locate and access the required drawings. Through the drawing management platform, the corresponding wiring drawings of different formats of the railway signal interlocking equipment are obtained, and at the same time, the drawing management platform provides a convenient batch export function of the railway signal interlocking drawings, that is, the drawings are integrated and exported into a unified and standard electronic document or system, the user can select the type and range of the drawings to be exported, and the system will automatically generate the integrated drawing file, and the exported drawing format is xls format. It is convenient for subsequent distribution, printing or further processing in other design software, and the workflow of exporting a unified electronic document can be summarized as the following stages: first, input different types of drawings such as zero-layer wiring drawings, side wiring drawings and distribution panel wiring drawings into the system and convert them into a unified standardized template; then, the system exports the standardized drawings into a specific format of data file and imports it into the core database, next, the system integrates the wiring data of different specifications by using an intelligent algorithm to generate a complete and accurate electronic document for each station, on this basis, the drawings after the overhaul and the intermediate repair can also be updated and modified in real time to ensure the accuracy and timeliness of the drawings, and the latest drawings of each station can be viewed in real time on the dispatching terminal to meet the needs of emergency disposal.

[0087] According to one embodiment of the present application, in step S2, the drawing information is obtained according to the wiring drawing.

[0088] Figure 2 An exemplary flowchart of obtaining drawing information according to an embodiment of the present application is shown.

[0089] According to one embodiment of the present application, step S2 comprises:

[0090] In step S21, the recognizable formatted data is determined according to the wiring drawing.

[0091] In step S22, the cable ID is determined according to the recognizable formatted data.

[0092] Step S23, determining the cable start terminal number and the cable end terminal number according to the identifiable formatted data;

[0093] Step S24, determining a legal terminal number list according to the identifiable formatted data.

[0094] For example, different formats of wiring drawing papers (such as DWG, PDF, Excel wiring table) are converted into structured data (such as JSON, SQL database) that can be recognized by the system through a parser, ensuring uniform naming of fields; the cables in the wiring drawing paper have corresponding IDs, and the cable IDs are queried in the identifiable formatted data converted from the wiring drawing paper; the start terminal number and the end terminal number of the cable are queried in the identifiable formatted data, such as the start terminal number of the A cable is “X1-3” and the end terminal number is “X5-8”; all existing terminals in the design drawing are queried in the identifiable formatted data, and a legal terminal number list is determined according to the numbers of all existing terminals.

[0095] According to one embodiment of the present application, in step S3, a terminal wiring fault detection score is determined according to the drawing information.

[0096] Figure 3 An exemplary flowchart of terminal wiring fault detection score calculation according to an embodiment of the present application is shown.

[0097] According to one embodiment of the present application, step S3 includes:

[0098] Step S31, determining a missing terminal number according to the cable start terminal number, the cable end terminal number, and the legal terminal number list;

[0099] Step S32, determining the number of the missing terminal number;

[0100] Step S33, determining a single-end error fault detection score according to the number of the missing terminal number;

[0101] Step S34, determining a double-end error fault detection score according to the cable ID, the cable start terminal number, and the cable end terminal number;

[0102] Step S35, determining a terminal wiring fault detection score according to the single-end error fault detection score and the double-end error fault detection score.

[0103] For example, check whether the cable start terminal number and the cable end terminal number of each cable are in the legal terminal number list, if not, it is considered as a missing terminal, determine the number of the missing terminal, i.e. missing terminal number; determine the number of missing terminal numbers; if the number of missing terminal numbers is greater than 0, the single-end error fault detection score is 0, if the number of missing terminal numbers is equal to 0, the single-end error fault detection score is 1, the start or end terminal of a certain cable is not defined in the drawing, which may be misconnected to other terminals, resulting in short circuit, signal logic confusion and even traffic accident; according to the cable ID, the cable start terminal number and the cable end terminal number, it is judged whether double-end error occurs, and the double-end error fault detection score is determined, if double-end error occurs, the double-end error fault detection score is 0, if double-end error does not occur, the double-end error fault detection score is 2; according to the sum of the single-end error fault detection score and the double-end error fault detection score, the terminal wiring fault detection score is determined, by calculating the terminal wiring fault detection score, the wiring drawing can be intelligently checked, and whether the connection between the terminals is correct is automatically checked, when the terminal wiring fault detection score is less than 3, it indicates that the terminal has single-end error or double-end inconsistency, a prompt can be automatically generated, the incorrect wiring is highlighted, and drawing modification details are prompted, the drawing modification details contain the position information of the integrated drawing and the specific name of the integrated drawing. In order to facilitate the finding of specific errors, the drawing modification, and for the wiring design of the newly built signal station of the railway, a comprehensive consistency check can be performed, the wiring drawings of different systems and parts can be analyzed, and potential inconsistencies such as inconsistent terminal numbers and incorrect wiring sequence can be identified. Through automatic checking, the problems in the design can be found and corrected in time, and the coordination and consistency of the wiring information of each part are ensured.

[0104] According to one embodiment of the present application, step S34 comprises:

[0105] Step S341, according to the cable ID, determine the same cable;

[0106] Step S342, determine the cable start terminal number and the cable end terminal number of the same cable;

[0107] Step S343, according to the cable start terminal number and the cable end terminal number of the same cable, determine the double-end error fault detection score.

[0108] For example, according to the cable ID, the same cable in different wiring diagrams is determined, such as the A cable appearing in the power diagram and the interlocking diagram at the same time; the cable start terminal number and the cable end terminal number of the same cable in different wiring diagrams are determined, such as the cable start terminal number and the cable end terminal number of the A cable in the power diagram and the interlocking diagram respectively; it is judged whether the cable start terminal number and the cable end terminal number of the same cable match, if there is a mismatch, it indicates that the cable cross-diagram definition conflict (for example, the cable W001 is connected X1-3→X2-5 in the power diagram, but is connected X1-3→X3-2 in the interlocking diagram), which may cause signal malfunction or equipment damage, and the double-end error fault detection score is 0, if there is no mismatch, the double-end error fault detection score is 2.

[0109] According to one embodiment of the present application, in step S4, the hardware state parameters are obtained at multiple time points in the detection period.

[0110] For example, the railway signal interlocking equipment (such as the track circuit, system power supply and turnout motor) is detected by professional detection equipment (such as a digital multimeter and a track circuit analyzer) to obtain the hardware state parameters (such as the track circuit frequency and the track circuit impedance), wherein the hardware state parameters are the average values of the railway signal interlocking equipment in the detection period, such as the track circuit frequency in the first detection period being the average value of the track circuit frequency at multiple time points in the first detection period.

[0111] According to one embodiment of the present application, in step S5, the equipment hardware fault detection score can be determined, and in the process of determining the equipment hardware fault detection score, the time of the signal interlocking equipment failure predicted by the trained fault occurrence prediction model can be predicted, and the equipment hardware fault detection score can be determined according to the predicted time of the signal interlocking equipment failure.

[0112] According to one embodiment of the present application, the training step of the fault occurrence prediction model comprises:

[0113] The historical hardware state parameters and the historical maintenance information of other signal interlocking equipment in the historical detection period are obtained, wherein the historical hardware state parameters comprise historical track circuit frequency, historical track circuit impedance value, historical power supply voltage and historical equipment current, and the historical maintenance information comprises historical maintenance frequency and historical recent maintenance time;

[0114] The historical hardware state parameters and the historical maintenance information are input into the fault occurrence prediction model to determine the sample predicted fault occurrence time;

[0115] The historical fault occurrence time of other signal interlocking equipment in the historical detection period is obtained;

[0116] determine a training loss function of the failure occurrence prediction model according to the sample predicted failure occurrence time, the historical failure occurrence time, the historical hardware state parameter and the historical maintenance information;

[0117] train the failure occurrence prediction model according to the training loss function of the failure occurrence prediction model, and obtain a trained failure occurrence prediction model.

[0118] For example, a signal interlocking device in another railway line outside the railway line is determined as another signal interlocking device, and in the historical database, historical hardware state parameters and historical maintenance information of the other signal interlocking device in a historical detection period are obtained, wherein the historical track circuit frequency is an average frequency of a track circuit in the signal interlocking device in the historical detection period, the historical track circuit impedance value is an average impedance value of the track circuit in the signal interlocking device in the historical detection period, the historical power supply voltage is an average voltage of a system power supply in the signal interlocking device in the historical detection period, the historical device current is an average current of a switch motor in the signal interlocking device, the historical maintenance frequency is a total number of times of maintenance of all single devices contained in the signal interlocking device in the railway line, and the historical recent maintenance time is a time length from a date of the most recent maintenance of the signal interlocking device in the railway line to a date of the historical detection period. For example, the date corresponding to the historical detection period is January 8, and the most recent maintenance of the signal interlocking device in the railway line is on January 7, so the historical recent maintenance time of the other signal interlocking device in the historical detection period is 1 day. The failure occurrence prediction model is one of deep learning models, the failure occurrence prediction model can process hardware state parameters and maintenance information, and predict a time of failure occurrence of the signal interlocking device. The historical failure occurrence time of the other signal interlocking device in the historical detection period is obtained, for example, the first other signal interlocking device is detected in the first historical detection period, the date corresponding to the first historical detection period is January 1, and the other signal interlocking device fails on January 3, so the historical failure occurrence time of the first other signal interlocking device in the first historical detection period is 2 days. The training loss function of the failure occurrence prediction model is determined according to the sample predicted failure occurrence time, the historical failure occurrence time, the historical hardware state parameter and the historical maintenance information. The failure occurrence prediction model is trained using the training loss function of the failure occurrence prediction model, and a trained failure occurrence prediction model is obtained.

[0119] According to one embodiment of the present application, the training loss function of the failure occurrence prediction model is determined according to the sample predicted failure occurrence time, the historical failure occurrence time, the historical hardware state parameter and the historical maintenance information, including: determining the training loss function of the failure occurrence prediction model according to formula (1) ,

[0120] (1),

[0121] wherein, is the sample predicted failure occurrence time of the kth other signal interlocking device in the ith historical detection period, is the historical failure occurrence time of the kth other signal interlocking device in the ith historical detection period, is the historical track circuit frequency of the kth other signal interlocking device in the ith historical detection period, is a preset track circuit frequency threshold value, is the historical track circuit impedance value of the kth other signal interlocking device in the ith historical detection period, is a preset track circuit impedance threshold value, is the historical power supply voltage of the kth other signal interlocking device in the ith historical detection period, is a preset power supply voltage threshold value, is the historical device current of the kth other signal interlocking device in the ith historical detection period, is a preset device current threshold value, is the historical maintenance frequency of the kth other signal interlocking device, is a preset maintenance frequency threshold value, is the historical recent maintenance time of the kth other signal interlocking device, is a preset maintenance time threshold value, K is the number of other signal interlocking devices, n is the number of historical detection periods, k≤K, i≤n, k, K, i and n are all positive integers.

[0122] According to one embodiment of the present application, is the relative difference between the historical track circuit frequency of the kth other signal interlocking device in the ith historical detection period and the preset track circuit frequency threshold value, the greater the value, the greater the difference between the historical track circuit frequency of the kth other signal interlocking device in the ith historical detection period and the preset track circuit frequency threshold value, wherein the preset track circuit frequency threshold value is determined according to the setting scheme of the track circuit, and is generally 25 Hz, is the relative difference between the historical track circuit impedance value of the kth other signal interlocking device in the ith historical detection period and the preset track circuit impedance threshold value, the greater the value, the greater the difference between the historical track circuit impedance value of the kth other signal interlocking device in the ith historical detection period and the preset track circuit impedance threshold value, input the rail parameters and frequency into professional calculation software (such as MATLAB / Simulink, ETAP) to calculate the theoretical impedance value, i.e. the preset track circuit impedance threshold value, a relative difference between the historical power supply voltage of the kth other signal interlocking device in the ith historical detection period and a preset power supply voltage threshold, the larger the ratio, the greater the difference between the historical power supply voltage of the kth other signal interlocking device in the ith historical detection period and the preset power supply voltage threshold, wherein the preset power supply voltage threshold is determined according to the rated voltage of the power supply, a relative difference between the historical device current of the kth other signal interlocking device in the ith historical detection period and a preset device current threshold, the larger the ratio, the greater the difference between the historical device current of the kth other signal interlocking device in the ith historical detection period and the preset device current threshold, wherein the preset device current threshold is determined according to the rated current of the device, The relative difference between the historical track circuit frequency and the preset track circuit frequency threshold, the relative difference between the historical track circuit impedance value and the preset track circuit impedance threshold, the relative difference between the historical power supply voltage and the preset power supply voltage threshold, and the relative difference between the historical device current and the preset device current threshold are negatively correlated with the size of the sample predicted failure occurrence time. For example, when the track circuit frequency is too high relative to the preset track circuit frequency, it may be incorrectly received by the filter of the adjacent section, leading to a false judgment of the section being idle, and the greater the possibility of failure, the smaller the sample predicted failure occurrence time. When the track circuit frequency is too low relative to the preset track circuit frequency, the frequency reduction may cause signal energy attenuation (e.g., unstable power supply voltage or circuit resonance failure), and the receiving end cannot identify the valid signal, resulting in a false judgment of "occupied" and a greater possibility of failure, and the smaller the sample predicted failure occurrence time. When the historical track circuit impedance value is too large relative to the preset track circuit impedance threshold, the signal from the sending end may not reach the receiving end, resulting in a receiving voltage of zero and a false judgment of "occupied" and a greater possibility of failure, and the smaller the sample predicted failure occurrence time. When the historical track circuit impedance value is too small relative to the preset track circuit impedance threshold, a short circuit will shunt the track circuit current, causing a sudden drop in the receiving end voltage and a false judgment of "occupied", and a long-term short circuit may burn out the sending end device (e.g., transformer), resulting in a greater possibility of failure and a smaller sample predicted failure occurrence time. When the historical power supply voltage is too large relative to the preset power supply voltage threshold, it may cause the signal lamp to be incorrectly lit (e.g., the green light is abnormally bright), the relay coil to overheat and fuse, the capacitor to break down, and the electronic components to be damaged, resulting in a greater possibility of failure and a smaller sample predicted failure occurrence time. When the historical power supply voltage is too small relative to the preset power supply voltage threshold, it may cause the relay to fail to attract (resulting in a failure of the interlocking logic) and the signal lamp to be dim, resulting in a greater possibility of failure and a smaller sample predicted failure occurrence time. When the historical device current is too large relative to the preset device current threshold, it may trigger a false alarm (e.g., a false section occupied signal), resulting in a greater possibility of failure and a smaller sample predicted failure occurrence time. When the historical device current is too small relative to the preset device current threshold, it may cause the signal to be displayed incompletely (e.g., the yellow light is not lit, resulting in a driving instruction error), resulting in a greater possibility of failure and a smaller sample predicted failure occurrence time. Therefore, the terms related to the historical track circuit frequency, the historical track circuit impedance value, the historical power supply voltage, and the historical device current are placed in the denominator, and the smaller the values of 、 、 and are, the larger the value of the sample predicted failure occurrence time is.

[0123] According to one embodiment of the present application, a ratio of the historical maintenance times of the kth other signal interlocking device to a preset maintenance times threshold, the larger the ratio, the more the historical maintenance times of the kth other signal interlocking device, wherein the preset maintenance times threshold can be determined according to the service life of the signal interlocking device, for example, when the service life of the signal interlocking device is 1 year, the preset maintenance times threshold of the signal interlocking device is 1, when the service life of the signal interlocking device is 2 years, the preset maintenance times threshold of the signal interlocking device is 2, and so on, a ratio of the historical recent maintenance time of the kth other signal interlocking device to a preset maintenance time threshold, the larger the ratio, the larger the value of the historical recent maintenance time of the kth other signal interlocking device, wherein the preset maintenance time threshold can be set to 30 days, indicating that the historical maintenance times and the historical recent maintenance time are negatively correlated with the sample predicted failure occurrence time, for example, when the historical maintenance times are larger, it indicates that the device is frequently maintained, the service life of the device can be shorter, and the possibility of failure is larger, and the sample predicted failure occurrence time is smaller, when the value of the historical recent maintenance time is larger, it indicates that the time from the last maintenance of the device is longer, and the running state of the device can be poorer, and the possibility of failure is larger, and the sample predicted failure occurrence time is smaller. Therefore, the term related to the historical maintenance times and the historical recent maintenance time is placed in the denominator, indicating and the smaller the value of the sample predicted failure occurrence time is.

[0124] According to one embodiment of the present application, a relative error of the sample predicted failure occurrence time of the kth other signal interlocking device in the i th historical detection period to the historical failure occurrence time, using and the relative errors of the sample predicted failure occurrence time of the other signal interlocking device in the historical detection period to the historical failure occurrence time are weighted and averaged to obtain a training loss function. In the training process, the training loss function is reduced, so that the error between the sample predicted failure occurrence time and the historical failure occurrence time is reduced, the prediction accuracy of the failure occurrence prediction model for the failure occurrence time is improved, and the accuracy of the failure occurrence prediction model is improved

[0125] In this way, the fault occurrence prediction model training loss function can be determined according to the sample predicted fault occurrence time, the historical fault occurrence time, the historical hardware state parameter and the historical maintenance information. In the calculation process, the influence of the track circuit frequency, the track circuit impedance value, the power supply voltage, the equipment current, the maintenance frequency and the recent maintenance time on the possibility of the signal interlocking device failure can be determined to determine the influence of the above data on the error of the sample predicted fault occurrence time, and the training loss function is set based on the influence and the relative error of the sample predicted fault occurrence time, so that the fault occurrence prediction model reduces the training loss function in the training process, and more accurately improves the accuracy of the fault occurrence prediction model.

[0126] According to an embodiment of the application, in step S5, a device hardware fault detection score is determined according to the hardware state parameter.

[0127] Figure 4 An exemplary flowchart of device hardware fault detection score calculation according to an embodiment of the application is shown.

[0128] According to an embodiment of the application, step S5 includes:

[0129] Step S51, determining the track circuit frequency, the track circuit impedance value, the power supply voltage and the equipment current according to the hardware state parameter;

[0130] Step S52, obtaining maintenance information, wherein the maintenance information includes: maintenance frequency and recent maintenance time;

[0131] Step S53, inputting the track circuit frequency, the track circuit impedance value, the power supply voltage, the equipment current, the maintenance frequency and the recent maintenance time into the trained fault occurrence prediction model to determine the predicted fault occurrence time;

[0132] Step S54, determining the device hardware fault detection score according to the predicted fault occurrence time.

[0133] For example, the track circuit frequency, the track circuit impedance value, the power supply voltage and the equipment current of the signal interlocking device are obtained by a digital multimeter and a track circuit analyzer. The track circuit frequency, the track circuit impedance value, the power supply voltage, the equipment current, the maintenance frequency and the recent maintenance time are processed by the trained fault occurrence prediction model to obtain the time length from the current detection period to the next fault occurrence, i.e. the predicted fault occurrence time. According to the predicted fault occurrence time, the device hardware fault detection score is determined by evaluating whether the device hardware has failed and the running status of the hardware.

[0134] According to one embodiment of the present application, step S54 comprises determining the device hardware fault detection score according to formula (2) ,

[0135] (2),

[0136] wherein if is a conditional function, is a predicted fault occurrence time, is a preset fault occurrence time threshold.

[0137] According to one embodiment of the present application, in formula (2), the value of conditional function includes the following two cases: when the condition of 0 is met, it indicates that a fault has occurred at this time, and the value of the conditional function is 0; when the condition of 0 is not met, it indicates that no fault has occurred, and the value of the conditional function is , is the ratio of the predicted fault occurrence time to the preset fault occurrence time threshold, and the larger the ratio, the smaller the possibility of a fault occurring in the signal interlocking device, wherein the preset fault occurrence time threshold can be set to thirty days.

[0138] In this way, the device hardware fault detection score can be determined according to the predicted fault occurrence time, and in the calculation process, the operating condition of the hardware device can be evaluated according to the predicted fault occurrence time, thereby improving the accuracy of the device hardware fault detection score.

[0139] According to one embodiment of the present application, in step S6, the logical communication parameters are obtained at multiple times in the detection period.

[0140] For example, after authorization by the operating unit, the interlocking device status, communication messages and fault information are automatically collected by the signal centralized monitoring system (CSM), and the log information and communication parameters, i.e. the logical communication parameters, are obtained.

[0141] According to one embodiment of the present application, in step S7, a logical communication fault detection score is determined according to the logical communication parameters.

[0142] Figure 5 An exemplary flowchart of the calculation of the logical communication fault detection score according to an embodiment of the present application is shown.

[0143] According to one embodiment of the present application, step S7 comprises:

[0144] Step S71, determining the log information and communication parameters according to the logical communication parameters;

[0145] Step S72, according to the log information, determine the locking event trigger record and the unlocking event trigger record;

[0146] Step S73, according to the locking event trigger record and the unlocking event trigger record, determine the logical fault detection result;

[0147] Step S74, according to the communication parameter, determine the transmission delay and the bit error rate;

[0148] Step S75, according to the transmission delay and the bit error rate, determine the communication fault detection result;

[0149] Step S76, according to the logical fault detection result and the communication fault detection result, determine the logical communication fault detection score.

[0150] For example, the log information and the communication parameter are obtained through the signal centralized monitoring system; in the log information, the locking event trigger record and the unlocking event trigger record are queried; the use case is automatically generated by the scene-based test framework (such as TestRail), all locking / unlocking condition branches are covered, and the automatic tool is used to check whether the locking event trigger record and the unlocking event trigger record conform to the preset logic, if not, the logical fault detection result is 0, indicating that there is a conflict record in the interlocking system, and there is a logical error, if the logic is met, the logical fault detection result is 1; in the communication parameter, the transmission delay and the bit error rate of the signal interlocking device are obtained; the preset transmission delay threshold is set to 500ms, and the preset bit error rate threshold is set to if the transmission delay and the bit error rate are both less than the preset transmission delay threshold and the preset bit error rate threshold, the communication fault detection result is 2, if any of the transmission delay and the bit error rate is greater than the corresponding set threshold, the communication fault detection result is 0; the logical communication fault detection score is determined by summing the logical fault detection result and the communication fault detection result.

[0151] According to one embodiment of the present application, in step S8, according to the terminal wiring fault detection score, the equipment hardware fault detection score and the logical communication fault detection score, a production equipment fault detection report is generated.

[0152] For example, if the terminal wiring fault detection score is 3, it means that the connection between the terminals is correct, if the terminal wiring fault detection score is 1, it means that the terminals have double-end inconsistency, if the terminal wiring fault detection score is 2, it means that the terminals have single-end error, if the terminal wiring fault detection score is 0, it means that the terminals have double-end inconsistency and single-end error; if the equipment hardware fault detection score is equal to 0, it means that a fault has occurred, and the staff is notified to repair; if the equipment hardware fault detection score is less than 1, it means that the signal interlocking equipment has the possibility of malfunction, and the staff is notified to maintain the equipment; if the equipment hardware fault detection score is greater than 1, it means that the working condition of the signal interlocking equipment is good; if the logic communication fault detection score is 3, it means that the communication condition and logic condition of the signal interlocking equipment are good, if the logic communication fault detection score is 1, it means that the communication condition of the signal interlocking equipment is poor, if the logic communication fault detection score is 2, it means that the running logic of the signal interlocking equipment has errors, and if the logic communication fault detection score is 0, it means that the communication condition of the signal interlocking equipment is poor and the running logic has errors.

[0153] The railway signal interlocking device fault detection method according to the embodiment of the present application can accurately acquire the wiring drawing of the railway, and monitor the hardware state parameters and the logic communication parameters of the signal interlocking device, further, detects the terminal wiring fault condition according to the wiring drawing, detects the hardware fault condition according to the hardware state parameters, and detects the logic communication fault condition according to the logic communication parameters, thereby improving the comprehensiveness and accuracy of the signal interlocking device fault detection, and in the process of acquiring the wiring drawing, the railway signal interlocking drawing resource is re-integrated, all related drawings are integrated into a unified and standard electronic document or system, the drawing management system construction from individual functional nodes to advantageous functional nodes to full-process functional nodes is realized, the integrated management of drawing resources is formed, the structural innovation is realized, the transformation from paper resources to digital resources is realized, the single to big data transformation is promoted, the data innovation is completed, the accuracy and efficiency of work are improved, the efficiency of drawing integration and checking can be greatly improved, the errors of manual operation are reduced, and strong technical support is provided for the maintenance and management of railway signal equipment. When determining the training loss function of the fault occurrence prediction model, the training loss function of the fault occurrence prediction model can be determined according to the sample prediction fault occurrence time, the historical fault occurrence time, the historical hardware state parameters and the historical maintenance information. In the calculation process, the influence of the track circuit frequency, the track circuit impedance value, the power supply voltage, the equipment current, the maintenance frequency and the latest maintenance time on the possibility of the signal interlocking device failure can be determined, and the influence of the above data on the error of the sample prediction fault occurrence time is determined, and the training loss function is set based on the influence and the relative error of the sample prediction fault occurrence time, so that the fault occurrence prediction model in the training process reduces the training loss function and more accurately improves the precision of the fault occurrence prediction model. When determining the device hardware fault detection score, the device hardware fault detection score can be determined according to the prediction fault occurrence time. In the calculation process, the running condition of the hardware device can be evaluated according to the prediction fault occurrence time, thereby improving the accuracy of the device hardware fault detection score.

[0154] Figure 6 An example block diagram of a railway signal interlocking device fault detection system according to an embodiment of the present application is shown, which includes:

[0155] A wiring drawing module is configured to acquire a wiring drawing at the beginning of a detection period.

[0156] A drawing information module is configured to acquire drawing information according to the wiring drawing.

[0157] A wiring fault module is configured to determine a terminal wiring fault detection score according to the drawing information.

[0158] a hardware parameter module, configured to acquire hardware state parameters at multiple time points in a detection period;

[0159] a hardware fault module, configured to determine a device hardware fault detection score according to the hardware state parameters;

[0160] a software parameter module, configured to acquire logic communication parameters at multiple time points in the detection period;

[0161] a software fault module, configured to determine a logic communication fault detection score according to the logic communication parameters;

[0162] a detection report module, configured to produce a device fault detection report according to the terminal wiring fault detection score, the device hardware fault detection score and the logic communication fault detection score.

[0163] The present application can be a method, an apparatus, a system, and / or a computer program product. The computer program product can include a computer readable storage medium having computer readable program instructions embodied therewith, the computer readable program instructions being used to perform various aspects of the present application.

[0164] Those skilled in the art understand that the above-described embodiments of the present application shown in the description and drawings are only examples and do not limit the present application. The purpose of the present application has been fully and effectively achieved. The function and structural principle of the present application has been shown and described in the embodiments, and the embodiments of the present application can be any modification or modification without departing from the principle.

Claims

1. A method of detecting a failure of a railway signal interlocking device, characterized by, The method comprises: acquiring a wiring diagram at a start time of a detection period; acquiring diagram information according to the wiring diagram; determining a terminal wiring fault detection score according to the diagram information; acquiring hardware state parameters at multiple times in the detection period; determining a device hardware fault detection score according to the hardware state parameters; acquiring logic communication parameters at multiple times in the detection period; determining a logic communication fault detection score according to the logic communication parameters; producing a device fault detection report according to the terminal wiring fault detection score, the device hardware fault detection score, and the logic communication fault detection score; determining a device hardware fault detection score according to the hardware state parameters, comprising: determining a track circuit frequency, a track circuit impedance value, a power supply voltage, and a device current according to the hardware state parameters; acquiring maintenance information, wherein the maintenance information comprises a maintenance frequency and a recent maintenance time; inputting the track circuit frequency, the track circuit impedance value, the power supply voltage, the device current, the maintenance frequency, and the recent maintenance time into a trained fault occurrence prediction model to determine a predicted fault occurrence time; determining a device hardware fault detection score according to the predicted fault occurrence time; the training step of the fault occurrence prediction model comprises: acquiring historical hardware state parameters and historical maintenance information of other signal interlocking devices in a historical detection period, wherein the historical hardware state parameters comprise a historical track circuit frequency, a historical track circuit impedance value, a historical power supply voltage, and a historical device current, and the historical maintenance information comprises a historical maintenance frequency and a historical recent maintenance time; inputting the historical hardware state parameters and the historical maintenance information into a fault occurrence prediction model to determine a sample predicted fault occurrence time; acquiring a historical fault occurrence time of other signal interlocking devices in a historical detection period; determining a training loss function of the fault occurrence prediction model according to the sample predicted fault occurrence time, the historical fault occurrence time, the historical hardware state parameters, and the historical maintenance information; training the fault occurrence prediction model according to the training loss function of the fault occurrence prediction model to obtain a trained fault occurrence prediction model.

2. The railway signal interlocking device failure detection method according to claim 1, characterized by, acquiring diagram information according to the wiring diagram, comprising: determining identifiable formatted data according to the wiring diagram; determining a cable ID according to the identifiable formatted data; determining a cable start terminal number and a cable end terminal number according to the identifiable formatted data; determining a legal terminal number list according to the identifiable formatted data.

3. The railway signal interlocking device failure detection method according to claim 2, characterized by, determining a terminal wiring fault detection score according to the diagram information, comprising: determining a missing terminal number according to the cable start terminal number, the cable end terminal number, and the legal terminal number list; determining a number of the missing terminal numbers; determining a single-end error fault detection score according to the number of the missing terminal numbers; determining a double-end error fault detection score according to the cable ID, the cable start terminal number, and the cable end terminal number; According to the single-end error fault detection score and the double-end error fault detection score, a terminal wiring fault detection score is determined.

4. The railway signal interlocking device failure detection method according to claim 3, characterized by, According to the cable ID, the cable start terminal number and the cable end terminal number, a double-end error fault detection score is determined, including: According to the cable ID, a same cable is determined; The cable start terminal number and the cable end terminal number of the same cable are determined; According to the cable start terminal number and the cable end terminal number of the same cable, a double-end error fault detection score is determined.

5. The method of claim 1, wherein, According to the sample predicted fault occurrence time, the historical fault occurrence time, the historical hardware state parameter and the historical maintenance information, a training loss function of a fault occurrence prediction model is determined, including: According to the formula ， Training loss function for determining a failure occurrence prediction model wherein, is a sample predicted failure occurrence time of the kth other signal interlocking device in the ith historical detection period, is a historical failure occurrence time of the kth other signal interlocking device in the ith historical detection period, is a historical track circuit frequency of the kth other signal interlocking device in the ith historical detection period, is a preset track circuit frequency threshold, is a historical track circuit impedance value of the kth other signal interlocking device in the ith historical detection period, is a preset track circuit impedance threshold, is a historical power supply voltage of the kth other signal interlocking device in the ith historical detection period, is a preset power supply voltage threshold, is a historical device current of the kth other signal interlocking device in the ith historical detection period, is a preset device current threshold, is a historical maintenance frequency of the kth other signal interlocking device, is a preset maintenance frequency threshold, is a historical recent maintenance time of the kth other signal interlocking device, is a preset maintenance time threshold, K is the number of other signal interlocking devices, n is the number of historical detection periods, k≤K, i≤n, k, K, i and n are all positive integers.

6. The method of claim 1, wherein, According to the predicted fault occurrence time, a device hardware fault detection score is determined, including: According to the formula ， Determining device hardware failure detection scores where if is a conditional function, is a predicted time to failure, is a predetermined time to failure threshold.

7. The method of claim 1, wherein, According to the logical communication parameter, a logical communication fault detection score is determined, including: According to the logical communication parameter, log information and a first communication parameter are determined; According to the log information, a lock event trigger record and an unlock event trigger record are determined; According to the lock event trigger record and the unlock event trigger record, a logical fault detection result is determined; According to the first communication parameter, a transmission delay and a bit error rate are determined; According to the transmission delay and the bit error rate, a communication fault detection result is determined; According to the logical fault detection result and the communication fault detection result, a logical communication fault detection score is determined.

8. A railway signal interlocking equipment failure detection system for performing the method of any one of claims 1-7, characterized by Including: A wiring drawing module is configured to acquire a wiring drawing at a starting time of a detection period; A drawing information module is configured to acquire drawing information according to the wiring drawing; A wiring fault module is configured to determine a terminal wiring fault detection score according to the drawing information; A hardware parameter module is configured to acquire hardware state parameters at multiple time points in the detection period; A hardware fault module is configured to determine a device hardware fault detection score according to the hardware state parameters; A software parameter module is configured to acquire logical communication parameters at multiple time points in the detection period; A software fault module is configured to determine a logical communication fault detection score according to the logical communication parameters; A detection report module is configured to produce a device fault detection report according to the terminal wiring fault detection score, the device hardware fault detection score and the logical communication fault detection score.

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