A method and system for detecting the pressure resistance performance of LCD logic board substrate

Abstract

The present invention discloses a method and system for testing the withstand voltage performance of LCD logic board substrates. The method comprises the following steps: pre-processing a sample of the LCD logic board substrate; configuring a multi-stage stepped voltage loading sequence; installing a distributed electrode array; performing a dynamic withstand voltage test and recording test parameters, including inter-electrode leakage current and current fluctuation characteristic parameters, local temperature rise distribution data of the LCD logic board substrate sample, and surface deformation of the LCD logic board substrate sample; constructing a composite failure assessment model based on the test parameters and outputting a withstand voltage stability coefficient; and grading withstand voltage performance based on the withstand voltage stability coefficient. The present invention has the following advantages and effects: it can simultaneously monitor multiple electrical, thermal, and mechanical parameters and establish a core detection method for a dynamic failure quantification model, ultimately improving the accuracy and reliability of the withstand voltage performance test results of LCD logic board substrates.

Description

Technical Field

[0001] The present invention relates to the technical field of LCD logic board testing, and in particular to a method and system for detecting the voltage resistance performance of an LCD logic board substrate. Background Art

[0002] As a key component connecting the image processing chip and the panel, the insulation and voltage resistance of the LCD logic board substrate directly determines the reliability and safety of the entire device. Under conditions such as high-voltage drive signal transmission or surge impact, substrate insulation failure will cause circuit short circuits, signal distortion, device burnout, and even safety accidents. Therefore, accurate and reliable voltage resistance performance testing of LCD logic board substrates is crucial. Currently, the industry generally uses static breakdown voltage testing or single step voltage application methods to test the voltage resistance performance of LCD logic board substrates. These methods have the following fundamental flaws:

[0003] First, the failure mechanism is one-sided, using only the dielectric breakdown voltage as the sole criterion, ignoring the coupling effect of the electrical, thermal, and mechanical multi-physical fields in actual work; the leakage current fluctuations, local temperature rise gradients, and deformation accumulation generated by the LCD logic board substrate during the dynamic boost process are all key factors that induce insulation performance degradation, but existing methods are unable to capture these dynamic parameters.

[0004] Secondly, the lack of risk prediction caused by the one-sidedness of the above-mentioned failure mechanism leads to the final judgment results often deviating from the actual performance in the actual application scenario; and the output result of the traditional method is a binary judgment of pass / fail, which cannot reflect the stability margin and potential risk level of the material's pressure resistance performance.

[0005] Therefore, there is an urgent need for a core detection method that can simultaneously monitor multiple electrical, thermal, and mechanical parameters and establish a dynamic failure quantification model. Summary of the Invention

[0006] The purpose of the present invention is to provide a method and system for detecting the voltage resistance performance of an LCD logic board substrate, so as to solve the problems raised in the background technology.

[0007] The above technical objectives of the present invention are achieved through the following technical solutions:

[0008] The present invention provides a method for detecting the pressure resistance performance of an LCD logic board substrate, comprising the following steps:

[0009] S100, pre-treating a substrate sample of an LCD logic circuit board;

[0010] S200, configure a multi-step voltage loading sequence; including:

[0011] Based on the rated operating voltage of the substrate sample of the LCD logic circuit board, generating a stepped voltage loading sequence comprising multiple pressurization stages, wherein the voltage of the first stage is a proportional voltage of the rated voltage, and the voltage of each subsequent stage increases according to a preset proportion, and the duration of each stage is set to a preset holding time;

[0012] S300, installation of distributed electrode array; including:

[0013] Arranging a plurality of electrode pairs on the surface of the substrate sample of the LCD logic circuit board, wherein the spacing between each electrode pair is controlled within a preset tolerance range, and the electrodes in each electrode pair are coated with an insulating coating of a preset thickness;

[0014] S400, perform dynamic withstand voltage test; including:

[0015] Applying a test voltage to each electrode pair using a high-voltage generator according to the step-wise voltage loading sequence, while simultaneously monitoring and recording test parameters in real time at a preset sampling frequency; wherein the test parameters include inter-electrode leakage current value and current fluctuation characteristic parameters, local temperature rise distribution data of a substrate sample of an LCD logic circuit board, and surface deformation of the substrate sample of the LCD logic circuit board;

[0016] S500, constructing a composite failure assessment model based on the test parameters, and outputting a withstand voltage stability coefficient;

[0017] S600: Determine the pressure resistance performance level based on the pressure resistance stability coefficient.

[0018] By adopting the above technical solution, LCD logic circuit board substrate samples are pre-treated to ensure that they meet multiple quality control requirements for electrostatic discharge, charge, temperature and humidity, and surface cleanliness before testing. This eliminates interference from environmental or sample defects on withstand voltage test results and improves the reliability and repeatability of test data. A multi-step voltage loading sequence is automatically generated based on the rated operating voltage, accurately matching the loading voltage to the actual withstand capacity of the LCD logic circuit board substrate sample. The duration of each stage is maintained constant to fully reflect the transient and steady-state response characteristics of the medium at different voltage levels, thereby more comprehensively evaluating the withstand voltage performance. The design of a distributed electrode array and insulating coating enables multi-point, uniform electric field application and leakage current monitoring on the surface of the LCD logic circuit board substrate sample, avoiding false breakdown caused by local electric field concentration. The leakage current between electrodes and its fluctuation characteristics are accurately captured. Combined with real-time monitoring of local temperature rise and deformation distribution, this provides multi-dimensional, high-precision test parameters for constructing a composite failure assessment model. Ultimately, the withstand voltage stability coefficient provides an objective and quantitative withstand voltage performance level determination, significantly improving the accuracy and comparability of test results.

[0019] Further configuration is that the S100 includes the following steps:

[0020] S110, placing the substrate sample of the LCD logic circuit board in an anti-static carrier, wherein the surface resistance of the anti-static carrier is maintained within a preset surface resistance range; simultaneously, embedding a distributed resistance sensor in the contact area between the anti-static carrier and the substrate sample of the LCD logic circuit board to monitor the amount of electrostatic charge accumulation in real time; and activating a charge discharge circuit built into the carrier when the amount of electrostatic charge accumulation exceeds a preset safety threshold;

[0021] S120, moving the antistatic carrier carrying the LCD logic circuit board substrate sample into a constant temperature and humidity environment chamber, wherein the temperature of the environment chamber is controlled within a preset standard temperature range, the relative humidity is maintained within a preset standard humidity range, and the environment chamber is allowed to stand for a preset equilibrium time;

[0022] S130, scanning the surface of the substrate sample of the LCD logic circuit board using a non-contact laser dust particle counter, wherein when it is detected that the particle size exceeds a preset particle threshold or the particle density per unit area exceeds a preset density threshold, triggering an automatic cleaning instruction;

[0023] S140 , using a contact angle meter to select a plurality of preset detection sites on the substrate sample of the LCD logic circuit board, wherein when the deionized water contact angle of any detection site exceeds a preset contact angle threshold, performing plasma surface activation treatment on the site.

[0024] By adopting the above technical solution, the potential risk of electrostatic discharge damaging the LCD logic circuit board substrate samples and test instruments is minimized through real-time monitoring and automatic discharge of the anti-static carrier's surface resistance and electrostatic charge accumulation. Furthermore, the LCD logic circuit board substrate samples are placed in a constant temperature and humidity chamber for displacement balancing, ensuring stable and consistent temperature and humidity conditions, eliminating the effects of ambient humidity or temperature differences on the dielectric electrical parameters. Non-contact laser dust particle counting and automatic cleaning are used on the surface of the LCD logic circuit board substrate samples, ensuring that the substrate surface cleanliness meets strict standards while also preventing local electric field distortion caused by particulate contamination. Finally, contact angle measurement is used to determine the surface activity state, and when necessary, automatic plasma activation treatment is performed to optimize surface energy, thereby improving electrode coating adhesion and electric field uniformity, further enhancing the stability and repeatability of the testing process.

[0025] Further configuration is that the S200 includes the following steps:

[0026] S210, obtaining a nominal value of a rated operating voltage from a product specification database of the substrate sample of the LCD logic circuit board, and correlating it with a dielectric layer thickness distribution map of the substrate sample of the LCD logic circuit board;

[0027] S220. Based on the nominal value of the rated operating voltage and the coefficient of variation of the dielectric layer thickness, a basic test voltage is generated by voltage conversion, wherein the basic test voltage is negatively correlated with the coefficient of variation of the dielectric layer thickness;

[0028] S230: Retrieving a corresponding voltage increment proportional coefficient and a threshold value for the number of pressurization stages from a preset rule library based on a material type code of the LCD logic circuit board substrate sample; wherein the material type code is mapped to a preset material classification matrix;

[0029] S240, calculating a voltage safety factor by constructing a dielectric thickness-material safety matrix based on the dielectric layer thickness distribution map and the material type code, and automatically reducing a threshold value for the number of pressurization stages when the voltage safety factor is less than a preset safety factor threshold;

[0030] S250, constructing a stepped voltage loading sequence including the threshold number of pressurization stages, and verifying the sequence continuity using a voltage waveform analyzer.

[0031] By adopting the above technical solution, the rated operating voltage nominal value of the LCD logic circuit board substrate sample is automatically obtained from the product specification database. This is converted into a basic test voltage based on the dielectric layer thickness distribution map, fully accounting for the impact of dielectric thickness variation on the breakdown voltage. By calling the voltage increment proportional coefficient and the threshold for the number of pressurization stages corresponding to the material type from the rule library, the material properties are deeply coupled with the test parameters to avoid test deviations caused by blind pressurization or insufficient loading. Based on the joint analysis of thickness distribution and material type, the number of pressurization stages can also be dynamically adjusted to ensure that the test process fully reveals potential defects while avoiding excessive damage to the LCD logic circuit board substrate sample, thereby improving test efficiency and the credibility of the results.

[0032] Further configuration is that the S240 includes the following steps:

[0033] S240.1. Map the minimum dielectric layer thickness of the dielectric layer thickness distribution map to a preset safety reference curve corresponding to the material type code to construct a dielectric thickness-material safety matrix: wherein the preset safety reference curve is obtained as follows:

[0034] Input the material type code into a preset material safety database for matching query, and output a basic safety parameter group corresponding to the material type code, wherein the basic safety parameter group includes a material dielectric strength reference value, a thickness-field strength relationship function identification code, and a material safety correction factor;

[0035] According to the thickness-field intensity relationship function identification code, a corresponding thickness-field intensity relationship function is called from a physical property function library, where the function definition satisfies a mapping rule of a material classification matrix;

[0036] Based on the basic test voltage and the material safety correction factor, the thickness-field strength relationship function is solved by inverse function operation to obtain the theoretical safe thickness;

[0037] S240.2. Calculate the voltage safety factor based on the minimum dielectric layer thickness, theoretical safety thickness, and material safety correction factor;

[0038] S240.3. If the voltage safety factor is less than the preset safety factor threshold, the threshold for the number of pressurization stages is adjusted to a preset degradation ratio of the original value.

[0039] By adopting the above-mentioned technical solution, a mapping between the minimum dielectric thickness and the preset safety reference curve is introduced in the dielectric safety assessment stage, and the theoretical safety thickness is solved through inverse function operation to ensure that the calculation of the safety factor has sufficient theoretical basis and experimental data support; when the calculated voltage safety factor is lower than the threshold, the system can automatically reduce the number of pressurization stages to avoid causing electric field stress higher than the safety tolerance limit to the dielectric, thereby effectively preventing breakdown failure; this move not only improves the safety assurance level of the systematic design, but also realizes adaptive optimization of different materials and thickness distribution conditions, enhancing the versatility and scalability of the test solution.

[0040] It is further configured that the arrangement rules of the electrode array in S300 include:

[0041] The electrode pairs are distributed at equal intervals along the diagonal direction of the substrate sample of the LCD logic circuit board;

[0042] The electrodes of each electrode pair are connected to the substrate sample of the LCD logic circuit board through a conductive adhesive material, and the thickness of the conductive adhesive material is controlled within a preset thickness range after curing.

[0043] By adopting the above technical solution, multiple electrode pairs are arranged diagonally on the surface of the LCD logic circuit board substrate sample, and the electrode spacing and the thickness of the conductive adhesive material after curing are strictly controlled. This makes the electric field distribution in the entire test area more uniform and reasonable, avoiding the problems of false breakdown and data deviation caused by local electric field concentration. The precise control of the cured thickness of the conductive adhesive material ensures the stable and controllable contact impedance between the electrodes and the LCD logic circuit board substrate sample, providing a stable transmission channel for subsequent dynamic monitoring.

[0044] Further configuration is that the S500 includes the following steps:

[0045] S510, obtaining the test parameters and performing multi-dimensional feature extraction; including:

[0046] Obtaining a current fluctuation variation coefficient based on the inter-electrode leakage current value and the current fluctuation characteristic parameter;

[0047] Extracting a maximum temperature rise value and a temperature rise uniformity index based on the local temperature rise distribution data of the substrate sample of the LCD logic circuit board;

[0048] Calculating a deformation gradient and a maximum deformation based on a surface deformation of a substrate sample of the LCD logic circuit board;

[0049] Confirming the current fluctuation variation coefficient, maximum temperature rise value, temperature rise uniformity index, deformation gradient and maximum deformation as characteristic vectors;

[0050] S520: Based on the material type code of the LCD logic circuit board substrate sample, retrieve initial weight coefficients from a preset weight rule library; wherein the initial weight coefficients include a current weight coefficient, a thermal weight coefficient, and a mechanical weight coefficient, and the material type code is mapped to the preset material classification matrix in S230;

[0051] Adjusting and normalizing the initial weight coefficient to obtain a final weight coefficient;

[0052] S530, calculating sub-item failure risk indicators, wherein the sub-item failure risk indicators include a current-related failure risk indicator, a heat-related failure risk indicator, and a mechanical-related failure risk indicator; including:

[0053] Based on the current fluctuation variation coefficient, a current-related failure risk index is obtained;

[0054] Obtaining a heat-related failure risk index based on the maximum temperature rise value and the temperature rise uniformity index;

[0055] Obtaining a mechanical-related failure risk index based on the deformation gradient and the maximum deformation;

[0056] S540 , inputting the current-related failure risk index, the heat-related failure risk index, and the mechanical-related failure risk index into a composite failure assessment model to obtain a composite failure risk score; then, generating a withstand voltage stability coefficient based on the composite failure risk score.

[0057] By adopting the above technical solution, this method introduces multi-dimensional feature extraction in the construction of the composite failure assessment model, systematically processes key parameters such as the current fluctuation variation coefficient, temperature rise distribution and surface deformation, and confirms them as feature vectors, thereby achieving comprehensive capture of the three major failure modes of current, heat and mechanical; through the retrieval and normalization of the initial weight coefficient, as well as the precise calculation of the sub-item risks of each failure indicator, the contribution of each failure mechanism can be reasonably quantified; finally, the sub-item risk indicators are input into the composite assessment model, the composite failure risk score is output and the voltage stability coefficient is generated, providing multi-dimensional and interpretable quantitative results for quality assessment, greatly improving the accuracy and foresight of failure prediction.

[0058] It is further configured that the initial weight coefficient is adjusted and normalized in S520 to obtain the final weight coefficient including:

[0059] Dynamically adjusting the initial weight coefficient based on data quality indicators of the feature vector; wherein the data quality indicators include the signal-to-noise ratio of current data, the spatial resolution score of temperature rise data, and the accuracy score of deformation data;

[0060] The adjusted initial weight coefficient is normalized to obtain the final weight coefficient.

[0061] By adopting the above technical solution, a dynamic correction mechanism for data quality indicators is introduced for the adjustment of the initial weight coefficients. The signal-to-noise ratio of current data, the spatial resolution score of temperature rise measurement, and the accuracy score of deformation data are evaluated in real time. The weights are adjusted based on these indicators to ensure that the model still has stable discrimination capabilities under different sampling conditions. Normalization is then performed to ensure that the sum of all weights remains consistent, thereby avoiding model offsets caused by fluctuations in the quality of a single data. This not only enhances the robustness of the composite evaluation model, but also makes the weight distribution more in line with the actual test environment, thereby improving the reliability of the evaluation results.

[0062] Further configuration is that the S500 further includes the following steps:

[0063] S550, verify and output the pressure stability coefficient; including:

[0064] Performing a range check on the withstand voltage stability coefficient, and triggering a data re-collection instruction if the withstand voltage stability coefficient is less than 0 or greater than 100;

[0065] If the verification passes, the withstand voltage stability coefficient is output to S600.

[0066] By adopting the above technical solution, the method adds a range verification link before outputting the withstand voltage stability coefficient. When the coefficient exceeds a reasonable range, it can automatically trigger a data re-collection instruction, thereby realizing automatic correction and secondary verification of abnormal test results, avoiding unreasonable judgments caused by occasional errors, and thus ensuring that the final output withstand voltage stability coefficient is strictly within the preset range, thereby enhancing the credibility of the test results.

[0067] Further configuration is that the S600 includes the following steps:

[0068] S610, receiving the pressure stability coefficient and synchronously retrieving the material type code;

[0069] S620: According to the material type code, retrieve the corresponding grading threshold table from the preset grading rule library, compare the pressure resistance stability coefficient with the grading threshold table, and confirm the pressure resistance performance level.

[0070] By adopting the above technical solution, the pressure stability coefficient is automatically compared with the preset grading threshold table during the pressure resistance performance grade determination stage, and the corresponding grading rules are quickly obtained in combination with the material type code to ensure the objectivity and consistency of the determination results. The entire grading process realizes the standardized and automated grading management of pressure resistance performance grades, providing efficient and reliable decision-making support for quality traceability, batch comparison and failure analysis in the subsequent production process.

[0071] The present invention also provides a pressure resistance performance detection system for LCD logic board substrates, including the following modules:

[0072] A pre-processing module; used to execute S100, including an anti-static carrier unit, an environmental balance unit, a particle cleaning unit, and a surface activation unit;

[0073] A voltage sequence configuration module; used to execute S200, including a data acquisition unit, a voltage calculation unit, and a sequence verification unit;

[0074] An electrode array deployment module; used to execute S300, comprising an electrode arrangement unit and a bonding control unit;

[0075] Test execution module: used to execute S400, including integrated high-voltage generator, parameter monitoring unit and equipment coordination unit;

[0076] A composite assessment module; used to execute S500, including a feature extraction unit, a weight optimization unit, a risk calculation unit, and a coefficient generation unit;

[0077] A grading determination module: used to execute S600, including a coefficient receiving unit and a grade mapping unit.

[0078] In summary, the present invention has the following beneficial effects:

[0079] The core detection method can simultaneously monitor multiple electrical, thermal and mechanical parameters and establish a dynamic failure quantification model, ultimately improving the accuracy and reliability of the voltage resistance performance test results of LCD logic board substrates. BRIEF DESCRIPTION OF THE DRAWINGS

[0080] Figure 1 It is a main flow chart of the embodiment;

[0081] Figure 2 This is a schematic diagram of the process of S500 in the embodiment;

[0082] Figure 3 A system block diagram of an embodiment. DETAILED DESCRIPTION

[0083] The present invention will be further described in detail below with reference to the accompanying drawings.

[0084] As attached Figures 1 to 3 As shown;

[0085] This embodiment discloses a method for detecting the pressure resistance performance of an LCD logic board substrate, comprising the following steps:

[0086] S100, pre-treating a substrate sample of an LCD logic circuit board;

[0087] S200, configure a multi-step voltage loading sequence; including:

[0088] Based on the rated operating voltage of the LCD logic circuit board substrate sample, a stepped voltage loading sequence consisting of multiple pressurization stages is generated, wherein the voltage of the first stage is a proportional voltage of the rated voltage, and the voltage of each subsequent stage increases according to a preset ratio, and the duration of each stage is set to the preset voltage holding time;

[0089] S300, installation of distributed electrode array; including:

[0090] Arranging multiple electrode pairs on the surface of a substrate sample of an LCD logic circuit board, wherein the spacing between each electrode pair is controlled within a preset tolerance range, and the electrodes in each electrode pair are coated with an insulating coating of a preset thickness;

[0091] S400, perform dynamic withstand voltage test; including:

[0092] A high-voltage generator applies a test voltage to each electrode pair according to a stepped voltage loading sequence, while simultaneously monitoring and recording test parameters in real time at a preset sampling frequency. The test parameters include inter-electrode leakage current values and current fluctuation characteristic parameters, local temperature rise distribution data of the LCD logic circuit board substrate sample, and surface deformation of the LCD logic circuit board substrate sample.

[0093] Preferably, a high-precision micro-current measuring device is used to measure the leakage current, and the measuring range covers the preset current range; the temperature rise data is collected by infrared thermal imaging equipment, and the spatial resolution is not lower than the preset resolution threshold; and the deformation amount is detected using optical deformation detection equipment.

[0094] S500: construct a composite failure assessment model based on the test parameters and output a withstand voltage stability coefficient;

[0095] S600: Determine the pressure resistance performance level based on the pressure resistance stability coefficient.

[0096] In a possible implementation, S100 includes the following steps:

[0097] S110, placing the LCD logic circuit board substrate sample in an anti-static carrier, wherein the surface resistance of the anti-static carrier is maintained within a preset surface resistance range; simultaneously, embedding a distributed resistance sensor in the contact area between the anti-static carrier and the LCD logic circuit board substrate sample to monitor the amount of electrostatic charge accumulation in real time; when the monitored electrostatic charge accumulation exceeds a preset safety threshold, activating a charge discharge circuit built into the carrier;

[0098] Preferably, the carrier contact surface is covered with a cationic antistatic coating;

[0099] Preferably, the surface resistance of the antistatic carrier is measured, and if it exceeds a preset surface resistance range, a resistance correction coating is applied;

[0100] S120, moving the antistatic carrier carrying the LCD logic circuit board substrate sample into a constant temperature and humidity environment chamber, wherein the temperature of the environment chamber is controlled within a preset standard temperature range, the relative humidity is maintained within a preset standard humidity range, and the environment chamber is allowed to stand for a preset equilibrium time;

[0101] Specifically, the control logic of the environmental parameters is:

[0102] The environmental chamber parameters are adjusted using a temperature and humidity linkage controller, with the temperature control accuracy reaching a preset temperature accuracy level, and the humidity control accuracy reaching a preset humidity accuracy level. During the static process, the hygroscopic expansion coefficient of the substrate sample of the LCD logic circuit board is recorded at each preset monitoring period. When the change in the hygroscopic expansion coefficient over three consecutive monitoring periods is less than a preset stability threshold, it is determined that the environmental equilibrium state has been reached.

[0103] S130, using a non-contact laser dust particle counter to scan the surface of the substrate sample of the LCD logic circuit board, wherein when a particle size exceeding a preset particle threshold or a particle density per unit area exceeding a preset density threshold is detected, an automatic cleaning instruction is triggered; specifically, after the automatic cleaning instruction is triggered, a coordinated cleaning system consisting of an electrostatic eliminator and a negative pressure adsorption device is activated, wherein the electrostatic eliminator generates an ion wind beam of a preset frequency, and the adsorption head of the negative pressure adsorption device maintains a preset working distance from the surface of the substrate sample of the LCD logic circuit board;

[0104] The collaborative cleaning system operating rules include:

[0105] The coverage area of the ion wind beam and the negative pressure adsorption area form an overlapping area of a preset ratio;

[0106] The negative pressure adsorption intensity is dynamically adjusted according to the particle size distribution, wherein the corresponding relationship between the adsorption intensity and the particle size satisfies the preset adsorption force curve.

[0107] S140, using a contact angle meter to select multiple preset detection sites on the substrate sample of the LCD logic circuit board, wherein when the deionized water contact angle of any detection site exceeds a preset contact angle threshold, plasma surface activation treatment is performed on the site.

[0108] Preferably, the process of plasma surface activation treatment includes:

[0109] The plasma treatment power is calculated based on the excessive contact angle value, where the treatment power and the contact angle deviation value show a preset positive correlation; a thermally sensitive zone is set around the treatment area, and the cooling gas injection is activated when the area temperature exceeds the preset temperature limit; the contact angle is re-tested after the activation treatment until all detection sites meet the preset contact angle threshold requirements.

[0110] Example 1

[0111] The LCD logic circuit board substrate sample is placed in a The anti-static carrier is coated with a cationic anti-static coating on the contact surface of the anti-static carrier, and a distributed resistance sensor is embedded in the contact area; when the electrostatic charge accumulation exceeds When the anti-static carrier is connected to the power supply, the built-in charge discharge circuit of the anti-static carrier is activated.

[0112] Then, move the anti-static carrier into the constant temperature and humidity environment chamber and control the temperature at , relative humidity The temperature and humidity linkage controller records the hygroscopic expansion coefficient of the substrate sample every 5 minutes. When the change in the hygroscopic expansion coefficient is less than 3 times in a row, When the environment is in balance.

[0113] Then, use a non-contact laser dust particle counter to scan the substrate surface. If the particle size is larger than 5μm or the density is greater than 100 particles / cm 2 , triggering the collaborative cleaning system:

[0114] The static eliminator generates a 1.2kH ion wind beam, the coverage of which overlaps with the negative pressure adsorption area by 70%; the negative pressure adsorption intensity is calculated according to the formula Dynamic adjustment, where d is the particle diameter in μm; the adsorption head is 10 mm away from the surface;

[0115] Finally, measure the contact angle of deionized water at five test sites on the LCD logic circuit board substrate sample. If the contact angle at any site is greater than 85°:

[0116] Calculate the plasma processing power and monitor the temperature of the heat-sensitive area during activation. Start the argon cooling injection when it exceeds 60°C.

[0117] The treatment was repeated until the contact angle was less than or equal to 85°.

[0118] In a possible implementation, S200 includes the following steps:

[0119] S210, obtaining a nominal value of a rated operating voltage from a product specification database of a substrate sample of an LCD logic circuit board, and correlating the nominal value with a dielectric layer thickness distribution map of the substrate sample of the LCD logic circuit board;

[0120] Preferably, the product specification database is a cloud-based product specification database;

[0121] Preferably, the thickness distribution map of the dielectric layer is obtained by a laser thickness gauge, and the thickness variation coefficient is calculated. ,in, is the thickness variation coefficient; is the standard deviation of the dielectric layer thickness measurement value, is the average thickness of the dielectric layer measurements.

[0122] S220, generating a basic test voltage by voltage conversion based on the nominal value of the rated operating voltage and the coefficient of variation of the dielectric layer thickness, wherein the basic test voltage is negatively correlated with the coefficient of variation of the dielectric layer thickness;

[0123] Preferably, the process of generating the basic test voltage through voltage conversion is as follows:

[0124] ;

[0125] in, is the nominal value of the rated operating voltage; is the preset basic proportional constant; is the thickness sensitivity coefficient; is the thickness variation coefficient; Is the basic test voltage;

[0126] S230: Based on the material type code of the LCD logic circuit board substrate sample, retrieve the corresponding voltage increment proportional coefficient and pressure stage number threshold from a preset rule library; wherein the material type code is mapped to a preset material classification matrix; specifically, the matrix includes three categories: epoxy resin substrate, polyimide substrate, and ceramic-filled substrate;

[0127] S240, based on the dielectric layer thickness distribution map and the material type code, calculate the voltage safety factor by constructing a dielectric thickness-material safety matrix, and automatically reduce the threshold value of the number of pressurization stages when the voltage safety factor is less than a preset safety factor threshold;

[0128] S250. Construct a stepped voltage loading sequence containing a threshold for the number of pressurization stages, and verify the sequence continuity using a voltage waveform analyzer.

[0129] Specifically, the voltage value at each stage in the step-by-step voltage loading sequence is calculated as follows:

[0130] ;

[0131] in, Is the basic test voltage; is the voltage increment proportional coefficient; is the material attenuation factor; For the Voltage value during the pressurization phase; It is the pressurization stage number.

[0132] In a possible implementation, S240 includes the following steps:

[0133] S240.1. Map the minimum dielectric layer thickness in the dielectric layer thickness distribution map to a preset safety reference curve corresponding to the material type code to construct a dielectric thickness-material safety matrix. The preset safety reference curve is obtained as follows:

[0134] Input the material type code into the preset material safety database for matching query, and output the basic safety parameter group corresponding to the material type code, where the basic safety parameter group includes the material dielectric strength reference value, thickness-field strength relationship function identification code and material safety correction factor;

[0135] According to the thickness-field intensity relationship function identification code, the corresponding thickness-field intensity relationship function is called from the physical property function library , this function defines the mapping rules that satisfy the material classification matrix;

[0136] The specific mapping rules are:

[0137] The epoxy resin substrate corresponds to the first thickness-field intensity relationship function;

[0138] The polyimide substrate corresponds to the second thickness-field strength relationship function;

[0139] The ceramic-filled substrate corresponds to the third thickness-field strength relationship function;

[0140] Based on the basic test voltage and material safety correction factor, the thickness-field strength relationship function is solved through inverse function calculation to obtain the theoretical safe thickness;

[0141] The specific process of solving the thickness-field strength relationship function through inverse function operation and obtaining the theoretical safe thickness is as follows:

[0142] ;

[0143] in, Is the basic test voltage; is the material safety correction factor, is the theoretical safety thickness;

[0144] Material safety correction factor The acquisition process is:

[0145] Parse the coding structure of the material type code and extract the substrate type identifier;

[0146] Look up the preset safety correction factor table based on the substrate type identifier:

[0147] The epoxy resin substrate corresponds to the first safety correction factor;

[0148] The polyimide substrate corresponds to the second safety correction factor;

[0149] Ceramic-filled substrates correspond to the third safety correction factor;

[0150] The safety correction factor obtained from the query is used as the material safety correction factor Write the basic security parameter group.

[0151] Specifically, the thickness-field strength relationship function of each material type is defined as:

[0152] The first thickness-field strength relationship function of the epoxy resin substrate is: ;

[0153] The second thickness-field strength relationship function of the polyimide substrate is ;

[0154] The third thickness-field strength relationship function of the ceramic-filled substrate is ;

[0155] in 、 、 、 、 、 、 、 、 are the pre-calibrated material characteristic parameters respectively.

[0156] S240.2. Calculate the voltage safety factor based on the minimum dielectric layer thickness, theoretical safety thickness, and material safety correction factor;

[0157] The corresponding formula is as follows:

[0158] ;

[0159] in, is the minimum dielectric layer thickness; is the voltage safety factor.

[0160] S240.3. If the voltage safety factor is less than the preset safety factor threshold, the threshold for the number of pressurization stages is adjusted to a preset degradation ratio of the original value.

[0161] Example 2

[0162] Retrieve the rated operating voltage from the cloud-based product specification database kV;

[0163] Laser thickness gauge scans to generate dielectric layer thickness distribution map and calculates thickness variation coefficient ;

[0164] Calculating the base test voltage About 2.1kV, of which Set to 0.85, Set to 0.12;

[0165] The material type code "EP-425" is mapped to the epoxy resin base material and retrieved from the rule library:

[0166] Voltage increment proportional coefficient , threshold value of the number of pressurization stages .

[0167] Then, calculate the voltage safety factor as follows:

[0168] Minimum dielectric layer thickness ;

[0169] Matching material safety database, epoxy resin substrate, its thickness-field strength relationship function , material safety correction factor ;

[0170] Calculate theoretical safety thickness ;

[0171] Voltage safety factor , voltage safety factor Greater than the preset safety factor threshold 1, the number of pressurization stages threshold .

[0172] Finally, the voltage sequence is constructed as follows:

[0173] No. Stage voltage value ; among them , is the epoxy resin attenuation factor.

[0174] An example of a voltage sequence is shown in Table 1;

[0175] Table 1 Voltage sequence example

[0176]

[0177] In a possible implementation, the arrangement rule of the electrode array in S300 includes:

[0178] The electrode pairs are distributed at equal intervals along the diagonal direction of the substrate sample of the LCD logic circuit board;

[0179] Preferably, the center distance between adjacent electrode pairs is satisfy:

[0180] ;

[0181] in, Indicates the minimum spacing, satisfying ; represents the maximum spacing, satisfying; 、 are the lengths of the short side and long side of the substrate sample of the LCD logic circuit board;

[0182] The electrodes of each electrode pair are connected to the substrate sample of the LCD logic circuit board through a conductive adhesive material, and the thickness of the conductive adhesive material is controlled within a preset thickness range after curing.

[0183] Example 3

[0184] The process of installing a distributed electrode array is as follows:

[0185] Eight electrode pairs are arranged along the diagonal of the substrate sample, , ; Center distance between adjacent electrode pairs satisfy ;

[0186] And perform the following treatment on the electrode:

[0187] The electrodes are coated with a 10 μm aluminum oxide insulating coating and connected to the substrate via conductive bonding with silver paste, with a cured thickness of 25 ± 2 μm.

[0188] In a possible implementation, S500 includes the following steps:

[0189] S510, obtaining test parameters and performing multi-dimensional feature extraction; including:

[0190] Based on the inter-electrode leakage current value and the current fluctuation characteristic parameters, the current fluctuation variation coefficient is obtained; specifically:

[0191] ;

[0192] in, is the current fluctuation coefficient of variation; is the standard deviation of the leakage current value, is the average value of the leakage current.

[0193] Based on the local temperature rise distribution data of the LCD logic circuit board substrate sample, the maximum temperature rise value and temperature rise uniformity index are extracted; specifically:

[0194] ;

[0195] in, It is the temperature rise uniformity index; For the Temperature rise value of each monitoring point; Indicates the maximum temperature rise value among all monitoring points; Indicates the lowest temperature rise value among all monitoring points.

[0196] Based on the surface deformation of the LCD logic circuit board substrate sample, the deformation gradient and maximum deformation are calculated; specifically:

[0197] ;

[0198] in, is the deformation gradient; For the The deformation of each monitoring point, The reference length of the substrate sample of the LCD logic circuit board; Indicates the maximum deformation among all monitoring points; Indicates the minimum deformation among all monitoring points.

[0199] The current fluctuation variation coefficient, maximum temperature rise value, temperature rise uniformity index, deformation gradient and maximum deformation amount are identified as characteristic vectors;

[0200] S520: Based on the material type code of the LCD logic circuit board substrate sample, retrieve initial weight coefficients from a preset weight rule library; wherein the initial weight coefficients include a current weight coefficient, a thermal weight coefficient, and a mechanical weight coefficient, and the material type code is mapped to the preset material classification matrix in S230;

[0201] Adjust and normalize the initial weight coefficient to obtain the final weight coefficient;

[0202] S530. Calculate sub-item failure risk indicators, where the sub-item failure risk indicators include a current-related failure risk indicator, a heat-related failure risk indicator, and a mechanical-related failure risk indicator; including:

[0203] Based on the current fluctuation coefficient of variation, the current-related failure risk index is obtained;

[0204] The generation process of the current-related failure risk index is as follows:

[0205] ;

[0206] in, is the current-related failure risk indicator; It is the preset current fluctuation coefficient of variation threshold.

[0207] Based on the maximum temperature rise value and the temperature rise uniformity index, the heat-related failure risk index is obtained;

[0208] The process of generating the thermal-related failure risk index is as follows:

[0209] ;

[0210] in, is an indicator of the risk of heat-related failure; and is the preset proportional coefficient; is the maximum temperature rise value; It is the preset allowable temperature rise value; It is an indicator of temperature rise uniformity.

[0211] Based on the deformation gradient and maximum deformation, the mechanical related failure risk index is obtained;

[0212] The process of generating the mechanical related failure risk index is as follows:

[0213] ;

[0214] in, It is an indicator of the risk of mechanical related failure; is the deformation gradient; Preset deformation gradient threshold; is the maximum deformation; is the preset maximum deformation threshold; and is the preset weight factor;

[0215] S540 , inputting the current-related failure risk index, the heat-related failure risk index, and the mechanical-related failure risk index into a composite failure assessment model to obtain a composite failure risk score; then, generating a withstand voltage stability coefficient based on the composite failure risk score.

[0216] The composite failure risk score is generated as follows:

[0217] ;

[0218] in, is the composite failure risk score; is the voltage safety correction function, specifically: ,in is the voltage safety factor, is the safety correction gain factor, obtained from the material safety database;

[0219] The generation process of the pressure stability coefficient is as follows:

[0220] ;

[0221] in, is the pressure stability coefficient; The preset maximum composite failure risk score threshold.

[0222] In one possible implementation, the initial weight coefficients are adjusted and normalized in S520 to obtain final weight coefficients including:

[0223] Dynamically adjust the initial weight coefficient based on the data quality indicators of the feature vector; the data quality indicators include the signal-to-noise ratio of the current data, the spatial resolution score of the temperature rise data, and the accuracy score of the deformation data;

[0224] The adjusted initial weight coefficient is normalized to obtain the final weight coefficient.

[0225] It should be noted that the current data signal-to-noise ratio, temperature rise data spatial resolution score, and deformation data accuracy score are obtained by obtaining the real-time performance parameters of the S400 high-precision microcurrent measurement device, infrared thermal imaging device, and optical deformation detection device through the device self-test protocol;

[0226] Specifically, they performed zero-drift tests on high-precision microcurrent measurement devices and calculated the signal-to-noise ratio of current data; parsed the technical specifications of infrared thermal imaging equipment to extract the spatial resolution score of temperature rise data; and obtained the deformation data accuracy score from the calibration certificate of optical deformation detection equipment.

[0227] Specifically, the process of adjusting the initial weight coefficient is:

[0228] For the current weight coefficient, ;in, is the current weight coefficient; is the adjusted current weight coefficient; is the preset sensitivity coefficient; is the signal-to-noise ratio of current data;

[0229] For the thermal weight coefficient, ;in, is the thermal weight coefficient; is the adjusted thermal weight coefficient; is the preset sensitivity coefficient; Score the spatial resolution of the temperature rise data;

[0230] For the mechanical weight coefficient, ;in, is the mechanical weight coefficient; is the adjusted mechanical weight coefficient; is the preset sensitivity coefficient; Score for deformation data accuracy;

[0231] Normalize the adjusted initial weight coefficient to obtain the final weight coefficient 、 and .

[0232] Example 4

[0233] Current fluctuation coefficient of variation About 6.7%, temperature rise uniformity index About 0.77, deformation gradient 0.0135μm / mm;

[0234] Retrieve the initial weight of the epoxy resin substrate:

[0235] Current weight coefficient ;

[0236] Thermal weight coefficient ;

[0237] Mechanical weight coefficient .

[0238] An example of adjusting weights based on device performance is shown in Table 2;

[0239] Table 2 Example of device performance adjustment weights

[0240]

[0241] Normalize the adjusted initial weight coefficient to obtain the final weight coefficient About 0.40, About 0.31, and About 0.29.

[0242] Among the sub-item failure risk indicators:

[0243] Flow-related failure risk indicators ,in ;

[0244] Thermally related failure risk indicators ,in , , ;

[0245] Mechanically related failure risk indicators ,in , , , ;

[0246] Next, generate the composite failure risk score ,in , ;

[0247] Finally, the pressure stability coefficient is generated .

[0248] In a possible implementation, S500 further includes the following steps:

[0249] S550, verify and output the pressure stability coefficient; including:

[0250] Perform range check on the withstand voltage stability coefficient. If the withstand voltage stability coefficient is less than 0 or greater than 100, the data re-collection instruction is triggered.

[0251] If the verification is passed, the withstand voltage stability coefficient is output to S600.

[0252] Example 5

[0253] Pressure stability coefficient , , verification passed.

[0254] In a possible implementation, S600 includes the following steps:

[0255] S610, receiving the pressure stability coefficient and synchronously retrieving the material type code;

[0256] S620: According to the material type code, retrieve the corresponding grading threshold table from the preset grading rule library, compare the pressure resistance stability coefficient with the grading threshold table, and confirm the pressure resistance performance level.

[0257] Specifically, examples of retrieving the corresponding grading threshold table in the grading rule library are shown in Table 3, Table 4, and Table 5;

[0258] Table 3 Example of classification threshold value for epoxy resin substrate

[0259]

[0260] Table 4 Example of classification threshold value for polyimide substrate

[0261]

[0262] Table 5 Example of classification thresholds for ceramic-filled substrates

[0263]

[0264] Example 6

[0265] Output voltage withstand performance level: qualified.

[0266] This embodiment also discloses a pressure resistance performance detection system for an LCD logic board substrate, which includes the following modules:

[0267] A pre-processing module; used to execute S100, including an anti-static carrier unit, an environmental balance unit, a particle cleaning unit, and a surface activation unit;

[0268] Specifically, the anti-static carrier unit integrates a distributed resistance sensor and a charge discharge circuit to maintain a preset surface resistance range and control the amount of electrostatic charge accumulation;

[0269] The environmental balance unit adjusts the parameters of the constant temperature and humidity environment chamber through the temperature and humidity linkage controller, and monitors the hygroscopic expansion coefficient of the substrate sample of the LCD logic circuit board until the environmental balance state is reached;

[0270] The particle cleaning unit is a collaborative cleaning system consisting of a non-contact laser dust particle counter triggering an electrostatic eliminator and a negative pressure adsorption device;

[0271] The surface activation unit detects a plurality of preset detection sites using a contact angle meter and performs plasma surface activation treatment.

[0272] A voltage sequence configuration module; used to execute S200, including a data acquisition unit, a voltage calculation unit, and a sequence verification unit;

[0273] Specifically, the data acquisition unit extracts the nominal value of the rated operating voltage from the cloud-based product specification database and obtains the dielectric layer thickness distribution map through a laser thickness gauge;

[0274] The voltage calculation unit performs the following operations:

[0275] Based on the nominal value of the rated working voltage and the coefficient of variation of the dielectric layer thickness Generates base test voltage ;

[0276] Get the voltage increment proportional coefficient based on the material type code and the threshold value for the number of pressurization stages;

[0277] Construct a dielectric thickness-material safety matrix to calculate the voltage safety factor λ and dynamically adjust the threshold for the number of pressurization stages;

[0278] The sequence verification unit verifies the continuity of the step voltage loading sequence through a voltage waveform analyzer.

[0279] An electrode array deployment module; used to execute S300, comprising an electrode arrangement unit and a bonding control unit;

[0280] Specifically, the electrode arrangement unit arranges multiple groups of electrode pairs at equal intervals in the diagonal direction on the surface of the substrate sample of the LCD logic circuit board, and the center distance between adjacent electrode pairs is satisfy ;

[0281] The bonding control unit connects the electrode and the substrate by curing the conductive bonding material, and the thickness is controlled within a preset range.

[0282] Test execution module: used to execute S400, including integrated high-voltage generator, parameter monitoring unit and equipment coordination unit;

[0283] Specifically, the high voltage generator outputs a test voltage to each electrode pair according to a step-wise voltage loading sequence;

[0284] The parameter monitoring unit includes:

[0285] High-precision micro-current measuring device, real-time collection of leakage current value between electrodes and current fluctuation characteristic parameters;

[0286] Infrared thermal imaging equipment to obtain local temperature rise distribution data of LCD logic circuit board substrate samples

[0287] Optical deformation detection equipment, used to detect the surface deformation of substrate samples of LCD logic circuit boards;

[0288] The equipment coordination unit synchronously controls the data collection of each device according to the preset sampling frequency.

[0289] A composite assessment module; used to execute S500, including a feature extraction unit, a weight optimization unit, a risk calculation unit, and a coefficient generation unit;

[0290] Specifically, the feature extraction unit calculates the current fluctuation coefficient of variation from the test parameters , maximum temperature rise , Temperature rise uniformity index , deformation gradient and maximum deformation ;

[0291] The weight optimization unit retrieves the initial weight coefficient according to the material type code, and dynamically adjusts and normalizes it based on the current data signal-to-noise ratio, the temperature rise data spatial resolution score, and the deformation data accuracy score;

[0292] The risk calculation unit generates current-related failure risk indicators , thermal-related failure risk indicators and mechanical related failure risk indicators ;

[0293] The coefficient generation unit outputs the pressure stability coefficient through the composite failure assessment model , and execute range check and re-collection instruction trigger.

[0294] A grading determination module: used to execute S600, including a coefficient receiving unit and a grade mapping unit;

[0295] Specifically, the coefficient receiving unit obtains the withstand voltage stability coefficient and material type code;

[0296] The level mapping unit retrieves the level threshold table from the level rule library and matches the output voltage withstand performance level.

[0297] This specific embodiment is merely an explanation of the present invention and is not intended to limit the present invention. After reading this specification, those skilled in the art may make non-creative modifications to this embodiment as needed. However, as long as such modifications are within the scope of the claims of the present invention, they are protected by patent law.

Claims

1. A method for detecting the pressure resistance performance of an LCD logic board substrate, characterized in that: The following steps are involved: S100, pre-treating a substrate sample of an LCD logic circuit board; S200, configure a multi-step voltage loading sequence; including: Based on the rated operating voltage of the substrate sample of the LCD logic circuit board, generating a stepped voltage loading sequence comprising multiple pressurization stages, wherein the voltage of the first stage is a proportional voltage of the rated voltage, and the voltage of each subsequent stage increases according to a preset proportion, and the duration of each stage is set to a preset holding time; S300, installation of distributed electrode array; including: Arranging a plurality of electrode pairs on the surface of the substrate sample of the LCD logic circuit board, wherein the spacing between each electrode pair is controlled within a preset tolerance range, and the electrodes in each electrode pair are coated with an insulating coating of a preset thickness; S400, perform dynamic withstand voltage test; including: Applying a test voltage to each electrode pair using a high-voltage generator according to the step-wise voltage loading sequence, while simultaneously monitoring and recording test parameters in real time at a preset sampling frequency; wherein the test parameters include inter-electrode leakage current value and current fluctuation characteristic parameters, local temperature rise distribution data of a substrate sample of an LCD logic circuit board, and surface deformation of the substrate sample of the LCD logic circuit board; S500, constructing a composite failure assessment model based on the test parameters, and outputting a withstand voltage stability coefficient; S600: Determine the pressure resistance performance level based on the pressure resistance stability coefficient.

2. The method for testing the pressure resistance performance of an LCD logic board substrate according to claim 1, wherein: The S100 includes the following steps: S110, placing the substrate sample of the LCD logic circuit board in an anti-static carrier, wherein the surface resistance of the anti-static carrier is maintained within a preset surface resistance range; simultaneously, embedding a distributed resistance sensor in the contact area between the anti-static carrier and the substrate sample of the LCD logic circuit board to monitor the amount of electrostatic charge accumulation in real time; and activating a charge discharge circuit built into the carrier when the amount of electrostatic charge accumulation exceeds a preset safety threshold; S120, moving the antistatic carrier carrying the LCD logic circuit board substrate sample into a constant temperature and humidity environment chamber, wherein the temperature of the environment chamber is controlled within a preset standard temperature range, the relative humidity is maintained within a preset standard humidity range, and the environment chamber is allowed to stand for a preset equilibrium time; S130, scanning the surface of the substrate sample of the LCD logic circuit board using a non-contact laser dust particle counter, wherein when it is detected that the particle size exceeds a preset particle threshold or the particle density per unit area exceeds a preset density threshold, triggering an automatic cleaning instruction; S140 , using a contact angle meter to select a plurality of preset detection sites on the substrate sample of the LCD logic circuit board, wherein when the deionized water contact angle of any detection site exceeds a preset contact angle threshold, performing plasma surface activation treatment on the site.

3. The method for testing the pressure resistance performance of an LCD logic board substrate according to claim 1, wherein: The S200 includes the following steps: S210, obtaining a nominal value of a rated operating voltage from a product specification database of the substrate sample of the LCD logic circuit board, and correlating it with a dielectric layer thickness distribution map of the substrate sample of the LCD logic circuit board; S220. Based on the nominal value of the rated operating voltage and the coefficient of variation of the dielectric layer thickness, a basic test voltage is generated by voltage conversion, wherein the basic test voltage is negatively correlated with the coefficient of variation of the dielectric layer thickness; S230: Retrieving a corresponding voltage increment proportional coefficient and a threshold value for the number of pressurization stages from a preset rule library based on a material type code of the LCD logic circuit board substrate sample; wherein the material type code is mapped to a preset material classification matrix; S240, calculating a voltage safety factor by constructing a dielectric thickness-material safety matrix based on the dielectric layer thickness distribution map and the material type code, and automatically reducing a threshold value for the number of pressurization stages when the voltage safety factor is less than a preset safety factor threshold; S250, constructing a stepped voltage loading sequence including the threshold number of pressurization stages, and verifying the sequence continuity using a voltage waveform analyzer.

4. The method for testing the pressure resistance of an LCD logic board substrate according to claim 3, wherein: The S240 includes the following steps: S240.

1. Map the minimum dielectric layer thickness of the dielectric layer thickness distribution map to a preset safety reference curve corresponding to the material type code to construct a dielectric thickness-material safety matrix: wherein the preset safety reference curve is obtained as follows: Input the material type code into a preset material safety database for matching query, and output a basic safety parameter group corresponding to the material type code, wherein the basic safety parameter group includes a material dielectric strength reference value, a thickness-field strength relationship function identification code, and a material safety correction factor; According to the thickness-field intensity relationship function identification code, a corresponding thickness-field intensity relationship function is called from a physical property function library, where the function definition satisfies a mapping rule of a material classification matrix; Based on the basic test voltage and the material safety correction factor, the thickness-field strength relationship function is solved by inverse function operation to obtain the theoretical safe thickness; S240.

2. Calculate the voltage safety factor based on the minimum dielectric layer thickness, theoretical safety thickness, and material safety correction factor; S240.

3. If the voltage safety factor is less than the preset safety factor threshold, the threshold for the number of pressurization stages is adjusted to a preset degradation ratio of the original value.

5. The method for testing the pressure resistance performance of an LCD logic board substrate according to claim 3, wherein: In S300, the arrangement rules of the electrode array include: The electrode pairs are distributed at equal intervals along the diagonal direction of the substrate sample of the LCD logic circuit board; The electrodes of each electrode pair are connected to the substrate sample of the LCD logic circuit board through a conductive adhesive material, and the thickness of the conductive adhesive material is controlled within a preset thickness range after curing.

6. The method for testing the pressure resistance performance of an LCD logic board substrate according to claim 1, wherein: The S500 includes the following steps: S510, obtaining the test parameters and performing multi-dimensional feature extraction; including: Obtaining a current fluctuation variation coefficient based on the inter-electrode leakage current value and the current fluctuation characteristic parameter; Extracting a maximum temperature rise value and a temperature rise uniformity index based on the local temperature rise distribution data of the substrate sample of the LCD logic circuit board; Calculating a deformation gradient and a maximum deformation based on a surface deformation of a substrate sample of the LCD logic circuit board; Confirming the current fluctuation variation coefficient, maximum temperature rise value, temperature rise uniformity index, deformation gradient and maximum deformation as characteristic vectors; S520: Based on the material type code of the LCD logic circuit board substrate sample, retrieve initial weight coefficients from a preset weight rule library; wherein the initial weight coefficients include a current weight coefficient, a thermal weight coefficient, and a mechanical weight coefficient, and the material type code is mapped to the preset material classification matrix in S230; Adjusting and normalizing the initial weight coefficient to obtain a final weight coefficient; S530, calculating sub-item failure risk indicators, wherein the sub-item failure risk indicators include a current-related failure risk indicator, a heat-related failure risk indicator, and a mechanical-related failure risk indicator; including: Based on the current fluctuation variation coefficient, a current-related failure risk index is obtained; Obtaining a heat-related failure risk index based on the maximum temperature rise value and the temperature rise uniformity index; Obtaining a mechanical-related failure risk index based on the deformation gradient and the maximum deformation; S540 , inputting the current-related failure risk index, the heat-related failure risk index, and the mechanical-related failure risk index into a composite failure assessment model to obtain a composite failure risk score; then, generating a withstand voltage stability coefficient based on the composite failure risk score.

7. The method for testing the pressure resistance performance of an LCD logic board substrate according to claim 6, wherein: In step S520, the initial weight coefficient is adjusted and normalized to obtain the final weight coefficient, which includes: Dynamically adjusting the initial weight coefficient based on data quality indicators of the feature vector; wherein the data quality indicators include the signal-to-noise ratio of current data, the spatial resolution score of temperature rise data, and the accuracy score of deformation data; The adjusted initial weight coefficient is normalized to obtain the final weight coefficient.

8. The method for testing the pressure resistance performance of an LCD logic board substrate according to claim 6, wherein: The S500 further includes the following steps: S550, verify and output the pressure stability coefficient; including: Performing a range check on the withstand voltage stability coefficient, and triggering a data re-collection instruction if the withstand voltage stability coefficient is less than 0 or greater than 100; If the verification passes, the withstand voltage stability coefficient is output to S600.

9. The method for testing the pressure resistance performance of an LCD logic board substrate according to claim 1, wherein: The S600 includes the following steps: S610, receiving the pressure stability coefficient and synchronously retrieving the material type code; S620: According to the material type code, retrieve the corresponding grading threshold table from the preset grading rule library, compare the pressure resistance stability coefficient with the grading threshold table, and confirm the pressure resistance performance level.

10. A pressure resistance performance testing system for an LCD logic board substrate, applied to the pressure resistance performance testing method for an LCD logic board substrate according to any one of claims 1 to 9, characterized in that: Includes the following modules: A preprocessing module, configured to execute S100; A voltage sequence configuration module, used to execute S200; an electrode array deployment module, configured to execute S300; A test execution module, configured to execute S400; A composite evaluation module for executing S500; The classification determination module is configured to execute S600.

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