A low voltage bandgap reference startup circuit

Abstract

The present invention discloses a low-voltage bandgap reference startup circuit, which includes: the negative terminal of an operational amplifier is connected to ground via a bipolar transistor Q1, the positive terminal of the operational amplifier is connected to ground via R1 and a bipolar transistor Q2 in series; the negative terminal of the operational amplifier is connected to ground via R3, and the positive terminal of the operational amplifier is connected to ground via R2; the sources of PMOS transistors M1, M2, and M3 are connected to a power supply voltage; the gates of M1, M2, and M3 are connected to the output terminal of the operational amplifier; R6 is connected between the negative terminal of the operational amplifier and the drain of M1; R7 is connected between the positive terminal of the operational amplifier and the drain of M2; the drain of M3 is grounded via R4; the gate of NMOS transistor M4 is connected to the drain of M1, the drain of M4 is connected to the gate of NMOS transistor M5, the drain of M5 is connected to the gate of M1, the sources of M4 and M5 are connected to ground; and the drain of M4 is connected to the power supply voltage via R5. The present invention enables the circuit to operate normally at any process foot.

Description

Technical Field

[0001] The present invention relates to the technical field of integrated circuits, and in particular to a low-voltage bandgap reference startup circuit. Background Art

[0002] In low-voltage analog circuit design, a bandgap reference that can generate voltage even with a low power supply is often required. The operation of a bandgap reference often requires a suitable startup circuit to ensure that the circuit operates normally.

[0003] An existing conventional low-voltage bandgap reference structure specifically includes an operational amplifier for clamping, two bipolar junction transistors (BJTs), a resistor R1 (ΔVBE / R1) for generating a current proportional to absolute temperature (PTAT), two identical resistors R2 and R3 (VBE / R2) for generating a negative temperature current, and three current mirrors M1, M2, and M3. PMOS transistors are used as current mirrors. Finally, a temperature-independent voltage VBG is generated on resistor R4 by combining the zero-temperature drift current of positive and negative temperatures.

[0004] By adding a startup circuit to the conventional low-voltage bandgap reference structure described above, a low-voltage bandgap reference with a startup circuit is obtained. The gate of NMOS transistor M4 is connected to the negative terminal of the operational amplifier, and the drain of NMOS transistor M5 is connected to the output of the operational amplifier. Without this startup circuit, at the moment of power-on, if the input of the operational amplifier is low voltage and the output of the operational amplifier is high voltage, the PMOS transistors M1 and M2 cannot start because their gates are at high voltage, and the entire circuit will not function. After adding the startup circuit, if the above situation occurs, the output of the operational amplifier is low voltage. At this time, the gate of the NMOS tube M4 is low voltage, the NMOS tube is not turned on, and the drain of the NMOS tube follows the power supply voltage VDD to a high voltage through the resistor R5. That is, the gate of the NMOS tube M5 is high voltage, M5 is turned on, and the voltage at the output end of the operational amplifier will be pulled down through M5, thereby turning on the PMOS tubes M1 and M2, and the input of the operational amplifier is also raised accordingly. At this time, M4 is turned on and M5 is turned off, and the operational amplifier establishes a loop, so that the entire circuit operates in a steady state.

[0005] However, a problem with this startup circuit is that M4's turn-on voltage, VTH, fluctuates with process pin variations. When VTH is too high, exceeding the VBE voltage at the negative terminal of the op amp, M4 may fail to turn on. Subsequently, M5 may not fully pull down M1's gate voltage, causing the op amp to operate in an incorrect metastable state. Therefore, to address this issue, a new low-voltage bandgap reference startup circuit is urgently needed. Summary of the Invention

[0006] The object of the present invention is to provide a low-voltage bandgap reference startup circuit in view of the deficiencies in the prior art.

[0007] The objective of the present invention is achieved through the following technical solutions: a low-voltage bandgap reference startup circuit, comprising: an operational amplifier, two bipolar transistors Q1 and Q2, a resistor R1 for generating a current proportional to absolute temperature, two resistors R2 and R3 for generating a negative temperature current, three PMOS transistors M1, M2 and M3, a zero-temperature drift resistor R4, two NMOS transistors M4 and M5, and three resistors R5, R6 and R7 for increasing the voltage; wherein the bases of Q1 and Q2 are connected to the collectors, the emitter or collector of Q1 is connected to the negative terminal of the operational amplifier, and the collector or emitter of Q1 is grounded; one end of R3 is grounded, and the other end is connected to the negative terminal of the operational amplifier; the positive terminal of the operational amplifier is connected to one end of R1, the other end of R1 is connected to the emitter or collector of Q2, and the collector or emitter of Q2 is connected to the ground. Ground; one end of R2 is grounded, and the other end is connected to the positive terminal of the operational amplifier; the sources of M1, M2 and M3 are connected together and to the power supply voltage VDD; the gates of M1, M2 and M3 are connected together and to the output terminal of the operational amplifier; the drain of M1 is connected to one end of R6, and the other end of R6 is connected to the negative terminal of the operational amplifier; the drain of M2 is connected to one end of R7, and the other end of R7 is connected to the positive terminal of the operational amplifier; the drain of M3 is connected to one end of R4, and the other end of R4 is grounded. The end of R4 away from ground generates a temperature-independent voltage VBG; the gate of M4 is connected to the drain of M1, the drain of M4 is connected to the gate of M5, and the drain of M5 is connected to the gate of M1. The sources of M4 and M5 are connected together and to ground; one end of R5 is connected to the drain of M4, and the other end is connected to VDD.

[0008] Furthermore, the bipolar transistors Q1 and Q2 are of the same type, both being PNP transistors or NPN transistors.

[0009] Furthermore, when the bipolar transistors Q1 and Q2 are both PNP transistors, the emitter of Q1 is connected to the negative terminal of the operational amplifier, the base of Q1 is connected to the collector and then grounded, the emitter of Q2 is connected to one end of the resistor R1, and the base of Q2 is connected to the collector and then grounded.

[0010] Furthermore, when the bipolar transistors Q1 and Q2 are both NPN transistors, the base and collector of Q1 are connected to the negative terminal of the operational amplifier, the emitter of Q1 is grounded, the base and collector of Q2 are connected to one end of the resistor R1, and the emitter of Q2 is grounded.

[0011] Furthermore, the resistance of the resistor R6 satisfies the following conditions:

[0012]

[0013] in, Represents the voltage between the base and emitter of the PMOS tube M1, Indicates the source-drain current of the PMOS tube M1, Indicates the resistance value of resistor R6, Indicates the threshold voltage of the NMOS tube M4.

[0014] Furthermore, the resistance of the resistor R7 is greater than the resistance of the resistor R6.

[0015] Furthermore, the resistor R5 can also be replaced by n PMOS inverse proportional transistors connected in series, where the drain of the previous PMOS inverse proportional transistor is connected to the source of the next PMOS inverse proportional transistor, where the source of the first PMOS inverse proportional transistor is connected to the power supply voltage VDD, and the drain of the last PMOS inverse proportional transistor is connected to the drain of the NMOS transistor M4; the gates of the n PMOS inverse proportional transistors are connected together and connected to one end of a resistor r, and the other end of the resistor r is connected to ground.

[0016] Furthermore, the width-to-length ratio W / L of the PMOS transistor is less than 1.

[0017] The beneficial effects of the present invention are as follows: by using two NMOS transistors M4 and M5, the present invention can simplify the circuit wiring structure, effectively saving area and cost; by adding a resistor R6 between the negative end of the operational amplifier and the drain of the PMOS transistor M1, the present invention can raise the voltage of the gate of the NMOS transistor M4 by changing the resistance value of the resistor R6, so that the circuit can operate normally at any process pin; at the same time, by adding a resistor R7 between the positive end of the operational amplifier and the drain of the PMOS transistor M2, and the resistance value of R7 is greater than that of R6, effectively ensuring that the negative feedback is always greater than the positive feedback; the present invention solves the problem that the threshold voltage of the MOS transistor is large in certain process pins, resulting in the startup circuit not operating normally, and at the same time, the overall loop still maintains negative feedback, without causing new problems, so that the circuit can operate normally. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] Figure 1The present invention is a circuit diagram of an existing low-voltage bandgap reference structure with an added startup circuit;

[0019] Figure 2 It is a circuit diagram of a low-voltage bandgap reference startup circuit of the present invention;

[0020] Figure 3 This is another circuit diagram of the low-voltage bandgap reference startup circuit of the present invention. DETAILED DESCRIPTION

[0021] Exemplary embodiments will be described in detail herein, examples of which are illustrated in the accompanying drawings. In the following description, when referring to the drawings, like numbers in different figures represent like or similar elements unless otherwise indicated. The embodiments described in the following exemplary embodiments are not intended to represent all possible embodiments consistent with the present invention. Rather, they are merely examples of apparatus and methods consistent with certain aspects of the present invention, as detailed in the appended claims.

[0022] The terms used in this invention are for the purpose of describing specific embodiments only and are not intended to limit the invention. The singular forms "a," "the," and "the" used in this invention and the appended claims are also intended to include plural forms unless the context clearly indicates otherwise. It should also be understood that the term "and / or" as used herein refers to and includes any or all possible combinations of one or more of the associated listed items.

[0023] It should be understood that although the terms "first," "second," "third," etc. may be used in the present invention to describe various information, such information should not be limited to these terms. These terms are merely used to distinguish information of the same type from one another. For example, first information may also be referred to as second information, and similarly, second information may also be referred to as first information, without departing from the scope of the present invention. Depending on the context, the term "if" as used herein may be interpreted as "when," "when," or "in response to determining."

[0024] The present invention will be described in detail below with reference to the accompanying drawings. Unless there is any conflict, the features of the following embodiments and implementations may be combined with each other.

[0025] Figure 1 The circuit diagram of the existing low-voltage bandgap reference structure with a startup circuit added is shown in FIG. Figure 1As shown, the circuit includes a low-voltage bandgap reference structure and a startup circuit. The low-voltage bandgap reference structure includes an operational amplifier, two bipolar transistors Q1 and Q2, a resistor R1 for generating a PTAT current, two resistors R2 and R3 for generating a negative temperature current, three PMOS transistors M1, M2 and M3, and a zero temperature drift resistor R4, and finally generates a temperature-independent voltage VBG; the startup circuit includes two NMOS transistors M4 and M5 and a resistor R5. Among them, in the low-voltage bandgap reference structure, when the two bipolar transistors Q1 and Q2 are PNP transistors, the negative terminal of the operational amplifier is connected to the emitter (Emitter) of the PNP transistor Q1, and the collector (Collertor) of the PNP transistor Q1 is connected to the base (Base) and then grounded; one end of the resistor R3 is grounded, and the other end is connected to the negative terminal of the operational amplifier; the positive terminal of the operational amplifier is connected to one end of the resistor R1, and the other end of the resistor R1 is connected to the emitter of the PNP transistor Q2, and the collector (Collertor) of the PNP transistor Q2 is connected to the base and then grounded; one end of the resistor R2 is grounded, and the other end is connected to The positive terminal of the operational amplifier is connected; the sources of the three PMOS transistors M1, M2, and M3 are connected together and connected to the power supply voltage VDD; the gates of the three PMOS transistors M1, M2, and M3 are connected together and connected to the output of the operational amplifier; the drain of PMOS transistor M1 is connected to the negative terminal of the operational amplifier, the drain of PMOS transistor M2 is connected to the positive terminal of the operational amplifier, and the drain of PMOS transistor M3 is connected to one end of zero-drift resistor R4, the other end of which is grounded. The end of zero-drift resistor R4 away from ground generates a temperature-independent voltage VBG. In the startup circuit, the gate of NMOS transistor M4 is connected to the negative terminal of the operational amplifier, the drain of NMOS transistor M4 is connected to the gate of NMOS transistor M5, and the drain of NMOS transistor M5 is connected to the output of the operational amplifier. The sources of NMOS transistors M4 and M5 are connected together and connected to ground. One end of resistor R5 is connected to the drain of NMOS transistor M4, and the other end is connected to the power supply voltage VDD.

[0026] It should be understood that the two bipolar transistors Q1 and Q2 may also be NPN transistors. In this case, the collector and base of the NPN transistor Q1 are connected to the negative terminal of the operational amplifier, and the emitter of the NPN transistor Q1 is grounded; the collector and base of the NPN transistor Q2 are connected to one end of the resistor R1, and the emitter of the NPN transistor Q2 is grounded.

[0027] In the embodiment of the present invention, Figure 1The circuit shown in FIG. 1 is improved by increasing the voltage of the gate of the NMOS tube M4 so that the circuit can work normally at any process foot, thereby obtaining the low-voltage bandgap reference startup circuit of the present invention. Figure 2 As shown, it specifically includes an operational amplifier, two bipolar transistors Q1 and Q2, a resistor R1 for generating PTAT current, two resistors R2 and R3 for generating negative temperature current, three PMOS tubes M1, M2 and M3, a zero temperature drift resistor R4, two NMOS tubes M4 and M5, and three resistors R5, R6 and R7 for increasing voltage. Among them, the bases of Q1 and Q2 are connected to the collectors, the emitter or collector of Q1 is connected to the negative terminal of the operational amplifier, and the collector or emitter of Q1 is grounded; one end of R3 is grounded, and the other end is connected to the negative terminal of the operational amplifier; the positive terminal of the operational amplifier is connected to one end of R1, the other end of R1 is connected to the emitter or collector of Q2, and the collector or emitter of Q2 is grounded; one end of R2 is grounded, and the other end is connected to the positive terminal of the operational amplifier; the sources of M1, M2 and M3 are connected together and to the power supply voltage VDD; the gates of M1, M2 and M3 are connected together and to the positive terminal of the operational amplifier. The output end is connected; the drain of M1 is connected to one end of R6, and the other end of R6 is connected to the negative end of the operational amplifier; the drain of M2 is connected to one end of R7, and the other end of R7 is connected to the positive end of the operational amplifier; the drain of M3 is connected to one end of R4, and the other end of R4 is grounded. The end of R4 away from the ground generates a temperature-independent voltage VBG; the gate of M4 is connected to the drain of M1, the drain of M4 is connected to the gate of M5, and the drain of M5 is connected to the gate of M1. The sources of M4 and M5 are connected together and connected to ground; one end of R5 is connected to the drain of M4, and the other end is connected to VDD. In this circuit, two NMOS tubes are used for pull-down, and the wiring structure is simple, saving area and cost. If they are replaced with PMOS tubes, the circuit will be complicated, with more tubes and high cost. Therefore, in the startup circuit, by using two NMOS tubes, the circuit wiring structure can be simplified, effectively saving area and cost. It also solves the problem that some process pins cause the threshold voltage of the MOS tube to be large, resulting in the startup circuit not working properly. At the same time, the overall loop is still negative feedback, without causing new problems, so that the circuit can work normally.

[0028] Furthermore, the two bipolar transistors Q1 and Q2 are of the same type, both being PNP transistors or NPN transistors. When the two bipolar transistors Q1 and Q2 are PNP transistors, the emitter of Q1 is connected to the negative terminal of the operational amplifier, the base of Q1 is connected to the collector and then to ground, the emitter of Q2 is connected to one end of the resistor R1, the base of Q2 is connected to the collector and then to ground, as shown in FIG. Figure 2As shown. When the two bipolar transistors Q1 and Q2 are NPN transistors, the base and collector of Q1 are connected to the negative terminal of the operational amplifier, the emitter of Q1 is grounded, the base and collector of Q2 are connected to one end of the resistor R1, and the emitter of Q2 is grounded.

[0029] Furthermore, the resistance of resistor R6 satisfies the following conditions:

[0030]

[0031] in, Represents the voltage between the base and emitter of the PMOS tube M1, Indicates the source-drain current of the PMOS tube M1, Indicates the resistance value of resistor R6, represents the threshold voltage of NMOS transistor M4. Resistor R6 raises the gate of NMOS transistor M4 by a voltage equal to R6*IDS1. By adjusting the resistance of R6 so that its value satisfies the above formula, the circuit will function properly. Furthermore, a resistor R7 with a greater resistance than R6 should be added to the positive path of the operational amplifier to ensure that the negative feedback loop always exceeds the positive feedback loop, ensuring normal circuit operation.

[0032] Furthermore, the resistance of resistor R7 is greater than the resistance of resistor R6. Figure 2 As shown in the figure, by adding a resistor R6 between the negative terminal of the operational amplifier and the drain of the PMOS tube M1, and adding a resistor R7 between the positive terminal of the operational amplifier and the drain of the PMOS tube M2, it is necessary to ensure that the resistance of R7 is greater than the resistance of R6. Because after adding R6, the feedback coefficient of the negative feedback will decrease, it is necessary to add R7 with a larger resistance than R6 to make the feedback coefficient of the positive feedback decrease more than the negative feedback, so as to ensure that the negative feedback is always greater than the positive feedback.

[0033] Since the startup circuit is an auxiliary circuit, it should not bring about a lot of power consumption. After the NMOS tube M4 is turned on, the over-drive voltage of M4 can be almost ignored. ,in Represents the source-drain current of NMOS tube M4, Indicates the power supply voltage, represents the resistance of resistor R5. If the source-drain current of NMOS tube M4 is required to be small, then R5 needs to have a large resistance and a large area. Figure 3As shown, n series-connected PMOS inverse ratio transistors are used to replace the resistor R5. These n PMOS inverse ratio transistors all adopt inverse ratio to increase the equivalent impedance of the NMOS transistor. The gates of the n series-connected PMOS inverse ratio transistors are connected to the ground through a small resistor to ensure better conduction. The area required for the n PMOS inverse ratio transistors to produce the same impedance as the resistor R5 is greatly reduced, thereby saving area.

[0034] Specifically, if Figure 3 As shown, the source of the first PMOS inverse proportional tube is connected to the power supply voltage VDD, the drain of the first PMOS inverse proportional tube is connected to the source of the second PMOS inverse proportional tube, the drain of the second PMOS inverse proportional tube is connected to the source of the third PMOS inverse proportional tube, and so on, the drain of the previous PMOS inverse proportional tube is connected to the source of the next PMOS inverse proportional tube, and the drain of the last PMOS inverse proportional tube is connected to the drain of the NMOS tube M4. The gates of the n PMOS inverse proportional tubes are connected together and connected to one end of a small resistor r, and the other end of the small resistor r is connected to ground.

[0035] Furthermore, the aspect ratio W / L of the PMOS transistor is less than 1.

[0036] In summary, the present invention simplifies the circuit wiring structure by using two NMOS transistors M4 and M5, effectively saving area and cost. The present invention adds a resistor R6 between the negative terminal of the operational amplifier and the drain of the PMOS transistor M1. By changing the resistance value of the resistor R6, the voltage at the gate of the NMOS transistor M4 can be raised, so that the circuit can operate normally at any process pin. At the same time, a resistor R7 is added between the positive terminal of the operational amplifier and the drain of the PMOS transistor M2, and the resistance value of R7 is greater than that of R6, effectively ensuring that the negative feedback is always greater than the positive feedback. The present invention solves the problem that the startup circuit cannot operate normally due to the high threshold voltage of the MOS transistor caused by certain process pins. At the same time, the overall loop still maintains negative feedback, without causing new problems, and the circuit can operate normally.

[0037] It should be noted that, in this document, the terms "comprises," "includes," or any other variations thereof are intended to encompass non-exclusive inclusion, such that a process, method, article, or apparatus comprising a series of elements includes not only those elements but also other elements not explicitly listed, or elements inherent to such process, method, article, or apparatus. In the absence of further limitations, an element defined by the phrase "comprising a ..." does not exclude the presence of other identical elements in the process, method, article, or apparatus comprising the element.

[0038] The embodiments of the present invention are described above in conjunction with the accompanying drawings, but the present invention is not limited to the above-mentioned specific implementation methods. The above-mentioned specific implementation methods are merely illustrative and not restrictive. Under the guidance of the present invention, ordinary technicians in this field can also make many forms without departing from the scope of protection of the present invention and the claims, all of which are protected by the present invention.

Claims

1. A low voltage bandgap reference startup circuit, characterized in that: include: An operational amplifier, two bipolar transistors Q1 and Q2, a resistor R1 for generating a current proportional to absolute temperature, two resistors R2 and R3 for generating a negative temperature current, three PMOS tubes M1, M2 and M3, a zero temperature drift resistor R4, two NMOS tubes M4 and M5, and three resistors R5, R6 and R7 for increasing the voltage; among them, the bases of Q1 and Q2 are connected to the collectors, the emitter or collector of Q1 is connected to the negative terminal of the operational amplifier, and the collector or emitter of Q1 is grounded; one end of R3 is grounded, and the other end is connected to the negative terminal of the operational amplifier; the positive terminal of the operational amplifier is connected to one end of R1, and the other end of R1 is connected to the emitter or collector of Q2, and the collector or emitter of Q2 is grounded; one end of R2 is grounded, and the other end is connected to the operational amplifier The positive terminal of the amplifier is connected; the sources of M1, M2 and M3 are connected together and connected to the power supply voltage VDD; the gates of M1, M2 and M3 are connected together and connected to the output terminal of the operational amplifier; the drain of M1 is connected to one end of R6, and the other end of R6 is connected to the negative terminal of the operational amplifier; the drain of M2 is connected to one end of R7, and the other end of R7 is connected to the positive terminal of the operational amplifier; the drain of M3 is connected to one end of R4, and the other end of R4 is grounded, and the end of R4 away from ground generates a temperature-independent voltage VBG; the gate of M4 is connected to the drain of M1, the drain of M4 is connected to the gate of M5, and the drain of M5 is connected to the gate of M1. The sources of M4 and M5 are connected together and connected to ground; one end of R5 is connected to the drain of M4, and the other end is connected to VDD; The resistance of the resistor R7 is greater than the resistance of the resistor R6; The resistor R5 can also be replaced by n PMOS inverse proportional transistors connected in series to provide a high output impedance; the drain of the previous PMOS inverse proportional transistor is connected to the source of the next PMOS inverse proportional transistor, wherein the source of the first PMOS inverse proportional transistor is connected to the power supply voltage VDD, and the drain of the last PMOS inverse proportional transistor is connected to the drain of the NMOS transistor M4; the gates of the n PMOS inverse proportional transistors are connected together and connected to one end of a resistor r, and the other end of the resistor r is connected to ground.

2. The low voltage bandgap reference startup circuit according to claim 1, characterized in that: The bipolar transistors Q1 and Q2 are of the same type, both being PNP transistors or NPN transistors.

3. The low voltage bandgap reference startup circuit according to claim 2, characterized in that: When the bipolar transistors Q1 and Q2 are both PNP transistors, the emitter of Q1 is connected to the negative terminal of the operational amplifier, the base of Q1 is connected to the collector and then grounded, the emitter of Q2 is connected to one end of the resistor R1, and the base of Q2 is connected to the collector and then grounded.

4. The low voltage bandgap reference startup circuit according to claim 2, wherein: When the bipolar transistors Q1 and Q2 are both NPN transistors, the base and collector of Q1 are connected to the negative terminal of the operational amplifier, the emitter of Q1 is grounded, the base and collector of Q2 are connected to one end of the resistor R1, and the emitter of Q2 is grounded.

5. The low voltage bandgap reference startup circuit according to claim 1, wherein: The resistance value of the resistor R6 satisfies the following conditions: ； in, Represents the voltage between the base and emitter of the PMOS tube M1, Indicates the source-drain current of the PMOS tube M1, Indicates the resistance value of resistor R6, Indicates the threshold voltage of the NMOS tube M4.

6. The low voltage bandgap reference startup circuit according to claim 1, characterized in that: The width-to-length ratio W / L of the PMOS inverted ratio transistor is less than 1.

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