Software generation using neural networks

Abstract

The invention relates to software generation using a neural network. Apparatuses, systems, and techniques for generating software code are disclosed. In at least one embodiment, one or more neural networks are used to generate one or more software programs having the indicated one or more software program dependencies using information indicative of the one or more software program dependencies.

Description

Technical Field

[0001] At least one embodiment relates to using a neural network to generate source code. For example, at least one embodiment relates to using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies. Background Art

[0002] The ability of a neural network to generate code largely stems from its autoregressive nature, which involves predicting new code tokens by identifying patterns in previously written code. However, this method may generate code that is not suitable for certain applications. The ability of a neural network to autonomously generate code can be improved. Brief Description of the Drawings

[0003] Figure 1 is a block diagram showing an example of a system for generating a software program using one or more neural networks according to at least one embodiment;

[0004] Figure 2 is a block diagram further showing an example of a system for generating a software program using one or more neural networks according to at least one embodiment;

[0005] Figure 3 is further showing according to at least one embodiment Figure 2 of the system in the block diagram.

[0006] Figure 4 is a block diagram further showing an attention chain for identifying code dependencies in previously generated code according to at least one embodiment;

[0007] Figure 5 shows detailed calculation steps in a cross-attention module according to at least one embodiment;

[0008] Figure 6 shows an example process of using one or more neural networks to generate one or more software programs having one or more software program dependencies indicated by information indicating one or more software program dependencies according to at least one embodiment;

[0009] Figure 7A shows the logic according to at least one embodiment;

[0010] Figure 7B shows the logic according to at least one embodiment;

[0011] Figure 8 shows the training and deployment of a neural network according to at least one embodiment;

[0012] Figure 9 illustrates an example data center system in accordance with at least one embodiment;

[0013] Figure 10A illustrates an example of an autonomous vehicle in accordance with at least one embodiment;

[0014] Figure 10B illustrates in accordance with at least one embodiment Figure 10A an example of the camera positions and fields of view of an autonomous vehicle;

[0015] Figure 10C is a block diagram of an example system architecture of an autonomous vehicle showing in accordance with at least one embodiment Figure 10A ;

[0016] Figure 10D is a diagram of a system showing for communication between one or more cloud-based servers and Figure 10A an autonomous vehicle in accordance with at least one embodiment;

[0017] Figure 11 is a block diagram of a computer system showing in accordance with at least one embodiment;

[0018] Figure 12 is a block diagram of a computer system showing in accordance with at least one embodiment;

[0019] Figure 13 illustrates a computer system in accordance with at least one embodiment;

[0020] Figure 14 illustrates a computer system in accordance with at least one embodiment;

[0021] Figure 15A illustrates a computer system in accordance with at least one embodiment;

[0022] Figure 15B illustrates a computer system in accordance with at least one embodiment;

[0023] Figure 15C illustrates a computer system in accordance with at least one embodiment;

[0024] Figure 15D illustrates a computer system in accordance with at least one embodiment;

[0025] Figure 15E and Figure 15F illustrates a shared programming model in accordance with at least one embodiment;

[0026] Figure 16 illustrates an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0027] Figure 17A and Figure 17B illustrates an exemplary integrated circuit and associated graphics processor in accordance with at least one embodiment;

[0028] Figure 18A and Figure 18B illustrates additional exemplary graphics processor logic in accordance with at least one embodiment;

[0029] Figure 19 illustrates a computer system in accordance with at least one embodiment;

[0030] Figure 20A illustrates a parallel processor in accordance with at least one embodiment;

[0031] Figure 20B illustrates a partitioning unit in accordance with at least one embodiment;

[0032] Figure 20C illustrates a processing cluster in accordance with at least one embodiment;

[0033] Figure 20D illustrates a graphics multiprocessor in accordance with at least one embodiment;

[0034] Figure 21 illustrates a multi - graphics processing unit (GPU) system in accordance with at least one embodiment;

[0035] Figure 22 illustrates a graphics processor in accordance with at least one embodiment;

[0036] Figure 23 is a block diagram illustrating a processor micro - architecture for a processor in accordance with at least one embodiment;

[0037] Figure 24 illustrates a deep - learning application processor in accordance with at least one embodiment;

[0038] Figure 25 is a block diagram illustrating an example neuromorphic processor in accordance with at least one embodiment;

[0039] Figure 26 illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

[0040] Figure 27 illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

[0041] Figure 28 illustrates at least a portion of a graphics processor in accordance with one or more embodiments;

[0042] Figure 29is a block diagram of a graphics processing engine of a graphics processor according to at least one embodiment;

[0043] Figure 30 is a block diagram of at least a portion of a graphics processor core according to at least one embodiment;

[0044] Figure 31A and Figure 31B illustrates thread execution logic according to at least one embodiment, which includes an array of processing elements of a graphics processor core.

[0045] Figure 32 illustrates a parallel processing unit (“PPU”) according to at least one embodiment;

[0046] Figure 33 illustrates a general processing cluster (“GPC”) according to at least one embodiment;

[0047] Figure 34 illustrates a memory partition unit of a parallel processing unit (“PPU”) according to at least one embodiment;

[0048] Figure 35 illustrates a streaming multiprocessor according to at least one embodiment;

[0049] Figure 36 is an example data flow diagram of an advanced computing pipeline according to at least one embodiment;

[0050] Figure 37 is a system diagram of an example system for training, adapting, instantiating, and deploying a machine learning model in an advanced computing pipeline according to at least one embodiment;

[0051] Figure 38 includes an example illustration of an advanced computing pipeline for processing imaging data according to at least one embodiment;

[0052] Figure 39A includes an example data flow diagram of a virtual instrument supporting an ultrasound device according to at least one embodiment;

[0053] Figure 39B includes an example data flow diagram of a virtual instrument supporting a CT scanner according to at least one embodiment;

[0054] Figure 40A illustrates a data flow diagram of a process for training a machine learning model according to at least one embodiment;

[0055] Figure 40B is an example illustration of a client - server architecture for enhancing an annotation tool using a pre - trained annotation model according to at least one embodiment; and

[0056] Figure 41 Shows components of a system for accessing a large language model according to at least one embodiment. Detailed implementation

[0057] At least one embodiment of the techniques described and proposed herein relates to training and inferring a neural network to generate a software program that complies with a specification including one or more software program dependencies. In at least one embodiment, the software program dependencies used herein refer to dependencies between different levels (such as namespaces, modules, classes, functions, and lines of code) within a code hierarchy. For example, in at least one embodiment, a code segment including a function may consist of multiple lines of code and also belong to a class within a module, where the module is part of a namespace. In this example, the code segment represents a code hierarchy with four levels from bottom to top: lines of code, functions, modules, and namespaces. In at least one embodiment, the relationships between these four levels of the code hierarchy are examples of software program dependencies. In at least one embodiment, software program dependencies are also referred to as code dependencies.

[0058] In at least one embodiment, the neural network performs multiple self-attention operations on each pair of adjacent levels in the code hierarchy of previously generated code for a code generation task using an attention chain. In at least one embodiment, the previously generated code corresponds to code related to the code being generated, such as code previously generated in a session related to the code being generated. In at least one embodiment, each self-attention operation on a pair of code hierarchy levels is performed between a lower-level raw code token and a higher-level summary data token. In at least one embodiment, the self-attention operation enables the neural network to identify dependencies between different hierarchy levels in the previously generated code. In at least one embodiment, the identified dependencies allow the neural network to generate the next code token for the code generation task. In at least one embodiment, the neural network performs at least one cross-attention between the previously generated code and the specification of the target software program to prevent inconsistencies between the previously generated code and the specification. In at least one embodiment, the neural network performs at least one cross-attention operation between the previously generated code and content retrieved from an external code library to introduce additional context and reuse code from existing applications.

[0059] In at least one embodiment, the techniques proposed herein thus generate a cohesive software program that complies with the specification in a manner similar to real-world product-level software engineering.

[0060] In at least one embodiment, the techniques and embodiments presented herein are applicable to the training and inference of neural networks, except that during training, the neural network identifies code dependencies in the training source code, rather than in previously generated code for code generation tasks as in inference.

[0061] In at least one embodiment, during training, the neural network learns the relationship between a design document and its corresponding implementation solution such that this learning enables the neural network to generate new code for a new design document during inference. In at least one embodiment, during training, the parameters (e.g., weights and biases) of the neural network are adjusted to capture the relationship between the design document and its corresponding code implementation solution and the relationships between different levels of the code hierarchy. In at least one embodiment, although the neural network is exposed to pairs of design documents and their corresponding code implementation solutions, the neural network does not memorize these pairs to replicate them during inference. Instead, in at least one embodiment, the neural network learns the underlying patterns, relationships, and structures that link the specifications of the design document to its implementation in code. In at least one embodiment, the neural network is an autoregressive neural network that learns to predict each subsequent code token based on previous tokens and the neural network's learning of how the overall code structure relates to the parts of the design document.

[0062] More specifically, in at least one embodiment, a training dataset paired with a design document and its corresponding code implementation is used to train the neural network, where the design document details the requirements, specifications, and any relevant information needed to determine what a software program should do. In at least one embodiment, an input processor normalizes and preprocesses these training datasets, for example, formatting the design document and code in a consistent manner and tokenizing the design document and code, which involves breaking the text in the design document and code into tokens and encoding these tokens as vectors so that the neural network can process them. In at least one embodiment, the neural network is trained on the design document and corresponding code pairs to predict the next token based on the design document and code generated so far. In at least one embodiment, during training, a portion of a code segment is covered, and the visible portion and the design document are fed into the neural network. In at least one embodiment, the covered portion serves as ground truth data.

[0063] In at least one embodiment, during interference, the neural network generates code for a new design document token by token based on the context provided by a given design document using learned patterns. In at least one embodiment, the neural network does not simply output previously seen code. Instead, the neural network generalizes from the learned data and creates something applicable to new, unseen scenarios.

[0064] In at least one embodiment, the neural network initially relies on information in the design document to generate one or more initial tokens of a software program. In at least one embodiment, after generating the one or more code tokens, the neural network enters an autoregressive generation mode, where the neural network takes the generated code as part of the input context and attends to the design document and all previously generated code tokens to generate new code tokens.

[0065] In at least one embodiment, during inference, the neural network retrieves the design document encoding the design document that specifies the code hierarchy from the tensor, and generates a namespace and one or more class names in the namespace using the carrier tokens at the namespace level of the code hierarchy. Subsequently, in at least one embodiment, the neural network generates code for the class, e.g., code that does not belong to the functions within each class. In at least one embodiment, the neural network generates code for the functions within each class using the carrier tokens at the class level, and so on in a similar manner until a code segment including the code hierarchy is generated.

[0066] In at least one embodiment, to more accurately identify code dependencies in the generated source code, the input processor tokenizes the source code and extracts separate summary data from the tokens at each level of the code hierarchy. For example, if the code hierarchy includes a class with two functions, the code hierarchy will have three levels: the class, the functions within the class, and the lines of code within the functions. In at least one embodiment, the summary data at each level of the code hierarchy is information describing that level of the code hierarchy. For example, function-level summary data includes the function name, the text description attached to the function, and other available information (e.g., inline comments). Similarly, class-level summary data includes the class name, the text description attached to the class, and other available information (e.g., inline comments). In at least one embodiment, at least one carrier token is retrieved from a specification document that is provided as an initial input to the neural network and analyzed by an attention block in the neural network during the code generation process. In at least one embodiment, for example, the text description in the specification document can be used to generate carrier tokens.

[0067] In at least one embodiment, the input processor tokenizes the lines of code, the functions, and the classes at their respective code levels into code tokens. In at least one embodiment, for a line of code, each line of code can be decomposed into smaller chunks (e.g., words, variable names, etc.), and each chunk is called a token; for a function, the text describing the name and signature (e.g., input parameters) of the function can be decomposed into code tokens; and for a class, the text describing the name and signature (e.g., input parameters) of the class can be decomposed into code tokens. Similarly, in at least one embodiment, the input processor tokenizes the summary data at each level of the code hierarchy into summary data tokens (also referred to herein as carrier tokens) and analyzes the relationships between different levels within the code hierarchy in a top-down pairwise order. In at least one embodiment, according to the top-down pairwise order, a carrier token at one level is paired with the code tokens at the immediately lower level. For example, a carrier token at the namespace level is paired with code tokens at the module level, a carrier token at the module level is paired with code tokens at the class level, and so on. In at least one embodiment, the higher levels in the code hierarchy are more abstract levels. Thus, the class level is higher than the function level, and the function level is higher than the line of code level.

[0068] In at least one embodiment, for each pair of levels in the code hierarchy, the attention block retrieves content from one or more external code libraries and performs self-attention and cross-attention on the combined tokens of the two levels in multiple iterations. In at least one embodiment, during each iteration, the attention block separates the code tokens and the carrier tokens at least once so that self-attention can be performed within the same type of data without being interfered by irrelevant data. In at least one embodiment, during each iteration, the attention block performs cross-attention between the carrier tokens and the content retrieved from one or more external code libraries (e.g., Figure 1 the private code library 117 and the public code library 115 in []) to introduce additional context. In at least one embodiment, the additional context includes code patterns related to the current code generation task. In at least one embodiment, during each iteration, the attention block performs cross-attention between the generated code and the specification (e.g., design document) of the software program to be generated so that any generated code is contextually aligned with the specification. Thus, in at least one embodiment, through various self-attention and cross-attention, the attention block identifies the appropriate context for the neural network to generate code relevant to the current requirements and consistent with the existing code libraries.

[0069] Figure 1FIG. is a block diagram illustrating an example of a system 100 for generating a software program using one or more neural networks according to at least one embodiment. In at least one embodiment, system 100 includes a neural network 101 and a retrieval block 119. In at least one embodiment, neural network 101 is a Transformer LLM that includes a Transformer encoder 105 and a plurality of Transformer decoders (e.g., Transformer decoder 107). In at least one embodiment, the plurality of Transformer decoders constitute an attention block 106. In at least one embodiment, retrieval block 119 and neural network 101 are executed (e.g., run) on processors 118 and 120, respectively. In at least one embodiment, processors 118 and 120 can be one processor or two different processors. In at least one embodiment, each of processors 118 and 120 includes one or more circuits. In at least one embodiment, each of processors 118 and 120 is a central processing unit (CPU), a graphics processing unit (GPU), a parallel processing unit (PPU), a general-purpose graphics processing unit (GPGPU), a computing cluster, and / or a combination of these and / or other such processors. In at least one embodiment, each of processors 118 and 120 is part of a computer system (e.g., the computer system described herein).

[0070] In at least one embodiment, Transformer encoder 105 processes a data input, such as a specification 103. In at least one embodiment, the specification is included in a file providing the technical requirements of the software program 109 to be generated. For example, the file defines the layered architecture of software program 109, detailing the functional layers and code dependencies, from the high-level user interface down to the low-level system operations. In at least one embodiment, the file has multiple formats (e.g., PDF, Word, text) and will be uploaded to the interface of neural network 101. In at least one embodiment, specification 103 is provided as a text prompt to neural network 101 as an input. In at least one embodiment, specification 103 is provided as a voice input to neural network 101. In at least one embodiment, neural network 101 is integrated with an interactive development environment (IDE) such that specification 103 is provided to the neural network through the IDE.

[0071] In at least one embodiment, retrieval block 119 includes a plurality of encoders for encoding multi-modal (e.g., text, video, image, and audio) information from a common code library 115 and a private code library 117. The retrieved information is used by neural network 101 as external knowledge to enhance its code generation performance.

[0072] In at least one embodiment, the encoder 105 parses the specification 103 to determine its content, which involves tokenizing the text describing the specification 103 and embedding the generated tokens into high-dimensional vectors. In at least one embodiment, the attention block 106 receives the encoded representation of the specification 103 from the transformer encoder 105 and generates an initial output sequence. In at least one embodiment, this initial output sequence is part of the software program 109 and is treated as previously generated code in the code generation task for generating the software program 109. In at least one embodiment, the previously generated code is provided as input to the neural network 101, where the attention block 106 iteratively performs self-attention operations in multiple decoder blocks at each pair of adjacent hierarchical levels to relate the code blocks between the hierarchical levels, thereby identifying code dependencies in the previously generated code. In at least one embodiment, the neural network 101 uses this learned code dependency and the specification 103 to generate new code for the code generation task.

[0073] In at least one embodiment, self-attention is a mechanism that allows a neural network to weigh the importance of different parts of an input when processing a particular part of the input. In at least one embodiment, during self-attention, each token (e.g., word) in the input sequence "attends to" each token in the input sequence to determine which tokens are more important and which tokens are less important when predicting the next token. In at least one embodiment, attending to a token means focusing on that token and giving it importance. Thus, in at least one embodiment, self-attention allows a neural network to identify the internal structure and relationships within a given input sequence (e.g., a single sentence or document).

[0074] In at least one embodiment, the self-attention module in each transformer decoder in the attention block 106 attends to the original code tokens at the code hierarchical level below the generated code, as well as the carrier tokens (e.g., compressed summaries of high-level information) at the immediately adjacent level of the code hierarchy. In at least one embodiment, by encapsulating high-level information in the carrier tokens and appending the carrier tokens to the original code tokens, the neural network 101 can iterate over multiple hierarchical levels. In at least one embodiment, the carrier tokens at different hierarchical levels act as anchors to connect the hierarchical levels in a cohesive order. In at least one embodiment, these iterations enable the neural network 101 to more accurately identify code dependencies in the previously generated code than by relying solely on the original code tokens.

[0075] In at least one embodiment, the cross-attention module in each transformer decoder (e.g., transformer decoder 107) performs one or more cross-attention operations between the carrier tokens at one or more hierarchical levels of the previously generated and retrieved content from the private codebase 117 and the public codebase 115 to introduce external information, and performs one or more cross-attention operations between the previously generated code and the specification 103 to guide the neural network 101 to generate new code that conforms to the specification.

[0076] Figure 1 The elements and features described in the respective embodiments are compatible and can be combined with the elements and features in other figures described herein.

[0077] Figure 2 is a block diagram illustrating an example of a system 200 for generating a software program using one or more neural networks according to at least one embodiment. In at least one embodiment, the retrieval block 119 includes two sets of encoders 215 and 217 for the public codebase 115 and the private codebase 117, respectively. In at least one embodiment, these encoders 215 and 217 are pre-trained neural networks for retrieving multimodal information from the public codebase 115 and the private codebase 117. In at least one embodiment, such encoders 215 and 217 are jointly trained with the neural network 101 by balancing the retrieval loss and the autoregressive loss.

[0078] In at least one embodiment, the encoders 215 and 217 encode the information from each codebase to generate a public index 231 and a private index 235. In at least one embodiment, each encoder is trained for information of a specific modality. In at least one embodiment, each encoder splits the retrieved information into different slices and encodes each information slice into a vector, with each vector represented by a key. In at least one embodiment, the index is a key-value pair. For example, a text encoder for the private codebase 117 can encode a code segment for performing quicksort into a vector paired with a unique key. In this case, the code segment represented by the vector is the value.

[0079] In at least one embodiment, the input preprocessor 204 encodes the specification 103 and the code 203 into a representation tensor 247. In at least one embodiment, the input preprocessor 204 is a separate component that prepares the input data for further processing by the neural network 101. In at least one embodiment, the input preprocessor 204 is part of the neural network 101, e.g., part of the transformer encoder 105.

[0080] In at least one embodiment, the code 203 is for Figure 1The previously generated code for the code generation task of the software program 109 described in [reference]. In at least one embodiment, the code 203 is the code that has been generated during a code generation session of the software program 109. In at least one embodiment, the code 203 includes a multi-level hierarchical code structure. In at least one embodiment, the code 203 includes functions that contain multiple lines of code and belong to classes within a module that references another module. In at least one embodiment, identifying dependencies in the code 203 provides context for a neural network to generate new code suitable for the identified dependencies, such that the software program 109 can become a cohesive application.

[0081] In at least one embodiment, the representation tensor 247 is a data structure that holds the encoded representations of the specification 103 and the code 203. In at least one embodiment, the representation tensor 247 is a collection of vectors or a multi-dimensional array, where each element is a vector representing a specific input data, such as a line of code in the code 203 or a segment of the specification 103.

[0082] In at least one embodiment, the encoder 249 retrieves information from the representation tensor 247 and uses the information as queries in the common index 231 and the private index 235 to obtain the neighbors 237 and 239 respectively. In at least one embodiment, the neighbor 237 or the neighbor 239 includes the top N vectors that best match the query, and each vector represents a code segment. In at least one embodiment, the query generates more than one result. In at least one embodiment, for example, a query for a code segment that implements the QuickSort algorithm may generate multiple results, each representing a different implementation of the algorithm, and each result is a neighbor in the neighbor 237 or the neighbor 239.

[0083] In at least one embodiment, the trainable transformer encoder 105 receives the neighbors 237 and 239 and the representation tensor 247 after the representation tensor 247 passes through the self-attention module 251. In at least one embodiment, the self-attention module 251 performs one or more self-attention operations on different hierarchical levels of the code 203 to identify code dependencies therein. In at least one embodiment, the transformer encoder 105 generates the encoded neighbors 241 and 243 from the neighbors 237 and 239 respectively. In at least one embodiment, the encoded neighbors are the transformed representations of the neighbors, which incorporate information about the dependencies in the code 203 from the self-attention module 251. In at least one embodiment, the encoded neighbors 241 and 243 are referred to as the external memory 240, which represents the latest external knowledge.

[0084] In at least one embodiment, the cross-attention module 208 performs one or more cross-attention operations between the external memory and the identified code dependencies in the code 203 to generate new code that is contextually relevant and syntactically correct, reflecting patterns and conventions found in an existing codebase (e.g., private codebase 117).

[0085] In at least one embodiment, a feed-forward network (FFN) 253 operates on the output of the cross-attention module 208 to perform two linear transformations with a non-linear activation function between the two linear transformations. In at least one embodiment, the non-linear activation enables the neural network 101 to learn complex patterns in the output information from the cross-attention module 208, integrate and refine such information, and prepare such information for a softmax (normalized exponential function) 255. In at least one embodiment, the softmax 255 obtains a probability distribution over possible code tokens. In at least one embodiment, the token with the highest probability is selected as the next code token.

[0086] In at least one embodiment, during training, the softmax 255 will be the loss function that computes the loss, which measures the degree of deviation of the output code token from the ground-truth code token.

[0087] Figure 2 The elements and features described in the various embodiments are compatible and can be combined with the elements and features in other figures described herein.

[0088] Figure 3 is according to at least one embodiment of Figure 2 a block diagram of the system described Figure 3 Illustrated using two levels of a code hierarchy. The techniques described herein can be applied to code hierarchies with more than two levels. In at least one embodiment, the representation tensor 247 includes a representation of the input class 302. In at least one embodiment, the input class 302 is previously generated code for a code generation task. In at least one embodiment, the neural network 101 is used to generate the next token for a target software program given the input class 302 and an input (e.g., specification 103). In at least one embodiment, the input class 302 includes two functions 303 and 305.

[0089] In at least one embodiment, the input preprocessor 204 splits the original code of the input class 302 into two blocks 349, each block representing a function 303 and 305. In at least one embodiment, the input preprocessor also splits the original code of each function into a plurality of code tokens 353. In at least one embodiment, for each function 303 and 305, the input preprocessor generates a summary data block 351. In at least one embodiment, the block summary data 351 of each function includes summary information of the function, such as the name of the function, the text description of the function, and other available information. In at least one embodiment, the input preprocessor 204 further splits the block summary 351 into carrier tokens 355. In at least one embodiment, the carrier tokens 355 include two sets of carrier tokens, each set of carrier tokens for functions 303 and 305. In at least one embodiment, each of the code tokens 353 and the carrier tokens 355 is represented by a vector.

[0090] In at least one embodiment, the transformer decoder 359 performs a self-attention operation on different sets of carrier tokens in the carrier tokens 355, performs a cross-attention operation between the carrier tokens 355 and the external memory 240, and performs an FFN operation on the output of the cross-attention operation. In at least one embodiment, the transformer decoder 359 performs a cross-attention operation once for each set of carrier tokens in the carrier tokens 355 and the external memory 240. In at least one embodiment, the transformer decoder 359 performs a cross-attention operation once for all the carrier tokens in the carrier tokens 355 and the external memory 240.

[0091] In at least one embodiment, the transformer decoder 359 restores the original number of carrier tokens in the carrier tokens 355 after the self-attention operation and the FNN operation, and outputs a tensor that is appended to the code tokens 353 to form a concatenated token 360.

[0092] In at least one embodiment, the transformer decoder 359 passes the concatenated token 360 to the next transformer decoder 361, which further performs a self-attention operation on the concatenated token 360, a cross-attention operation between the concatenated token 360 and the external memory 240, and an FFN operation on the output of the cross-attention operation. In at least one embodiment, the transformer decoder 359 performs a cross-attention operation once for each set of concatenated tokens in the concatenated token 360 and the external memory 240. In at least one embodiment, the transformer decoder 359 performs a cross-attention operation once for all the tokens in the concatenated token 360 and the external memory 240.

[0093] In at least one embodiment, the carrier token 355 acts as an extension of the code token 353. In at least one embodiment, the self-attention on the link token 360 enables the complete mixing of information at two different levels of the code hierarchy. In at least one embodiment, the self-attention is multi-head self-attention, where the transformer decoder 361 jointly attends to information from different representation spaces to gain insights into the code dependencies in the code 203 from different dimensions (e.g., perspectives). In at least one embodiment, the transformer decoder 361 further performs a multi-layer perceptron (MLP), which is a specific type of FFN with one or more densely connected hidden layers and a non-linear activation function.

[0094] In at least one embodiment, the carrier token 355 provides a summary of the high-level information about each function. In at least one embodiment, the carrier token 355 allows cross-level reasoning between the original code tokens and the high-level function summaries. By concatenating the carrier token 355 with the code token 353, the transmission decoder 361 jointly attends to two levels of the code hierarchy and propagates information between the two levels of the code hierarchy. In at least one embodiment, the carrier token 355 is capable of modeling long-range dependencies across code dependencies at various levels of the code hierarchy (e.g., functions, classes, and namespaces). The carrier token 355 does not have a "flat" attention only to the original tokens, but rather the carrier token 355 provides an anchor that can associate relevant code blocks throughout the code structure. In at least one embodiment, the carrier token 355 simplifies multi-level hierarchical reasoning. By encapsulating the high-level representation in the carrier token 355, the attention block 106 traverses multiple levels of the code hierarchy without having to directly learn these high-level relationships from the original code tokens. In at least one embodiment, the carrier token allows the integration of external knowledge through interaction with the external memory 240 via the cross-attention operations performed in the transformer decoders 359 and 361.

[0095] In at least one embodiment, the output from the transformer decoder 361 is the concatenation token 363, which is a tensor. In at least one embodiment, these concatenation tokens 363 are split into two tensors: one for the code tokens 365 and the other for the carrier tokens 367. Subsequently, in at least one embodiment, these two tensors are forwarded to another attention block (not shown). In at least one embodiment, splitting the concatenation tokens 363 into two different tensors allows the subsequent attention block to perform self-attention operations within information of the same category. In at least one embodiment, this self-attention operation is performed on the carrier tokens 367 in the next attention block. In at least one embodiment, focusing self-attention on information of a single category, such as the carrier tokens 367, can minimize interference from irrelevant data, thereby enhancing the ability of the neural network 101 to accurately identify code dependencies.

[0096] In at least one embodiment, while applying self-attention separately to each level of information has advantages, such as reducing interference from irrelevant data, focusing attention on the carrier tokens 355 and the code tokens 353 as a combination enables the attention block 106 to integrate context from various levels of abstraction. For example, this approach helps in understanding how a particular function fits into the broader scope of the class or module to which the function belongs.

[0097] In at least one embodiment, when the combination and splitting within each attention block reach a predetermined count, the neural network 101 outputs the carrier tokens 370 and the code tokens 369. In at least one embodiment, the code tokens 369 include one or more tokens to be generated as possible subsequent tokens, and the carrier tokens 370 are annotations for the subsequent tokens. Meanwhile, in at least one embodiment, the carrier tokens 370 act as an annotation or commentary on these upcoming tokens. Thus, by combining the code tokens 369 with the carrier tokens 370 (denoted as merge 371), the resulting output includes the next tokens 372 accompanied by their respective annotations. This output forms part of a software program and is consistent with the code dependencies outlined, for example, in a specification document.

[0098] Figure 3 The elements and features described in various embodiments are compatible and can be combined with the elements and features in other figures described herein.

[0099] Figure 4FIG. is a block diagram showing an attention block chain 408 for identifying code dependencies in previously generated code according to at least one embodiment. In at least one embodiment, the representation tensor 402 includes code dependencies between a module 403, a class 404 within the module 403, a function 405 within the class 404, and a line of code 406 within the function 405. In at least one embodiment, during inference, the code dependencies are dependencies in previously generated code that is part of a target software program. In at least one embodiment, the attention block chain 408 attends to these code dependencies during multiple iterations, with each iteration corresponding to an attention block, such as attention block 106.

[0100] In at least one embodiment, during training, the previously generated code is existing code, where one or more lines of code are hidden or masked from the previously generated code. In at least one embodiment, the hidden or masked code can be used as a ground truth for calculating a loss.

[0101] In at least one embodiment, the attention block chain 408 includes a plurality of attention blocks, each attention block being similar to attention block 106. In at least one embodiment, each row of attention blocks belongs to two adjacent levels of a code hierarchy. In at least one embodiment, for each pair of adjacent levels of the code hierarchy, the neural network 101 performs at least one self-attention operation on the lower-level code tokens and at least one self-attention operation on the higher-level carrier tokens. In at least one embodiment, the neural network performs at least one cross-attention operation between the lower-level code tokens and the higher-level carrier tokens. In at least one embodiment, the neural network 101 performs at least one self-attention operation on the code tokens at the lower level and at least one self-attention operation on the code tokens at the higher level. In at least one embodiment, the neural network performs at least one cross-attention operation between the code tokens at the lower level and the code tokens at the higher level. In at least one embodiment, the neural network 101 performs at least one self-attention operation on the carrier tokens at the lower level and at least one self-attention operation on the carrier tokens at the higher level. In at least one embodiment, the neural network performs at least one cross-attention operation between the carrier tokens at the lower level and the carrier tokens at the higher level.

[0102] In at least one embodiment, a row of attention blocks including attention blocks 441, 447, and 453 corresponds to the function level and the code level of information, which has been described in Figure 3As described in. In at least one embodiment, a row of attention blocks including attention blocks 407, 411, and 417 corresponds to the module level and class level of information, where the code tag can be the name of a class in the module and its signature (e.g., parameters), and the carrier tag can be the name of the module and the text description of the module. In at least one embodiment, for example, the signature of the class can be the signature of the constructor of the class in the Java programming language. In at least one embodiment, a row of attention blocks including attention blocks 423, 429, and 435 corresponds to the class level and function level of information, where the code tag can be the name and signature of a function, and the carrier tag can be the name of the class containing the function and the text description of the class.

[0103] Figure 4 The elements and features described in various embodiments herein are compatible and can be combined with the elements and features in other figures described herein.

[0104] Figure 5 Shows the detailed calculation steps in the cross-attention module according to at least one embodiment. In at least one embodiment, the number m of tags 501 in the memory M (e.g., external knowledge) is significantly greater than the number n of tags 503 in the query X. In at least one embodiment, the tags in the memory M are multimodal and can be any one of text tags, audio frames, image patches, or video frames. In at least one embodiment, the multimodal memory M is included in the cross-attention calculation to enhance the autoregressive code generation ability of the neural network 101.

[0105] In at least one embodiment, X is the code generated so far or the code in the training dataset, depending on Figure 5 whether it is a process during training or a process during inference. In at least one embodiment, each tag in the code X is represented by a vector. In at least one embodiment, the external knowledge M is retrieved from a common code library and a private code library. In at least one embodiment, each tag in M is also represented by a vector. In at least one embodiment, the cross-attention module 208 uses the calculation steps described herein to integrate the external memory M and the query X to provide additional context to the query X. In at least one embodiment, the tags in the external memory M and the query X are both converted into vectors through an embedding layer, which is indicated by the "embedding size d".

[0106] In at least one embodiment, vectors derived from tokens in an external memory M and a query X are multiplied by weight matrices 505, 507, and 509 to respectively produce a matrix 511 for Q (query), a matrix 513 for K (key), and a matrix 515 for values. In at least one embodiment, matrix Q 511 is multiplied by the transpose of matrix K 513, and then the Softmax function 518 is applied to the result of the multiplication to produce an attention matrix 517. Then the Softmax function 518 is applied to the attention matrix 517 to convert the raw scores therein to probabilities that sum to 1. In at least one embodiment, the output probabilities are used to create a new matrix 519. In at least one embodiment, matrix 519 is then multiplied by matrix V 515 to produce a matrix Z 521, which is a contextually relevant weighted sum. In at least one embodiment, matrix Z 521 includes vectors of tokens having different values in X, which includes additional information from the external memory M. In at least one embodiment, after the operations described in Figure 5 the query X (e.g., previously generated code in a code generation task) has obtained additional context, which enables a neural network (e.g., neural network 101) to better generate more relevant new code.

[0107] Figure 5 The elements and features described in the various embodiments in

[0108] Figure 6 FIG. 600 illustrates an example process of using one or more neural networks to generate one or more software programs having one or more software program dependencies indicated using information indicative of the one or more software program dependencies, according to at least one embodiment.

[0109] In at least one embodiment, one or more steps in process 600 are otherwise combined, executed in series, and / or executed in parallel. In at least one embodiment, the steps in process 600 may be reordered or recombined in various ways, unless specifically stated or logically required. In at least one embodiment, some or all of process 600 (or any other process described herein, or its variations and / or combinations) is executed under the control of one or more computer systems configured with computer-executable instructions and is implemented as code (e.g., computer-executable instructions, one or more computer programs, or one or more applications) to be executed jointly on one or more processors, by hardware, software, or a combination thereof. In at least one embodiment, the code is stored on a computer-readable storage medium in the form of a computer program that includes a plurality of computer-readable instructions executable by one or more processors. In at least one embodiment, the computer-readable storage medium is a non-transitory computer-readable medium. In at least one embodiment, at least some of the computer-readable instructions executable to perform process 600 are not stored using only transient signals (e.g., propagating transient electrical or electromagnetic transmissions). In at least one embodiment, the non-transitory computer-readable medium does not necessarily include non-transitory data storage circuits (e.g., buffers, caches, and queues) within a transient signal transceiver. In at least one embodiment, process 600 is at least partially executed on a computer system (e.g., the computer systems described elsewhere in this disclosure). In at least one embodiment, logic (e.g., hardware, software, or a combination of hardware and software) performs process 600.

[0110] In at least one embodiment, the processor (e.g., Figure 1 processor 120 in ) that executes process 600 receives, in operation 601, an input specifying code dependencies to generate a software program. In at least one embodiment, the input is a document describing the specification requirements of the software program to be generated. In at least one embodiment, the input is received by one or more neural networks, as Figures 1 to 5 shown. In at least one embodiment, the input corresponds to Figure 1 specification document 103 in. In at least one embodiment, the code dependencies are the dependencies between namespaces, modules within the namespaces, classes within the modules, functions within the classes, and lines of code within the functions.

[0111] In at least one embodiment, process 600 further includes generating, in operation 603, code segments that conform to the code dependencies. In at least one embodiment, the input corresponds to Figure 3 input class 302 in. In at least one embodiment, the operation is performed by Figures 1 to 5 one or more neural networks described in.

[0112] In at least one embodiment, process 600 further includes: creating a representation tensor from the generated code segments in operation 605. In at least one embodiment, the representation tensor includes the encoded tokens in the generated code segments and the encoded tokens of the input specifying code dependencies. In at least one embodiment, the representation tensor is created by a separate program (e.g., input preprocessor 204) or by Figures 1 to 5 one or more neural networks as described in Figures 1 to 5 one or more of those described in

[0113] In at least one embodiment, process 600 further includes generating code blocks and block summaries for each pair of adjacent levels within the code hierarchy of the code segments in operation 607. In at least one embodiment, this operation is described in Figure 3 where code level and function level information is used for illustration.

[0114] In at least one embodiment, process 600 further includes performing self-attention and cross-attention on the tokenized code blocks and tokenized block summaries in operation 609. In at least one embodiment, this operation corresponds to the operation performed in attention block 106 and repeated a predetermined number of times in attention chain 408.

[0115] In at least one embodiment, process 600 further includes generating one or more next tokens as part of the software program in operation 611. In at least one embodiment, this operation corresponds to the operation performed in attention block 106.

[0116] Figure 6 The elements and features described in the various embodiments in

[0117] Logic

[0118] Figure 7A illustrates logic 715, which, as described elsewhere herein, can be used in one or more devices to perform operations such as those discussed herein according to at least one embodiment. In at least one embodiment, logic 715 is used to perform inference and / or training operations associated with one or more embodiments. In at least one embodiment, logic 715 is inference and / or training logic. In connection with the following Figure 7A and / or Figure 7BProvide details regarding logic 715. In at least one embodiment, logic refers to any combination of software logic, hardware logic, and / or firmware logic for providing the functions or operations described herein, where the logic can be embodied, jointly or separately, as circuitry that forms part of a larger system (e.g., an integrated circuit (IC), a system on a chip (SoC), or one or more processors (e.g., a CPU, a GPU)).

[0119] In at least one embodiment, logic 715 can include, but is not limited to, code and / or data storage 701 for storing forward and / or output weights and / or input / output data, and / or other parameters for configuring neurons or layers of a neural network that is trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, logic 715 can include or be coupled to code and / or data storage 701 for storing graph code or other software to control timing and / or sequence, where weight and / or other parameter information is loaded to configure the logic, which includes integer and / or floating-point units (collectively referred to as arithmetic logic units (ALUs)). In at least one embodiment, code (such as graph code) loads weight or other parameter information into the processor ALU based on the architecture of the neural network to which the code corresponds. In at least one embodiment, code and / or data storage 701 stores the weight parameters and / or input / output data of each layer of the neural network that is used in combination with one or more embodiments during forward propagation of input / output data and / or weight parameters during training and / or inference using aspects of one or more embodiments. In at least one embodiment, any portion of code and / or data storage 701 can be included within other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory.

[0120] In at least one embodiment, any portion of code and / or data storage 701 can be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 701 can be cache memory, dynamic random access memory (“DRAM”), static random access memory (“SRAM”), non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 701 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0121] In at least one embodiment, logic 715 may include, but is not limited to, code and / or data storage 705 for storing backward and / or output weights and / or input / output data corresponding to neurons or layers of a neural network that are trained and / or used for inference in aspects of one or more embodiments. In at least one embodiment, during training and / or inference using aspects of one or more embodiments, code and / or data storage 705 stores the weight parameters and / or input / output data of each layer of the neural network that is trained or used in conjunction with one or more embodiments during the backpropagation of the input / output data and / or weight parameters. In at least one embodiment, logic 715 may include or be coupled to code and / or data storage 705 for storing graph code or other software to control timing and / or sequencing, where weights and / or other parameter information is loaded to configure the logic, which includes integer and / or floating-point units (collectively arithmetic logic units (ALUs))

[0122] In at least one embodiment, the code (such as graph code) causes weights or other parameter information to be loaded into the processor ALU based on the architecture of the neural network corresponding to the code. In at least one embodiment, any portion of code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory. In at least one embodiment, any portion of code and / or data storage 705 may be internal or external to one or more processors or other hardware logic devices or circuits. In at least one embodiment, code and / or data storage 705 may be cache memory, DRAM, SRAM, non-volatile memory (such as flash memory), or other storage. In at least one embodiment, the choice of whether code and / or data storage 705 is internal or external to the processor, e.g., including DRAM, SRAM, flash memory, or some other storage type, may depend on the available on-chip versus off-chip storage, the latency requirements of the training and / or inference functions being performed, the batch size of the data used in the inference and / or training of the neural network, or some combination of these factors.

[0123] In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be separate storage structures. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be the same storage structure. In at least one embodiment, code and / or data storage 701 and code and / or data storage 705 may be partially combined and partially separated. In at least one embodiment, any portion of code and / or data storage 701 and code and / or data storage 705 may be included with other on-chip or off-chip data storage, including the processor's L1, L2, or L3 cache or system memory.

[0124] In at least one embodiment, the logic 715 may include, but is not limited to, one or more arithmetic logic units (“ALUs”) 710 (including integer and / or floating point units) for performing logical and / or mathematical operations based at least in part on training and / or inference code (e.g., graph code) or as directed thereby, the result of which may produce activations (e.g., output values from layers or neurons within a neural network) stored in the activation store 720, which are a function of input / output and / or weight parameter data stored in the code and / or data store 701 and / or the code and / or data store 705. In at least one embodiment, the activations stored in the activation store 720 are generated according to linear algebra and / or matrix-based mathematics performed by the ALU 710 in response to executing instructions or other code, where the weight values stored in the code and / or data store 705 and / or the code and / or data store 701 are used as operands along with other values such as bias values, gradient information, momentum values, or other parameters or hyperparameters, any or all of which may be stored in the code and / or data store 705 or the code and / or data store 701 or other on-chip or off-chip storage.

[0125] In at least one embodiment, one or more ALUs 710 are included in one or more processors or other hardware logic devices or circuits, while in another embodiment, one or more ALUs 710 may be external to the processors or other hardware logic devices or circuits that use them (e.g., coprocessors). In at least one embodiment, the ALU 710 may be included within the execution units of a processor or otherwise included in an ALU bank accessible by the execution units of a processor, which execution units of the processor may be within the same processor or distributed among different processors of different types (e.g., central processing units, graphics processing units, fixed function units, etc.). In at least one embodiment, the code and / or data store 701, the code and / or data store 705, and the activation store 720 may share a processor or other hardware logic device or circuit, while in another embodiment, they may be in different processors or other hardware logic devices or circuits or some combination of the same and different processors or other hardware logic devices or circuits. In at least one embodiment, any portion of the activation store 720 may be included with other on-chip or off-chip data storage, including the L1, L2, or L3 cache of the processor or system memory. Additionally, the inference and / or training code may be stored with other code accessible by the processor or other hardware logic or circuits and may be fetched and / or processed using the fetch, decode, schedule, execute, retire, and / or other logic circuits of the processor.

[0126] In at least one embodiment, the activation store 720 can be a cache memory, DRAM, SRAM, non-volatile memory (e.g., flash memory), or other storage. In at least one embodiment, the activation store 720 can be wholly or partially within or external to one or more processors or other logic circuits. In at least one embodiment, the choice of whether the activation store 720 is internal or external to the processor, e.g., or includes DRAM, SRAM, flash memory, or some other storage type, can depend on the on-chip versus off-chip available storage, the latency requirements for performing training and / or inference functions, the batch size of the data used in inferring and / or training a neural network, or some combination of these factors.

[0127] In at least one embodiment, Figure 7A the logic 715 shown in can be used in conjunction with an application specific integrated circuit (“ASIC”), such as the processing unit from Google, TM the inference processing unit (IPU) from Graphcore or the Figure 7A (e.g., “Lake Crest”) processor from Intel Corporation. In at least one embodiment,

[0128] Figure 7B FIG. shows the logic 715 according to at least one embodiment. In at least one embodiment, the logic 715 is inference and / or training logic. In at least one embodiment, the logic 715 can include, but is not limited to, hardware logic where computing resources are dedicated or otherwise exclusively used with weight values or other information corresponding to one or more layers of neurons within a neural network. In at least one embodiment, Figure 7B the logic 715 shown in can be used in conjunction with an application specific integrated circuit (ASIC), such as the processing unit from Google, the TM inference processing unit (IPU) from Graphcore or the Figure 7BThe logic 715 shown in the figure can be used in combination with central processing unit (CPU) hardware, graphics processing unit (GPU) hardware, or other hardware (such as field programmable gate array (FPGA)). In at least one embodiment, the logic 715 includes, but is not limited to, code and / or data storage 701 and code and / or data storage 705, which can be used to store code (such as graph code), weight values, and / or other information, including bias values, gradient information, momentum values, and / or other parameter or hyperparameter information. In Figure 7B In at least one embodiment shown in the figure, each of the code and / or data storage 701 and the code and / or data storage 705 is respectively associated with dedicated computing resources (such as computing hardware 702 and computing hardware 706). In at least one embodiment, each of the computing hardware 702 and the computing hardware 706 includes one or more ALUs, which respectively perform mathematical functions (such as linear algebra functions) only on the information stored in the code and / or data storage 701 and the code and / or data storage 705, and the results are stored in the activation storage 720.

[0129] In at least one embodiment, each of the code and / or data storage 701 and 705 and the corresponding computing hardware 702 and 706 respectively corresponds to different layers of a neural network, such that the activation obtained from one storage / computation pair 701 / 702 of the code and / or data storage 701 and the computing hardware 702 is provided as the input to the next storage / computation pair 705 / 706 of the code and / or data storage 705 and the computing hardware 706, in order to reflect the conceptual organization of the neural network. In at least one embodiment, each storage / computation pair 701 / 702 and 705 / 706 can correspond to more than one neural network layer. In at least one embodiment, additional storage / computation pairs (not shown) can be included in the logic 715 after or in parallel with the storage / computation pairs 701 / 702 and 705 / 706.

[0130] Neural network training and deployment

[0131] Figure 8Illustrates the training and deployment of a deep neural network according to at least one embodiment. In at least one embodiment, a training dataset 802 is used to train an untrained neural network 806. In at least one embodiment, the training framework 804 is the PyTorch framework, while in other embodiments, the training framework 804 is TensorFlow, Boost, Caffe, Microsoft Cognitive Toolkit / CNTK, MXNet, Chainer, Keras, Deeplearning4j, or other training frameworks. In at least one embodiment, the training framework 804 trains the untrained neural network 806 and allows it to be trained using the processing resources described herein to generate a trained neural network 808. In at least one embodiment, the weights can be selected randomly or pre-trained using a deep belief network. In at least one embodiment, the training can be performed in a supervised, partially supervised, or unsupervised manner.

[0132] In at least one embodiment, supervised learning is used to train the untrained neural network 806, where the training dataset 802 includes inputs paired with desired outputs for the inputs, or where the training dataset 802 includes inputs with known outputs and the outputs of the neural network 806 are manually graded. In at least one embodiment, the untrained neural network 806 is trained in a supervised manner, processes the inputs from the training dataset 802, and compares the resulting outputs with a set of desired or wanted outputs. In at least one embodiment, the error is then backpropagated through the untrained neural network 806. In at least one embodiment, the training framework 804 adjusts the weights that control the untrained neural network 806. In at least one embodiment, the training framework 804 includes tools for monitoring the degree to which the untrained neural network 806 converges to a model (such as the trained neural network 808) suitable for generating correct answers (such as result 814) based on input data (such as new dataset 812). In at least one embodiment, the training framework 804 repeatedly trains the untrained neural network 806 while adjusting the weights to refine the output of the untrained neural network 806 using a loss function and an adjustment algorithm (such as stochastic gradient descent). In at least one embodiment, the training framework 804 trains the untrained neural network 806 until the untrained neural network 806 reaches a desired accuracy. In at least one embodiment, the trained neural network 808 can then be deployed to implement any number of machine learning operations.

[0133] In at least one embodiment, unsupervised learning is used to train an untrained neural network 806, where the untrained neural network 806 attempts to train itself using unlabeled data. In at least one embodiment, the unsupervised learning training dataset 802 will include input data without any associated output data or "ground truth" data. In at least one embodiment, the untrained neural network 806 can learn groupings within the training dataset 802 and can determine how individual inputs relate to the untrained dataset 802. In at least one embodiment, unsupervised training can be used to generate a self-organizing map in the trained neural network 808, which can perform operations useful for reducing the dimensionality of a new dataset 812. In at least one embodiment, unsupervised training can also be used to perform anomaly detection, which allows identification of data points in the new dataset 812 that deviate from the normal pattern of the new dataset 812.

[0134] In at least one embodiment, semi-supervised learning can be used, which is a technique in which a mixture of labeled and unlabeled data is included in the training dataset 802. In at least one embodiment, the training framework 804 can be used to perform incremental learning, such as through transfer learning techniques. In at least one embodiment, incremental learning enables the trained neural network 808 to adapt to a new dataset 812 without forgetting the knowledge injected into the trained neural network 808 during initial training.

[0135] In at least one embodiment, the training framework 804 is a framework that processes in conjunction with a software development kit such as the OpenVINO (Open Visual Inference and Neural Network Optimization) toolkit. In at least one embodiment, the OpenVINO toolkit is a toolkit developed, for example, by Intel Corporation of Santa Clara, California. In at least one embodiment, OpenVINO includes logic 715 or uses logic 715 to perform the operations described herein. In at least one embodiment, a SoC, integrated circuit, or processor uses OpenVINO to perform the operations described herein.

[0136] In at least one embodiment, OpenVINO is a toolkit for facilitating the development of applications (especially neural network applications) for various tasks and operations such as human vision simulation, speech recognition, natural language processing, recommendation systems, and / or variants thereof. In at least one embodiment, OpenVINO supports neural networks such as convolutional neural networks (CNNs), recurrent neural networks, and / or attention-based neural networks, and / or various other neural network models. In at least one embodiment, OpenVINO supports various software libraries such as OpenCV, OpenCL, and / or variants thereof.

[0137] In at least one embodiment, OpenVINO supports neural network models for various tasks and operations such as classification, segmentation, object detection, face recognition, speech recognition, pose estimation (e.g., of a person and / or an object), monocular depth estimation, inpainting, style transfer, motion recognition, coloring, and / or variants thereof.

[0138] In at least one embodiment, OpenVINO includes one or more software tools and / or modules for model optimization, also referred to as the Model Optimizer. In at least one embodiment, the Model Optimizer is a command-line tool that facilitates the conversion between the training and deployment of neural network models. In at least one embodiment, the Model Optimizer optimizes neural network models for execution on various devices and / or processing units such as GPUs, CPUs, PPUs, GPGPUs, and / or variants thereof. In at least one embodiment, the Model Optimizer generates an internal representation of the model and optimizes the model to generate an intermediate representation. In at least one embodiment, the Model Optimizer reduces the number of layers of the model. In at least one embodiment, the Model Optimizer removes layers of the model used for training. In at least one embodiment, the Model Optimizer performs various neural network operations such as modifying the input of the model (e.g., resizing the input of the model), modifying the size of the input of the model (e.g., modifying the batch size of the model), modifying the model structure (e.g., modifying the layers of the model), normalization, standardization, quantization (e.g., converting the weights of the model from a first representation such as floating point to a second representation such as integer), and / or variants thereof.

[0139] In at least one embodiment, OpenVINO includes one or more software libraries for inference, also referred to as the Inference Engine. In at least one embodiment, the Inference Engine is a C++ library or a library in any suitable programming language. In at least one embodiment, the Inference Engine is used to infer input data. In at least one embodiment, the Inference Engine implements various classes to infer input data and generate one or more results. In at least one embodiment, the Inference Engine implements one or more API functions to process the intermediate representation, set the input and / or output format, and / or execute the model on one or more devices.

[0140] In at least one embodiment, OpenVINO provides various capabilities for the heterogeneous execution of one or more neural network models. In at least one embodiment, heterogeneous execution or heterogeneous computing refers to one or more computing processes and / or systems that utilize one or more types of processors and / or cores. In at least one embodiment, OpenVINO provides various software functions to execute programs on one or more devices. In at least one embodiment, OpenVINO provides various software functions to execute programs and / or parts of programs on different devices. In at least one embodiment, OpenVINO provides various software functions, for example, to run a first code portion on a CPU and a second code portion on a GPU and / or FPGA. In at least one embodiment, OpenVINO provides various software functions to execute one or more layers of a neural network on one or more devices (e.g., execute a first set of layers on a first device (e.g., GPU) and a second set of layers on a second device (e.g., CPU)).

[0141] In at least one embodiment, OpenVINO includes various functions similar to those associated with the CUDA programming model, such as various neural network model operations associated with frameworks such as TensorFlow, PyTorch, and / or their variants. In at least one embodiment, one or more CUDA programming model operations are performed using OpenVINO. In at least one embodiment, the various systems, methods, and / or technologies described herein are implemented using OpenVINO.

[0142] Data center

[0143] Figure 9 An exemplary data center 900 is shown in which at least one embodiment can be used. In at least one embodiment, data center 900 includes a data center infrastructure layer 910, a framework layer 920, a software layer 930, and an application layer 940.

[0144] In at least one embodiment, as Figure 9As shown, the data center infrastructure layer 910 may include a resource coordinator 912, grouped computing resources 914, and node computing resources ("node C.R.") 916(1)-916(N), where "N" represents a positive integer (which may be a different integer "N" from the integers used in other figures). In at least one embodiment, the node C.R. 916(1)-916(N) may include, but is not limited to, any number of central processing units ("CPU") or other processors (including accelerators, field programmable gate arrays (FPGAs), graphics processors, etc.), memory storage devices 918(1)-918(N) (such as dynamic read-only memory, solid-state storage, or disk drivers), network input / output ("NW I / O") devices, network switches, virtual machines ("VM"), power modules, and cooling modules, etc. In at least one embodiment, one or more of the node C.R. 916(1)-916(N) may be a server having one or more of the above computing resources.

[0145] In at least one embodiment, the grouped computing resources 914 may include separate groupings of node C.R. housed within one or more racks (not shown), or many racks housed within data centers (also not shown) in various geographical locations. In at least one embodiment, the separate groupings of node C.R. within the grouped computing resources 914 may include grouped computing, network, memory, or storage resources that may be configured or allocated to support one or more workloads. In at least one embodiment, several node C.R. including CPUs or processors may be grouped within one or more racks to provide computing resources to support one or more workloads. In at least one embodiment, one or more racks may also include any number of power modules, cooling modules, and network switches in any combination.

[0146] In at least one embodiment, the resource coordinator 912 may configure or otherwise control one or more of the node C.R. 916(1)-916(N) and / or the grouped computing resources 914. In at least one embodiment, the resource coordinator 912 may include a software design infrastructure ("SDI") management entity for the data center 900. In at least one embodiment, the resource coordinator 912 may include hardware, software, or some combination thereof.

[0147] In at least one embodiment, as Figure 9As shown, the framework layer 920 includes a job scheduler 922, a configuration manager 924, a resource manager 926, and a distributed file system 928. In at least one embodiment, the framework layer 920 may include a framework that supports software 932 of the software layer 930 and / or one or more applications 942 of the application layer 940. In at least one embodiment, the software 932 or the application 942 may respectively include web-based service software or applications, such as service software or applications provided by Amazon Web Services, Google Cloud, and Microsoft Azure. In at least one embodiment, the framework layer 920 may be, but is not limited to, a type of free and open-source software web application framework, such as Apache Spark that can utilize the distributed file system 928 for large-scale data processing (e.g., "big data"). TM (hereinafter referred to as "Spark"). In at least one embodiment, the job scheduler 922 may include a Spark driver for facilitating the scheduling of workloads supported by the various layers of the data center 900. In at least one embodiment, the configuration manager 924 may be capable of configuring different layers, such as the software layer 930 and the framework layer 920 including Spark and the distributed file system 928 for supporting large-scale data processing. In at least one embodiment, the resource manager 926 may be capable of managing the clustered or grouped computing resources mapped to or allocated for supporting the distributed file system 928 and the job scheduler 922. In at least one embodiment, the clustered or grouped computing resources may include the grouped computing resources 914 at the data center infrastructure layer 910. In at least one embodiment, the resource manager 926 may coordinate with the resource coordinator 912 to manage these mapped or allocated computing resources.

[0148] In at least one embodiment, the software 932 included in the software layer 930 may include software used by at least respective parts of the nodes C.R. 916(1)-916(N), the grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of software may include, but are not limited to, Internet web search software, email virus scanning software, database software, and streaming video content software.

[0149] In at least one embodiment, one or more applications 942 included in the application layer 940 may include one or more types of applications used by at least respective portions of nodes C.R. 916(1)-916(N), grouped computing resources 914, and / or the distributed file system 928 of the framework layer 920. In at least one embodiment, one or more types of applications may include, but are not limited to, any number of genomics applications, cognitive computing, applications, and machine learning applications, including training or inference software, machine learning framework software (such as PyTorch, TensorFlow, Caffe, etc.), or other machine learning applications used in conjunction with one or more embodiments.

[0150] In at least one embodiment, any one of the configuration manager 924, the resource manager 926, and the resource coordinator 912 may implement any number and type of self-modifying actions based on any amount and type of data obtained in any technically feasible manner. In at least one embodiment, the self-modifying actions may relieve the data center operator of the data center 900 from making potentially bad configuration decisions and may avoid underutilization and / or poorly performing portions of the data center.

[0151] In at least one embodiment, the data center 900 may include tools, services, software, or other resources for training one or more machine learning models or using one or more machine learning models to predict or infer information according to one or more embodiments described herein. For example, in at least one embodiment, a machine learning model may be trained by calculating weight parameters according to a neural network architecture by using the software and computing resources described above with respect to the data center 900. In at least one embodiment, by using the weight parameters calculated by one or more training techniques described herein, the resources described above with respect to the data center 900 may be used to infer or predict information using the trained machine learning model corresponding to one or more neural networks.

[0152] In at least one embodiment, the data center may use a CPU, an application-specific integrated circuit (ASIC), a GPU, an FPGA, or other hardware to perform training and / or inference using the above resources. In addition, one or more of the above software and / or hardware resources may be configured as a service for allowing a user to train or perform information inference, such as image recognition, speech recognition, or other artificial intelligence services.

[0153] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in conjunction with Figure 7A and / or Figure 7BProvide details regarding logic 715. In at least one embodiment, logic 715 may be used in data center 900 for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0154] In at least one embodiment, regarding Figures 7A to 9 the at least one component shown or described is used to implement in connection with Figures 1 to 6 the techniques and / or functions described. In at least one embodiment, logic 915 performs one or more operations involving using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in connection with Figures 1 to 6 the description herein, and as described herein.

[0155] Autonomous vehicle

[0156] Figure 10A An example of an autonomous vehicle 1000 is shown in accordance with at least one embodiment. In at least one embodiment, autonomous vehicle 1000 (alternatively referred to herein as "vehicle 1000") may be, but is not limited to, a passenger vehicle such as a car, truck, bus, and / or another type of vehicle that accommodates one or more passengers. In at least one embodiment, vehicle 1000 may be a semi-trailer truck for hauling cargo. In at least one embodiment, vehicle 1000 may be an airplane, a robotic vehicle, or another type of vehicle.

[0157] Autonomous vehicles may be described according to automation levels defined by the National Highway Traffic Safety Administration ("NHTSA") under the United States Department of Transportation and the Society of Automotive Engineers ("SAE") in "Taxonomy and Definitions for Terms Related to Driving Automation Systems for On-Road Motor Vehicles" (e.g., Standard No. J3016-201806, issued on June 15, 2018, Standard No. J3016-201609, issued on September 30, 2016, and previous and future versions of this standard). In at least one embodiment, vehicle 1000 may be capable of having functionality according to one or more of Levels 1 through 5 of the autonomous driving levels. For example, in at least one embodiment, vehicle 1000 may be capable of having conditional automation (Level 3), highly automated (Level 4), and / or fully automated (Level 5), depending on the embodiment.

[0158] In at least one embodiment, vehicle 1000 may include, but is not limited to, components such as a chassis, a body, wheels (e.g., 2, 4, 6, 8, 18, etc.), tires, axles, and other components of the vehicle. In at least one embodiment, vehicle 1000 may include, but is not limited to, a propulsion system 1050, such as an internal combustion engine, a hybrid device, a fully electric motor, and / or another type of propulsion system. In at least one embodiment, propulsion system 1050 may be connected to a driveline of vehicle 1000, which may include, but is not limited to, a transmission for enabling propulsion of vehicle 1000. In at least one embodiment, propulsion system 1050 may be controlled in response to receiving a signal from a throttle / accelerator 1052.

[0159] In at least one embodiment, when propulsion system 1050 is operating (e.g., when vehicle 1000 is in motion), a steering system 1054 (which may include, but is not limited to, a steering wheel) is used to steer vehicle 1000 (e.g., along a desired path or route). In at least one embodiment, steering system 1054 may receive a signal from a steering actuator 1056. In at least one embodiment, for fully automated (level 5) functionality, the steering wheel may be optional. In at least one embodiment, a brake sensor system 1046 may be used to operate vehicle brakes in response to receiving a signal from a brake actuator 1048 and / or a brake sensor.

[0160] In at least one embodiment, one or more controllers 1036, which may include, but is not limited to, one or more system-on-chips (“SoC”) ( Figure 10A(not shown) and / or a graphics processing unit (“GPU”) to provide signals (e.g., representative of commands) to one or more components and / or systems of the vehicle 1000. For example, in at least one embodiment, one or more controllers 1036 may send signals to operate vehicle brakes via a brake actuator 1048, operate a steering system 1054 via one or more steering actuators 1056, and operate a propulsion system 1050 via one or more throttle / accelerators 1052. In at least one embodiment, one or more controllers 1036 may include one or more on-vehicle (e.g., integrated) computing devices that process sensor signals and output operation commands (e.g., signals representative of commands) to effect autonomous driving and / or assist a human driver in driving the vehicle 1000. In at least one embodiment, one or more controllers 1036 may include a first controller for autonomous driving functions, a second controller for functional safety functions, a third controller for artificial intelligence functions (e.g., computer vision), a fourth controller for infotainment functions, a fifth controller for redundancy in emergency situations, and / or other controllers. In at least one embodiment, a single controller may process two or more of the above functions, and two or more controllers may process a single function and / or any combination thereof.

[0161] In at least one embodiment, one or more controllers 1036 provide signals for controlling one or more components and / or systems of the vehicle 1000 in response to sensor data received from one or more sensors (e.g., sensor inputs). In at least one embodiment, sensor data may be received from, for example but not limited to, the following sensors: one or more Global Navigation Satellite System (“GNSS”) sensors 1058 (e.g., one or more Global Positioning System sensors), one or more RADAR sensors 1060, one or more ultrasonic sensors 1062, one or more LIDAR sensors 1064, one or more Inertial Measurement Unit (IMU) sensors 1066 (e.g., one or more accelerometers, one or more gyroscopes, one or more magnetic compasses, one or more magnetometers, etc.), one or more microphones 1096, one or more stereo cameras 1068, one or more wide-angle cameras 1070 (e.g., fisheye cameras), one or more infrared cameras 1072, one or more surround cameras 1074 (e.g., 360-degree cameras), a remote camera ( Figure 10A (not shown), a mid-range camera ( Figure 10A(not shown), one or more speed sensors 1044 (e.g., for measuring the speed of vehicle 1000), one or more vibration sensors 1042, one or more steering sensors 1040, one or more braking sensors (e.g., as part of a braking sensor system 1046), and / or other sensor types.

[0162] In at least one embodiment, one or more controllers 1036 may receive inputs (e.g., represented by input data) from the instrument panel 1032 of vehicle 1000 and provide outputs (e.g., represented by output data, display data, etc.) via a human-machine interface (“HMI”) display 1034, a sound signaler, a speaker, and / or via other components of vehicle 1000. In at least one embodiment, the output may include information such as vehicle speed, speed, time, map data (e.g., high-definition map ( Figure 10A (not shown), location data (e.g., the location of vehicle 1000, e.g., on a map), direction, the locations of other vehicles (e.g., occupancy grids), information about objects, and the status of objects sensed by one or more controllers 1036, etc. For example, in at least one embodiment, the HMI display 1034 may display information about the presence of one or more objects (e.g., road signs, warning signs, traffic signal changes, etc.) and / or information about driving maneuvers that the vehicle has made, is making, or will make (e.g., changing lanes now, reaching exit 34B in two miles, etc.).

[0163] In at least one embodiment, vehicle 1000 further includes a network interface 1024, which may communicate via one or more networks using one or more wireless antennas 1026 and / or one or more modems. For example, in at least one embodiment, the network interface 1024 may be capable of communicating via Long Term Evolution (“LTE”), Wideband Code Division Multiple Access (“WCDMA”), Universal Mobile Telecommunications System (“UMTS”), Global System for Mobile Communications (“GSM”), IMT-CDMA Multi-Carrier (“CDMA2000”) networks, etc. In at least one embodiment, one or more wireless antennas 1026 may also enable communication between objects in the environment (e.g., vehicles, mobile devices, etc.) using one or more local area networks (such as Bluetooth, Bluetooth Low Energy (LE), Z-Wave, ZigBee, etc.) and / or one or more low-power wide area networks (“LPWAN”) (such as LoRaWAN, SigFox, etc. protocols).

[0164] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. As described herein in connection with Figure 7A and / or Figure 7BDetails are provided regarding logic 715. In at least one embodiment, logic 715 can be used in vehicle 1000 for performing inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions and / or architectures, or neural network use cases as described herein.

[0165] In at least one embodiment, Figure 10A At least one component shown or described is used to achieve the combination Figures 1 to 6 In at least one embodiment, the wireless antenna 1026 is used to send and / or receive one or more wireless signals for use as input to an efficient neural model, which uses the input indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, such as in combination with Figures 1 to 6 as described, and as herein described.

[0166] Figure 10B According to at least one embodiment, Figure 10A 1000. In at least one embodiment, the cameras and respective fields of view are an example embodiment and are not intended to be limiting. For example, in at least one embodiment, additional and / or alternative cameras may be included and / or the cameras may be located at different locations on the vehicle 1000.

[0167] In at least one embodiment, the camera type for the camera may include, but is not limited to, a digital camera that may be suitable for use with components and / or systems of the vehicle 1000. In at least one embodiment, one or more cameras may operate at an automotive safety integrity level ("ASIL") B and / or other ASILs. In at least one embodiment, the camera type may be capable of having any image capture rate, such as 60 frames per second (fps), 120fps, 240fps, etc., depending on the embodiment. In at least one embodiment, the camera may be capable of using a rolling shutter, a global shutter, other types of shutters, or a combination thereof. In at least one embodiment, the color filter array may include a red transparent transparent transparent ("RCCC") filter array, a red transparent transparent blue ("RCCB") filter array, a red blue green transparent ("RBGC") filter array, a Foveon X3 filter array, a Bayer sensor ("RGGB") filter array, a monochrome sensor filter array, and / or other types of filter arrays. In at least one embodiment, a transparent pixel camera, such as a camera having an RCCC, RCCB, and / or RBGC color filter array, may be used in an effort to improve photosensitivity.

[0168] In at least one embodiment, one or more cameras can be used to perform Advanced Driver Assistance System (“ADAS”) functions (e.g., as part of a redundant or fail-safe design). For example, in at least one embodiment, a multi-functional monocular camera can be installed to provide functions including lane departure warning, traffic sign assistance, and smart headlight control. In at least one embodiment, one or more cameras (e.g., all cameras) can record and provide image data (e.g., video) simultaneously.

[0169] In at least one embodiment, one or more cameras can be mounted in a mounting assembly, such as a custom-designed (three-dimensional (“3D”) printed) assembly, to remove stray light and reflected light from within the vehicle 1000 (e.g., reflected light from the dashboard reflected in the windshield mirror) that may interfere with the camera's image data capture ability. Regarding the rearview mirror mounting assembly, in at least one embodiment, the rearview mirror assembly can be 3D printed customized such that the camera mounting plate matches the shape of the rearview mirror. In at least one embodiment, one or more cameras can be integrated into the rearview mirror. In at least one embodiment, for side cameras, one or more cameras can also be integrated within the four pillars at each corner of the cabin.

[0170] In at least one embodiment, a camera having a field of view of portions of the environment in front of the vehicle 1000 (e.g., a forward camera) can be used for surround view to help identify the forward path and obstacles, and to assist in providing information crucial for generating an occupancy grid and / or determining a preferred vehicle path with the help of one or more controllers 1036 and / or a control SoC. In at least one embodiment, the forward camera can be used to perform many ADAS functions similar to LIDAR, including but not limited to emergency braking, pedestrian detection, and collision avoidance. In at least one embodiment, the forward camera can also be used for ADAS functions and systems, including but not limited to lane departure warning (“LDW”), adaptive cruise control (“ACC”), and / or other functions (such as traffic sign recognition).

[0171] In at least one embodiment, a variety of cameras can be used in a forward configuration, including for example a monocular camera platform including a CMOS (“Complementary Metal Oxide Semiconductor”) color imager. In at least one embodiment, a wide-angle camera 1070 can be used to sense objects entering the view from the periphery (e.g., pedestrians, intersection traffic, or bicycles). Although in Figure 10BOnly one wide - angle camera 1070 is shown, but in other embodiments, any number (including zero) of wide - angle cameras can be on vehicle 1000. In at least one embodiment, any number of long - range cameras 1098 (e.g., tele - stereo camera pairs) can be used for depth - based object detection, especially for objects for which a neural network has not been trained. In at least one embodiment, one or more long - range cameras 1098 can also be used for object detection and classification and basic object tracking.

[0172] In at least one embodiment, any number of stereo cameras 1068 can also be included in a forward configuration. In at least one embodiment, one or more stereo cameras 1068 can include an integrated control unit that includes a scalable processing unit that can provide programmable logic (“FPGA”) and a multi - core microprocessor with a controller area network (“CAN”) or Ethernet interface integrated on a single chip. In at least one embodiment, such a unit can be used to generate a 3D map of the environment of vehicle 1000, including distance estimates for all points in the image. In at least one embodiment, one or more stereo cameras 1068 can include, but are not limited to, a compact stereo vision sensor that can include, but is not limited to, two camera lenses (one on the left and one on the right) and an image processing chip that can measure the distance from vehicle 1000 to a target object and use the generated information (e.g., metadata) to activate autonomous emergency braking and lane departure warning functions. In at least one embodiment, other types of stereo cameras 1068 can be used in addition to or instead of those described herein.

[0173] In at least one embodiment, a camera having a field of view of portions of the environment including the sides of vehicle 1000 (e.g., a side - view camera) can be used for surround - view, which provides information for creating and updating an occupancy grid and generating side - impact collision warnings. For example, in at least one embodiment, surround cameras 1074 (e.g., four surround cameras as Figure 10B shown) can be positioned on vehicle 1000. In at least one embodiment, one or more surround cameras 1074 can include, but are not limited to, any number and combination of wide - angle cameras, one or more fisheye cameras, one or more 360 - degree cameras, and / or similar cameras. For example, in at least one embodiment, four fisheye cameras can be located at the front, rear, and sides of vehicle 1000. In at least one embodiment, vehicle 1000 can use three surround cameras 1074 (e.g., left, right, and rear) and can utilize one or more other cameras (e.g., a forward camera) as a fourth surround - view camera.

[0174] In at least one embodiment, a camera (e.g., a rearview camera) having a field of view that includes portions of the environment behind vehicle 1000 can be used for parking assistance, surround view, rear collision warning, and creating and updating an occupancy grid. In at least one embodiment, a variety of cameras can be used, including but not limited to cameras that are also suitable as front view cameras (e.g., long-range camera 1098 and / or mid-range camera 1076, stereo camera 1068, infrared camera 1072, etc.), as described herein.

[0175] In at least one embodiment, with respect to Figure 10B at least one of the components shown or described is used to implement in combination with Figures 1 to 6 the techniques and / or functions described. In at least one embodiment, wireless antenna 1026 is used to transmit and / or receive one or more wireless signals to be used as inputs to an efficient neural model that uses the inputs indicative of one or more software program dependencies to generate one or more software programs having the one or more software program dependencies indicated, as combined with Figures 1 to 6 described, and as described herein.

[0176] Figure 10C is a block diagram showing an exemplary system architecture of autonomous vehicle 1000 in accordance with at least one embodiment. In at least one embodiment, Figure 10A each of the components, features, and systems of vehicle 1000 in Figure 10C is shown connected via bus 1002. In at least one embodiment, bus 1002 can include but is not limited to a CAN data interface (which may alternatively be referred to herein as the "CAN bus"). In at least one embodiment, CAN can be a network inside vehicle 1000 for assisting in controlling various features and functions of vehicle 1000, such as actuation of brakes, acceleration, braking, steering, windshield wipers, etc. In at least one embodiment, bus 1002 can be configured to have dozens or even hundreds of nodes, each having its own unique identifier (e.g., CAN ID). In at least one embodiment, bus 1002 can be read to find steering wheel angle, ground speed, engine revolutions per minute ("RPM"), button positions, and / or other vehicle state indicators. In at least one embodiment, bus 1002 can be an ASIL B compliant CAN bus.

[0177] In at least one embodiment, in addition to or instead of CAN, FlexRay and / or Ethernet protocols may also be used. In at least one embodiment, there may be any number of buses forming bus 1002, which may include but are not limited to zero or more CAN buses, zero or more FlexRay buses, zero or more Ethernet buses, and / or zero or more other types of buses using different protocols. In at least one embodiment, two or more buses may be used to perform different functions and / or may be used for redundancy. For example, the first bus may be used for collision avoidance functions, and the second bus may be used for actuation control. In at least one embodiment, each bus in bus 1002 may communicate with any component of vehicle 1000, and two or more buses in bus 1002 may communicate with corresponding components. In at least one embodiment, each of any number of system-on-chips (“SoC”) 1004 (e.g., SoC 1004(A) and SoC 1004(B)), each of one or more controllers 1036, and / or each computer in the vehicle may access the same input data (e.g., input from sensors of vehicle 1000) and may be connected to a common bus, such as a CAN bus.

[0178] In at least one embodiment, vehicle 1000 may include one or more controllers 1036, such as those described herein with respect to Figure 10A In at least one embodiment, controller 1036 may be used for a variety of functions. In at least one embodiment, controller 1036 may be coupled to any of the various other components and systems of vehicle 1000 and may be used to control vehicle 1000, the artificial intelligence of vehicle 1000, the infotainment of vehicle 1000, and / or other functions.

[0179] In at least one embodiment, vehicle 1000 may include any number of SoCs 1004. In at least one embodiment, each of the SoCs 1004 may include, but is not limited to, a central processing unit (“one or more CPUs”) 1006, a graphics processing unit (“one or more GPUs”) 1008, one or more processors 1010, one or more caches 1012, one or more accelerators 1014, one or more data stores 1016, and / or other components and features not shown. In at least one embodiment, one or more SoCs 1004 may be used to control vehicle 1000 in a variety of platforms and systems. For example, in at least one embodiment, one or more SoCs 1004 may be combined with a high-definition (“HD”) map 1022 in a system (e.g., the system of vehicle 1000), and the HD map 1022 may obtain map refreshes and / or updates from one or more servers ( Figure 10C not shown in the figure) via network interface 1024.

[0180] In at least one embodiment, one or more CPUs 1006 may include a CPU cluster or CPU complex (alternatively referred to herein as “CCPLEX”). In at least one embodiment, one or more CPUs 1006 may include multiple cores and / or secondary (“L2”) caches. For example, in at least one embodiment, one or more CPUs 1006 may include eight cores in a coherent multi-processor configuration. In at least one embodiment, one or more CPUs 1006 may include four dual-core clusters, each of which has a dedicated L2 cache (e.g., 2 megabytes (MB) L2 cache). In at least one embodiment, one or more CPUs 1006 (e.g., CCPLEX) may be configured to support simultaneous cluster operations, which enables any combination of the clusters of one or more CPUs 1006 to be active at any given time.

[0181] In at least one embodiment, one or more CPUs 1006 may implement power management functions, which include but are not limited to one or more of the following features: automatically clock-gating individual hardware blocks during idle to save dynamic power; gating each core clock when the core is not actively executing instructions due to executing a wait-for-interrupt ("WFI") / wait-for-event ("WFE") instruction; each core may be independently power-gated; when all cores are clock-gated or power-gated, each core cluster may be independently clock-gated; and / or when all cores are power-gated, each core cluster may be independently power-gated. In at least one embodiment, one or more CPUs 1006 may further implement an enhanced algorithm for managing power states, where allowed power states and expected wake-up times are specified, and the hardware / microcode determines the optimal power states to enter for cores, clusters, and CCPLEX. In at least one embodiment, the processing core may support a simplified power state entry sequence in software, where the work is offloaded to the microcode.

[0182] In at least one embodiment, one or more GPUs 1008 may include an integrated GPU (alternatively referred to herein as "iGPU"). In at least one embodiment, one or more GPUs 1008 may be programmable and efficient for parallel workloads. In at least one embodiment, one or more GPUs 1008 may use an enhanced tensor instruction set. In at least one embodiment, one or more GPUs 1008 may include one or more streaming microprocessors, where each streaming microprocessor may include a level-1 ("L1") cache (e.g., an L1 cache with a storage capacity of at least 96KB), and two or more streaming microprocessors may share an L2 cache (e.g., an L2 cache with a storage capacity of 512KB). In at least one embodiment, one or more GPUs 1008 may include at least eight streaming microprocessors. In at least one embodiment, one or more GPUs 1008 may use one or more computing application programming interfaces (APIs). In at least one embodiment, one or more GPUs 1008 may use one or more parallel computing platforms and / or programming models (e.g., NVIDIA's CUDA model).

[0183] In at least one embodiment, one or more GPUs 1008 may be power optimized to achieve optimal performance in automotive and embedded use cases. For example, in at least one embodiment, one or more GPUs 1008 may be fabricated on fin field-effect transistor (“FinFET”) circuitry. In at least one embodiment, each streaming microprocessor may include multiple mixed-precision processing cores partitioned into multiple blocks. By way of example and not limitation, 64 FP32 cores and 32 FP64 cores may be partitioned into four processing blocks. In at least one embodiment, each processing block may be allocated 16 FP32 cores, 8 FP64 cores, 16 INT32 cores, two mixed-precision NVIDIA tensor cores for deep learning matrix arithmetic, a level zero (“L0”) instruction cache, a scheduler (e.g., a warp scheduler), or an orderer, a dispatch unit, and / or a 64KB register file. In at least one embodiment, the streaming microprocessor may include separate parallel integer and floating-point data paths for efficient execution of workloads with a mix of computational and addressing operations. In at least one embodiment, the streaming microprocessor may include separate thread scheduling capabilities to enable finer-grained synchronization and cooperation between parallel threads. In at least one embodiment, the streaming microprocessor may include a combined L1 data cache and shared memory unit to improve performance while simplifying programming.

[0184] In at least one embodiment, one or more GPUs 1008 may include high bandwidth memory (“HBM”) and / or a 16GB HBM2 memory subsystem, which in some examples is used to provide a peak memory bandwidth of approximately 900GB / second. In at least one embodiment, synchronous graphics random access memory (“SGRAM”), such as fifth-generation graphics double data rate type synchronous random access memory (“GDDR5”), may be used in addition to or in place of HBM memory.

[0185] In at least one embodiment, one or more GPUs 1008 may include unified memory technology. In at least one embodiment, address translation service (“ATS”) support may be used to allow one or more GPUs 1008 to directly access the page tables of one or more CPUs 1006. In at least one embodiment, when the memory management unit (“MMU”) of a GPU in one or more GPUs 1008 experiences a miss, an address translation request may be sent to one or more CPUs 1006. In response, in at least one embodiment, two CPUs in one or more CPUs 1006 may look up the virtual-physical mapping of the address in their page tables and send the translation back to one or more GPUs 1008. In at least one embodiment, unified memory technology may allow a single unified virtual address space for the memories of both one or more CPUs 1006 and one or more GPUs 1008, thus simplifying the programming of one or more GPUs 1008 and porting applications to one or more GPUs 1008.

[0186] In at least one embodiment, one or more GPUs 1008 may include any number of access counters, which may track the access frequency of one or more GPUs 1008 to the memories of other processors. In at least one embodiment, one or more access counters may help ensure that memory pages are moved to the physical memory of the processor that most frequently accesses the pages, thus improving the efficiency of sharing memory ranges among processors.

[0187] In at least one embodiment, one or more SoCs 1004 may include any number of caches 1012, including those described herein. For example, in at least one embodiment, one or more caches 1012 may include a level three (“L3”) cache that may be available to both one or more CPUs 1006 and one or more GPUs 1008 (e.g., connected to one or more CPUs 1006 and one or more GPUs 1008). In at least one embodiment, one or more caches 1012 may include a write-back cache that may track the state of each line, such as by using a cache coherence protocol (e.g., MEI, MESI, MSI, etc.). In at least one embodiment, although a smaller cache size may be used, depending on the embodiment, the L3 cache may include 4MB of memory or more.

[0188] In at least one embodiment, one or more SoCs 1004 may include one or more accelerators 1014 (e.g., hardware accelerators, software accelerators, or a combination thereof). In at least one embodiment, one or more SoCs 1004 may include a hardware acceleration cluster, which may include optimized hardware accelerators and / or large on-chip memories. In at least one embodiment, the large on-chip memory (e.g., 4MB of SRAM) may enable the hardware acceleration cluster to accelerate neural networks and other computations. In at least one embodiment, the hardware acceleration cluster may be used to supplement one or more GPUs 1008 and offload some tasks of one or more GPUs 1008 (e.g., to free up more cycles of one or more GPUs 1008 to perform other tasks). In at least one embodiment, one or more accelerators 1014 may be used for target workloads that are stable enough to withstand acceleration (e.g., perception, convolutional neural network (“CNN”), recurrent neural network (“RNN”), etc.). In at least one embodiment, the CNN may include region-based or region convolutional neural network (“RCNN”) and fast RCNN (e.g., as used for object detection) or other types of CNNs.

[0189] In at least one embodiment, one or more accelerators 1014 (e.g., a hardware acceleration cluster) may include one or more deep learning accelerators (“DLAs”). In at least one embodiment, one or more DLAs may include, but are not limited to, one or more tensor processing units (“TPUs”), which may be configured to provide an additional 10 trillion operations per second for deep learning applications and inference. In at least one embodiment, a TPU may be an accelerator configured and optimized to perform image processing functions (e.g., for CNNs, RCNNs, etc.). In at least one embodiment, one or more DLAs may be further optimized for a particular set of neural network types and floating-point operations as well as inference. In at least one embodiment, the design of one or more DLAs may provide higher performance per millimeter than a typical general-purpose GPU and generally far exceed the performance of a CPU. In at least one embodiment, one or more TPUs may perform several functions, including supporting, for example, INT8, INT16, and FP16 data types for single-instance convolution functions for features and weights as well as post-processor functions. In at least one embodiment, one or more DLAs may execute a neural network, especially a CNN, quickly and efficiently on processed or unprocessed data for any of a variety of functions, including, for example, but not limited to: a CNN for object recognition and detection using data from a camera sensor; a CNN for distance estimation using data from a camera sensor; a CNN for emergency vehicle detection as well as recognition and detection using data from a microphone; a CNN for face recognition and vehicle owner recognition using data from a camera sensor; and / or a CNN for security and / or safety-related events.

[0190] In at least one embodiment, one or more DLAs may perform any function of one or more GPUs 1008, and by using an inference accelerator, for example, a designer may target one or more DLAs or one or more GPUs 1008 for any function. For example, in at least one embodiment, a designer may concentrate the processing and floating-point operations of a CNN on one or more DLAs and leave other functions to one or more GPUs 1008 and / or one or more accelerators 1014.

[0191] In at least one embodiment, one or more accelerators 1014 may include a programmable vision accelerator (“PVA”), which may alternatively be referred to herein as a computer vision accelerator. In at least one embodiment, the PVA may be designed and configured to accelerate computer vision algorithms for advanced driver assistance systems (“ADAS”) 1038, autonomous driving, augmented reality (“AR”) applications, and / or virtual reality (“VR”) applications. In at least one embodiment, the PVA may provide a balance between performance and flexibility. For example, in at least one embodiment, each PVA may include, for example but not limited to, any number of reduced instruction set computer (“RISC”) cores, direct memory access (“DMA”), and / or any number of vector processors.

[0192] In at least one embodiment, the RISC cores may interact with an image sensor (e.g., the image sensor of any of the cameras described herein), an image signal processor, and the like. In at least one embodiment, each RISC core may include any number of memories. In at least one embodiment, depending on the embodiment, the RISC cores may use any one of a variety of protocols. In at least one embodiment, the RISC cores may execute a real-time operating system (“RTOS”). In at least one embodiment, one or more integrated circuit devices, application specific integrated circuits (“ASICs”), and / or memory devices may be used to implement the RISC cores. For example, in at least one embodiment, the RISC cores may include an instruction cache and / or tightly coupled RAM.

[0193] In at least one embodiment, the DMA may enable the components of the PVA to access system memory independently of one or more CPUs 1006. In at least one embodiment, the DMA may support any number of features for optimizing the delivery to the PVA, including but not limited to, supporting multi-dimensional addressing and / or circular addressing. In at least one embodiment, the DMA may support up to six or more dimensions of addressing, which may include but are not limited to block width, block height, block depth, horizontal block stride, vertical block stride, and / or depth stride.

[0194] In at least one embodiment, the vector processor may be a programmable processor that can be designed to efficiently and flexibly execute programming for computer vision algorithms and provide signal processing capabilities. In at least one embodiment, the PVA may include a PVA core and two vector processing subsystem partitions. In at least one embodiment, the PVA core may include a processor subsystem, one or more DMA engines (e.g., two DMA engines), and / or other peripherals. In at least one embodiment, the vector processing subsystem may operate as the main processing engine of the PVA and may include a vector processing unit (“VPU”), an instruction cache, and / or a vector memory (e.g., “VMEM”). In at least one embodiment, the VPU core may include a digital signal processor, such as, for example, a single instruction multiple data (“SIMD”), very long instruction word (“VLIW”) digital signal processor. In at least one embodiment, the combination of SIMD and VLIW may improve throughput and speed.

[0195] In at least one embodiment, each vector processor may include an instruction cache and may be coupled to dedicated memory. Thus, in at least one embodiment, each vector processor may be configured to execute independently of other vector processors. In at least one embodiment, the vector processors included in a particular PVA may be configured to employ data parallelism. For example, in at least one embodiment, multiple vector processors included in a single PVA may execute a general computer vision algorithm, but on different regions of an image. In at least one embodiment, the vector processors included in a particular PVA may simultaneously execute different computer vision algorithms on one image, or even execute different algorithms on sequential images or portions of an image. In at least one embodiment, any number of PVAs may be included in a hardware acceleration cluster, and any number of vector processors may be included in each PVA. In at least one embodiment, the PVA may include additional error correction code (“ECC”) memory for enhancing overall system security.

[0196] In at least one embodiment, one or more accelerators 1014 may include an on-chip computer vision network and static random access memory (“SRAM”) to provide high-bandwidth, low-latency SRAM for the one or more accelerators 1014. In at least one embodiment, the on-chip memory may include at least 4MB SRAM, which includes, for example but not limited to, eight field-configurable memory blocks that can be accessed by both the PVA and the DLA. In at least one embodiment, each pair of memory blocks may include an Advanced Peripheral Bus (“APB”) interface, configuration circuitry, a controller, and a multiplexer. In at least one embodiment, any type of memory may be used. In at least one embodiment, the PVA and the DLA may access the memory via a backbone that provides high-speed access to the memory for the PVA and the DLA. In at least one embodiment, the backbone may include an on-chip computer vision network that interconnects the PVA and the DLA to the memory (e.g., using APB).

[0197] In at least one embodiment, the on-chip computer vision network may include an interface that determines that both the PVA and the DLA provide ready and valid signals before transmitting any control signals / address / data. In at least one embodiment, the interface may provide separate phases and separate channels for transmitting control signals / address / data, as well as burst-type communication for continuous data transfer. In at least one embodiment, the interface may conform to the International Organization for Standardization (“ISO”) 26262 or the International Electrotechnical Commission (“IEC”) 61508 standard, although other standards and protocols may be used.

[0198] In at least one embodiment, one or more SoCs 1004 may include a real-time ray tracing hardware accelerator. In at least one embodiment, the real-time ray tracing hardware accelerator may be used to quickly and efficiently determine the position and extent of an object (e.g., within a world model) to generate a real-time visualization simulation for RADAR signal interpretation, for sound propagation synthesis and / or analysis, for SONAR system simulation, for general wave propagation simulation, for comparison with LIDAR data for positioning and / or other functions, and / or for other uses.

[0199] In at least one embodiment, one or more accelerators 1014 can have a wide range of uses for autonomous driving. In at least one embodiment, PVA can be used in critical processing stages in ADAS and autonomous vehicles. In at least one embodiment, the capabilities of PVA at low power and low latency are well-matched to algorithmic domains that require predictable processing. In other words, PVA excels in semi-dense or dense conventional computations, even on small data sets, which may require predictable runtimes with low latency and low power. In at least one embodiment, such as in vehicle 1000, PVA can be designed to run classical computer vision algorithms as they can be efficient in object detection and integer math operations.

[0200] For example, according to at least one embodiment of the technology, PVA is used to perform computer stereo vision. In at least one embodiment, algorithms based on semi-global matching can be used in some examples, but this is not meant to be limiting. In at least one embodiment, applications for level 3 - 5 autonomous driving use motion estimation / stereo matching in operation (e.g., structure from motion, pedestrian recognition, lane detection, etc.). In at least one embodiment, PVA can perform computer stereo vision functions on inputs from two monocular cameras.

[0201] In at least one embodiment, PVA can be used to perform dense optical flow. For example, in at least one embodiment, PVA can process raw RADAR data (e.g., using 4D fast Fourier transform) to provide processed RADAR data. In at least one embodiment, for example, PVA is used for time-of-flight depth processing by processing raw time-of-flight data to provide processed time-of-flight data.

[0202] In at least one embodiment, the DLA can be used to run any type of network to enhance control and driving safety, including, for example but not limited to, neural networks, the outputs of which are measurements of confidence for each object detection. In at least one embodiment, the confidence can be represented or interpreted as a probability, or as providing a relative "weight" of each detection compared to other detections. In at least one embodiment, the confidence measurements enable the system to make further decisions, namely, regarding which detections should be considered true positive detections rather than false positive detections. In at least one embodiment, the system can set a threshold for the confidence, and only consider detections that exceed the threshold as true positive detections. In embodiments using an automatic emergency braking ("AEB") system, false positive detections will cause the vehicle to automatically perform emergency braking, which is clearly undesirable. In at least one embodiment, highly confident detections can be considered as triggers for AEB. In at least one embodiment, the DLA can run a neural network for regressing confidence values. In at least one embodiment, the neural network can take at least some subset of parameters as its input, such as bounding box dimensions, a ground plane estimate obtained (e.g., from another subsystem), and the outputs of one or more IMU sensors 1066 related to the vehicle 1000 direction, distance, and 3D position estimates of the object obtained from the neural network and / or other sensors (e.g., one or more LIDAR sensors 1064 or one or more RADAR sensors 1060).

[0203] In at least one embodiment, one or more SoCs 1004 can include one or more data stores 1016 (e.g., memories). In at least one embodiment, one or more data stores 1016 can be on-chip memories of one or more SoCs 1004, which can store neural networks to be executed on one or more GPUs 1008 and / or the DLA. In at least one embodiment, one or more data stores 1016 can have a large enough capacity to store multiple instances of neural networks for redundancy and safety. In at least one embodiment, one or more data stores 1016 can include one or more L2 or L3 caches.

[0204] In at least one embodiment, one or more SoCs 1004 may include any number of processors 1010 (e.g., embedded processors). In at least one embodiment, one or more processors 1010 may include a boot and power management processor, which may be a dedicated processor and subsystem for handling boot power and management functions as well as related secure execution. In at least one embodiment, the boot and power management processor may be part of the boot sequence of one or more SoCs 1004 and may provide runtime power management services. In at least one embodiment, the boot power and management processor may provide clock and voltage programming, assist in system low power state transitions, manage one or more SoC 1004 thermal and temperature sensors, and / or manage the power state of one or more SoCs 1004. In at least one embodiment, each temperature sensor may be implemented as a ring oscillator whose output frequency is proportional to temperature, and one or more SoCs 1004 may use the ring oscillator to detect the temperature of one or more CPUs 1006, one or more GPUs 1008, and / or one or more accelerators 1014. In at least one embodiment, if it is determined that the temperature exceeds a threshold, the boot and power management processor may enter a temperature fault routine and place one or more SoCs 1004 in a lower power state and / or place the vehicle 1000 in a driver's safe parking mode (e.g., cause the vehicle 1000 to safely park).

[0205] In at least one embodiment, one or more processors 1010 may further include a set of embedded processors, which may be used as an audio processing engine. The audio processing engine may be an audio subsystem that provides full hardware support for multi-channel audio through multiple interfaces and a wide and flexible range of audio I / O interfaces. In at least one embodiment, the audio processing engine is a dedicated processor core that has a digital signal processor with dedicated RAM.

[0206] In at least one embodiment, one or more processors 1010 may further include an always-on processor engine that may provide the necessary hardware features to support low power sensor management and wake-up use cases. In at least one embodiment, the always-on processor engine may include, but is not limited to, a processor core, tightly coupled RAM, supporting peripherals (e.g., timers and interrupt controllers), various I / O controller peripherals, and routing logic.

[0207] In at least one embodiment, one or more processors 1010 may further include a secure cluster engine, which includes but is not limited to a dedicated processor subsystem for handling security management of automotive applications. In at least one embodiment, the secure cluster engine may include but is not limited to two or more processor cores, tightly coupled RAM, supporting peripherals (e.g., timers, interrupt controllers, etc.) and / or routing logic. In secure mode, in at least one embodiment, two or more cores may operate in lockstep mode and may be used as a single core with comparison logic for detecting any differences between their operations. In at least one embodiment, one or more processors 1010 may further include a real-time camera engine, which may include but is not limited to a dedicated processor subsystem for handling real-time camera management. In at least one embodiment, one or more processors 1010 may further include a high-dynamic range signal processor, which may include but is not limited to an image signal processor, which is a hardware engine that is part of a camera processing pipeline.

[0208] In at least one embodiment, one or more processors 1010 may include a video image synthesizer, which may be a processing block (e.g., implemented on a microprocessor) that implements the video post-processing functions required for a video playback application to produce a final image for a player window. In at least one embodiment, the video image synthesizer may perform lens distortion correction on one or more wide-angle cameras 1070, one or more surround cameras 1074, and / or one or more in-cabin monitoring camera sensors. In at least one embodiment, preferably, the in-cabin monitoring camera sensors are monitored by a neural network running on another instance of the SoC 1004, which is configured to identify in-cabin events and respond accordingly. In at least one embodiment, the in-cabin system may perform but is not limited to lip reading to activate cellular services and make phone calls, indicate emails, change the destination of the vehicle, activate or change the vehicle's infotainment system and settings, or provide voice-activated web surfing. In at least one embodiment, certain functions are available to the driver when the vehicle is operating in autonomous mode and are otherwise disabled.

[0209] In at least one embodiment, the video image synthesizer may include enhanced temporal noise reduction for both spatial and temporal noise reduction. For example, in at least one embodiment, in the case of motion occurring in the video, the noise reduction appropriately weights the spatial information, thereby reducing the weight of the information provided by adjacent frames. In at least one embodiment, in the case where an image or a part of an image does not include motion, the temporal noise reduction performed by the video image synthesizer may use information from a previous image to reduce the noise in the current image.

[0210] In at least one embodiment, the video image synthesizer may also be configured to perform stereoscopic correction on input stereoscopic shot frames. In at least one embodiment, when the operating system desktop is in use, the video image synthesizer may also be used for user interface synthesis and does not require one or more GPUs 1008 to continuously render new surfaces. In at least one embodiment, when one or more GPUs 1008 are powered on and active for 3D rendering, the video image synthesizer may be used to offload one or more GPUs 1008 to improve performance and responsiveness.

[0211] In at least one embodiment, one or more of the SoCs 1004 may further include a Mobile Industry Processor Interface (“MIPI”) camera serial interface, a high-speed interface, and / or a video input block for receiving video and inputs from cameras, which can be used for camera and related pixel input functions. In at least one embodiment, one or more of the SoCs 1004 may further include an input / output controller, which can be software-controlled and can be used to receive I / O signals not committed to a specific role.

[0212] In at least one embodiment, one or more of the SoCs 1004 may further include a wide range of peripheral interfaces for enabling communication with peripheral devices, audio encoder / decoders (“codecs”), power management, and / or other devices. In at least one embodiment, one or more of the SoCs 1004 can be used to process data from cameras (e.g., connected via Gigabit Multimedia Serial Link and Ethernet channels), sensors (e.g., one or more LIDAR sensors 1064, one or more RADAR sensors 1060, etc., which can be connected via Ethernet channels), data from the bus 1002 (e.g., the speed of the vehicle 1000, the steering wheel position, etc.), data from one or more GNSS sensors 1058 (e.g., connected via Ethernet bus or CAN bus), etc. In at least one embodiment, one or more of the SoCs 1004 may further include dedicated high-performance mass storage controllers, which may include their own DMA engines and can be used to free one or more CPUs 1006 from routine data management tasks.

[0213] In at least one embodiment, one or more SoCs 1004 can be an end-to-end platform with a flexible architecture that spans automation levels 3 - 5, thereby providing an integrated functional safety architecture for a platform that leverages and effectively uses computer vision and ADAS technologies to achieve diversity and redundancy, and provides a flexible and reliable driving software stack as well as deep learning tools. In at least one embodiment, one or more SoCs 1004 can be faster, more reliable, and even more energy - and space - efficient than conventional systems. For example, in at least one embodiment, one or more accelerators 1014, when combined with one or more CPUs 1006, one or more GPUs 1008, and one or more data stores 1016, can provide a fast and efficient platform for level 3 - 5 autonomous vehicles.

[0214] In at least one embodiment, computer vision algorithms can be executed on a CPU, which can be configured using a high - level programming language (such as C) to execute various processing algorithms on various visual data. However, in at least one embodiment, a CPU generally cannot meet the performance requirements of many computer vision applications, such as performance requirements related to execution time and power consumption. In at least one embodiment, many CPUs cannot execute complex object detection algorithms in real - time, which are used in in - vehicle ADAS applications and actual level 3 - 5 autonomous vehicles.

[0215] The embodiments described herein allow multiple neural networks to be executed simultaneously and / or sequentially, and allow the results to be combined together to achieve level 3 - 5 autonomous driving functions. For example, in at least one embodiment, a CNN executed on a DLA or a discrete GPU (e.g., one or more GPUs 1020) can include text and word recognition, thereby allowing traffic signs to be read and understood, including signs that the neural network has not been specifically trained for. In at least one embodiment, the DLA can also include a neural network that can recognize, interpret, and provide semantic understanding of the signs, and pass that semantic understanding to a path - planning module running on a CPU complex.

[0216] In at least one embodiment, for level 3, 4, or 5 driving, multiple neural networks can be run simultaneously. For example, in at least one embodiment, a warning sign stating "Caution: flashing lights indicate icy conditions", along with the electric lights, can be interpreted independently or jointly by several neural networks. In at least one embodiment, the warning sign itself can be recognized as a traffic sign by a first deployed neural network (e.g., a neural network that has been trained), and the text "flashing lights indicate icy conditions" can be interpreted by a second deployed neural network, which notifies the vehicle's path planning software (preferably executed on the CPU complex) that when flashing lights are detected, there is an icy condition. In at least one embodiment, the flashing lights can be recognized by operating a third deployed neural network on multiple frames, notifying the vehicle's path planning software of the presence (or absence) of flashing lights. In at least one embodiment, all three neural networks can run simultaneously, e.g., within the DLA and / or on one or more GPUs 1008.

[0217] In at least one embodiment, a CNN for face recognition and vehicle owner recognition can use data from the camera sensor to recognize the presence of an authorized driver and / or the owner of the vehicle 1000. In at least one embodiment, when the owner approaches the driver's door and turns on the lights, the normally open sensor processing engine can be used to unlock the vehicle, and in a secure mode, when the owner leaves the vehicle, it can be used to disable the vehicle. In this way, one or more SoCs 1004 provide protection against theft and / or carjacking.

[0218] In at least one embodiment, a CNN for emergency vehicle detection and recognition can use data from the microphone 1096 to detect and recognize emergency vehicle sirens. In at least one embodiment, one or more SoCs 1004 use a CNN to classify environmental and urban sounds, as well as visual data. In at least one embodiment, a CNN running on the DLA is trained to recognize the relative approach speed of an emergency vehicle (e.g., by using the Doppler effect). In at least one embodiment, the CNN can also be trained to recognize emergency vehicles specific to the local area in which the vehicle is operating, as identified by one or more GNSS sensors 1058. In at least one embodiment, when operating in Europe, the CNN will seek to detect European sirens, while in North America, the CNN will seek to recognize only North American sirens. In at least one embodiment, once an emergency vehicle is detected, a control program can be used, with the assistance of one or more ultrasonic sensors 1062, to execute emergency vehicle safety routines, slow down the vehicle, drive the vehicle to the side of the road, park, and / or idle the vehicle until the emergency vehicle has passed.

[0219] In at least one embodiment, vehicle 1000 may include one or more CPUs 1018 (e.g., one or more discrete CPUs or one or more dCPUs), which may be coupled to one or more SoCs 1004 via a high-speed interconnect (e.g., PCIe). In at least one embodiment, one or more CPUs 1018 may include, for example, X86 processors. One or more CPUs 1018 may be used to perform any of a variety of functions, such as arbitrating potentially inconsistent results between ADAS sensors and one or more SoCs 1004, and / or monitoring the status and health of one or more controllers 1036 and / or the on-chip infotainment system (“infotainment SoC”) 1030. In at least one embodiment, one or more SoCs 1004 include one or more interconnects, and the interconnects may include Peripheral Component Interconnect Express (PCIe).

[0220] In at least one embodiment, vehicle 1000 may include one or more GPUs 1020 (e.g., one or more discrete GPUs or one or more dGPUs), which may be coupled to one or more SoCs 1004 via a high-speed interconnect (e.g., NVIDIA's NVLINK channel). In at least one embodiment, one or more GPUs 1020 may provide additional artificial intelligence capabilities, such as by executing redundant and / or different neural networks, and may be used to train and / or update neural networks at least in part based on inputs (e.g., sensor data) from sensors of vehicle 1000.

[0221] In at least one embodiment, vehicle 1000 may further include a network interface 1024, which may include, but is not limited to, one or more wireless antennas 1026 (e.g., one or more wireless antennas for different communication protocols, such as cellular antennas, Bluetooth antennas, etc.). In at least one embodiment, network interface 1024 may be used to implement wireless connections to Internet cloud services (e.g., with servers and / or other network devices), to other vehicles, and / or to computing devices (e.g., a passenger's client device). In at least one embodiment, to communicate with other vehicles, a direct link may be established between vehicle 1000 and another vehicle and / or an indirect link (e.g., via a network and the Internet) may be established. In at least one embodiment, a vehicle-to-vehicle communication link may be used to provide the direct link. In at least one embodiment, the vehicle-to-vehicle communication link may provide vehicle 1000 with information about vehicles in the vicinity of vehicle 1000 (e.g., vehicles in front of, to the side of, and / or behind vehicle 1000). In at least one embodiment, the foregoing functionality may be part of the cooperative adaptive cruise control function of vehicle 1000.

[0222] In at least one embodiment, network interface 1024 may include a SoC that provides modulation and demodulation functions and enables one or more controllers 1036 to communicate over a wireless network. In at least one embodiment, network interface 1024 may include a radio frequency front end for up-conversion from baseband to radio frequency and down-conversion from radio frequency to baseband. In at least one embodiment, frequency conversion may be performed in any technically feasible manner. For example, frequency conversion may be performed by known processes and / or using a super-heterodyne process. In at least one embodiment, the radio frequency front end functions may be provided by a separate chip. In at least one embodiment, the network interface may include wireless capabilities for communicating over LTE, WCDMA, UMTS, GSM, CDMA2000, Bluetooth, Bluetooth LE, Wi-Fi, Z-Wave, ZigBee, LoRaWAN, and / or other wireless protocols.

[0223] In at least one embodiment, vehicle 1000 may further include one or more data stores 1028, which may include, but are not limited to, off-chip (e.g., one or more off-chip SoCs 1004) storage. In at least one embodiment, one or more data stores 1028 may include, but are not limited to, one or more storage elements, including RAM, SRAM, dynamic random access memory (“DRAM”), video random access memory (“VRAM”), flash memory, hard drives, and / or other components and / or devices that can store at least one bit of data.

[0224] In at least one embodiment, vehicle 1000 may further include one or more GNSS sensors 1058 (e.g., GPS and / or assisted GPS sensors) to assist in mapping, perception, occupancy grid generation, and / or path planning functions. In at least one embodiment, any number of GNSS sensors 1058 may be used, including, for example but not limited to, a GPS using a USB connector with an Ethernet to serial interface (e.g., RS-232) bridge.

[0225] In at least one embodiment, vehicle 1000 may further include one or more RADAR sensors 1060. In at least one embodiment, the one or more RADAR sensors 1060 may be used by vehicle 1000 for remote vehicle detection, even in dark and / or adverse weather conditions. In at least one embodiment, the RADAR functional safety level may be ASIL B. In at least one embodiment, the one or more RADAR sensors 1060 may use the CAN bus and / or bus 1002 (e.g., for transmitting data generated by the one or more RADAR sensors 1060) to control and access object tracking data and, in some examples, may access an Ethernet channel to access raw data. In at least one embodiment, a variety of RADAR sensor types may be used. By way of example and not limitation, the one or more RADAR sensors 1060 may be suitable for front, rear, and side RADAR use. In at least one embodiment, one or more of the one or more RADAR sensors 1060 are pulsed Doppler RADAR sensors.

[0226] In at least one embodiment, the one or more RADAR sensors 1060 may include different configurations, such as long-range with a narrow field of view, short-range with a wide field of view, short-range side coverage, etc. In at least one embodiment, the long-range RADAR may be used for an adaptive cruise control function. In at least one embodiment, the long-range RADAR system may provide a wide field of view achieved through two or more independent scans (e.g., within a range of 250 m (meters)). In at least one embodiment, the one or more RADAR sensors 1060 may assist in differentiating between static and moving objects and may be used by the ADAS system 1038 for emergency braking assistance and forward collision warning. In at least one embodiment, one or more of the sensors 1060 included in the long-range RADAR system may include, but are not limited to, a monostatic multimodal RADAR having multiple (e.g., six or more) fixed RADAR antennas and high-speed CAN and FlexRay interfaces. In at least one embodiment, with six antennas, the central four antennas may create a focused beam pattern designed to record the surrounding environment of vehicle 1000 at a relatively high speed with minimal traffic interference from adjacent lanes. In at least one embodiment, the other two antennas may widen the field of view, enabling it to quickly detect vehicles entering or leaving the lane of vehicle 1000.

[0227] In at least one embodiment, by way of example, a mid-range RADAR system may include a range of up to 160 m (front) or 80 m (rear), and a field of view of up to 42 degrees (front) or 150 degrees (rear). In at least one embodiment, a short-range RADAR system may include, but is not limited to, any number of RADAR sensors 1060 designed to be mounted at both ends of the rear bumper. When mounted at both ends of the rear bumper, in at least one embodiment, the RADAR sensor system may generate two beams that continuously monitor the rear direction of the vehicle and the blind spots in the vicinity. In at least one embodiment, the short-range RADAR system may be used in the ADAS system 1038 for blind spot detection and / or lane change assistance.

[0228] In at least one embodiment, the vehicle 1000 may further include one or more ultrasonic sensors 1062. In at least one embodiment, one or more ultrasonic sensors 1062 that may be positioned at the front, rear, and / or side positions of the vehicle 1000 may be used for parking assistance and / or creating and updating an occupancy grid. In at least one embodiment, a variety of ultrasonic sensors 1062 may be used, and different ultrasonic sensors 1062 may be used for different detection ranges (e.g., 2.5 m, 4 m). In at least one embodiment, the ultrasonic sensors 1062 may operate at a functional safety level of ASIL B.

[0229] In at least one embodiment, the vehicle 1000 may include one or more LIDAR sensors 1064. In at least one embodiment, one or more LIDAR sensors 1064 may be used for object and pedestrian detection, emergency braking, collision avoidance, and / or other functions. In at least one embodiment, one or more LIDAR sensors 1064 may operate at a functional safety level of ASIL B. In at least one embodiment, the vehicle 1000 may include multiple (e.g., two, four, six, etc.) LIDAR sensors 1064 that may use an Ethernet channel (e.g., to provide data to a gigabit Ethernet switch).

[0230] In at least one embodiment, one or more LIDAR sensors 1064 may be capable of providing a list of objects and their distances for a 360-degree field of view. In at least one embodiment, commercially available one or more LIDAR sensors 1064 may, for example, have an advertised range of approximately 100 m, an accuracy of 2 cm - 3 cm, and support an Ethernet connection of 100 Mbps. In at least one embodiment, one or more non-protruding LIDAR sensors may be used. In such an embodiment, one or more LIDAR sensors 1064 may include small devices that can be embedded in the front, rear, sides, and / or corner positions of the vehicle 1000. In at least one embodiment, one or more LIDAR sensors 1064, in such an embodiment, may provide a horizontal field of view of up to 120 degrees and a vertical field of view of 35 degrees, and have a range of 200 m, even for low-reflectivity objects. In at least one embodiment, the one or more forward-mounted LIDAR sensors 1064 may be configured for a horizontal field of view between 45 degrees and 135 degrees.

[0231] In at least one embodiment, LIDAR techniques (such as 3D flash LIDAR) may also be used. In at least one embodiment, 3D flash LIDAR uses a laser flash as a transmission source to illuminate up to approximately 200 m around the vehicle 1000. In at least one embodiment, the flash LIDAR unit includes, but is not limited to, a receiver that records the laser pulse propagation time and the reflected light on each pixel, which in turn corresponds to the range from the vehicle 1000 to the object. In at least one embodiment, flash LIDAR may allow the generation of a highly accurate and distortion-free image of the surrounding environment using each laser flash. In at least one embodiment, four flash LIDAR sensors may be deployed, with one on each side of the vehicle 1000. In at least one embodiment, the 3D flash LIDAR system includes, but is not limited to, a solid-state 3D staring array LIDAR camera that has no moving parts other than a fan (e.g., a non-scanning LIDAR device). In at least one embodiment, the flash LIDAR device may use a Class I (eye-safe) laser pulse of 5 nanoseconds per frame and may capture the reflected laser as a 3D range point cloud and co-registered intensity data.

[0232] In at least one embodiment, vehicle 1000 may further include one or more IMU sensors 1066. In at least one embodiment, one or more IMU sensors 1066 may be located at the center of the rear axle of vehicle 1000. In at least one embodiment, one or more IMU sensors 1066 may include, for example but not limited to, one or more accelerometers, one or more magnetometers, one or more gyroscopes, one or more magnetic compasses, and / or other sensor types. In at least one embodiment, for example in a six-axis application, one or more IMU sensors 1066 may include but are not limited to accelerometers and gyroscopes. In at least one embodiment, for example in a nine-axis application, one or more IMU sensors 1066 may include but are not limited to accelerometers, gyroscopes, and magnetometers.

[0233] In at least one embodiment, one or more IMU sensors 1066 may be implemented as a miniature high-performance GPS-aided inertial navigation system (“GPS / INS”) that combines microelectromechanical system (“MEMS”) inertial sensors, a high-sensitivity GPS receiver, and an advanced Kalman filtering algorithm for providing estimates of position, velocity, and attitude. In at least one embodiment, one or more IMU sensors 1066 may enable vehicle 1000 to estimate its heading by directly observing and correlating speed changes from GPS to one or more IMU sensors 1066 without input from a magnetic sensor. In at least one embodiment, one or more IMU sensors 1066 and one or more GNSS sensors 1058 may be combined in a single integrated unit.

[0234] In at least one embodiment, vehicle 1000 may include one or more microphones 1096 placed inside and / or around vehicle 1000. In at least one embodiment, one or more microphones 1096 may be used for emergency vehicle detection and identification.

[0235] In at least one embodiment, vehicle 1000 may further include any number of camera types, including one or more stereo cameras 1068, one or more wide-angle cameras 1070, one or more infrared cameras 1072, one or more surround cameras 1074, one or more long-range cameras 1098, one or more mid-range cameras 1076, and / or other camera types. In at least one embodiment, the cameras can be used to capture image data around the entire periphery of vehicle 1000. In at least one embodiment, the type of cameras used depends on vehicle 1000. In at least one embodiment, any combination of camera types can be used to provide the necessary coverage around vehicle 1000. In at least one embodiment, the number of cameras deployed can vary according to the embodiment. For example, in at least one embodiment, vehicle 1000 can include six cameras, seven cameras, ten cameras, twelve cameras, or other numbers of cameras. In at least one embodiment, the cameras can support, by way of example but not limitation, Gigabit Multimedia Serial Link (“GMSL”) and / or Gigabit Ethernet communications. In at least one embodiment, each camera is described in more detail previously herein with reference to Figure 10A and Figure 10B Each camera is described in more detail previously herein with reference to

[0236] In at least one embodiment, vehicle 1000 may further include one or more vibration sensors 1042. In at least one embodiment, one or more vibration sensors 1042 can measure the vibration of components of vehicle 1000 (e.g., an axle). For example, in at least one embodiment, a change in vibration can indicate a change in the road surface. In at least one embodiment, when two or more vibration sensors 1042 are used, the difference between the vibrations can be used to determine road surface friction or slippage (e.g., when there is a vibration difference between a power-driven axle and a freely rotating axle).

[0237] In at least one embodiment, vehicle 1000 may include an ADAS system 1038. In at least one embodiment, the ADAS system 1038 may include, in some examples, but not be limited to, a SoC. In at least one embodiment, the ADAS system 1038 may include, but not be limited to, any number and any combination of autonomous / adaptive / automatic cruise control (“ACC”) systems, cooperative adaptive cruise control (“CACC”) systems, forward collision warning (“FCW”) systems, automatic emergency braking (“AEB”) systems, lane departure warning (“LDW”) systems, lane keeping assist (“LKA”) systems, blind spot warning (“BSW”) systems, rear cross traffic warning (“RCTW”) systems, collision warning (“CW”) systems, lane centering (“LC”) systems, and / or other systems, features, and / or functions.

[0238] In at least one embodiment, the ACC system may use one or more RADAR sensors 1060, one or more LIDAR sensors 1064, and / or any number of cameras. In at least one embodiment, the ACC system may include a longitudinal ACC system and / or a lateral ACC system. In at least one embodiment, the longitudinal ACC system monitors and controls the distance to another vehicle immediately in front of vehicle 1000 and automatically adjusts the speed of vehicle 1000 to maintain a safe distance from the vehicle ahead. In at least one embodiment, the lateral ACC system performs distance keeping and recommends that vehicle 1000 change lanes when necessary. In at least one embodiment, the lateral ACC is related to other ADAS applications, such as LC and CW.

[0239] In at least one embodiment, the CACC system uses information from other vehicles, which may be received indirectly from other vehicles via the network interface 1024 and / or one or more wireless antennas 1026 via a wireless link or through a network connection (e.g., via the Internet). In at least one embodiment, the direct link may be provided by a vehicle-to-vehicle (“V2V”) communication link, while the indirect link may be provided by an infrastructure-to-vehicle (“I2V”) communication link. Generally, V2V communication provides information about the vehicle immediately in front (e.g., the vehicle immediately in front of and in the same lane as vehicle 1000), while I2V communication provides information about traffic further ahead. In at least one embodiment, the CACC system may include one or both of the I2V and V2V information sources. In at least one embodiment, given information about the vehicles in front of a given vehicle 1000, the CACC system may be more reliable and has the potential to improve the smoothness of traffic flow and reduce road congestion.

[0240] In at least one embodiment, the FCW system is designed to warn the driver of a hazard so that the driver can take corrective action. In at least one embodiment, the FCW system uses a forward camera and / or one or more RADAR sensors 1060, which are coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback, such as a display, speaker, and / or vibration component. In at least one embodiment, the FCW system may provide warnings, such as in the form of a sound, visual warning, vibration, and / or rapid braking pulse.

[0241] In at least one embodiment, the AEB system detects an impending forward collision with another vehicle or other object and can automatically apply the brakes if the driver does not take corrective action within specified time or distance parameters. In at least one embodiment, the AEB system can use one or more forward cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC. In at least one embodiment, when the AEB system detects a hazard, it typically first warns the driver to take corrective action to avoid the collision, and, if the driver does not take corrective action, the AEB system can automatically apply the brakes to attempt to prevent or at least mitigate the effects of the predicted collision. In at least one embodiment, the AEB system can include technologies such as dynamic brake support and / or collision imminent braking.

[0242] In at least one embodiment, when vehicle 1000 crosses a lane marking, the LDW system provides visual, audible, and / or tactile warnings, such as steering wheel or seat vibration, to warn the driver. In at least one embodiment, the LDW system does not activate when the driver indicates an intentional lane departure, such as by activating a turn signal. In at least one embodiment, the LDW system can use a forward-facing camera coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which is electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component. In at least one embodiment, the LKA system is a variant of the LDW system. In at least one embodiment, if vehicle 1000 starts to leave its lane, the LKA system provides steering input or braking to correct vehicle 1000.

[0243] In at least one embodiment, the BSW system detects and warns the driver that the vehicle is in the blind spot of a vehicle. In at least one embodiment, the BSW system can provide visual, audible, and / or tactile alerts to indicate that merging or changing lanes is unsafe. In at least one embodiment, the BSW system can provide additional warnings when the driver uses a turn signal. In at least one embodiment, the BSW system can use one or more rear-facing cameras and / or one or more RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to driver feedback such as a display, speaker, and / or vibration component.

[0244] In at least one embodiment, when the vehicle 1000 detects an object outside the rear camera range while reversing, the RCTW system can provide visual, audible, and / or tactile notifications. In at least one embodiment, the RCTW system includes an AEB system for ensuring that vehicle braking is applied to avoid a collision. In at least one embodiment, the RCTW system can use one or more rear-facing RADAR sensors 1060 coupled to a dedicated processor, DSP, FPGA, and / or ASIC, which are electrically coupled to provide driver feedback such as a display, speaker, and / or vibration component.

[0245] In at least one embodiment, conventional ADAS systems may be prone to producing false positive results, which may annoy and distract the driver, but are generally not catastrophic because conventional ADAS systems warn the driver and allow the driver to decide whether a safety situation truly exists and take action accordingly. In at least one embodiment, in the case of conflicting results, the vehicle 1000 itself decides whether to follow the result of the primary computer or the secondary computer (e.g., the first controller or the second controller in the controller 1036). For example, in at least one embodiment, the ADAS system 1038 can be a backup and / or secondary computer for providing perception information to a backup computer rationality module. In at least one embodiment, the backup computer rationality monitor can run various software redundantly on hardware components to detect faults in perception and dynamic driving tasks. In at least one embodiment, the output from the ADAS system 1038 can be provided to the supervisory MCU. In at least one embodiment, if the output from the primary computer and the output from the secondary computer conflict, the supervisory MCU decides how to reconcile the conflict to ensure safe operation.

[0246] In at least one embodiment, the primary computer can be configured to provide a confidence score to the supervisory MCU, which indicates the primary computer's confidence in the selected result. In at least one embodiment, if the confidence score exceeds a threshold, the supervisory MCU can follow the primary computer's instructions regardless of whether the secondary computer provides conflicting or inconsistent results. In at least one embodiment, in the case where the confidence score does not meet the threshold and the primary computer and the secondary computer indicate different results (e.g., conflict), the supervisory MCU can arbitrate between the computers to determine an appropriate result.

[0247] In at least one embodiment, the supervisory MCU can be configured to run a neural network that is trained and configured to determine conditions under which the auxiliary computer provides an error alert based at least in part on outputs from the host computer and outputs from the auxiliary computer. In at least one embodiment, one or more neural networks in the supervisory MCU can learn when the output of the auxiliary computer can be trusted and when it cannot be trusted. For example, in at least one embodiment, when the auxiliary computer is a RADAR-based FCW system, one or more neural networks in the supervisory MCU can learn when the FCW system is identifying metal objects that are not actually dangerous, such as drain grates or manhole covers that would trigger an alert. In at least one embodiment, when the auxiliary computer is a camera-based LDW system, the neural network in the supervisory MCU can learn to override the LDW when there is a bicyclist or pedestrian present and lane departure is actually the safest course of action. In at least one embodiment, the supervisory MCU can include at least one of a DLA or a GPU suitable for running one or more neural networks with associated memory. In at least one embodiment, the supervisory MCU can be included as and / or included in components of one or more SoCs 1004.

[0248] In at least one embodiment, the ADAS system 1038 can include an auxiliary computer that performs ADAS functions using traditional computer vision rules. In at least one embodiment, the auxiliary computer can use classical computer vision rules (if-then), and the presence of one or more neural networks in the supervisory MCU can improve reliability, safety, and performance. For example, in at least one embodiment, the diverse implementation and intentional non-identity make the overall system more fault-tolerant, especially for faults caused by software (or software-hardware interface) functions. For example, in at least one embodiment, if there is a software vulnerability or error in the software running on the host computer and the not-identical software code running on the auxiliary computer provides a consistent overall result, the supervisory MCU can have greater confidence that the overall result is correct, and the vulnerability in the software or hardware on the host computer will not result in a major error.

[0249] In at least one embodiment, the output of the ADAS system 1038 can be fed into the perception block of the host computer and / or the dynamic driving task block of the host computer. For example, in at least one embodiment, if the ADAS system 1038 indicates a forward collision warning due to an object directly ahead, the perception block can use that information when the object is identified. In at least one embodiment, as described herein, the auxiliary computer can have its own neural network that is trained to reduce the risk of false alarms.

[0250] In at least one embodiment, vehicle 1000 may further include an infotainment SoC 1030 (e.g., in-vehicle infotainment system (IVI)). Although shown and described as an SoC, in at least one embodiment, infotainment system SoC 1030 may not be an SoC and may include, but is not limited to, two or more discrete components. In at least one embodiment, infotainment SoC 1030 may include, but is not limited to, a combination of hardware and software that may be used to provide audio (e.g., music, personal digital assistant, navigation instructions, news, radio, etc.), video (e.g., television, movies, streaming, etc.), telephone (e.g., hands-free calling), network connectivity (e.g., LTE, WiFi, etc.), and / or information services (e.g., navigation system, rear parking assist, radio data system, vehicle-related information such as fuel level, total covered distance, brake fuel level, oil level, door open / closed, air filter information, etc.) to vehicle 1000. For example, infotainment SoC 1030 may include a radio, disk player, navigation system, video player, USB and Bluetooth connectivity, in-vehicle computer, in-vehicle entertainment system, WiFi, steering wheel audio control, hands-free voice control, head-up display (“HUD”), HMI display 1034, telematics device, control panel (e.g., for controlling various components, features, and / or systems and / or interacting therewith), and / or other components. In at least one embodiment, infotainment SoC 1030 may further be used to provide information (e.g., visual and / or auditory information) to one or more users of vehicle 1000, such as information from ADAS system 1038, autonomous driving information (such as planned vehicle maneuvers), trajectories, surrounding environment information (e.g., intersection information, vehicle information, road information, etc.), and / or other information.

[0251] In at least one embodiment, infotainment SoC 1030 may include any number and type of GPU functionality. In at least one embodiment, infotainment SoC 1030 may communicate with other devices, systems, and / or components of vehicle 1000 via bus 1002. In at least one embodiment, infotainment SoC 1030 may be coupled to a supervisory MCU such that the GPU of the infotainment system may perform some autonomous driving functions in the event of a failure of one or more main controllers 1036 (e.g., the main computer and / or backup computer of vehicle 1000). In at least one embodiment, infotainment SoC 1030 may place vehicle 1000 into a driver-to-safe parking mode as described herein.

[0252] In at least one embodiment, vehicle 1000 may further include a dashboard 1032 (e.g., a digital dashboard, an electronic dashboard, a digital instrument panel, etc.). In at least one embodiment, the dashboard 1032 may include, but is not limited to, a controller and / or a supercomputer (e.g., a discrete controller or supercomputer). In at least one embodiment, the dashboard 1032 may include, but is not limited to, a set of gauges in any number and combination, such as a speedometer, a fuel level, an oil pressure, a tachometer, an odometer, a turn indicator, a shift position indicator, one or more seatbelt warning lights, one or more parking brake warning lights, one or more engine fault lights, airbag (e.g., auxiliary restraint system) information, lighting controls, safety system controls, navigation information, etc. In some examples, information may be displayed and / or shared between the infotainment SoC 1030 and the dashboard 1032. In at least one embodiment, the dashboard 1032 may be included as part of the infotainment SoC 1030, and vice versa.

[0253] In at least one embodiment, Figure 10C at least one of the components shown or described is used to implement the techniques and / or functions associated with Figures 1 to 6 the description. In at least one embodiment, the wireless antenna 1026 is used to transmit and / or receive one or more wireless signals to be used as inputs to an efficient neural model that uses the inputs indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in conjunction with Figures 1 to 6 the description, and as described herein.

[0254] Figure 10D is according to at least one embodiment between one or more cloud-based servers and Figure 10ADiagram of a system for communication between autonomous vehicles 1000. In at least one embodiment, the system may include, but is not limited to, one or more servers 1078, one or more networks 1090, and any number and type of vehicles, including vehicle 1000. In at least one embodiment, one or more servers 1078 may include, but is not limited to, multiple GPUs 1084(A)-1084(H) (collectively referred to herein as GPU 1084), PCIe switches 1082(A)-1082(D) (collectively referred to herein as PCIe switch 1082), and / or CPUs 1080(A)-1080(B) (collectively referred to herein as CPU 1080). In at least one embodiment, GPUs 1084, CPUs 1080, and PCIe switches 1082 may be interconnected with a high-speed interconnect, such as, for example but not limited to, the NVLink interface 1088 developed by NVIDIA and / or the PCIe connection 1086. In at least one embodiment, GPUs 1084 are connected via NVLink and / or NVSwitch SoC, and GPUs 1084 and PCIe switches 1082 are connected via PCIe interconnect. Although eight GPUs 1084, two CPUs 1080, and four PCIe switches 1082 are shown, this is not intended to be limiting. In at least one embodiment, each of one or more servers 1078 may include, but is not limited to, any number of GPUs 1084, CPUs 1080, and / or PCIe switches 1082 in any combination. For example, in at least one embodiment, one or more servers 1078 may each include eight, sixteen, thirty-two, and / or more GPUs 1084.

[0255] In at least one embodiment, one or more servers 1078 may receive image data representing an image from a vehicle via one or more networks 1090, the image showing an unexpected or changed road condition, such as recently started road work. In at least one embodiment, one or more servers 1078 may send updated equal neural networks 1092 and / or map information 1094 to the vehicle via one or more networks 1090, including but not limited to information about traffic and road conditions. In at least one embodiment, the update to map information 1094 may include, but is not limited to, an update to the HD map 1022, such as information about construction sites, potholes, sidewalks, floods, and / or other obstacles. In at least one embodiment, neural network 1092 and / or map information 1094 may be generated by new training and / or experience represented in data received from any number of vehicles in the environment, and / or at least based on training performed at the data center (e.g., using one or more servers 1078 and / or other servers).

[0256] In at least one embodiment, one or more servers 1078 may be used to train a machine learning model (e.g., a neural network) at least in part based on training data. In at least one embodiment, the training data may be generated by a vehicle and / or may be generated in a simulation (e.g., using a game engine). In at least one embodiment, any amount of training data may be labeled (e.g., in cases where the associated neural network benefits from supervised learning) and / or may undergo other preprocessing. In at least one embodiment, no amount of training data may be labeled and / or preprocessed (e.g., in cases where the associated neural network does not require supervised learning). In at least one embodiment, once the machine learning model is trained, the machine learning model may be used by the vehicle (e.g., sent to the vehicle via one or more networks 1090), and / or the machine learning model may be used by one or more servers 1078 to remotely monitor the vehicle.

[0257] In at least one embodiment, one or more servers 1078 may receive data from a vehicle and apply the data to a latest real-time neural network for real-time intelligent inference. In at least one embodiment, one or more servers 1078 may include a deep learning supercomputer powered by one or more GPUs 1084 and / or a dedicated AI computer, such as DGX and DGX Station machines developed by NVIDIA. However, in at least one embodiment, one or more servers 1078 may include a deep learning infrastructure of a data center powered by a CPU.

[0258] In at least one embodiment, the deep learning infrastructure of one or more servers 1078 may be capable of performing fast, real-time inference and may use that ability to evaluate and verify the health of the processors, software, and / or associated hardware in vehicle 1000. For example, in at least one embodiment, the deep learning infrastructure may receive periodic updates from vehicle 1000, such as an image sequence and / or objects that vehicle 1000 is located in within that image sequence (e.g., via computer vision and / or other machine learning object classification techniques). In at least one embodiment, the deep learning infrastructure may run its own neural network to identify the objects and compare them to the objects identified by vehicle 1000, and if the results do not match and the deep learning infrastructure determines that the AI in vehicle 1000 is malfunctioning, one or more servers 1078 may send a signal to vehicle 1000 that instructs the fail-safe computer in vehicle 1000 to take control, notify the passengers, and complete a safe parking operation.

[0259] In at least one embodiment, one or more servers 1078 may include one or more GPUs 1084 and one or more programmable inference accelerators (e.g., NVIDIA's TensorRT 3 device). In at least one embodiment, the combination of GPU-driven servers and inference acceleration can enable real-time response. In at least one embodiment, in cases where performance is less critical, for example, servers driven by CPUs, FPGAs, and other processors can be used for inference. In at least one embodiment, one or more hardware structures 715 are used to execute one or more embodiments. This document combines Figure 7A and / or Figure 7B to provide details about the hardware structure 715.

[0260] Computer system

[0261] Figure 11 is a block diagram showing an exemplary computer system according to at least one embodiment. The exemplary computer system can be a system with interconnected devices and components, a system-on-chip (SOC), or some combination thereof formed with a processor that can include execution units for executing instructions. In at least one embodiment, according to the present disclosure, such as in the embodiments described herein, the computer system 1100 may include, but is not limited to, components such as a processor 1102 for executing algorithms for processing data using execution units (including logic). In at least one embodiment, the computer system 1100 may include a processor, such as those available from Intel Corporation of Santa Clara, California, processor families, Xeon TM , XScale TM and / or StrongARM TM , Core TM or Nervana TM microprocessors, although other systems (including PCs, engineering workstations, set-top boxes, etc. with other microprocessors) can also be used. In at least one embodiment, the computer system 1100 may execute a version of the WINDOWS operating system available from Microsoft Corporation of Redmond, Wash., although other operating systems (such as UNIX and Linux), embedded software, and / or graphical user interfaces can also be used.

[0262] Embodiments can be used in other devices such as handheld devices and embedded applications. Some examples of handheld devices include cellular phones, Internet Protocol devices, digital cameras, personal digital assistants (“PDAs”), and handheld PCs. In at least one embodiment, an embedded application can include a microcontroller, a digital signal processor (“DSP”), a system-on-chip, a network computer (“NetPC”), a set-top box, a network hub, a wide area network (“WAN”) switch, or any other system that can execute one or more instructions according to at least one embodiment.

[0263] In at least one embodiment, computer system 1100 can include, but is not limited to, a processor 1102 that can include, but is not limited to, one or more execution units 1108 for performing machine learning model training and / or inference according to the techniques described herein. In at least one embodiment, computer system 1100 is a single-processor desktop or server system, but in another embodiment, computer system 1100 can be a multi-processor system. In at least one embodiment, processor 1102 can include, but is not limited to, for example, a complex instruction set computer (“CISC”) microprocessor, a reduced instruction set computing (“RISC”) microprocessor, a very long instruction word (“VLIW”) microprocessor, a processor implementing an instruction set combination, or any other processor device such as a digital signal processor. In at least one embodiment, processor 1102 can be coupled to a processor bus 1110 that can transfer data signals between processor 1102 and other components in computer system 1100.

[0264] In at least one embodiment, processor 1102 can include, but is not limited to, a level 1 (“L1”) internal cache memory (“cache”) 1104. In at least one embodiment, processor 1102 can have a single internal cache or multiple levels of internal caches. In at least one embodiment, the cache memory can reside external to processor 1102. Depending on the particular implementation and requirements, other embodiments can also include a combination of internal and external caches. In at least one embodiment, register file 1106 can store different types of data in various registers, including but not limited to integer registers, floating-point registers, status registers, and instruction pointer registers.

[0265] In at least one embodiment, execution unit 1108, which includes, but is not limited to, logic for performing integer and floating point operations, is also located within processor 1102. In at least one embodiment, processor 1102 may also include a microcode (“ucode”) read only memory (“ROM”) that stores microcode for certain macroinstructions. In at least one embodiment, execution unit 1108 may include logic for processing a packed instruction set 1109. In at least one embodiment, by including the packed instruction set 1109 in the instruction set of a general purpose processor and the associated circuitry that is to execute the instructions, operations used by many multimedia applications can be performed using packed data within processor 1102. In at least one embodiment, many multimedia applications can be accelerated and executed more efficiently by performing operations on packed data using the full width of the processor's data bus, which can eliminate the need to transfer smaller data units on the processor's data bus to perform one or more operations on one data element at a time.

[0266] In at least one embodiment, execution unit 1108 may also be used in microcontrollers, embedded processors, graphics devices, DSPs, and other types of logic circuits. In at least one embodiment, computer system 1100 may include, but is not limited to, memory 1120. In at least one embodiment, memory 1120 may be a dynamic random access memory (“DRAM”) device, a static random access memory (“SRAM”) device, a flash memory device, or other memory device. In at least one embodiment, memory 1120 may store one or more instructions 1119 and / or data 1121 represented by data signals that may be executed by processor 1102.

[0267] In at least one embodiment, the system logic chip may be coupled to the processor bus 1110 and the memory 1120. In at least one embodiment, the system logic chip may include, but is not limited to, a Memory Controller Hub (“MCH”) 1116, and the processor 1102 may communicate with the MCH 1116 via the processor bus 1110. In at least one embodiment, the MCH 1116 may provide a high-bandwidth memory path 1118 to the memory 1120 for instruction and data storage and for storage of graphics commands, data, and textures. In at least one embodiment, the MCH 1116 may direct data signals among the processor 1102, the memory 1120, and other components in the computer system 1100, and may bridge data signals among the processor bus 1110, the memory 1120, and the system I / O interface 1122. In at least one embodiment, the system logic chip may provide a graphics port for coupling to a graphics controller. In at least one embodiment, the MCH 1116 may be coupled to the memory 1120 via the high-bandwidth memory path 1118, and the graphics / video card 1112 may be coupled to the MCH 1116 via an Accelerated Graphics Port (“AGP”) interconnect 1114.

[0268] In at least one embodiment, the computer system 1100 may use the system I / O interface 1122 as a proprietary hub interface bus to couple the MCH 1116 to an I / O Controller Hub (“ICH”) 1130. In at least one embodiment, the ICH 1130 may provide direct connections to certain I / O devices via a local I / O bus. In at least one embodiment, the local I / O bus may include, but is not limited to, a high-speed I / O bus for connecting peripheral devices to the memory 1120, the chipset, and the processor 1102. Examples may include, but are not limited to, an audio controller 1129, a Firmware Hub (“Flash BIOS”) 1128, a wireless transceiver 1126, a data storage 1124, a legacy I / O controller 1123 that includes a user input and keyboard interface 1125, a serial expansion port 1127 (such as a Universal Serial Bus (“USB”) port), and a network controller 1134. In at least one embodiment, the data storage 1124 may include a hard disk driver, a floppy disk driver, a CD-ROM device, a flash device, or other mass storage devices.

[0269] In at least one embodiment, Figure 11 a system including interconnected hardware devices or “chips” is shown, while in other embodiments, Figure 11 an exemplary SoC may be shown. In at least one embodiment, Figure 11The devices shown can be interconnected using proprietary interconnects, standardized interconnects (e.g., PCIe), or some combination thereof. In at least one embodiment, one or more components of computer system 1100 are interconnected using Compute Express Link (CXL) interconnects.

[0270] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Figure 7A and / or Figure 7B Logic 715 are provided. In at least one embodiment, Logic 715 can be used in computer system 1100 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0271] In at least one embodiment, at least one component shown or described is used to implement the techniques and / or functions described in connection with Figures 10D to 11 In at least one embodiment, processor 1102 performs one or more operations involving generating one or more software programs having the indicated one or more software program dependencies using information indicating one or more software program dependencies, as described in connection with Figures 1 to 6 and as described herein. Figures 1 to 6

[0272] Figure 12 is a block diagram showing an electronic device 1200 for utilizing processor 1210 according to at least one embodiment. In at least one embodiment, electronic device 1200 can be, for example but not limited to, a laptop computer, a tower server, a rack server, a blade server, a laptop, a desktop computer, a tablet, a mobile device, a phone, an embedded computer, or any other suitable electronic device.

[0273] In at least one embodiment, electronic device 1200 can include, but is not limited to, processor 1210 communicatively coupled to any suitable number or type of components, peripherals, modules, or devices. In at least one embodiment, processor 1210 is coupled using a bus or interface such as an I 2 2C bus, a System Management Bus (“SMBus”), a Low Pin Count (LPC) bus, a Serial Peripheral Interface (“SPI”), a High Definition Audio (“HDA”) bus, a Serial Advanced Technology Attachment (“SATA”) bus, a Universal Serial Bus (“USB”) (versions 1, 2, 3, etc.), or a Universal Asynchronous Receiver / Transmitter (“UART”) bus. In at least one embodiment, Figure 12 shows a system that includes interconnected hardware devices or “chips,” while in other embodiments, Figure 12 ​An exemplary SoC can be shown. In at least one embodiment, Figure 12 the devices shown in can be interconnected using proprietary interconnections, standardized interconnections (e.g., PCIe), or some combination thereof. In at least one embodiment, Figure 12 one or more components of are interconnected using Compute Express Link (CXL) interconnections.

[0274] In at least one embodiment, Figure 12 it can include a display 1224, a touch screen 1225, a touch pad 1230, a Near Field Communication unit (“NFC”) 1245, a sensor hub 1240, a thermal sensor 1246, an Embedded Controller (“EC”) 1235, a Trusted Platform Module (“TPM”) 1238, BIOS / Firmware / Flash (“BIOS, FW Flash”) 1222, a DSP 1260, drivers 1220 (such as a Solid State Drive (“SSD”) or a Hard Disk Drive (“HDD”)), a Wireless Local Area Network unit (“WLAN”) 1250, a Bluetooth unit 1252, a Wireless Wide Area Network unit (“WWAN”) 1256, a Global Positioning System (GPS) unit 1255, a camera (“USB 3.0 camera”) 1254 (such as a USB 3.0 camera) and / or a Low Power Double Data Rate (“LPDDR”) memory unit (“LPDDR3”) 1215 implemented to, for example, the LPDDR3 standard. These components can each be implemented in any suitable manner.

[0275] In at least one embodiment, other components can be communicatively coupled to the processor 1210 via the components described herein. In at least one embodiment, an accelerometer 1241, an Ambient Light Sensor (“ALS”) 1242, a compass 1243, and a gyroscope 1244 can be communicatively coupled to the sensor hub 1240. In at least one embodiment, a thermal sensor 1239, a fan 1237, a keyboard 1236, and a touch pad 1230 can be communicatively coupled to the EC 1235. In at least one embodiment, a speaker 1263, headphones 1264, and a microphone (“mic”) 1265 can be communicatively coupled to an audio unit (“audio codec and class-D amplifier”) 1262, which can in turn be communicatively coupled to the DSP 1260. In at least one embodiment, the audio unit 1262 can include, for example but not limited to, an audio encoder / decoder (“codec”) and a class-D amplifier. In at least one embodiment, a Subscriber Identity Module (“SIM”) 1257 can be communicatively coupled to the WWAN unit 1256. In at least one embodiment, components (such as the WLAN unit 1250, the Bluetooth unit 1252, and the WWAN unit 1256) can be implemented in a next-generation form factor (“NGFF”).

[0276] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 7A and / or Figure 7B to provide details regarding Logic 715. In at least one embodiment, Logic 715 may be used in an electronic device 1200 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0277] In at least one embodiment, Figure 12 at least one component shown or described in is used to implement the techniques and / or functions described in connection with Figures 1 to 6 described. In at least one embodiment, the processor 1215 performs one or more operations involving using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in connection with Figures 1 to 6 described, and as described herein.

[0278] Figure 13 FIG. shows a computer system 1300 according to at least one embodiment. In at least one embodiment, the computer system 1300 is configured to implement the various processes and methods described throughout this disclosure.

[0279] In at least one embodiment, the computer system 1300 includes, but is not limited to, at least one central processing unit (“CPU”) 1302 connected to a communication bus 1310 implemented using any suitable protocol, such as PCI (“Peripheral Component Interconnect”), Peripheral Component Interconnect Express (“PCI-Express”), AGP (“Accelerated Graphics Port”), HyperTransport, or any other bus or point-to-point communication protocol. In at least one embodiment, the computer system 1300 includes, but is not limited to, a main memory 1304 and control logic (e.g., implemented as hardware, software, or a combination thereof), and data is stored in the main memory 1304, which may take the form of random access memory (“RAM”). In at least one embodiment, a network interface subsystem (“network interface”) 1322 provides an interface to other computing devices and networks for receiving data from other systems using the computer system 1300 and for sending data to other systems.

[0280] In at least one embodiment, computer system 1300 includes, but is not limited to, an input device 1308, a parallel processing system 1312, and a display device 1306 in at least one embodiment, which may be implemented using a conventional cathode ray tube (“CRT”), liquid crystal display (“LCD”), light emitting diode (“LED”) display, plasma display, or other suitable display technology. In at least one embodiment, user input is received from the input device 1308 (such as a keyboard, mouse, touchpad, microphone, etc.). In at least one embodiment, each module described herein may be located on a single semiconductor platform to form a processing system.

[0281] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the inference and / or training logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, logic 715 may be used in computer system 1300 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0282] In at least one embodiment, Figure 13 at least one component shown or described in is used to implement the techniques and / or functions described in connection with Figures 1 to 6 In at least one embodiment, computer system 1300 performs one or more operations involving generating one or more software programs having the indicated one or more software program dependencies using information indicating one or more software program dependencies, as described in connection with Figures 1 to 6 and as described herein.

[0283] Figure 14 FIG. shows a computer system 1400 according to at least one embodiment. In at least one embodiment, computer system 1400 includes, but is not limited to, a computer 1410 and a USB drive 1420. In at least one embodiment, computer 1410 may include, but is not limited to, any number and type of processors (not shown) and memories (not shown). In at least one embodiment, computer 1410 includes, but is not limited to, a server, a cloud instance, a laptop computer, and a desktop computer.

[0284] In at least one embodiment, the USB drive 1420 includes, but is not limited to, a processing unit 1430, a USB interface 1440, and USB interface logic 1450. In at least one embodiment, the processing unit 1430 can be any instruction execution system, apparatus, or device capable of executing instructions. In at least one embodiment, the processing unit 1430 can include, but is not limited to, any number and type of processing cores (not shown). In at least one embodiment, the processing unit 1430 includes an application specific integrated circuit (“ASIC”) that is optimized to perform any number and type of operations associated with machine learning. For example, in at least one embodiment, the processing unit 1430 is a tensor processing unit (“TPC”) that is optimized to perform machine learning inference operations. In at least one embodiment, the processing unit 1430 is a vision processing unit (“VPU”) that is optimized to perform machine vision and machine learning inference operations.

[0285] In at least one embodiment, the USB interface 1440 can be any type of USB connector or USB socket. For example, in at least one embodiment, the USB interface 1440 is a USB 3.0 Type-C socket for data and power. In at least one embodiment, the USB interface 1440 is a USB 3.0 Type-A connector. In at least one embodiment, the USB interface logic 1450 can include any number and type of logic that enables the processing unit 1430 to interface with a device (such as computer 1410) via the USB connector 1440.

[0286] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, logic 715 can be used in computer system 1400 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0287] In at least one embodiment, Figure 14 at least one of the components shown or described in Figures 1 to 6 is used to implement the techniques and / or functions described in connection with Figures 1 to 6 In at least one embodiment, computer system 1400 performs one or more operations that involve using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in connection with

[0288] Figure 15AAn exemplary architecture is shown, in which multiple GPUs 1510(1)-1510(N) are communicatively coupled to multiple multi-core processors 1505(1)-1505(M) via high-speed links 1540(1)-1540(N) (e.g., buses, point-to-point interconnects, etc.). In at least one embodiment, the high-speed links 1540(1)-1540(N) support a communication throughput of 4 GB / s, 30 GB / s, 80 GB / s, or higher. In at least one embodiment, various interconnect protocols can be used, including but not limited to PCIe 4.0 or 5.0 and NVLink 2.0. In the various figures, "N" and "M" represent positive integers, and their values can vary from figure to figure. In at least one embodiment, one or more of the multiple GPUs 1510(1)-1510(N) include one or more graphics cores (also simply referred to as "cores") 1800 as Figure 18A and Figure 18B disclosed. In at least one embodiment, one or more graphics cores 1800 can be referred to as streaming multi-processors ("SMs"), stream processors ("SPs"), stream processing units ("SPUs"), compute units ("CUs"), execution units ("EUs"), and / or slices, where a slice in this context can refer to a portion of the processing resources in a processing unit (e.g., 16 cores, ray tracing units, thread directors or schedulers).

[0289] Furthermore, in at least one embodiment, two or more GPUs 1510 are interconnected via high-speed links 1529(1)-1529(2), which can be implemented using a protocol / link similar to or different from the protocol / link used for the high-speed links 1540(1)-1540(N). Similarly, two or more multi-core processors 1505 can be connected via a high-speed link 1528, which can be a symmetric multi-processor (SMP) bus operating at a speed of 20 GB / s, 30 GB / s, 120 GB / s, or higher. Alternatively, similar protocols / links (e.g., via a common interconnect structure) can be used to accomplish Figure 15A all communications between the various system components shown.

[0290] In at least one embodiment, each multi-core processor 1505 is communicatively coupled to a processor memory 1501(1)-1501(M) via a memory interconnect 1526(1)-1526(M), respectively, and each GPU 1510(1)-1510(N) is communicatively coupled to a GPU memory 1520(1)-1520(N) via a GPU memory interconnect 1550(1)-1550(N), respectively. In at least one embodiment, the memory interconnects 1526 and 1550 may utilize similar or different memory access technologies. By way of example and not limitation, the processor memories 1501(1)-1501(M) and the GPU memory 1520 may be volatile memories such as dynamic random access memory (DRAM) (including stacked DRAM), graphics double data rate SDRAM (GDDR) (e.g., GDDR5, GDDR6), or high bandwidth memory (HBM), and / or may be non-volatile memories such as 3D XPoint or Nano-Ram. In at least one embodiment, some portions of the processor memory 1501 may be volatile memory while another portion may be non-volatile memory (e.g., using a two-level memory (2LM) hierarchy).

[0291] As described herein, although the respective multi-core processors 1505 and GPUs 1510 may be physically coupled to specific memories 1501, 1520, respectively, and / or a unified memory architecture may be implemented where a virtual system address space (also referred to as the "effective address" space) is distributed among the respective physical memories. For example, the processor memories 1501(1)-1501(M) may each include 64 GB of system memory address space, and the GPU memories 1520(1)-1520(N) may each include 32 GB of system memory address space, such that when M = 2 and N = 4, a total of 256 GB of addressable memory results. Other values of N and M are possible.

[0292] Figure 15B Additional details of an interconnection between a multi-core processor 1507 and a graphics acceleration module 1546 are shown. In at least one embodiment, the graphics acceleration module 1546 may include one or more GPU chips integrated on a line card that is coupled to the processor 1507 via a high-speed link 1540 (e.g., a PCIe bus, NVLink, etc.). In at least one embodiment, the graphics acceleration module 1546 may alternatively be integrated on a package or chip with the processor 1507.

[0293] In at least one embodiment, the processor 1507 includes multiple cores 1560A - 1560D (which may be referred to as "execution units"), each core having a translation lookaside buffer ("TLB") 1561A - 1561D and one or more caches 1562A - 1562D. In at least one embodiment, the cores 1560A - 1560D may include various other components (not shown) for executing instructions and processing data. In at least one embodiment, the caches 1562A - 1562D may include level 1 (L1) and level 2 (L2) caches. Additionally, one or more shared caches 1556 may be included within the caches 1562A - 1562D and shared by groups of cores 1560A - 1560D. For example, one embodiment of the processor 1507 includes 24 cores, each core having its own L1 cache, 12 shared L2 caches, and 12 shared L3 caches. In this embodiment, two adjacent cores share one or more L2 and L3 caches. In at least one embodiment, the processor 1507 and the graphics acceleration module 1546 are connected to the system memory 1514, which may include Figure 15A processor memories 1501(1) - 1501(M) therein.

[0294] In at least one embodiment, data and instructions stored in the respective caches 1562A - 1562D, 1556, and the system memory 1514 are maintained consistent via the coherence bus 1564 for inter - core communication. In at least one embodiment, for example, each cache may have cache coherence logic / circuit associated therewith to communicate via the coherence bus 1564 in response to detecting a read or write to a particular cache line. In at least one embodiment, a cache snooping protocol is implemented via the coherence bus 1564 to snoop on cache accesses.

[0295] In at least one embodiment, the proxy circuit 1525 communicatively couples the graphics acceleration module 1546 to the coherence bus 1564, thereby allowing the graphics acceleration module 1546 to participate in the cache coherence protocol as a peer of the cores 1560A - 1560D. In particular, in at least one embodiment, the interface 1535 provides a connection to the proxy circuit 1525 via the high - speed link 1540, and the interface 1537 connects the graphics acceleration module 1546 to the high - speed link 1540.

[0296] In at least one embodiment, the accelerator integrated circuit 1536 provides cache management, memory access, context management, and interrupt management services for a plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546. In at least one embodiment, each of the graphics processing engines 1531(1)-1531(N) may include a separate graphics processing unit (GPU). In at least one embodiment, the plurality of graphics processing engines 1531(1)-1531(N) of the graphics acceleration module 1546 includes one or more graphics cores 1800, as discussed in connection with Figure 18A and Figure 18B . In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may alternatively include different types of graphics processing engines within the GPU, such as graphics execution units, media processing engines (e.g., video encoder / decoder), samplers, and blit engines. In at least one embodiment, the graphics acceleration module 1546 may be a GPU having a plurality of graphics processing engines 1531(1)-1531(N), or the graphics processing engines 1531(1)-1531(N) may be individual GPUs integrated on a common package, line card, or chip.

[0297] In at least one embodiment, the accelerator integrated circuit 1536 includes a memory management unit (MMU) 1539 for performing various memory management functions, such as virtual-to-physical memory translation (also known as effective-to-real memory translation), and also includes a memory access protocol for accessing system memory 1514. In at least one embodiment, the MMU 1539 may also include a translation lookaside buffer (“TLB”) (not shown) for caching virtual / effective-to-physical / real address translations. In at least one embodiment, the cache 1538 may store commands and data for efficient access by the graphics processing engines 1531(1)-1531(N). In at least one embodiment, a fetch unit 1544 may be used to keep the data stored in the cache 1538 and the graphics memories 1533(1)-1533(M) consistent with the core caches 1562A-1562D, 1556, and the system memory 1514. As previously described, this may be representative of the cache 1538 and the memories 1533(1)-1533(M) being implemented via the proxy circuit 1525 (e.g., sending updates related to modifications / accesses of cache lines on the processor caches 1562A-1562D, 1556 to the cache 1538 and receiving updates from the cache 1538).

[0298] In at least one embodiment, a set of registers 1545 stores context data for threads executed by the graphics processing engines 1531(1)-1531(N), and a context management circuit 1548 manages thread contexts. For example, the context management circuit 1548 may perform save and restore operations to save and restore the contexts of individual threads during a context switch (e.g., where a first thread is saved and a second thread is stored so that the second thread can be executed by the graphics processing engine). For example, the context management circuit 1548 may store the current register values to a specified area in memory (e.g., identified by a context pointer) during a context switch. Then, the register values can be restored when returning to the context. In at least one embodiment, an interrupt management circuit 1547 receives and processes interrupts received from system devices.

[0299] In at least one embodiment, the MMU 1539 translates virtual / valid addresses from the graphics processing engine 1531 into real / physical addresses in the system memory 1514. In at least one embodiment, the accelerator integrated circuit 1536 supports multiple (e.g., 4, 8, 16) graphics accelerator modules 1546 and / or other accelerator devices. In at least one embodiment, the graphics accelerator module 1546 may be dedicated to a single application executed on the processor 1507 or may be shared among multiple applications. In at least one embodiment, a virtualized graphics execution environment is presented where the resources of the graphics processing engines 1531(1)-1531(N) are shared among multiple applications or virtual machines (VMs). In at least one embodiment, resources may be subdivided into "slices" based on the processing requirements and priorities associated with the VMs and / or applications, and these slices are allocated to different VMs and / or applications.

[0300] In at least one embodiment, the accelerator integrated circuit 1536 acts as a bridge for the system of graphics accelerator modules 1546 and provides address translation and system memory cache services. Additionally, in at least one embodiment, the accelerator integrated circuit 1536 may provide virtualization facilities for the host processor to manage the virtualization, interrupts, and memory management of the graphics processing engines 1531(1)-1531(N).

[0301] In at least one embodiment, since the hardware resources of the graphics processing engines 1531(1)-1531(N) are explicitly mapped to the real address space seen by the host processor 1507, any host processor can directly address these resources using valid address values. In at least one embodiment, one function of the accelerator integrated circuit 1536 is the physical separation of the graphics processing engines 1531(1)-1531(N) such that they appear as independent units to the system.

[0302] In at least one embodiment, one or more graphics memories 1533(1)-1533(M) are coupled to each graphics processing engine 1531(1)-1531(N) respectively, and N = M. In at least one embodiment, the graphics memories 1533(1)-1533(M) store the instructions and data being processed by each graphics processing engine 1531(1)-1531(N). In at least one embodiment, the graphics memories 1533(1)-1533(M) can be volatile memories such as DRAM (including stacked DRAM), GDDR memories (e.g., GDDR5, GDDR6) or HBM, and / or can be non-volatile memories such as 3D XPoint or Nano-Ram.

[0303] In at least one embodiment, to reduce the data traffic on the high-speed link 1540, bias techniques can be used to ensure that the data stored in the graphics memories 1533(1)-1533(M) is the data most frequently used by the graphics processing engines 1531(1)-1531(N), and preferably is data not used (at least not frequently used) by the cores 1560A-1560D. Similarly, in at least one embodiment, the bias mechanism attempts to keep the data required by the cores (and preferably not required by the graphics processing engines 1531(1)-1531(N)) in the caches 1562A-1562D, 1556 and the system memory 1514.

[0304] Figure 15C Another exemplary embodiment is shown, in which the accelerator integrated circuit 1536 is integrated within the processor 1507. In this embodiment, the graphics processing engines 1531(1)-1531(N) communicate directly with the accelerator integrated circuit 1536 via the interface 1537 and the interface 1535 (again, which can be any form of bus or interface protocol) through the high-speed link 1540. In at least one embodiment, the accelerator integrated circuit 1536 can perform operations similar to those described with respect to Figure 15B but may have higher throughput due to its close proximity to the coherence bus 1564 and the caches 1562A-1562D, 1556. In at least one embodiment, the accelerator integrated circuit supports different programming models, which include a process-specific programming model (without graphics acceleration module virtualization) and a shared programming model (with virtualization), and the programming models can include a programming model controlled by the accelerator integrated circuit 1536 and a programming model controlled by the graphics acceleration module 1546.

[0305] In at least one embodiment, the graphics processing engines 1531(1)-1531(N) are dedicated to a single application or process under a single operating system. In at least one embodiment, a single application may funnel requests from other applications to the graphics processing engines 1531(1)-1531(N), thereby providing virtualization within a VM / partition.

[0306] In at least one embodiment, the graphics processing engines 1531(1)-1531(N) may be shared by multiple VM / application partitions. In at least one embodiment, the shared model may use a hypervisor to virtualize the graphics processing engines 1531(1)-1531(N) to allow each operating system to access them. In at least one embodiment, for a single-partition system without a hypervisor, the operating system owns the graphics processing engines 1531(1)-1531(N). In at least one embodiment, the operating system may virtualize the graphics processing engines 1531(1)-1531(N) to provide access to each process or application.

[0307] In at least one embodiment, the graphics acceleration module 1546 or individual graphics processing engines 1531(1)-1531(N) use a process handle to select process elements. In at least one embodiment, the process elements are stored in the system memory 1514 and can be addressed using the effective address to real address translation techniques described herein. In at least one embodiment, the process handle may be an implementation-specific value that is provided to the host process when registering its context with the graphics processing engines 1531(1)-1531(N) (i.e., calling the system software to add a process element to the process element linked list). In at least one embodiment, the lower 16 bits of the process handle may be the offset of the process element in the process element linked list.

[0308] Figure 15DAn exemplary accelerator integrated slice 1590 is shown. In at least one embodiment, a "slice" includes a designated portion of the processing resources of the accelerator integrated circuit 1536. In at least one embodiment, an application is a valid address space 1582 in system memory 1514 that stores process elements 1583. In at least one embodiment, the process elements 1583 are stored in response to a GPU call 1581 from an application 1580 executing on the processor 1507. In at least one embodiment, the process element 1583 contains the process state of the corresponding application 1580. In at least one embodiment, the work descriptor (WD) 1584 contained in the process element 1583 can be a single job requested by the application, or can include a pointer to a job queue. In at least one embodiment, the WD 1584 is a pointer to a job request queue in the valid address space 1582 of the application.

[0309] In at least one embodiment, the graphics acceleration module 1546 and / or the individual graphics processing engines 1531(1)-1531(N) can be shared by all processes or a subset of processes in the system. In at least one embodiment, an infrastructure can be included for setting the process state and sending the WD 1584 to the graphics acceleration module 1546 to start a job in a virtualized environment.

[0310] In at least one embodiment, the process-specific programming model is implementation-specific. In at least one embodiment, in this model, a single process owns the graphics acceleration module 1546 or an individual graphics processing engine 1531. In at least one embodiment, when the graphics acceleration module 1546 is owned by a single process, the hypervisor initializes the accelerator integrated circuit 1536 for the owned partition, and when the graphics acceleration module 1546 is assigned, the operating system initializes the accelerator integrated circuit 1536 for the owned process.

[0311] In at least one embodiment, in operation, the WD fetch unit 1591 in the accelerator integrated slice 1590 fetches the next WD 1584, which includes an indication of work to be completed by one or more graphics processing engines of the graphics acceleration module 1546. In at least one embodiment, data from the WD 1584 may be stored in the register 1545 and used by the MMU 1539, the interrupt management circuit 1547, and / or the context management circuit 1548, as shown. For example, one embodiment of the MMU 1539 includes a segment / page walk circuit for accessing the segment / page table 1586 within the OS virtual address space 1585. In at least one embodiment, the interrupt management circuit 1547 may process the interrupt event 1592 received from the graphics acceleration module 1546. In at least one embodiment, when performing a graphics operation, the effective address 1593 generated by the graphics processing engines 1531(1)-1531(N) is translated to a real address by the MMU 1539.

[0312] In at least one embodiment, the register 1545 is replicated for each graphics processing engine 1531(1)-1531(N) and / or the graphics acceleration module 1546, and the register 1545 may be initialized by a hypervisor or an operating system. In at least one embodiment, each of these replicated registers may be included in the accelerator integrated slice 1590. Exemplary registers that may be initialized by a hypervisor are shown in Table 1.

[0313] Table 1 – Registers Initialized by Hypervisor

[0314]

[0315] Exemplary registers that may be initialized by an operating system are shown in Table 2.

[0316] Table 2 – Registers Initialized by Operating System

[0317]

[0318] In at least one embodiment, each WD 1584 is specific to a particular graphics acceleration module 1546 and / or graphics processing engine 1531(1)-1531(N). In at least one embodiment, it contains all the information required for the graphics processing engines 1531(1)-1531(N) to complete the work, or it may be a pointer to a memory location where the application has set up a command queue for the work to be done.

[0319] Figure 15EAdditional details of an exemplary embodiment of the shared model are shown. This embodiment includes a hypervisor real address space 1598 in which a process element list 1599 is stored. In at least one embodiment, the hypervisor real address space 1598 can be accessed via a hypervisor 1596 that virtualizes a graphics acceleration module engine for an operating system 1595.

[0320] In at least one embodiment, the shared programming model allows all processes or subsets of processes from all partitions or subsets of partitions in the system to use the graphics acceleration module 1546. In at least one embodiment, there are two programming models in which the graphics acceleration module 1546 is shared by multiple processes and partitions, namely time slice sharing and graphics directed sharing.

[0321] In at least one embodiment, in this model, the hypervisor 1596 owns the graphics acceleration module 1546 and makes its functions available to all operating systems 1595. In at least one embodiment, for the graphics acceleration module 1546 to support virtualization through the hypervisor 1596, the graphics acceleration module 1546 may have to comply with certain requirements, such as (1) the job requests of the application must be autonomous (i.e., do not need to maintain state between jobs), or the graphics acceleration module 1546 must provide a context save and restore mechanism, (2) the graphics acceleration module 1546 guarantees that the job requests of the application are completed within a specified amount of time, including any translation errors, or the graphics acceleration module 1546 provides the ability to preempt job processing, and (3) when operating in the directed sharing programming model, it must be ensured that the graphics acceleration module 1546 is fair among processes.

[0322] In at least one embodiment, the application 1580 is required to use a graphics acceleration module type, a work descriptor (WD), a privilege mask register (AMR) value, and a context save / restore area pointer (CSRP) for an operating system 1595 system call. In at least one embodiment, the graphics acceleration module type describes the target acceleration function for the system call. In at least one embodiment, the graphics acceleration module type can be a system-specific value. In at least one embodiment, the WD is formatted specifically for the graphics acceleration module 1546 and can take the form of a graphics acceleration module 1546 command, a valid address pointer to a user-defined structure, a valid address pointer to a command queue, or any other data structure that describes the work to be done by the graphics acceleration module 1546.

[0323] In at least one embodiment, the AMR value is the AMR state for the current process. In at least one embodiment, the value passed to the operating system is similar to the application that sets the AMR. In at least one embodiment, if the implementation of accelerator integrated circuit 1536 (not shown) and graphics acceleration module 1546 does not support the user authority mask override register (UAMOR), the operating system may apply the current UAMOR value to the AMR value before passing the AMR in a hypervisor call. In at least one embodiment, the hypervisor 1596 may selectively apply the current authority mask override register (AMOR) value before placing the AMR in the process element 1583. In at least one embodiment, the CSRP is one of the registers 1545 that contains the effective address of the region in the effective address space 1582 of the application for the graphics acceleration module 1546 to save and restore the context state. In at least one embodiment, the pointer is optional if it is not necessary to save the state between jobs or when a job is preempted. In at least one embodiment, the context save / restore region may be fixed system memory.

[0324] Upon receiving a system call, the operating system 1595 may verify that the application 1580 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the operating system 1595 uses the information shown in Table 3 to call the hypervisor 1596.

[0325] Table 3 – Operating System to Hypervisor Call Parameters

[0326]

[0327] In at least one embodiment, upon receiving a hypervisor call, the hypervisor 1596 verifies that the operating system 1595 has been registered and granted permission to use the graphics acceleration module 1546. Then, in at least one embodiment, the hypervisor 1596 places the process element 1583 in a linked list of process elements of the corresponding graphics acceleration module 1546 type. In at least one embodiment, the process element may include the information shown in Table 4.

[0328] Table 4 – Process Element Information

[0329]

[0330] In at least one embodiment, the hypervisor initializes multiple accelerator integrated slice 1590 registers 1545.

[0331] As Figure 15FAs shown, in at least one embodiment, a unified memory is used, and the unified memory can be addressed via a common virtual memory address space for accessing physical processor memories 1501(1)-1501(N) and GPU memories 1520(1)-1520(N). In this implementation, operations executed on GPUs 1510(1)-1510(N) utilize the same virtual / effective memory address space to access processor memories 1501(1)-1501(M), and vice versa, thus simplifying programmability. In at least one embodiment, a first portion of the virtual / effective address space is allocated to processor memory 1501(1), a second portion is allocated to second processor memory 1501(N), a third portion is allocated to GPU memory 1520(1), and so on. In at least one embodiment, the entire virtual / effective memory space (sometimes referred to as the effective address space) is thus distributed across each of processor memories 1501 and GPU memories 1520, allowing any processor or GPU to access the memory using a virtual address mapped to any physical memory.

[0332] In at least one embodiment, bias / coherency management circuits 1594A-1594E within one or more MMUs 1539A-1539E ensure cache coherency between one or more host processors (e.g., 1505) and the cache of GPU 1510, and implement a bias technique for physical memory indicating where certain types of data should be stored. In at least one embodiment, although multiple instances of bias / coherency management circuits 1594A-1594E are shown Figure 15F in, the bias / coherency circuit can be implemented within the MMU of one or more host processors 1505 and / or within accelerator integrated circuit 1536.

[0333] One embodiment allows the GPU memory 1520 to be mapped as part of the system memory and accessed using shared virtual memory (SVM) techniques without suffering the performance drawbacks associated with full-system cache coherence. In at least one embodiment, the ability of the GPU memory 1520 to be accessed as system memory without heavy cache coherence overhead provides a favorable operating environment for GPU offloading. In at least one embodiment, this arrangement allows the software of the host processor 1505 to set operands and access computation results without the overhead of traditional I / O DMA data copying. In at least one embodiment, such traditional copying includes driver calls, interrupts, and memory-mapped I / O (MMIO) accesses, which are all less efficient than simple memory accesses. In at least one embodiment, the ability to access the GPU memory 1520 without cache coherence overhead can be critical to the execution time of offloaded computations. In at least one embodiment, for example, in the case of a large amount of streaming write memory traffic, the cache coherence overhead can significantly reduce the effective write bandwidth seen by the GPU 1510. In at least one embodiment, the efficiency of operand setting, the efficiency of result access, and the efficiency of GPU computation may play a role in determining the effectiveness of GPU offloading.

[0334] In at least one embodiment, the selection of GPU bias and host processor bias is driven by a bias tracker data structure. In at least one embodiment, for example, a bias table may be used, which may be a page-granularity structure (e.g., controlled at the granularity of memory pages), and this page-granularity structure includes 1 or 2 bits per GPU-attached memory page. In at least one embodiment, with or without a bias cache in the GPU 1510 (e.g., for caching frequently / most recently used entries of the bias table), the bias table may be implemented in the stolen memory ranges of one or more GPU memories 1520. Alternatively, in at least one embodiment, the entire bias table may be maintained within the GPU.

[0335] In at least one embodiment, before actually accessing the GPU memory, the bias table entry associated with each access to the GPU attached memory 1520 is accessed, thereby causing the following operations. In at least one embodiment, a local request from the GPU 1510 that finds its page in the GPU bias is directly forwarded to the corresponding GPU memory 1520. In at least one embodiment, a local request from the GPU that finds its page in the host bias is forwarded to the processor 1505 (e.g., via the high-speed link described herein). In at least one embodiment, a request from the processor 1505 that finds the requested page in the host processor bias completes a request similar to a normal memory read. Alternatively, a request pointing to a GPU bias page can be forwarded to the GPU 1510. In at least one embodiment, if the GPU is not currently using a page, the GPU can migrate the page to the host processor bias. In at least one embodiment, the bias state of a page can be changed by a software-based mechanism, a software mechanism assisted by hardware, or in a limited set of cases by a purely hardware-based mechanism.

[0336] In at least one embodiment, a mechanism for changing the bias state employs an API call (e.g., OpenCL), which in turn calls the device driver of the GPU, which in turn sends a message (or enqueues a command descriptor) to the GPU to direct the GPU to change the bias state and perform a cache flush operation in the host in certain migrations. In at least one embodiment, the cache flush operation is used for migration from the host processor 1505 bias to the GPU bias, but not for the reverse migration.

[0337] In at least one embodiment, cache coherence is maintained by temporarily rendering GPU bias pages that cannot be cached by the host processor 1505. In at least one embodiment, to access these pages, the processor 1505 can request access from the GPU 1510, and the GPU 1510 may or may not immediately grant access. Thus, in at least one embodiment, to reduce communication between the processor 1505 and the GPU 1510, it is beneficial to ensure that the GPU bias pages are pages required by the GPU rather than by the host processor 1505, and vice versa.

[0338] One or more hardware structures 715 are used to implement one or more embodiments. Details regarding one or more hardware structures 715 may be provided herein in combination with Figure 7A and / or Figure 7B provide details regarding one or more hardware structures 715.

[0339] Figure 16Illustrated is an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to what is illustrated, in at least one embodiment, other logic and circuitry may also be included, including additional graphics processors / cores, peripheral interface controllers, or general-purpose processor cores.

[0340] Figure 16 FIG. 4 is a block diagram of an exemplary system on a chip integrated circuit 1600 that may be fabricated using one or more IP cores. In at least one embodiment, integrated circuit 1600 includes one or more application processors 1605 (e.g., CPUs), at least one graphics processor 1610, and may additionally include an image processor 1615 and / or a video processor 1620, any of which may be a modular IP core. In at least one embodiment, integrated circuit 1600 includes peripheral or bus logic, which includes a USB controller 1625, a UART controller 1630, an SPI / SDIO controller 1635, and an I 2 S / I 2 2 C controller 1640. In at least one embodiment, integrated circuit 1600 may include a display device 1645 coupled to one or more of a high-definition multimedia interface (HDMI) controller 1650 and a mobile industry processor interface (MIPI) display interface 1655. In at least one embodiment, storage may be provided by a flash memory subsystem 1660, which includes flash memory and a flash memory controller. In at least one embodiment, a memory interface may be provided via a memory controller 1665 for accessing SDRAM or SRAM memory devices. In at least one embodiment, some integrated circuits also include an embedded security engine 1670.

[0341] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, logic 715 may be in integrated circuit 1600 for inferring or predicting operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0342] In at least one embodiment, Figures 15A to 16 at least one component shown or described in Figures 1 to 6The described technology and / or functionality. In at least one embodiment, the SOC1600 performs one or more operations that involve using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in connection with Figures 1 to 6 as described, and as described herein.

[0343] Figures 17A to 17B Illustrated is an exemplary integrated circuit and associated graphics processor in accordance with various embodiments described herein, which may be fabricated using one or more IP cores. In addition to those illustrated, in at least one embodiment other logic and circuitry may be included, including additional graphics processor(s) / core(s), peripheral interface controllers, or general processor cores.

[0344] Figures 17A to 17B is a block diagram illustrating an exemplary graphics processor used within a SoC in accordance with embodiments described herein. Figure 17A Illustrated is an exemplary graphics processor 1710 of a system-on-chip integrated circuit in accordance with at least one embodiment, which may be fabricated using one or more IP cores. Figure 17B Illustrated is an additional exemplary graphics processor 1740 of a system-on-chip integrated circuit in accordance with at least one embodiment, which may be fabricated using one or more IP cores. In at least one embodiment, Figure 17A the graphics processor 1710 is a low-power graphics processor core. In at least one embodiment, Figure 17B the graphics processor 1740 is a higher-performance graphics processor core. In at least one embodiment, each of the graphics processors 1710, 1740 may be Figure 16 a variant of the graphics processor 1610.

[0345] In at least one embodiment, the graphics processor 1710 includes a vertex processor 1705 and one or more fragment processors 1715A - 1715N (e.g., 1715A, 1715B, 1715C, 1715D to 1715N - 1, and 1715N). In at least one embodiment, the graphics processor 1710 may execute different shader programs via separate logic such that the vertex processor 1705 is optimized to perform operations for vertex shader programs, while the one or more fragment processors 1715A - 1715N perform fragment (e.g., pixel) shading operations for fragment or pixel shader programs. In at least one embodiment, the vertex processor 1705 executes the vertex processing stage of the 3D graphics pipeline and generates primitives and vertex data. In at least one embodiment, the one or more fragment processors 1715A - 1715N use the primitives and vertex data generated by the vertex processor 1705 to produce a frame buffer for display on a display device. In at least one embodiment, the one or more fragment processors 1715A - 1715N are optimized to execute fragment shader programs as provided in the OpenGL API, which can be used to perform operations similar to pixel shader programs provided in the Direct 3D API.

[0346] In at least one embodiment, the graphics processor 1710 additionally includes one or more memory management units (MMUs) 1720A - 1720B, one or more caches 1725A - 1725B, and one or more circuit interconnects 1730A - 1730B. In at least one embodiment, the one or more MMUs 1720A - 1720B provide virtual - to - physical address mapping for the graphics processor 1710 (including for the vertex processor 1705 and / or the fragment processors 1715A - 1715N), which may also reference vertex or image / texture data stored in memory in addition to vertex or image / texture data stored in the one or more caches 1725A - 1725B. In at least one embodiment, the one or more MMUs 1720A - 1720B may be synchronized with other MMUs within the system, including one or more MMUs associated with Figure 16 one or more application processors 1605, image processors 1615, and / or video processors 1620 such that each processor 1605 - 1620 can participate in a shared or unified virtual memory system. In at least one embodiment, the one or more circuit interconnects 1730A - 1730B enable the graphics processor 1710 to interface with other IP cores within the SoC via the internal bus of the SoC or via a direct connection.

[0347] In at least one embodiment, the graphics processor 1740 includes asFigure 17B One or more shader cores 1755A - 1755N (e.g., 1755A, 1755B, 1755C, 1755D, 1755E, 1755F to 1755N - 1 and 1755N) as shown provide a unified shader core architecture where a single core or type of core can execute all types of programmable shader code, including shader program code for implementing vertex shaders, fragment shaders, and / or compute shaders. In at least one embodiment, the number of shader cores can vary. In at least one embodiment, the graphics processor 1740 includes an inter - core task manager 1745 that acts as a thread dispatcher for dispatching execution threads to one or more shader cores 1755A - 1755N and a tiling unit 1758 to accelerate tiling operations for tile - based rendering where the rendering operation of a scene is subdivided in image space, e.g., to exploit local spatial coherence within the scene or optimize the use of internal caches.

[0348] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding Figure 7A and / or Figure 7B are provided. In at least one embodiment, logic 715 can be used in graphics processors 1710 and / or 1740 to perform inference or prediction operations at least in part based on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0349] In at least one embodiment, regarding Figure 17A and Figure 17B at least one of the components shown or described is used to implement the techniques and / or functions described in connection with Figures 1 to 6 described. In at least one embodiment, the graphics processor 1710 performs one or more operations involving using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in connection with Figures 1 to 6 described and as described herein.

[0350] Figures 18A to 18B Additional exemplary graphics processor logic according to embodiments described herein is shown. In at least one embodiment, the components shown in Figures 18A to 18B and described in connection with Figures 18A - 18B are integrated into a single system, such as a graphics processing unit (GPU), a system - on - a - chip (SoC), or another type of processor. In at least one embodiment, Figure 18A shows what can be included in at least one embodiment in Figure 16within the graphics core 1800 of the graphics processor 1610, and in at least one embodiment, the graphics core 1800 can be, for example, the unified shader core 1755A-1755N as shown in Figure 17B Figure 1755A-1755N. Figure 18B Figure 1755A-1755N shows a highly parallel general-purpose graphics processing unit (“GPGPU,” which may also be referred to as a “graphics processing unit”) 1830 suitable for deployment on a multi-chip module in at least one embodiment. In at least one embodiment, the graphics processing unit 1830 is a GPGPU that includes a graphics processor. In at least one embodiment, the integrated circuit 1600 includes the graphics core 1800, for example, for forming an integrated circuit and / or forming an SoC, where such an integrated circuit and / or such an SoC performs the operations described herein.

[0351] In at least one embodiment, the graphics core 1800 includes a shared instruction cache 1802, texture units 1818, and cache / shared memory 1820 (e.g., which includes L1, L2, L3, last-level cache, or other cache) that are shared among the execution resources within the graphics core 1800. In at least one embodiment, the graphics core 1800 may include multiple slices 1801A-1801N or partitions per core, and the graphics processor may include multiple instances of the graphics core 1800. In at least one embodiment, each slice 1801A-1801N refers to the graphics core 1800. In at least one embodiment, the slices 1801A-1801N have sub-slices that are part of the slices 1801A-1801N. In at least one embodiment, the slices 1801A-1801N are independent of or dependent on other slices. In at least one embodiment, the slices 1801A-1801N may include support logic including local instruction caches 1804A-1804N, thread schedulers (orderers) 1806A-1806N, thread dispatchers 1807A-1808N, and a set of registers 1810A-1810N. In at least one embodiment, the slices 1801A-1801N may include a set of additional functional units (AFU 1812A-1812N), floating-point units (FPU 1814A-1814N), integer arithmetic logic units (ALU 1816A-1816N), address calculation units (ACU 1813A-1813N), double-precision floating-point units (DPFPU 1815A-1815N), and matrix processing units (MPU 1817A-1817N). In at least one embodiment, the MPU 1817A-1817N is referred to as a matrix engine.

[0352] In at least one embodiment, each of slices 1801A - 1801N includes one or more engines for floating - point and integer vector operations, and one or more engines for accelerating convolution and matrix operations in AI, machine learning, or large - dataset workloads. In at least one embodiment, one or more of slices 1801A - 1801N include one or more vector engines for computing vectors (e.g., performing mathematical operations on vectors). In at least one embodiment, the vector engines can compute vector operations in 16 - bit floating - point (also known as "FP16"), 32 - bit floating - point (also known as "FP32"), or 64 - bit floating - point (also known as "FP64"). In at least one embodiment, one or more of slices 1801A - 1801N include 16 vector engines that are paired with 16 matrix math units to compute matrix / tensor operations, where the vector engines and math units are exposed via matrix expansion. In at least one embodiment, a slice is a designated portion of the processing resources of a processing unit, e.g., 16 cores and ray - tracing units or 8 cores, a thread scheduler, a thread dispatcher, and additional functional units of a processor. In at least one embodiment, the graphics core 1800 includes one or more matrix engines for computing matrix operations, e.g., when computing tensor operations.

[0353] In at least one embodiment, one or more of slices 1801A - 1801N include one or more ray - tracing units for computing ray - tracing operations (e.g., 16 ray - tracing units per slice 1801A - 1801N). In at least one embodiment, the ray - tracing units compute ray traversal, triangle intersection, bounding - box intersection, or other ray - tracing operations.

[0354] In at least one embodiment, one or more of slices 1801A - 1801N include media slices that encode, decode, and / or transcode data; scale and / or format - convert data; and / or perform video - quality operations on video data.

[0355] In at least one embodiment, one or more slices 1801A - 1801N are linked to an L2 cache and memory structure, a link connector, a high - bandwidth memory (HBM) (e.g., HBM2e, HDM3) stack, and a media engine. In at least one embodiment, one or more slices 1801A - 1801N include a plurality of cores (e.g., 16 cores) paired with each core and a plurality of ray - tracing units (e.g., 16). In at least one embodiment, one or more slices 1801A - 1801N have one or more L1 caches. In at least one embodiment, one or more slices 1801A - 1801N include one or more vector engines; one or more instruction caches for storing instructions; one or more L1 caches for caching data; one or more shared local memories (SLM) (e.g., corresponding to instructions) for storing data; one or more samplers for sampling data; one or more ray - tracing units for performing ray - tracing operations; one or more geometry units for performing operations in a geometry pipeline and / or applying geometric transformations to vertices or polygons; one or more rasterizers for describing an image in a vector - graphics format (e.g., shape) and converting it into a raster image (e.g., a series of pixels, points, or lines that, when displayed together, create an image represented by the shape); one or more hierarchical depth buffers (Hiz) for caching data; and / or one or more pixel back - ends. In at least one embodiment, slices 1801A - 1801N include a memory structure, e.g., an L2 cache.

[0356] In at least one embodiment, FPU 1814A - 1814N can perform single - precision (32 - bit) and half - precision (16 - bit) floating - point operations, while DPFPU 1815A - 1815N performs double - precision (64 - bit) floating - point operations. In at least one embodiment, ALU1816A - 1816N can perform variable - precision integer operations with 8 - bit, 16 - bit, and 32 - bit precision and can be configured for mixed - precision operations. In at least one embodiment, MPU 1817A - 1817N can also be configured for mixed - precision matrix operations, including half - precision floating - point operations and 8 - bit integer operations. In at least one embodiment, MPU1817A - 1817N can perform various matrix operations to accelerate machine - learning application frameworks, including enabling support for accelerated general matrix - to - matrix multiplication (GEMM). In at least one embodiment, AFU 1812A - 1812N can perform additional logical operations not supported by a floating - point unit or an integer unit, including trigonometric operations (e.g., sine, cosine, etc.).

[0357] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This is described in conjunction withFigure 7A and / or Figure 7B Provide details about the logic 715. In at least one embodiment, the logic 715 can be used in the graphics core 1800 for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0358] In at least one embodiment, the graphics core 1800 includes an interconnect and link structure sub-layer attached to a switch and a GPU-GPU bridge that enables multiple graphics processors 1800 (e.g., 8) to be linked to each other using load / store units (LSUs), data transfer units, and synchronization semantics across multiple graphics processors 1800 without glue. In at least one embodiment, the interconnect includes a standardized interconnect (e.g., PCIe) or some combination thereof.

[0359] In at least one embodiment, the graphics core 1800 includes multiple tiles. In at least one embodiment, a tile is an individual die or one or more dies, where each die can be connected using an interconnect (e.g., an Embedded Multi-Die Interconnect Bridge (EMIB)). In at least one embodiment, the graphics core 1800 includes a compute tile, a storage tile (e.g., where the storage tile can be exclusively accessed by different tiles or different chip sets, such as a Rambo tile), a base tile, a foundation tile, an HMB tile, a link tile, and an EMIB tile, where all tiles are encapsulated together in the graphics core 1800 as part of the GPU. In at least one embodiment, the graphics core 1800 can include multiple tiles (also referred to as a "multi-tile package") in a single package. In at least one embodiment, the compute tile can have 8 graphics cores 1800, an L1 cache; and the base tile can have a host interface using PCIe 5.0, HBM2e, MDFI, and EMIB, a link tile with 8 links, and 8 ports with an embedded switch. In at least one embodiment, each tile is connected using fine-pitch 36-micron microbumps (e.g., copper pillars) with face-to-face (F2F) chip bonding. In at least one embodiment, the graphics core 1800 includes a memory structure that includes memory and is accessible by multiple tiles. In at least one embodiment, the graphics core 1800 stores, accesses, or loads its own hardware context in the memory, where the hardware context is a set of data loaded from registers before process restoration, and where the hardware context can indicate the state of the hardware (e.g., the state of the GPU).

[0360] In at least one embodiment, the graphics core 1800 includes serializer / deserializer (SERDES) circuitry that converts a serial data stream to a parallel data stream or a parallel data stream to a serial data stream.

[0361] In at least one embodiment, the graphics core 1800 includes a high-speed coherent unified fabric (GPU-to-GPU), load / store units, bulk data transfer and synchronization semantics, and GPUs connected by an embedded switch, where the GPU-GPU bridge is controlled by a controller.

[0362] In at least one embodiment, the graphics core 1800 executes an API, where the API abstracts the hardware of the graphics core 1800 and utilizes instruction access libraries to perform mathematical operations (e.g., math kernel libraries), deep neural network operations (e.g., deep neural network libraries), vector operations, collective communications, thread building blocks, video processing, data analysis libraries, and / or ray tracing operations.

[0363] In at least one embodiment, Figure 18A at least one component shown or described is used to implement the techniques and / or functions associated with Figures 1 to 6 described. In at least one embodiment, the graphics core 1800 performs one or more operations that involve using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as associated with Figures 1 to 6 described, and as described herein.

[0364] Figure 18BIllustrated is the GPGPU 1830 in at least one embodiment, which can be configured such that highly parallel computing operations can be performed by an array of graphics processing units. In at least one embodiment, the GPGPU 1830 can be directly linked to other instances of the GPGPU 1830 to create a multi-GPU cluster to increase the training speed for deep neural networks. In at least one embodiment, the GPGPU 1830 includes a host interface 1832 for implementing a connection to a host processor. In at least one embodiment, the host interface 1832 is a PCI Express interface. In at least one embodiment, the host interface 1832 can be a vendor-specific communication interface or communication fabric. In at least one embodiment, the GPGPU 1830 receives commands from the host processor and uses a global scheduler 1834 (which can be referred to as a thread sequencer and / or asynchronous computing engine) to assign execution threads associated with those commands to a set of compute clusters 1836A - 1836H. In at least one embodiment, the compute clusters 1836A - 1836H share a cache memory 1838. In at least one embodiment, the cache memory 1838 can be used as a higher-level cache for the cache memories within the compute clusters 1836A - 1836H. In at least one embodiment, the compute clusters 1836A - 1836H include slices or are referred to as "slices". In at least one embodiment, the GPGPU 1830 is part of a SoC, such as part of the integrated circuit 1600( Figure 16 ).

[0365] In at least one embodiment, the GPGPU 1830 includes memories 1844A - 1844B, which are coupled to the compute clusters 1836A - 1836H via a set of memory controllers 1842A - 1842B (e.g., one or more controllers of HBM2e). In at least one embodiment, the memories 1844A - 1844B can include various types of memory devices, which include dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), which includes graphics double data rate (GDDR) memory.

[0366] In at least one embodiment, each of the compute clusters 1836A - 1836H includes a set of graphics cores, such as Figure 18AThe graphics core 1800, which can include various types of integer and floating-point logic units that can perform computational operations over a range of precisions suitable for machine learning computations. For example, in at least one embodiment, at least a subset of the floating-point units in each of the compute clusters 1836A - 1836H can be configured to perform 16-bit or 32-bit floating-point operations, while a different subset of the floating-point units can be configured to perform 64-bit floating-point operations.

[0367] In at least one embodiment, multiple instances of the GPGPU 1830 can be configured to operate as compute clusters. In at least one embodiment, the communication for synchronization and data exchange among the compute clusters 1836A - 1836H varies between embodiments. In at least one embodiment, multiple instances of the GPGPU 1830 communicate via the host interface 1832. In at least one embodiment, the GPGPU 1830 includes an I / O hub 1839 that couples the GPGPU 1830 to a GPU link 1840, which enables a direct connection to other instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a dedicated GPU-to-GPU bridge that enables communication and synchronization among multiple instances of the GPGPU 1830. In at least one embodiment, the GPU link 1840 is coupled to a high-speed interconnect to send and receive data to / from other GPGPUs or parallel processors. In at least one embodiment, multiple instances of the GPGPU 1830 are located in separate data processing systems and communicate via network devices accessible via the host interface 1832. In at least one embodiment, in addition to or in place of the host interface 1832, the GPU link 1840 can also be configured to enable a connection to the host processor.

[0368] In at least one embodiment, the GPGPU 1830 can be configured to train a neural network. In at least one embodiment, the GPGPU 1830 can be used within an inference platform. In at least one embodiment, in the case of using the GPGPU 1830 for inference, the GPGPU 1830 can include fewer compute clusters 1836A - 1836H compared to when using the GPGPU 1830 to train a neural network. In at least one embodiment, the memory technology associated with the memories 1844A - 1844B can differ between inference and training configurations, with higher-bandwidth memory technology dedicated to the training configuration. In at least one embodiment, the inference configuration of the GPGPU 1830 can support inference-specific instructions. For example, in at least one embodiment, the inference configuration can provide support for one or more 8-bit integer dot product instructions that can be used during the inference operations of a deployed neural network.

[0369] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in conjunction with Figure 7A and / or Figure 7B to provide details regarding Logic 715. In at least one embodiment, Logic 715 may be used in GPGPU 1830 to perform inference or prediction operations based at least in part on weight parameters calculated using neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0370] In at least one embodiment, at least one component shown or described with respect to Figure 18B is used to implement the techniques and / or functions described in conjunction with Figures 1 to 8 described. In at least one embodiment, GPGPU 1830 performs one or more operations that involve using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in conjunction with Figures 1 to 6 and as described herein.

[0371] Figure 19 is a block diagram illustrating a computing system 1900 in accordance with at least one embodiment. In at least one embodiment, the computing system 1900 includes a processing subsystem 1901 having one or more processors 1902 and a system memory 1904 communicating via an interconnect path that may include a memory hub 1905. In at least one embodiment, the memory hub 1905 may be a separate component within a chipset component or may be integrated within one or more processors 1902. In at least one embodiment, the memory hub 1905 is coupled to an I / O subsystem 1911 via a communication link 1906. In at least one embodiment, the I / O subsystem 1911 includes an I / O hub 1907 that may enable the computing system 1900 to receive input from one or more input devices 1908. In at least one embodiment, the I / O hub 1907 may enable a display controller to provide output to one or more display devices 1910A, where the display controller may be included within one or more processors 1902. In at least one embodiment, one or more display devices 1910A coupled to the I / O hub 1907 may include local, internal, or embedded display devices.

[0372] In at least one embodiment, the processing subsystem 1901 includes one or more parallel processors 1912 coupled to the memory hub 1905 via a bus or other communication link 1913. In at least one embodiment, the communication link 1913 may use any one of a number of standards based on communication link technologies or protocols (such as but not limited to PCI Express), or may be a vendor-specific communication interface or communication fabric. In at least one embodiment, the one or more parallel processors 1912 form a parallel or vector processing system in a computing center, which may include a large number of processing cores and / or processing clusters, such as an integrated many-core (MIC) processor. In at least one embodiment, some or all of the one or more parallel processors 1912 form a graphics processing subsystem, which may output pixels to one of the one or more display devices 1910A coupled via the I / O hub 1907. In at least one embodiment, the one or more parallel processors 1912 may also include a display controller and a display interface (not shown) for implementing a direct connection to one or more display devices 1910B. In at least one embodiment, the parallel processor 1912 includes one or more cores, such as the graphics core 1800 discussed herein.

[0373] In at least one embodiment, the system storage unit 1914 may be connected to the I / O hub 1907 to provide a storage mechanism for the computing system 1900. In at least one embodiment, the I / O switch 1916 may be used to provide an interface mechanism for implementing connections between the I / O hub 1907 and other components, such as a network adapter 1918 and / or a wireless network adapter 1919 that may be integrated into the platform, and various other devices that may be added via one or more additional devices 1920. In at least one embodiment, the network adapter 1918 may be an Ethernet adapter or another wired network adapter. In at least one embodiment, the wireless network adapter 1919 may include one or more of Wi-Fi, Bluetooth, near field communication (NFC), or other network devices including one or more radio devices.

[0374] In at least one embodiment, the computing system 1900 may include other components not explicitly shown that may also be connected to the I / O hub 1907, including USB or other port connections, optical storage drivers, video capture devices, etc. In at least one embodiment, any suitable protocol (such as a PCI (Peripheral Component Interconnect)-based protocol (e.g., PCI-Express) or other bus or point-to-point communication interface and / or protocol (such as NV-Link high-speed interconnect or interconnect protocol)) may be used to implement the communication paths of the various components. Figure 19 among the components.

[0375] In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for graphics and video processing, the circuitry including, for example, video output circuitry and constituting a graphics processing unit (GPU), such as one or more parallel processors 1912 include a graphics core 1800. In at least one embodiment, one or more parallel processors 1912 include circuitry optimized for general-purpose processing. In at least one embodiment, the components of the computing system 1900 may be integrated with one or more other system elements on a single integrated circuit. For example, in at least one embodiment, one or more parallel processors 1912, a memory hub 1905, one or more processors 1902, and an I / O hub 1907 may be integrated into a system-on-chip (SoC) integrated circuit. In at least one embodiment, the components of the computing system 1900 may be integrated into a single package to form a system-in-package (SIP) configuration. In at least one embodiment, at least a portion of the components of the computing system 1900 may be integrated into a multi-chip module (MCM), which may be interconnected with other multi-chip modules into a modular computing system.

[0376] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, logic 715 may be used in the computing system 1900 for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0377] In at least one embodiment, Figure 19 at least one component shown or described in Figures 1 to 6 is used to implement the techniques and / or functions described in connection with Figures 1 to 6 as described, and as described herein.

[0378] Processor

[0379] Figure 20AFIG. 2000 shows a parallel processor in accordance with at least one embodiment. In at least one embodiment, the various components of the parallel processor 2000 may be implemented using one or more integrated circuit devices, such as programmable processors, application specific integrated circuits (ASICs), or field programmable gate arrays (FPGAs). In at least one embodiment, the illustrated parallel processor 2000 is a variant of one or more of the parallel processors 1912 shown in accordance with an exemplary embodiment. Figure 19 In at least one embodiment, the parallel processor 2000 includes one or more graphics cores 1800.

[0380] In at least one embodiment, the parallel processor 2000 includes a parallel processing unit 2002. In at least one embodiment, the parallel processing unit 2002 includes an I / O unit 2004 that enables communication with other devices, including other instances of the parallel processing unit 2002. In at least one embodiment, the I / O unit 2004 may be directly connected to other devices. In at least one embodiment, the I / O unit 2004 is connected to other devices via a hub or switch interface (e.g., a memory hub 2005). In at least one embodiment, the connection between the memory hub 2005 and the I / O unit 2004 forms a communication link 2013. In at least one embodiment, the I / O unit 2004 is connected to a host interface 2006 and a memory crossbar 2016, where the host interface 2006 receives commands for performing processing operations and the memory crossbar 2016 receives commands for performing memory operations.

[0381] In at least one embodiment, when the host interface 2006 receives a command buffer via the I / O unit 2004, the host interface 2006 may direct the work operations for executing those commands to the front end 2008. In at least one embodiment, the front end 2008 is coupled to a scheduler 2010 (which may be referred to as an orderer), and the scheduler 2010 is configured to allocate commands or other work items to the array of processing clusters 2012. In at least one embodiment, the scheduler 2010 ensures that the array of processing clusters 2012 is properly configured and in an active state before tasks are allocated to the clusters in the array of processing clusters 2012. In at least one embodiment, the scheduler 2010 is implemented via firmware logic executed on a microcontroller. In at least one embodiment, the microcontroller-implemented scheduler 2010 can be configured to perform complex scheduling and work allocation operations at both a coarse-grained and a fine-grained level, enabling fast preemption and context switching of threads executing on the array of processing clusters 2012. In at least one embodiment, the host software may attest to the workload to be scheduled on the array of processing clusters 2012 via one of multiple graphics processing paths. In at least one embodiment, the workload may then be automatically allocated on the array of processing clusters 2012 by the scheduler 2010 logic within the microcontroller including the scheduler 2010.

[0382] In at least one embodiment, the array of processing clusters 2012 may include up to "N" processing clusters (e.g., cluster 2014A, cluster 2014B through cluster 2014N), where "N" represents a positive integer (which may be a different integer "N" than the integer used in other figures). In at least one embodiment, each of the clusters 2014A - 2014N in the array of processing clusters 2012 may execute a large number of concurrent threads. In at least one embodiment, the scheduler 2010 may use various scheduling and / or work allocation algorithms to allocate work to the clusters 2014A - 2014N in the array of processing clusters 2012, and these algorithms may vary depending on the workload generated for each type of program or computation. In at least one embodiment, the scheduling may be handled dynamically by the scheduler 2010, or may be assisted in part by compiler logic during the compilation of the program logic configured to be executed by the array of processing clusters 2012. In at least one embodiment, different clusters 2014A - 2014N in the array of processing clusters 2012 may be assigned to process different types of programs or to perform different types of computations.

[0383] In at least one embodiment, the processing cluster array 2012 can be configured to perform various types of parallel processing operations. In at least one embodiment, the processing cluster array 2012 is configured to perform general-purpose parallel computing operations. For example, in at least one embodiment, the processing cluster array 2012 can include logic for performing processing tasks that include filtering of video and / or audio data, performing modeling operations, including physical operations, and performing data transformations.

[0384] In at least one embodiment, the processing cluster array 2012 is configured to perform parallel graphics processing operations. In at least one embodiment, the processing cluster array 2012 can include additional logic for supporting the execution of such graphics processing operations, including but not limited to texture sampling logic for performing texture operations, and tessellation logic and other vertex processing logic. In at least one embodiment, the processing cluster array 2012 can be configured to execute shader programs related to graphics processing, such as but not limited to vertex shaders, tessellation shaders, geometry shaders, and pixel shaders. In at least one embodiment, the parallel processing unit 2002 can transfer data from the system memory via the I / O unit 2004 for processing. In at least one embodiment, during processing, the transferred data can be stored in on-chip memory (e.g., parallel processor memory 2022) during processing and then written back to the system memory.

[0385] In at least one embodiment, when the parallel processing unit 2002 is used to perform graphics processing, the scheduler 2010 can be configured to divide the processing workload into tasks of approximately equal size to better enable the distribution of graphics processing operations to the multiple clusters 2014A - 2014N in the processing cluster array 2012. In at least one embodiment, portions of the processing cluster array 2012 can be configured to perform different types of processing. For example, in at least one embodiment, the first portion can be configured to perform vertex shading and topology generation, the second portion can be configured to perform tessellation and geometry shading, and the third portion can be configured to perform pixel shading or other screen space operations to produce a rendered image for display. In at least one embodiment, intermediate data generated by one or more of the clusters 2014A - 2014N can be stored in a buffer to allow the transfer of intermediate data between the clusters 2014A - 2014N for further processing.

[0386] In at least one embodiment, the processing cluster array 2012 can receive processing tasks to be executed via the scheduler 2010, which receives commands defining the processing tasks from the front end 2008. In at least one embodiment, the processing tasks can include an index of the data to be processed, e.g., surface (patch) data, raw data, vertex data, and / or pixel data, as well as status parameters and commands defining how to process the data (e.g., what program to execute). In at least one embodiment, the scheduler 2010 can be configured to obtain an index corresponding to the task, or can receive the index from the front end 2008. In at least one embodiment, the front end 2008 can be configured to ensure that the processing cluster array 2012 is configured in a valid state before starting the workload specified by the incoming command buffer (e.g., batch-buffer, push buffer, etc.).

[0387] In at least one embodiment, each of one or more instances of the parallel processing unit 2002 can be coupled to the parallel processor memory 2022. In at least one embodiment, the parallel processor memory 2022 can be accessed via the memory crossbar 2016, which can receive memory requests from the processing cluster array 2012 as well as the I / O unit 2004. In at least one embodiment, the memory crossbar 2016 can access the parallel processor memory 2022 via the memory interface 2018. In at least one embodiment, the memory interface 2018 can include a plurality of partitioning units (e.g., partitioning unit 2020A, partitioning unit 2020B to partitioning unit 2020N), each of which can be coupled to a portion (e.g., memory unit) of the parallel processor memory 2022. In at least one embodiment, the number of partitioning units 2020A-2020N is configured to be equal to the number of memory units, such that the first partitioning unit 2020A has a corresponding first memory unit 2024A, the second partitioning unit 2020B has a corresponding second memory unit 2024B, and the Nth partitioning unit 2020N has a corresponding Nth memory unit 2024N. In at least one embodiment, the number of partitioning units 2020A-2020N may not be equal to the number of memory units.

[0388] In at least one embodiment, the memory units 2024A - 2024N can include various types of memory devices, including dynamic random access memory (DRAM) or graphics random access memory, such as synchronous graphics random access memory (SGRAM), including graphics double data rate (GDDR) memory. In at least one embodiment, the memory units 2024A - 2024N can also include 3D stacked memory, including but not limited to high bandwidth memory (HBM), HBM2e, HBM3. In at least one embodiment, rendering targets such as frame buffers or texture maps can be stored across the memory units 2024A - 2024N, allowing the partitioning units 2020A - 2020N to write portions of each rendering target in parallel to efficiently utilize the available bandwidth of the parallel processor memory 2022. In at least one embodiment, local instances of the parallel processor memory 2022 can be excluded in favor of a unified memory design that utilizes system memory as well as local cache memory.

[0389] In at least one embodiment, any one of the clusters 2014A - 2014N in the cluster array 2012 of processing clusters can process data to be written into any of the memory units 2024A - 2024N within the parallel processor memory 2022. In at least one embodiment, the memory crossbar 2016 can be configured to transfer the output of each cluster 2014A - 2014N to any of the partitioning units 2020A - 2020N or to another cluster 2014A - 2014N, and the other cluster 2014A - 2014N can perform additional processing operations on the output. In at least one embodiment, each cluster 2014A - 2014N can communicate with the memory interface 2018 through the memory crossbar 2016 to read from or write to various external memory devices. In at least one embodiment, the memory crossbar 2016 has a connection to the memory interface 2018 for communicating with the I / O unit 2004, as well as a connection to a local instance of the parallel processor memory 2022, which enables processing units within different processing clusters 2014A - 2014N to communicate with system memory or other memory that is not local to the parallel processing units 2002. In at least one embodiment, the memory crossbar 2016 can use virtual channels to separate the traffic flow between the clusters 2014A - 2014N and the partitioning units 2020A - 2020N.

[0390] In at least one embodiment, multiple instances of the parallel processing unit 2002 may be provided on a single add-in card, or multiple add-in cards may be interconnected. In at least one embodiment, different instances of the parallel processing unit 2002 may be configured to operate with each other even if the different instances have different numbers of processing cores, different numbers of local parallel processor memories, and / or other configuration differences. For example, in at least one embodiment, some instances of the parallel processing unit 2002 may include floating-point units with higher precision relative to other instances. In at least one embodiment, a system including one or more instances of the parallel processing unit 2002 or the parallel processor 2000 may be implemented in various configurations and form factors, including but not limited to desktop computers, laptop computers, or handheld personal computers, servers, workstations, game consoles, and / or embedded systems.

[0391] Figure 20B is a block diagram of a partitioning unit 2020 according to at least one embodiment. In at least one embodiment, the partitioning unit 2020 is Figure 20A an instance of one of the partitioning units 2020A - 2020N. In at least one embodiment, the partitioning unit 2020 includes an L2 cache 2021, a frame buffer interface 2025, and a ROP 2026 (raster operation unit). In at least one embodiment, the L2 cache 2021 is a read / write cache that is configured to perform load and store operations received from the memory crossbar 2016 and the ROP 2026. In at least one embodiment, the L2 cache 2021 outputs read misses and urgent write-back requests to the frame buffer interface 2025 for processing. In at least one embodiment, updates may also be sent to the frame buffer via the frame buffer interface 2025 for processing. In at least one embodiment, the frame buffer interface 2025 interfaces with one of the memory units (such as Figure 20A the memory units 2024A - 2024N (e.g., within the parallel processor memory 2022)) of

[0392] In at least one embodiment, the ROP 2026 is a processing unit that performs raster operations such as stencil, z-test, blending, etc. In at least one embodiment, the ROP 2026 then outputs the processed graphics data stored in the graphics memory. In at least one embodiment, the ROP 2026 includes compression logic for compressing depth or color data written to the memory and decompressing depth or color data read from the memory. In at least one embodiment, the compression logic can be lossless compression logic that utilizes one or more of a variety of compression algorithms. In at least one embodiment, the type of compression performed by the ROP 2026 can vary based on the statistical characteristics of the data to be compressed. For example, in at least one embodiment, delta color compression is performed on depth and color data per tile.

[0393] In at least one embodiment, the ROP 2026 is included within each processing cluster (e.g., Figure 20A clusters 2014A - 2014N), rather than within the partitioning unit 2020. In at least one embodiment, read and write requests for pixel data rather than pixel fragment data are transmitted through the memory crossbar 2016. In at least one embodiment, the processed graphics data can be displayed on a display device (such as Figure 19 one of one or more display devices 1910), routed by the processor 1902 for further processing, or routed by Figure 20A one of the processing entities within the parallel processor 2000 of

[0394] Figure 20C is a block diagram of a processing cluster 2014 within a parallel processing unit according to at least one embodiment. In at least one embodiment, the processing cluster is Figure 20A an instance of one of the processing clusters 2014A - 2014N. In at least one embodiment, the processing cluster 2014 can be configured to execute many threads in parallel, where a "thread" refers to an instance of a particular program executed on a particular set of input data. In at least one embodiment, single instruction multiple data (SIMD) instruction issue techniques are used to support the parallel execution of a large number of threads without providing multiple independent instruction units. In at least one embodiment, single instruction multiple thread (SIMT) techniques are used to support the parallel execution of a large number of generally synchronized threads using a common instruction unit that is configured to issue instructions to a set of processing engines within each processing cluster.

[0395] In at least one embodiment, the operation of the processing cluster 2014 can be controlled via a pipeline manager 2032 that assigns processing tasks to the SIMT parallel processor. In at least one embodiment, the pipeline manager 2032 receives from Figure 20AThe scheduler 2010 receives instructions and manages the execution of these instructions via the graphics multiprocessor 2034 and / or the texture unit 2036. In at least one embodiment, the graphics multiprocessor 2034 is an exemplary instance of a SIMT parallel processor. However, in at least one embodiment, various types of SIMT parallel processors of different architectures may be included within the processing cluster 2014. In at least one embodiment, one or more instances of the graphics multiprocessor 2034 may be included within the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 may process data, and the data crossbar 2040 may be used to distribute the processed data to one of multiple possible destinations (including other shader units). In at least one embodiment, the pipeline manager 2032 may facilitate the distribution of the processed data by specifying the destination of the processed data to be distributed via the data crossbar 2040.

[0396] In at least one embodiment, each graphics multiprocessor 2034 within the processing cluster 2014 may include the same set of functional execution logic (e.g., arithmetic logic units, load-store units, etc.). In at least one embodiment, the functional execution logic may be configured in a pipelined manner, where new instructions may be issued before the previous instructions are completed. In at least one embodiment, the functional execution logic supports various operations, including integer and floating-point arithmetic, comparison operations, boolean operations, bit shifting, and the calculation of various algebraic functions. In at least one embodiment, the same functional unit hardware may be utilized to perform different operations, and any combination of functional units may exist.

[0397] In at least one embodiment, the instructions transmitted to the processing cluster 2014 constitute threads. In at least one embodiment, a set of threads executed across a set of parallel processing engines is a thread group. In at least one embodiment, the thread group executes a general program on different input data. In at least one embodiment, each thread within the thread group may be assigned to a different processing engine within the graphics multiprocessor 2034. In at least one embodiment, the thread group may include fewer threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the thread group includes fewer threads than the number of processing engines, one or more processing engines may be idle during the cycle of processing the thread group. In at least one embodiment, the thread group may also include more threads than the number of processing engines within the graphics multiprocessor 2034. In at least one embodiment, when the thread group includes more threads than the number of processing engines within the graphics multiprocessor 2034, processing may be performed in consecutive clock cycles. In at least one embodiment, multiple thread groups may be executed concurrently on the graphics multiprocessor 2034.

[0398] In at least one embodiment, the graphics multiprocessor 2034 includes an internal cache memory for performing load and store operations. In at least one embodiment, the graphics multiprocessor 2034 can forgo the internal cache and use the cache memory within the processing cluster 2014 (e.g., the L1 cache 2048). In at least one embodiment, each graphics multiprocessor 2034 can also access the L2 cache within the partition units (e.g., Figure 20A the partition units 2020A - 2020N) of Figure 20A , which are shared among all the processing clusters 2014 and can be used to transfer data between threads. In at least one embodiment, the graphics multiprocessor 2034 can also access off-chip global memory, which can include one or more of local parallel processor memory and / or system memory. In at least one embodiment, any memory external to the parallel processing unit 2002 can be used as global memory. In at least one embodiment, the processing cluster 2014 includes multiple instances of the graphics multiprocessor 2034, which can share common instructions and data that can be stored in the L1 cache 2048.

[0399] In at least one embodiment, each processing cluster 2014 can include a memory management unit (“MMU”) 2045 configured to map virtual addresses to physical addresses. In at least one embodiment, one or more instances of the MMU 2045 can reside within Figure 20A the memory interface 2018 of Figure 20A . In at least one embodiment, the MMU 2045 includes a set of page table entries (PTEs) for mapping virtual addresses to the physical addresses of tiles and optionally to cache line indices. In at least one embodiment, the MMU 2045 can include a translation lookaside buffer (TLB) or a cache that can reside within the graphics multiprocessor 2034 or the L1 cache 2048 or the processing cluster 2014. In at least one embodiment, the physical addresses are processed to allocate surface data access locality for efficient request interleaving between partition units. In at least one embodiment, the cache line index can be used to determine whether a request to a cache line is a hit or a miss.

[0400] In at least one embodiment, the processing cluster 2014 can be configured such that each graphics multiprocessor 2034 is coupled to a texture unit 2036 to perform a texture mapping operation that determines texture sample positions, reads texture data, and filters the texture data. In at least one embodiment, texture data is read, as needed, from an internal texture L1 cache (not shown) or from an L1 cache within the graphics multiprocessor 2034, and texture data is fetched from an L2 cache, local parallel processor memory, or system memory. In at least one embodiment, each graphics multiprocessor 2034 outputs the processed task to a data crossbar 2040 to provide the processed task to another processing cluster 2014 for further processing or to store the processed task in an L2 cache, local parallel processor memory, or in system memory via a memory crossbar 2016. In at least one embodiment, the preROP 2042 (pre-raster operation unit) is configured to receive data from the graphics multiprocessor 2034 and direct the data to a ROP unit that can be located together with the partitioning units (e.g., Figure 20A partitioning units 2020A - 2020N) described herein. In at least one embodiment, the PreROP 2042 unit can perform optimizations for color blending, organizing pixel color data, and performing address translation.

[0401] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, the logic 715 can be used in the graphics processing cluster 2014 to perform inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0402] In at least one embodiment, Figures 20A to 20C at least one component shown or described in Figures 1 to 6 is used to implement the techniques and / or functions described in connection with Figures 1 to 6 as described, and as described herein.

[0403] Figure 20DShows a graphics multiprocessor 2034 according to at least one embodiment. In at least one embodiment, the graphics multiprocessor 2034 is coupled to the pipeline manager 2032 of the processing cluster 2014. In at least one embodiment, the graphics multiprocessor 2034 has an execution pipeline that includes, but is not limited to, an instruction cache 2052, an instruction unit 2054, an address mapping unit 2056, a register file 2058, one or more general-purpose graphics processing unit (GPGPU) cores 2062, and one or more load / store units 2066, where one or more load / store units 2066 can perform load / store operations to load / store instructions corresponding to the execution operations. In at least one embodiment, the GPGPU cores 2062 and the load / store units 2066 are coupled to a cache memory 2072 and a shared memory 2070 via a memory and cache interconnect 2068. In at least one embodiment, the GPGPU cores 2062 are part of a SoC, such as Figure 16 part of the integrated circuit 1600 in

[0404] In at least one embodiment, the instruction cache 2052 receives a stream of instructions to be executed from the pipeline manager 2032. In at least one embodiment, the instructions are cached in the instruction cache 2052 and dispatched for execution by the instruction unit 2054. In at least one embodiment, the instruction unit 2054 can dispatch instructions as a thread group (e.g., a warp, a wavefront, a wave), where each thread in the thread group is assigned to a different execution unit within the GPGPU core 2062. In at least one embodiment, instructions can access any local, shared, or global address space by specifying an address within a unified address space. In at least one embodiment, the address mapping unit 2056 can be used to convert an address in the unified address space into a different memory address that can be accessed by the load / store units 2066.

[0405] In at least one embodiment, the register file 2058 provides a set of registers for the functional units of the graphics multiprocessor 2034. In at least one embodiment, the register file 2058 provides temporary storage for the operands of the data paths of the functional units (e.g., the GPGPU cores 2062, the load / store units 2066) connected to the graphics multiprocessor 2034. In at least one embodiment, the register file 2058 is divided among each functional unit such that a dedicated portion of the register file 2058 is allocated to each functional unit. In at least one embodiment, the register file 2058 is divided among different warps (which can be referred to as wavefronts and / or waves) being executed by the graphics multiprocessor 2034.

[0406] In at least one embodiment, each of the GPGPU cores 2062 may include a floating-point unit (FPU) and / or an integer arithmetic logic unit (ALU) for executing instructions of the graphics multiprocessor 2034. In at least one embodiment, the architectures of the respective GPGPU cores 2062 may be similar or may be different. In at least one embodiment, a first portion of the GPGPU core 2062 includes a single-precision FPU and an integer ALU, while a second portion of the GPGPU core includes a double-precision FPU. In at least one embodiment, the FPU may implement the IEEE 754-2008 standard for floating-point algorithms or enable variable-precision floating-point algorithms. In at least one embodiment, the graphics multiprocessor 2034 may additionally include one or more fixed-function or special-function units for performing specific functions such as copy rectangle or pixel blend operations. In at least one embodiment, one or more of the GPGPU cores 2062 may also include fixed or special-function logic.

[0407] In at least one embodiment, the GPGPU core 2062 includes SIMD logic capable of executing a single instruction on multiple sets of data. In at least one embodiment, the GPGPU core 2062 may physically execute SIMD4, SIMD8, and SIMD16 instructions and logically execute SIMD1, SIMD2, and SIMD32 instructions. In at least one embodiment, the SIMD instructions for the GPGPU core may be generated by a shader compiler at compile time or automatically generated when executing a program written and compiled for a single-program multiple-data (SPMD) or SIMT architecture. In at least one embodiment, multiple threads of a program configured for the SIMT execution model may be executed via a single SIMD instruction. For example, in at least one embodiment, eight SIMT threads performing the same or similar operations may be executed in parallel via a single SIMD8 logic unit.

[0408] In at least one embodiment, the memory and cache interconnect 2068 is an interconnect network that connects each functional unit of the graphics multiprocessor 2034 to the register file 2058 and the shared memory 2070. In at least one embodiment, the memory and cache interconnect 2068 is a crossbar interconnect that allows the load / store unit 2066 to perform load and store operations between the shared memory 2070 and the register file 2058. In at least one embodiment, the register file 2058 can operate at the same frequency as the GPGPU core 2062, resulting in a very low latency for data transfer between the GPGPU core 2062 and the register file 2058. In at least one embodiment, the shared memory 2070 can be used to enable communication between threads executing on the functional units within the graphics multiprocessor 2034. In at least one embodiment, the cache memory 2072 can be used as, for example, a data cache for caching texture data communicated between the functional units and the texture unit 2036. In at least one embodiment, the shared memory 2070 can also be used as a program-managed cache. In at least one embodiment, in addition to the automatically cached data stored in the cache memory 2072, threads executing on the GPGPU core 2062 can also programmatically store data in the shared memory.

[0409] In at least one embodiment, a parallel processor or GPGPU as described herein is communicatively coupled to a host / processor core to accelerate graphics operations, machine learning operations, pattern analysis operations, and various general-purpose GPU (GPGPU) functions. In at least one embodiment, the GPU can be communicatively coupled to the host processor / core via a bus or other interconnect (e.g., a high-speed interconnect such as PCIe or NVLink). In at least one embodiment, the SoC includes a parallel processor or GPGPU as described herein, where the parallel processor or the GPGPU is executed on the SoC. In at least one embodiment, the GPU can be integrated with the core in a package or on a chip and communicatively coupled to the core via an internal processor bus / interconnect within the package or chip. In at least one embodiment, regardless of how the GPU is connected, the processor core can allocate work to the GPU in the form of a sequence of commands / instructions contained in a work descriptor. In at least one embodiment, the GPU then uses dedicated circuitry / logic to efficiently process these commands / instructions.

[0410] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. This is described herein in connection with Figure 7A and / or Figure 7BProvide details regarding logic 715. In at least one embodiment, logic 715 may be used in the graphics multiprocessor 2034 for performing inference or prediction operations based at least in part on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0411] In at least one embodiment, Figure 20D at least one of the components shown or described is used to implement the techniques and / or functions associated with Figures 1 to 6 described. In at least one embodiment, the graphics multiprocessor 2034 performs one or more operations that involve using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in conjunction with Figures 1 to 6 described, and as described herein.

[0412] Figure 21FIG. 2100 shows a multi-GPU computing system 2100 according to at least one embodiment. In at least one embodiment, the multi-GPU computing system 2100 may include a processor 2102 coupled to a plurality of general-purpose graphics processing units (GPGPUs) 2106A-D via a host interface switch 2104. In at least one embodiment, the host interface switch 2104 is a PCI Express switch device that couples the processor 2102 to a PCI Express bus, and the processor 2102 may communicate with the GPGPUs 2106A-D via the PCI Express bus. In at least one embodiment, the GPGPUs 2106A-D may be interconnected via a set of high-speed P2P (peer-to-peer) GPU-to-GPU links 2116. In at least one embodiment, the GPU-to-GPU link 2116 is connected to each of the GPGPUs 2106A-D via a dedicated GPU link. In at least one embodiment, the P2P GPU link 2116 enables direct communication between each of the GPGPUs 2106A-D without communicating through the host interface bus 2104 to which the processor 2102 is connected. In at least one embodiment, in the case where GPU-to-GPU traffic is directed to the P2P GPU link 2116, the host interface bus 2104 remains available for system memory access or for communicating with other instances of the multi-GPU computing system 2100 via, for example, one or more network devices. Although in at least one embodiment, the GPGPUs 2106A-D are connected to the processor 2102 via the host interface switch 2104, in at least one embodiment, the processor 2102 includes direct support for the P2P GPU link 2116 and may be directly connected to the GPGPUs 2106A-D. In at least one embodiment, the GPGPUs 2106A-D are part of a SoC, such as Figure 16 part of the integrated circuit 1600 in, where the GPGPUs 2106A-D perform the operations described herein.

[0413] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding the logic 715 are provided herein in connection with Figure 7A and / or Figure 7B In at least one embodiment, the logic 715 may be used in the multi-GPU computing system 2100 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0414] In at least one embodiment, the multi-GPU computing system 2100 includes one or more graphics cores 1800.

[0415] In at least one embodiment, Figure 21 at least one component shown or described in is used to implement the techniques and / or functions associated with Figures 1 to 6 described. In at least one embodiment, the processor 2102 performs one or more operations that involve using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as associated with Figures 1 to 6 described, and as described herein.

[0416] Figure is a block diagram of a graphics processor 2200 according to at least one embodiment. In at least one embodiment, the graphics processor 2200 includes a ring interconnect 2202, a pipeline front end 2204, a media engine 2237, and graphics cores 2280A - 2280N. In at least one embodiment, the ring interconnect 2202 couples the graphics processor 2200 to other processing units, which include other graphics processors or one or more general - purpose processor cores. In at least one embodiment, the graphics processor 2200 is one of many processors integrated within a multi - core processing system. In at least one embodiment, the graphics processor 2200 includes a graphics core 1800.

[0417] In at least one embodiment, the graphics processor 2200 receives multiple batches of commands via the ring interconnect 2202. In at least one embodiment, the input commands are interpreted by a command streamer 2203 in the pipeline front end 2204. In at least one embodiment, the graphics processor 2200 includes scalable execution logic for performing 3D geometry processing and media processing via the graphics cores 2280A - 2280N. In at least one embodiment, for 3D geometry processing commands, the command streamer 2203 provides the commands to the geometry pipeline 2236. In at least one embodiment, for at least some media processing commands, the command streamer 2203 provides the commands to a video front end 2234, which is coupled to the media engine 2237. In at least one embodiment, the media engine 2237 includes a video quality engine (VQE) 2230 for video and image post - processing, and a multi - format encoding / decoding (MFX) 2233 engine for providing hardware - accelerated encoding and decoding of media data. In at least one embodiment, the geometry pipeline 2236 and the media engine 2237 each generate execution threads for thread execution resources provided by at least one graphics core 2280.

[0418] In at least one embodiment, the graphics processor 2200 includes scalable thread execution resources featuring graphics cores 2280A - 2280N (which may be modular and sometimes referred to as core slices), each graphics core having multiple sub - cores 2250A - 2250N, 2260A - 2260N (sometimes referred to as core sub - slices). In at least one embodiment, the graphics processor 2200 may have any number of graphics cores 2280A. In at least one embodiment, the graphics processor 2200 includes a graphics core 2280A having at least a first sub - core 2250A and a second sub - core 2260A. In at least one embodiment, the graphics processor 2200 is a low - power processor having a single sub - core (e.g., 2250A). In at least one embodiment, the graphics processor 2200 includes multiple graphics cores 2280A - 2280N, each graphics core including a set of first sub - cores 2250A - 2250N and a set of second sub - cores 2260A - 2260N. In at least one embodiment, each of the first sub - cores 2250A - 2250N includes at least a first set of execution units 2252A - 2252N and media / texture samplers 2254A - 2254N. In at least one embodiment, each of the second sub - cores 2260A - 2260N includes at least a second set of execution units 2262A - 2262N and samplers 2264A - 2264N. In at least one embodiment, each of the sub - cores 2250A - 2250N, 2260A - 2260N shares a set of shared resources 2270A - 2270N. In at least one embodiment, the shared resources include shared cache memory and pixel operation logic. In at least one embodiment, the graphics processor 2200 includes load / store units in the pipeline front - end 2204.

[0419] Logic 715 is used to perform inference and / or training operations associated with one or more embodiments. Details regarding logic 715 are provided herein in connection with ​ and / or ​ In at least one embodiment, logic 715 may be used in the graphics processor 2200 to perform inference or prediction operations at least in part based on weight parameters calculated using the neural network training operations, neural network functions, and / or architectures, or neural network use cases described herein.

[0420] In at least one embodiment, ​ at least one component shown or described in ​The described technology and / or functionality. In at least one embodiment, the graphics processor 2200 performs one or more operations that involve using information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies, as described in conjunction with Figures 1 to 6 as described, and as described herein.

[0421] Figure 23 is a block diagram showing a microarchitecture for a processor 2300 according to at least one embodiment. The processor 2300 may include logic circuitry for executing instructions. In at least one embodiment, the processor 2300 may execute instructions, including x86 instructions, ARM instructions, special instructions for application specific integrated circuits (ASICs), etc. In at least one embodiment, the processor 2300 may include registers for storing packed data, such as the 64-bit wide MMX TM registers in a microprocessor implemented with Intel Corporation's MMX technology in Santa Clara, California. In at least one embodiment, the MMX registers available in both integer and floating-point forms may operate with packed data elements that accompany single instruction multiple data (“SIMD”) and streaming SIMD extensions (“SSE”) instructions. In at least one embodiment, the 128-bit wide XMM registers associated with SSE2, SSE3, SSE4, AVX, or beyond (commonly referred to as “SSEx”) technology may hold such packed data operands. In at least one embodiment, the processor 2300 may execute instructions that accelerate machine learning or deep learning algorithms, training, or inference.

[0422] In at least one embodiment, the processor 2300 includes an in-order front end (“front end”) 2301 for fetching instructions to be executed and preparing the instructions for later use in the processor pipeline. In at least one embodiment, the front end 2301 may include a number of units. In at least one embodiment, the instruction prefetcher 2326 fetches instructions from memory and feeds the instructions to the instruction decoder 2328, which in turn decodes or interprets the instructions. For example, in at least one embodiment, the instruction decoder 2328 decodes the received instructions into one or more operations of so-called “micro-operations” or “micro-instructions” (also referred to as “micro ops” or “uops” or “μ-ops”) that are machine-executable. In at least one embodiment, the instruction decoder 2328 parses the instruction into an opcode and corresponding data and control fields, which may be used by the microarchitecture to perform operations according to at least one embodiment. In at least one embodiment, the trace cache 2330 may assemble the decoded micro-operations into a program-ordered sequence or trace in the micro-operation queue 2334 for execution. In at least one embodiment, when the trace cache 2330 encounters a complex instruction, the microcode ROM 2332 provides the micro-operations required to complete the operation.

[0423] In at least one embodiment, some instructions may be converted into a single micro-operation, while other instructions require several micro-operations to complete the entire operation. In at least one embodiment, if more than four micro-operations are required to complete an instruction, the instruction decoder 2328 may access the microcode ROM 2332 to execute the instruction. In at least one embodiment, instructions may be decoded into a small number of micro-operations for processing at the instruction decoder 2328. In at least one embodiment, if multiple micro-operations are required to complete the operation, the instruction may be stored in the microcode ROM 2332. In at least one embodiment, the trace cache 2330 references an entry point programmable logic array (“PLA”) to determine the correct micro-instruction pointer for reading a microcode sequence from the microcode ROM 2332 to complete one or more instructions according to at least one embodiment. In at least one embodiment, after the microcode ROM 2332 finishes serializing the micro-operations for an instruction, the front end 2301 of the machine may resume fetching micro-operations from the trace...

Claims

1. A processor, comprising: One or more circuits for causing one or more neural networks to use information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies.

2. The processor according to claim 1, wherein, The one or more software program dependencies include dependencies between different levels within a code hierarchy, wherein the different levels of the code hierarchy include at least one of one or more namespaces, one or more modules, one or more classes, one or more functions, or one or more lines of code.

3. The processor according to claim 1, wherein, The information indicating the one or more software program dependencies is included in a document provided as an input to the one or more neural networks.

4. The processor according to claim 1, wherein, The one or more circuits are for encoding the information and previously generated code for the one or more software programs.

5. The processor according to claim 1, wherein, The one or more circuits are for retrieving additional information from a first code library and a second code library using a plurality of encoders and encoding the additional information as one or more indexes.

6. The processor according to claim 1, wherein, The one or more circuits are for causing the one or more neural networks to attend to a first set of tokens and a second set of tokens individually and in combination, wherein the first set of tokens are code tokens under a first level of a code hierarchy in previously generated code, and the second set of tokens are description tokens under a second level of the code hierarchy.

7. The processor according to claim 1, wherein The one or more circuits are for jointly training the one or more neural networks and the plurality of encoders in a retrieval block based at least in part on a balance between a retrieval loss and an autoregressive loss.

8. A system, comprising: One or more processors for causing one or more neural networks to use information indicating one or more software program dependencies to generate one or more software programs having the indicated one or more software program dependencies.

9. The system according to claim 8, wherein, The one or more software program dependencies include dependencies between different levels within a code hierarchy, wherein the different levels of the code hierarchy include at least one namespace.

10. The system according to claim 8, wherein, The information indicating the one or more software program dependencies is included in one or more documents that specify at least one of a technical design or a functional design of the one or more software programs.

11. The system according to claim 8, wherein, The one or more processors are for causing the one or more neural networks to receive the information as an initial input and receive generated code in response to the initial input as an additional input.

12. The system according to claim 8, wherein, The one or more processors are for causing the one or more neural networks to retrieve additional information from a code library stored at a location external to the system.

13. The system according to claim 8, wherein, The one or more processors are for causing the one or more neural networks to attend to multiple levels in a code hierarchy in previously generated code for the one or more software programs in a pairwise sequential manner.

14. The system according to claim 8, wherein, The one or more processors are used to jointly train the one or more neural networks and the plurality of encoders based at least in part on a balance between a retrieval loss and an autoregressive loss.

15. A method, comprising: causing one or more neural networks to generate one or more software programs having the indicated one or more software program dependencies using information indicating the one or more software program dependencies.

16. The method according to claim 15, wherein, The one or more software program dependencies include dependencies between different levels within a code hierarchy.

17. The method according to claim 15, wherein The information indicating the one or more software program dependencies is included in a document that is an input to the one or more neural networks.

18. The method according to claim 15, wherein, The one or more neural networks use one or more code libraries to generate the one or more software programs.

19. The method according to claim 15, wherein, The one or more neural networks attend to multiple levels in a code hierarchy in previously generated code for the one or more software programs in a top-down pairwise sequential manner, where each level and its immediately lower level are attended to as a pair.

20. The method according to claim 15 further comprises: Jointly training the one or more neural networks and the plurality of encoders by balancing at least a retrieval loss and an autoregressive loss.

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