Method, system, equipment, medium and product for dynamic repair of controller function abnormality

Abstract

The present application discloses a method, system, device, medium and product for dynamically repairing controller functional abnormalities, wherein a processor sends a signal to be processed to a signal processing component, and the signal processing component parses the signal to be processed, obtains the instruction type of the signal to be processed and the signal content of the signal to be processed, and intercepts the signal to be processed when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, and generates first response data based on the signal content of the signal to be processed, and sends the first response data to the controller. Since the signal processing component can dynamically decide whether to intercept the signal based on different instruction types and repair the signal content to generate response data, the system can flexibly respond to various functional abnormalities of the controller. When the system needs to add new functions or repair new defects, it only needs to update the logic of the signal processing component without replacing the entire controller or redesigning the hardware architecture.

Description

Technical Field

[0001] The present application relates to the field of server technology, and in particular to methods, systems, devices, media, and products for dynamically repairing controller function anomalies. Background Art

[0002] In the server field, the CPU (Central Processing Unit) and BMC (Baseboard Management Controller) currently interact through the eSPI interface (Enhanced Serial Peripheral Interface). The eSPI provides the vgpio (virtual GPIO to reduce the number of pins) function to complete the handshake work of the CPU power-on timing.

[0003] In related technologies, the BMC connects to the CPU's CS0 (chip select 0) via the eSPI (Enhanced Serial Peripheral Interface) to implement basic eSPI protocol functions. The eSPI bus includes peripheral channels, virtual GPIO channels, out-of-band management channels, and flash memory access channels. Furthermore, a complex programmable logic device (CPLD) connects to the CPU's CS1 (chip select 1) to assist in implementing simple functions, primarily virtual GPIO channels. However, if the BMC chip itself has functional defects, key functions such as boot sequence interactive control (a key function) must be implemented on CS0, making critical functions completely dependent on the BMC chip. Furthermore, the fixed functional division between CS0 and CS1 makes it difficult to flexibly expand functionality through software or simple hardware adjustments. Therefore, it is impossible to expand CS1 or other channels to implement the same key functions as CS0. Therefore, if the BMC chip fails, the system may not boot or operate normally.

[0004] Therefore, how to ensure the normal operation of the system when the BMC has functional defects is an urgent problem that needs to be solved. Summary of the Invention

[0005] The present application provides a method, system, device, medium and product for dynamically repairing controller function abnormalities, so as to at least solve the problem in the related art of how to ensure the normal operation of the system when the BMC has function defects.

[0006] The present application provides a method for dynamically repairing controller function abnormalities, which is applied to a system for dynamically repairing controller function abnormalities. The system includes a processor, a signal processing component, and a controller. The processor is connected to the signal processing component, which is connected to the controller. The controller has a target function defect. The method includes:

[0007] The processor sends a signal to be processed to the signal processing component;

[0008] The signal processing component receives the signal to be processed sent by the processor; parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed; when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, intercepts the signal to be processed and generates first response data according to the signal content of the signal to be processed; and sends the first response data to the controller.

[0009] The present application also provides a controller function abnormality dynamic repair system, the controller function abnormality dynamic repair system includes: a processor, a signal processing component and a controller, the processor is connected to the signal processing component, the signal processing component is connected to the controller, and the controller has a target function defect;

[0010] The processor is configured to: send a signal to be processed to the signal processing component;

[0011] The signal processing component is configured to: receive the signal to be processed sent by the processor; parse the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed; when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, intercept the signal to be processed and generate first response data according to the signal content of the signal to be processed; and send the first response data to the controller.

[0012] The present application also provides an electronic device, comprising: a memory for storing a computer program; and a processor for implementing the steps of any of the above-mentioned methods for dynamically repairing controller function abnormalities when executing the computer program.

[0013] The present application also provides a computer-readable storage medium, in which a computer program is stored. When the computer program is executed by a processor, the steps of any of the above-mentioned methods for dynamically repairing controller function abnormalities are implemented.

[0014] The present application also provides a computer program product, including a computer program, which implements the steps of any of the above-mentioned methods for dynamically repairing controller function abnormalities when the computer program is executed by a processor.

[0015] Through this application, the processor sends a signal to be processed to the signal processing component, the signal processing component parses the signal to be processed, obtains the instruction type of the signal to be processed and the signal content of the signal to be processed, and when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, the signal to be processed is intercepted, and first response data is generated according to the signal content of the signal to be processed, and the first response data is sent to the controller. Since the signal processing component can dynamically decide whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly respond to various functional anomalies of the controller without large-scale modifications to the hardware. When the system needs to add new functions or repair new defects, it only needs to update the logic of the signal processing component without replacing the entire controller or redesigning the hardware architecture. Dynamically repairing the controller with functional defects through the signal processing component can effectively make up for the shortcomings of the controller and ensure that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional anomalies and improve the overall stability of the system. For example, in a server system, the BMC (baseboard management controller) has certain functional defects, such as the failure of the Virtual WireChannel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to the Virtual Wire, repair the signal content, and generate a response signal back to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0017] Figure 1 A schematic diagram of the architecture of a system for dynamically repairing controller function abnormalities provided by an embodiment of the present application;

[0018] Figure 2 A flowchart of a method for dynamically repairing controller function abnormalities provided in an embodiment of the present application. DETAILED DESCRIPTION

[0019] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0020] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0021] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0022] Explanation of terms:

[0023] BMC: Baseboard Management Controller.

[0024] IPMI: Intelligent Platform Management Interface.

[0025] eSPI: Enhanced Serial Peripheral Interface, enhanced serial peripheral interface.

[0026] SPI: Serial Peripheral Interface, serial peripheral interface.

[0027] BIOS: Basic Input Output System.

[0028] I2C stands for Inter-Integrated Circuit (IC). I2C is a synchronous serial communication protocol used to connect low-speed devices. It is commonly used between microcontrollers and peripherals such as sensors and EEPROMs. I2C uses two wires (clock line SCL and data line SDA) for communication and supports a multi-master and multi-slave architecture.

[0029] UART: Universal Asynchronous Receiver / Transmitter. UART is a universal serial communication protocol used for asynchronous communication. It allows data to be transmitted between devices at variable baud rates and is commonly used for communication between computers and modems, and between embedded systems and peripherals. A UART interface typically consists of two lines: RX (receive) and TX (transmit).

[0030] GPIO (General Purpose Input / Output) is a programmable digital interface used to implement simple digital signal interaction between a microcontroller or processor and external devices. GPIO pins can be configured as input or output and are used to control devices such as LEDs, buttons, relays, or read digital signals from sensors.

[0031] A Complex Programmable Logic Device (CPLD) is a programmable logic device that belongs to the field-programmable gate array (FPGA) and programmable logic device (PLD) families. A CPLD is a general-purpose digital logic chip that can be programmed to implement a variety of digital circuit functions. Its key features are its flexibility and reconfigurability, enabling rapid customization of logic functions to meet user needs. It is widely used in digital circuit design.

[0032] Abnormalities in the eSPI (enhanced serial peripheral interface) of the BMC (baseboard management controller) can cause system crashes or malfunctions. Common types of eSPI abnormalities include: 1) Internal BMC failure, i.e., a BMC fault that causes eSPI abnormality; 2) Large BMC log files that may occupy excessive storage space and affect eSPI functionality; 3) Communication failures: Bus master communication abnormalities. An eSPI bus master (such as a BMC) may encounter errors when communicating with a slave device. Examples include incomplete transactions, data overflow, or interrupted transmissions. Alternatively, channel link errors can occur. When two eSPI channels are linked, if master channel 1 encounters an error during transmission on channel 2, communication may be interrupted.

[0033] In the server field, the CPU (Central Processing Unit) and BMC (Baseboard Management Controller) currently interact through the eSPI interface (Enhanced Serial Peripheral Interface). The eSPI provides the vgpio (virtual GPIO to reduce the number of pins) function to complete the handshake work of the CPU power-on timing.

[0034] In related technologies, the BMC connects to the CPU's CS0 (chip select 0) via the eSPI (Enhanced Serial Peripheral Interface) to implement basic eSPI protocol functions. The eSPI bus includes peripheral channels, virtual GPIO channels, out-of-band management channels, and flash memory access channels. Furthermore, a complex programmable logic device (CPLD) connects to the CPU's CS1 (chip select 1) to assist in implementing simple functions, primarily virtual GPIO channels. However, if the BMC chip itself has functional defects, key functions such as boot sequence interactive control (a key function) must be implemented on CS0, making critical functions completely dependent on the BMC chip. Furthermore, the fixed functional division between CS0 and CS1 makes it difficult to flexibly expand functionality through software or simple hardware adjustments. Therefore, it is impossible to expand CS1 or other channels to implement the same key functions as CS0. Therefore, if the BMC chip fails, the system may not boot or operate normally.

[0035] Therefore, how to ensure the normal operation of the system when the BMC has functional defects is an urgent problem that needs to be solved.

[0036] In conjunction with the specific application environment architecture or specific hardware architecture on which the execution of the controller function abnormality dynamic repair method depends, the specific application environment architecture or specific hardware architecture is described here.

[0037] The embodiment of the present application provides a controller function abnormality dynamic repair system, referring to Figure 1As shown, the system includes a processor 11, a signal processing component 12, and a controller 13. The processor 11 is connected to the signal processing component 12, which is in turn connected to the controller 13. The controller 13 has a target functional defect. In the disclosed embodiments, the processor 11 may include, but is not limited to, a data processing processor such as a CPU, CPU, or MCU. The signal processing component 12 may include, but is not limited to, a programmable logic device such as a CPLD or FPGA. The programmable nature of CPLDs and FPGAs allows for dynamic updates of repair logic to adapt to different application requirements and emerging issues. The controller 13 may include, but is not limited to, various BMC chips. The CPLD is inserted between the CPU and BMC, forming a cascaded CPU-CPLD-BMC structure. The CPLD connects the CPU and BMC via an eSPI interface, enabling functions such as data interception and parsing, dynamic repair, and transparent forwarding. Hardware-level repair using the CPLD avoids software-level delays and limitations, enabling real-time interception and processing of eSPI communication data, ensuring efficient repair. This hardware-level automatic repair function reduces the need for manual intervention and lowers system maintenance costs. The target functional defect includes one of the following: peripheral channel dysfunction, virtual GPIO channel failure, out-of-band management channel dysfunction, and flash memory access channel dysfunction. It should be noted that after a BMC chip is selected, its functional defect is known, and the CPLD extends and repairs the eSPI function based on the known functional defect. For example, a failure in the BMC's Virtual Wire Channel (vgpio) function may render the BMC incompatible with certain peripherals or protocols. In this system, processor 11 sends a signal to be processed to signal processing component 12. Signal processing component 12 receives the signal sent by processor 11 and parses the signal to obtain the instruction type and signal content of the signal. If the instruction type of the signal corresponds to the target functional defect, the signal is intercepted and first response data is generated based on the signal content. The first response data is then sent to controller 13. Because the signal processing component can dynamically decide whether to intercept the signal and repair the signal content based on different instruction types, this dynamic mechanism enables the system to flexibly respond to various controller functional anomalies without requiring large-scale hardware modifications. When the system needs to add new features or fix new defects, it only needs to update the signal processing component logic, without having to replace the entire controller or redesign the hardware architecture. Dynamically repairing controllers with functional defects through the signal processing component effectively compensates for the controller's shortcomings and ensures that the system continues to operate normally despite the defect. This dynamic repair mechanism prevents system crashes or malfunctions caused by controller malfunctions, thereby improving overall system stability.For example, in a server system, the BMC (baseboard management controller) has certain functional defects, such as the failure of the Virtual Wire Channel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to the Virtual Wire, repair the signal content, and generate a response signal back to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0038] An embodiment of the present application provides a method for dynamically repairing controller function abnormalities, which is applied to a system for dynamically repairing controller function abnormalities. The method is described in detail in conjunction with the execution flow of the method for dynamically repairing controller function abnormalities.

[0039] Reference Figure 2 As shown, the method for dynamically repairing controller function abnormality provided by the embodiment of the present invention includes the following steps:

[0040] S21. The processor sends a signal to be processed to the signal processing component.

[0041] Among them, the processor is the main control unit of the system, responsible for generating and sending signals to be processed.

[0042] The signal processing component is used to receive and process the signal to be processed. The signal processing component may include but is not limited to CPLD, FPGA, ASIC or other dedicated hardware modules.

[0043] Exemplarily, the processor generates a signal to be processed based on system requirements. The signal to be processed can be a control signal, a data signal, or another type of signal. For example, the processor may need to send a command via a Virtual Wire Channel to read or write a register.

[0044] Optionally, the processor and the signal processing component are communicatively connected via a preset protocol bus interface.

[0045] Among them, the preset protocol bus interface is a communication bridge between the processor and the signal processing component, and is used to transmit signals.

[0046] In some embodiments, the above step S21 can be implemented as follows:

[0047] The processor sends the signal to be processed to the signal processing component through the preset protocol bus interface.

[0048] Specifically, the processor sends the signal to be processed to the signal processing component through a preset protocol bus interface (such as eSPI).

[0049] For example, the processor sends a GET_VWIRE command with the command code 0x01 via the eSPI bus. The GET_VWIRE command is used in the eSPI (enhanced serial peripheral interface) protocol to read the status of the Virtual Wire signal. The Virtual Wire channel is used to transmit simple control signals and status information, similar to traditional GPIO functionality, but implemented over the eSPI bus. The command data format includes a signal index (Index) and a signal value (Data).

[0050] Optionally, the preset protocol bus is an enhanced serial peripheral interface bus.

[0051] In the embodiment of the present disclosure, the preset protocol bus interface may be eSPI.

[0052] S22. The signal processing component receives the signal to be processed sent by the processor; parses the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed; when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, intercepts the signal to be processed and generates first response data according to the signal content of the signal to be processed; and sends the first response data to the controller.

[0053] Among them, the target functional defects include: peripheral channel function abnormality, virtual GPIO channel function failure, out-of-band management channel function abnormality, and flash memory access channel function abnormality.

[0054] For example, when the target functional defect is a peripheral channel malfunction, the signal processing component can intercept commands from the Peripheral Channel and generate a correct response. When the target functional defect is a virtual GPIO channel malfunction, the signal processing component can intercept commands from the Virtual Wire Channel and generate a correct response. When the target functional defect is an out-of-band management channel malfunction, the signal processing component can intercept commands from the OOB Channel and generate a correct response. When the target functional defect is a flash access channel malfunction, the signal processing component can intercept commands from the Run-time Flash Access Channel and generate a correct response.

[0055] In the disclosed embodiments, dynamic repair of BMC eSPI functional anomalies is performed to avoid system crashes or malfunctions caused by such anomalies. The use of a hardware-level repair mechanism improves repair reliability and reduces system failures caused by software errors.

[0056] Protocol parsing can identify transaction types in the eSPI protocol (such as read, write, and configuration) and extract address, data, and control information.

[0057] Through the above steps, the signal processing component can effectively receive, analyze, process, and respond to signals sent by the processor, thereby compensating for functional deficiencies of the BMC or other controllers. This approach is suitable for complex systems that require high reliability and flexibility, such as servers and embedded systems.

[0058] Through this application, the processor sends a signal to be processed to the signal processing component, the signal processing component parses the signal to be processed, obtains the instruction type of the signal to be processed and the signal content of the signal to be processed, and when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, the signal to be processed is intercepted, and first response data is generated according to the signal content of the signal to be processed, and the first response data is sent to the controller. Since the signal processing component can dynamically decide whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly respond to various functional anomalies of the controller without large-scale modifications to the hardware. When the system needs to add new functions or repair new defects, it only needs to update the logic of the signal processing component without replacing the entire controller or redesigning the hardware architecture. Dynamically repairing the controller with functional defects through the signal processing component can effectively make up for the shortcomings of the controller and ensure that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional anomalies and improve the overall stability of the system. For example, in a server system, the BMC (baseboard management controller) has certain functional defects, such as the failure of the Virtual WireChannel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to the Virtual Wire, repair the signal content, and generate a response signal back to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0059] Accordingly, since the processor and the signal processing component are communicatively connected via a preset protocol bus interface, the above step S22 (the signal processing component receives the signal to be processed sent by the processor) can be implemented in the following manner:

[0060] The signal processing component receives the signal to be processed sent by the processor through the preset protocol bus interface.

[0061] Specifically, the signal processing component receives signals to be processed from the processor via a predefined protocol bus interface (e.g., eSPI). Specifically, the signal processing component monitors signals on the eSPI bus and receives signals when a new transaction is detected. The signal processing component parses the received signals to extract the instruction type and signal content.

[0062] For example, the signal processing component parses the command instruction on the eSPI bus, determines the instruction type, and extracts relevant data content, such as register address, data value, etc., based on the instruction type.

[0063] The signal processing component determines whether to intercept the signal based on predefined rules. If the instruction type corresponds to the target functional defect (such as a virtual GPIO channel failure), interception is performed. The signal processing component processes the signal content according to predefined repair logic. For example, if the virtual GPIO channel fails, the signal processing component can read or write data from internal registers. Based on the repair results, the signal processing component generates correct response data. The signal processing component sends the generated first response data back to the processor via the predefined protocol bus interface.

[0064] In some embodiments, the signal processing component is connected to the controller via a preset protocol bus interface. The above step S12 (sending the first response data to the controller) can be implemented as follows:

[0065] The signal processing component sends the first response data to the processor through the preset protocol bus interface.

[0066] Through communication between the processor and signal processing components, as well as the dynamic processing of signals by the signal processing components, functional defects in the system can be effectively resolved. This architecture is particularly suitable for complex systems that require high reliability and flexibility, such as servers and embedded systems.

[0067] Optionally, the signal processing component and the controller are also connected via a preset communication interface.

[0068] When the preset protocol bus interface fails, the above step S12 (sending the first response data to the controller) can also be implemented in the following manner:

[0069] The signal processing component sends the first response data to the processor through the preset communication interface.

[0070] Furthermore, in some embodiments, the preset communication interface includes: a serial integrated circuit bus interface, a universal input / output interface, and a universal asynchronous receiver / transmitter interface.

[0071] When the preset protocol bus interface fails, the above step S12 (sending the first response data to the controller) can also be implemented in the following manner:

[0072] The signal processing component sends the first response data to the processor through at least one of the serial integrated circuit bus interface, the general input / output interface, and the universal asynchronous receiver / transmitter interface.

[0073] In the disclosed embodiments, the processor is configured to generate and send signals to be processed and receive response data from the processing component. The signal processing component is configured to receive the signals to be processed from the processor, parse the signal content, process the signals according to predefined logic, generate response data, and send the response data back to the processor. The controller is a BMC, configured to receive the response data from the signal processing component. A preset protocol bus interface, such as the eSPI bus, is the primary communication interface used for communication between the processor and the signal processing component. The preset communication interface is a backup communication interface, such as I2C, SPI, or UART, providing a backup communication path in the event of a failure in the primary communication interface. For example, if a preset protocol bus interface fails, the signal processing component sends response data to the processor via the preset communication interface (e.g., I2C, SPI, or UART). For example, a GPIO interface is used to notify the BMC to retrieve data after the CPLD has processed data. Another example of an I2C interface is when the CPU needs to use eSPI to set or query the status of a GPIO, but the BMC is functionally defective and cannot perform the corresponding function, requiring the CPLD to handle the process. Since the number of VGPIOs may be relatively large, if physical GPIOs are used, too many GPIOs will be occupied. Using I2C can more conveniently expand and reduce IO occupancy.

[0074] Illustratively, the signal processing component detects whether an eSPI bus fault has occurred using a heartbeat mechanism or an error detection mechanism. If a fault is detected, the eSPI_fault flag is set. When the eSPI_fault flag is set, the signal processing component switches to a backup communication interface (e.g., I2C). The backup communication interface is initialized to ensure proper operation. The signal processing component then sends response data to the processor via the backup communication interface (e.g., I2C). For example, the value of a Virtual Wire register is sent via the I2C bus.

[0075] By introducing a backup communication interface, the signal processing component can send response data through a backup communication interface (such as I2C, SPI, or UART) when the primary communication interface (such as the eSPI bus) fails, ensuring that the system can still operate normally even if the primary communication interface fails. The backup communication interface can be selected according to specific needs, such as I2C, SPI, or UART.

[0076] Through this application, the processor sends a signal to be processed to the signal processing component, the signal processing component parses the signal to be processed, obtains the instruction type of the signal to be processed and the signal content of the signal to be processed, and when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, the signal to be processed is intercepted, and first response data is generated according to the signal content of the signal to be processed, and the first response data is sent to the controller. Since the signal processing component can dynamically decide whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly respond to various functional anomalies of the controller without large-scale modifications to the hardware. When the system needs to add new functions or repair new defects, it only needs to update the logic of the signal processing component without replacing the entire controller or redesigning the hardware architecture. Dynamically repairing the controller with functional defects through the signal processing component can effectively make up for the shortcomings of the controller and ensure that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional anomalies and improve the overall stability of the system. For example, in a server system, the BMC (baseboard management controller) has certain functional defects, such as the failure of the Virtual WireChannel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to the Virtual Wire, repair the signal content, and generate a response signal back to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0077] In some embodiments, when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, the following steps may be further performed before intercepting the signal to be processed:

[0078] According to a preset interception instruction database, it is determined whether the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect; the preset interception instruction database includes: multiple instruction types corresponding to the target functional defect of the controller.

[0079] The preset interception instruction database stores all known instruction types corresponding to target functional defects. This helps the signal processing component quickly determine whether a received signal needs to be intercepted. This database can be a simple lookup table (LUT) or a more complex storage structure, depending on the complexity and requirements of the system.

[0080] For example, if the target functional defect includes a failure of a Virtual GPIO channel function, the database will include instruction types related to Virtual GPIO, such as GET_VWIRE (0x01) and PUT_VWIRE (0x02).

[0081] Furthermore, in some embodiments, the above step (determining whether the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect according to the preset interception instruction database) can be implemented as follows:

[0082] Comparing the instruction type of the signal to be processed with the preset interception instruction database;

[0083] If the instruction type of the signal to be processed matches the target interception instruction type in the preset interception instruction database, it is determined that the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect; the target interception instruction type is the instruction type corresponding to the target functional defect.

[0084] Specifically, after the signal processing component receives the signal to be processed, it parses the signal to obtain the instruction type. Then, the signal processing component determines whether the instruction type corresponds to the target functional defect based on the preset interception instruction database. The signal processing component receives the signal through the preset protocol bus interface and parses the instruction type and data content. The signal processing component searches for the parsed instruction type in the preset interception instruction database to determine whether the instruction needs to be intercepted. If the instruction type corresponds to the target functional defect, the signal processing component will intercept the signal, and its interception logic is: the signal processing component prevents the signal from being directly transmitted to the controller, but processes it locally and executes the predefined repair logic. The signal processing component sends the generated response data back to the processor to complete the entire processing process.

[0085] By pre-setting the interception instruction database, the signal processing component can more accurately determine which signals need to be intercepted and processed without modifying the hardware logic. In addition, the types of instructions that need to be intercepted can be easily added or removed to adapt to different functional defects and application scenarios.

[0086] Through this application, the processor sends a signal to be processed to the signal processing component, the signal processing component parses the signal to be processed, obtains the instruction type of the signal to be processed and the signal content of the signal to be processed, and when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, the signal to be processed is intercepted, and first response data is generated according to the signal content of the signal to be processed, and the first response data is sent to the controller. Since the signal processing component can dynamically decide whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly respond to various functional anomalies of the controller without large-scale modifications to the hardware. When the system needs to add new functions or repair new defects, it only needs to update the logic of the signal processing component without replacing the entire controller or redesigning the hardware architecture. Dynamically repairing the controller with functional defects through the signal processing component can effectively make up for the shortcomings of the controller and ensure that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional anomalies and improve the overall stability of the system. For example, in a server system, the BMC (baseboard management controller) has certain functional defects, such as the failure of the Virtual WireChannel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to the Virtual Wire, repair the signal content, and generate a response signal back to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0087] In some embodiments, the above step (generating first response data according to the signal content of the signal to be processed) can be implemented as follows:

[0088] Obtaining a preset repair strategy corresponding to the instruction type of the signal to be processed;

[0089] According to the preset repair strategy, the signal content of the signal to be processed is repaired or processed to generate first response data.

[0090] It is understood that the preset repair strategy can be stored in a lookup table that stores a set of repair logic corresponding to all known target functional defects. This table is used to assist the signal processing component in performing corresponding repair or processing operations based on different instruction types and signal content. For example, the repair strategy for CMD_GET_VWIRE is to read the Virtual Wire register, while the repair strategy for CMD_PUT_VWIRE is to write to the Virtual Wire register.

[0091] Specifically, the signal processing component retrieves the preset repair strategy corresponding to the instruction type of the signal to be processed from the lookup table and then repairs or processes the signal content according to the preset repair strategy. For example, for a GET_VWIRE command, the signal processing component reads data from an internal register; for a PUT_VWIRE command, the signal processing component writes data to an internal register. After the repair or processing is complete, the signal processing component generates the first response data and sends it back to the processor via the eSPI bus.

[0092] Through preset repair strategies, the signal processing component can execute corresponding repair or processing logic according to different instruction types and signal contents, thereby generating correct response data.

[0093] In some embodiments, when the instruction type of the signal to be processed is not the instruction type corresponding to the target functional defect, the signal processing component sends the signal to be processed to the controller;

[0094] The controller responds to the signal to be processed, obtains second response data of the signal to be processed; and sends the second response data to the signal processing component;

[0095] The signal processing component receives the second response data sent by the controller; and forwards the second response data to the processor.

[0096] Specifically, the signal processing component searches the preset interception instruction database for the parsed instruction type and determines whether the instruction needs to be intercepted. If the instruction type does not belong to the instruction type corresponding to the target functional defect, the signal processing component forwards the received signal directly to the controller without any processing. After receiving the signal, the controller processes the signal according to normal logic and generates second response data, which is sent to the signal processing component. The signal processing component receives the second response data sent by the controller and feeds the second response data back to the processor.

[0097] The signal processing component can flexibly decide whether to intervene based on different instruction types. The signal processing component intervenes only when necessary and maintains normal signal transmission in other cases.

[0098] Optionally, before forwarding the second response data to the processor, the following steps may be further performed:

[0099] The signal processing component processes the second response data according to a preset data format to obtain processed second response data.

[0100] Specifically, before forwarding the second response data to the processor, the signal processing component performs format conversion, verification or encryption on the response data according to the preset data format to obtain the processed second response data. Signal escape refers to converting one signal format or protocol into another format or protocol. A CPLD is added between the BMC and the CPU, and the CPLD can serve as the core component of signal escape. The CPLD can realize the conversion of multiple signal formats through its programmable logic resources. For example, converting an SPI signal into an I2C signal, or converting a parallel signal into a serial signal. The CPLD can intercept signals sent from the CPU to the BMC, or signals sent from the BMC to the CPU.

[0101] By presetting the data format, the signal processing component can flexibly process response data in different formats without modifying the hardware logic, and ensure that the format of the response data meets the requirements of the processor, thereby improving the compatibility of the system.

[0102] Additionally, if the CPLD detects a BMC malfunction (e.g., a heartbeat signal is not being sent to the CPLD after power-on), it can take over the power-on sequence control for the BMC and CPU, forcing a return to normal operation so that the CPU can power on normally. If the BMC supports forced repairs in the system, you can perform a firmware repair in the system to enhance reliability.

[0103] The embodiment of the present disclosure provides a method for dynamically repairing controller functional anomalies. The processor sends a signal to be processed to a signal processing component. The signal processing component parses the signal to be processed, obtains the instruction type of the signal to be processed and the signal content of the signal to be processed, and intercepts the signal to be processed when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect. The signal to be processed is generated according to the signal content of the signal to be processed. The first response data is sent to the controller. Since the signal processing component can dynamically decide whether to intercept the signal according to different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly respond to various functional anomalies of the controller without the need for large-scale hardware modifications. When the system needs to add new functions or repair new defects, it only needs to update the logic of the signal processing component without replacing the entire controller or redesigning the hardware architecture. Dynamically repairing a controller with functional defects through the signal processing component can effectively make up for the shortcomings of the controller and ensure that the system can still operate normally when the controller has defects. This dynamic repair mechanism can avoid system crashes or malfunctions caused by controller functional anomalies and improve the overall stability of the system. For example, in a server system, the BMC (baseboard management controller) has certain functional defects, such as the failure of the Virtual Wire Channel (virtual GPIO) function. Through this dynamic repair method, the CPLD (signal processing component) can intercept signals related to the Virtual Wire, repair the signal content, and generate a response signal back to the CPU. In this way, even if the BMC has functional defects, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0104] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0105] Figure 1 This is a schematic diagram of the architecture of a controller function abnormality dynamic repair system provided by the present disclosure, referring to Figure 1 As shown, the controller function abnormality dynamic repair system includes: a processor 11, a signal processing component 12 and a controller 13, the processor 11 is connected to the signal processing component 12, the signal processing component 12 is connected to the controller 13, and the controller 13 has a target function defect;

[0106] The processor 11 is configured to: send a signal to be processed to the signal processing component;

[0107] The signal processing component 12 is configured to: receive the signal to be processed sent by the processor; parse the signal to be processed to obtain the instruction type of the signal to be processed and the signal content of the signal to be processed; when the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, intercept the signal to be processed and generate first response data according to the signal content of the signal to be processed; and send the first response data to the controller 13.

[0108] As an optional implementation of the embodiment of the present disclosure, the signal processing component is further configured to: when the instruction type of the signal to be processed is not the instruction type corresponding to the target functional defect, send the signal to be processed to the controller;

[0109] The controller is configured to: respond to the signal to be processed, obtain second response data of the signal to be processed; and send the second response data to the signal processing component;

[0110] The signal processing component is further configured to: receive the second response data sent by the controller; and forward the second response data to the processor.

[0111] As an optional implementation of the embodiment of the present disclosure, the signal processing component is further configured to: process the second response data according to a preset data format to obtain processed second response data.

[0112] As an optional implementation of the embodiment of the present disclosure, the target functional defect includes: peripheral channel function abnormality, virtual GPIO channel function failure, out-of-band management channel function abnormality, and flash memory access channel function abnormality.

[0113] As an optional implementation of the embodiment of the present disclosure, the signal processing component is further configured to:

[0114] According to a preset interception instruction database, it is determined whether the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect; the preset interception instruction database includes: multiple instruction types corresponding to the target functional defect of the controller.

[0115] As an optional implementation of the embodiment of the present disclosure, the signal processing component is further specifically configured to: compare the instruction type of the signal to be processed with the preset interception instruction database;

[0116] If the instruction type of the signal to be processed matches the target interception instruction type in the preset interception instruction database, it is determined that the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect; the target interception instruction type is the instruction type corresponding to the target functional defect.

[0117] As an optional implementation of the embodiment of the present disclosure, the signal processing component is further specifically configured to: obtain a preset repair strategy corresponding to the instruction type of the signal to be processed;

[0118] According to the preset repair strategy, the signal content of the signal to be processed is repaired or processed to generate first response data.

[0119] As an optional implementation of the embodiment of the present disclosure, the processor and the signal processing component are communicatively connected via a preset protocol bus interface;

[0120] The processor is specifically configured to: send a signal to be processed to the signal processing component via the preset protocol bus interface;

[0121] The signal processing component is specifically configured to receive the signal to be processed sent by the processor through the preset protocol bus interface.

[0122] As an optional implementation of the embodiment of the present disclosure, the signal processing component is connected to the controller via a preset protocol bus interface;

[0123] The signal processing component is further specifically configured to: send the first response data to the processor through the preset protocol bus interface.

[0124] As an optional implementation of the embodiment of the present disclosure, the signal processing component and the controller are further connected via a preset communication interface;

[0125] When the preset protocol bus interface fails, the signal processing component is further specifically configured to: send the first response data to the processor through the preset communication interface.

[0126] As an optional implementation of the embodiment of the present disclosure, the preset communication interface includes: a serial integrated circuit bus interface, a universal input / output interface, and a universal asynchronous receiver / transmitter interface;

[0127] When the preset protocol bus interface fails, the signal processing component is further specifically configured to: send the first response data to the processor through at least one of the serial integrated circuit bus interface, the universal input / output interface, and the universal asynchronous receiver / transmitter interface.

[0128] For the description of the features in the embodiment corresponding to the system for dynamically repairing controller function abnormalities, please refer to the relevant description of the embodiment corresponding to the method for dynamically repairing controller function abnormalities, and no further details will be given here.

[0129] The present disclosure provides a system for dynamically repairing controller functional anomalies. The system includes a processor, a signal processing component, and a controller. The processor is connected to the signal processing component, which is connected to the controller. When a target functional defect exists in the controller, the processor sends a signal to be processed to the signal processing component. The signal processing component parses the signal to be processed, obtains the instruction type and signal content of the signal to be processed, and intercepts the signal to be processed when the instruction type of the signal to be processed corresponds to the target functional defect. The signal to be processed is generated based on the signal content of the signal to be processed and sent to the controller. The first response data is generated. Since the signal processing component can dynamically decide whether to intercept the signal based on different instruction types and repair the signal content, this dynamic mechanism enables the system to flexibly respond to various functional anomalies of the controller without requiring large-scale hardware modifications. When the system needs to add new functions or repair new defects, it only needs to update the logic of the signal processing component without replacing the entire controller or redesigning the hardware architecture. Dynamically repairing controllers with functional defects through the signal processing component can effectively make up for the shortcomings of the controller and ensure that the system can still operate normally even when the controller has defects. This dynamic repair mechanism can prevent system crashes or malfunctions caused by controller malfunctions, improving overall system stability. For example, in a server system, if the BMC (baseboard management controller) has certain functional defects, such as the failure of the Virtual WireChannel (virtual GPIO) function, this dynamic repair method allows the CPLD (signal processing component) to intercept Virtual Wire-related signals, repair the signal content, and generate a response signal back to the CPU. In this way, even if the BMC has a functional defect, the system can still operate normally without replacing the BMC or redesigning the hardware.

[0130] An embodiment of the present application further provides an electronic device comprising a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above-mentioned embodiments of the method for dynamically repairing controller function abnormalities.

[0131] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned embodiments of the method for dynamically repairing controller function abnormalities when running.

[0132] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0133] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned controller function abnormality dynamic repair method embodiments are implemented.

[0134] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, which stores a computer program. When the computer program is executed by a processor, it implements the steps of any of the above-mentioned controller function abnormality dynamic repair method embodiments.

[0135] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0136] The above is a detailed introduction to a method for dynamically repairing controller function abnormalities provided by the present application. This article uses specific examples to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method of the present application and its core ideas. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. A method for dynamically repairing abnormal controller functions, characterized in that: Applicable to a dynamic repair system for controller function abnormality, the dynamic repair system for controller function abnormality includes a processor, a signal processing component and a controller, the processor is connected to the signal processing component, the signal processing component is connected to the controller, and the controller has a target function defect; the target function defect includes: peripheral channel function abnormality, virtual GPIO channel function failure, out-of-band management channel function abnormality, flash memory access channel function abnormality; The method comprises: The processor sends a signal to be processed to the signal processing component; The signal processing component receives a signal to be processed sent by the processor; parses the signal to be processed to obtain an instruction type and signal content of the signal to be processed; intercepts the signal to be processed when the instruction type of the signal to be processed is an instruction type corresponding to the target functional defect, and generates first response data based on the signal content of the signal to be processed; and sends the first response data to the controller; The step of generating first response data according to the signal content of the signal to be processed includes: Obtaining a preset repair strategy corresponding to the instruction type of the signal to be processed; According to the preset repair strategy, the signal content of the signal to be processed is repaired or processed to generate first response data.

2. The method for dynamically repairing controller function abnormality according to claim 1, characterized in that: The method further comprises: The signal processing component sends the signal to be processed to the controller when the instruction type of the signal to be processed is not the instruction type corresponding to the target functional defect; The controller responds to the signal to be processed, obtains second response data of the signal to be processed; and sends the second response data to the signal processing component; The signal processing component receives the second response data sent by the controller; and forwards the second response data to the processor.

3. The method for dynamically repairing controller function abnormality according to claim 2, characterized in that: Before forwarding the second response data to the processor, the method further includes: The signal processing component processes the second response data according to a preset data format to obtain processed second response data.

4. The method for dynamically repairing controller function abnormality according to claim 1, characterized in that: When the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect, before intercepting the signal to be processed, the method further includes: The signal processing component determines whether the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect based on a preset interception instruction database; the preset interception instruction database includes: multiple instruction types corresponding to the target functional defect of the controller.

5. The method for dynamically repairing controller function abnormality according to claim 4, characterized in that: The determining, based on a preset interception instruction database, whether the instruction type of the signal to be processed is an instruction type corresponding to the target functional defect includes: Comparing the instruction type of the signal to be processed with the preset interception instruction database; If the instruction type of the signal to be processed matches the target interception instruction type in the preset interception instruction database, it is determined that the instruction type of the signal to be processed is the instruction type corresponding to the target functional defect; the target interception instruction type is the instruction type corresponding to the target functional defect.

6. The method for dynamically repairing controller function abnormality according to claim 1, characterized in that: The processor is communicatively connected to the signal processing component via a preset protocol bus interface; The processor sends a signal to be processed to the signal processing component, comprising: The processor sends the signal to be processed to the signal processing component through the preset protocol bus interface; The signal processing component receives the signal to be processed sent by the processor, including: The signal processing component receives the signal to be processed sent by the processor through the preset protocol bus interface.

7. The method for dynamically repairing controller function abnormality according to claim 1, characterized in that: The signal processing component is connected to the controller via a preset protocol bus interface; The sending the first response data to the controller includes: The signal processing component sends the first response data to the controller through the preset protocol bus interface.

8. The method for dynamically repairing controller function abnormality according to claim 7, characterized in that: The signal processing component and the controller are also connected via a preset communication interface; When the preset protocol bus interface fails, the sending of the first response data to the controller further includes: The signal processing component sends the first response data to the controller through the preset communication interface.

9. The method for dynamically repairing controller function abnormality according to claim 8, characterized in that: The preset communication interface includes: a serial integrated circuit bus interface, a universal input / output interface, and a universal asynchronous receiver / transmitter interface; When the preset protocol bus interface fails, the sending of the first response data to the controller further includes: The signal processing component sends the first response data to the controller through at least one of the serial integrated circuit bus interface, the universal input / output interface, and the universal asynchronous receiver / transmitter interface.

10. A controller function abnormality dynamic repair system, characterized in that: The controller function abnormality dynamic repair system includes: a processor, a signal processing component and a controller, the processor is connected to the signal processing component, the signal processing component is connected to the controller, and the controller has a target function defect; the target function defect includes: peripheral channel function abnormality, virtual GPIO channel function failure, out-of-band management channel function abnormality, flash memory access channel function abnormality; The processor is configured to: send a signal to be processed to the signal processing component; The signal processing component is configured to: receive a signal to be processed sent by the processor; parse the signal to be processed to obtain an instruction type and signal content of the signal to be processed; when the instruction type of the signal to be processed is an instruction type corresponding to the target functional defect, intercept the signal to be processed and generate first response data according to the signal content of the signal to be processed; and send the first response data to the controller; The step of generating first response data according to the signal content of the signal to be processed includes: Obtaining a preset repair strategy corresponding to the instruction type of the signal to be processed; According to the preset repair strategy, the signal content of the signal to be processed is repaired or processed to generate first response data.

11. The system according to claim 10, wherein: The system further comprises: The signal processing component is further configured to: when the instruction type of the signal to be processed is not the instruction type corresponding to the target functional defect, send the signal to be processed to the controller; The controller is configured to: respond to the signal to be processed, obtain second response data of the signal to be processed; and send the second response data to the signal processing component; The signal processing component is further configured to: receive the second response data sent by the controller; and forward the second response data to the processor.

12. The system according to claim 10, wherein: The processor is communicatively connected to the signal processing component via a preset protocol bus interface; the signal processing component is communicatively connected to the controller via a preset protocol bus interface and / or a preset communication interface.

13. The system according to claim 12, wherein: The preset protocol bus is an enhanced serial peripheral interface bus.

14. The system according to claim 12, wherein: The preset communication interface includes: a serial integrated circuit bus interface, a universal input / output interface, and a universal asynchronous receiver / transmitter interface.

15. The system according to claim 12, wherein: When the preset protocol bus interface fails, the signal processing component and the controller are connected via the preset communication interface.

16. An electronic device, characterized in that: include: memory for storing computer programs; A processor, configured to implement the steps of the method for dynamically repairing controller function abnormality according to any one of claims 1 to 9 when executing the computer program.

17. A computer-readable storage medium, characterized in that The computer-readable storage medium stores a computer program, wherein when the computer program is executed by a processor, the steps of the method for dynamically repairing controller function abnormality according to any one of claims 1 to 9 are implemented.

18. A computer program product comprising a computer program, characterized in that When the computer program is executed by a processor, the steps of the method for dynamically repairing controller function abnormality according to any one of claims 1 to 9 are implemented.

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