Information processing method and device, electronic equipment and storage medium

Through the two-level dimensional performance evaluation method, combined with processor-level and computing unit-level data flow analysis, the problem of inaccurate performance evaluation of GEMM operators in the prior art is solved, and more efficient resource utilization and program optimization are achieved.

CN120353685AActive Publication Date: 2025-07-22SHANGHAI BIREN TECH CO LTD
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Patent Information

Application Number
CN202510846763.6
Authority / Receiving Office
CN · China
Patent Type
Applications(China)
Current Assignee / Owner
Filing Date
2025-06-24
Publication Date
2025-07-22
Estimated Expiration
2045-06-24

AI Technical Summary

Technical Problem

In the prior art, the performance evaluation of GEMM operators only considers chip-level performance, resulting in the inability to accurately obtain the execution situation, affecting subsequent performance optimization and targeted improvements.

Method used

The theoretical performance evaluation method of a two-level dimension is adopted, combined with the data flow analysis of the processor level and the computing unit level, and the theoretical performance of the processor is determined through the first utilization rate and the second utilization rate, taking into account the data flow between memory and shared memory and between shared memory and register heap, and comprehensively considering the influence of various factors.

Benefits of technology

It provides more accurate performance evaluation results to help developers better understand the execution of GEMM operators, thereby performing targeted optimizations, and improving resource utilization and program performance.

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Abstract

The invention discloses an information processing method and device, electronic equipment and a storage medium, and is applied to the field of information processing. The information processing method comprises the steps that a first utilization rate is determined in combination with a data flow between a memory and a shared memory when a processor executes a general matrix multiplication operator, and the first utilization rate is used for indicating performance evaluation of the general matrix multiplication operator at a processor level; determining a second utilization rate in combination with a data stream between a shared memory and a register file in a single computing unit when the processor executes the general matrix multiplication operator, the second utilization rate being used for indicating performance evaluation of the general matrix multiplication operator at the computing unit level; and based on the smaller one of the first utilization rate and the second utilization rate, determining the theoretical performance of the processor when executing the universal matrix multiplication operator. At present, only chip-level performance evaluation is considered in performance evaluation of a GEMM operator, and double-level-dimension theoretical performance evaluation is provided, so that the evaluation result is more accurate.
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