Method for accessing flash memory unit based on descriptor, flash memory controller and system

Abstract

The invention discloses a method for accessing a flash memory unit based on descriptors, a flash memory controller and a system, and relates to the technical field of flash memories. The method comprises the following steps: obtaining a descriptor chain through a descriptor queue; sequentially reading the descriptors through a task scheduler, and judging whether uncompleted access tasks of other descriptors exist in the suspension waiting area or not; if not, judging whether a channel scheduling switch of the current descriptor is in a first state or not through a task scheduler; if yes, enabling the pending waiting area to suspend to regularly query the task completion states of other descriptors in the pending waiting area from the execution unit; scheduling the current descriptor to a task resolver through a task scheduler, and enabling the task resolver to analyze the current descriptor to form a control instruction; and executing an access operation on the flash memory particles through an execution unit according to the control instruction. According to the method, the requirements of sequential read-write and random read-write scenes can be met at the same time, and the working efficiency of the flash memory controller is improved.

Description

Technical Field

[0001] The present invention relates to the technical field of flash memory, and in particular to a method for accessing flash memory cells based on descriptors, a flash memory controller and system, and a storage medium. Background Art

[0002] Large-capacity storage devices such as eMMC, UFS, and SSD generally use multiple flash memory cells stacked. Therefore, during the read and write processes, it is inevitable to access NAND Flash of different CE / LUNs. For the random read and write scenario, multiple instructions of the same CE / LUN are usually random and cross, allowing out-of-order completion. However, for the sequential read and write scenario, if there are tasks of different CE / LUNs in the descriptor queue, there will be scheduling. Under this mechanism, consecutive multiple instructions of the same CE / LUN will be disrupted.

[0003] In order to meet the requirements of the sequential read and write scenario and enable consecutive multiple instructions of the same CE / LUN to be executed in order and not be interrupted by other CE / LUNs in the middle, the prior art is that only one or more descriptors of one CE / LUN are allowed in the descriptor queue of each flash memory access channel at the same time, and descriptors of different CE / LUNs are not allowed to exist simultaneously. The specific method is that the access requests (one or more descriptors) of each CE / LUN form a separate descriptor chain. Before the head address of the descriptor chain of a certain CE / LUN is written into the register of the descriptor reader, it is necessary to wait for the flash memory controller of the corresponding channel to return to the idle state, that is, if there are tasks of other CE / LUNs being executed in the current channel, it is necessary to wait for them all to be parsed and executed, which reduces the overall working efficiency of the controller. Summary of the Invention

[0004] The present invention aims to at least solve one of the technical problems existing in the prior art. For this purpose, the present invention provides a method for accessing flash memory cells based on descriptors, a flash memory controller and system, and a storage medium. In the sequential read and write scenario, descriptors of different CE / LUNs can exist in the descriptor queue, and the requirements of both sequential read and write and random read and write scenarios can be met simultaneously, improving the working efficiency of the flash memory controller.

[0005] The method for accessing flash memory cells based on descriptors according to an embodiment of the present invention is applied to a flash memory controller. The flash memory controller includes a descriptor queue, a task scheduler, a task parser, an execution unit, and a suspension waiting area. The method includes the following steps: Obtain a number of descriptor chains sent by a descriptor reader through the descriptor queue; each descriptor chain includes a plurality of descriptors, each descriptor includes access unit information and a channel scheduling switch. When the descriptor chain is for sequential read and write, the channel scheduling switch is in the first state, and the access unit information of all the descriptors in the descriptor chain is the same. When the descriptor chain is for random read and write, the channel scheduling switch is in the second state; Read the descriptors in the descriptor queue sequentially through the task scheduler, and determine whether there are unfinished access tasks of other descriptors with the same access unit information as the current descriptor in the pending waiting area; If not, determine through the task scheduler whether the channel scheduling switch of the current descriptor is in the first state; If so, send a signal to the pending waiting area through the task scheduler to cause the pending waiting area to suspend periodically querying the task completion status of other descriptors in the pending waiting area to the execution unit; Schedule the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction; Execute the access operation on the flash memory particles according to the control instruction through the execution unit.

[0006] According to some embodiments of the present invention, each descriptor further includes a channel scheduling flag. Before obtaining the descriptor chain sent by the descriptor reader through the descriptor queue, it further includes: Create descriptors through the CPU, concatenate multiple descriptors into a descriptor chain, and configure the channel scheduling flag of the last descriptor in the descriptor chain as the first flag, and configure the channel scheduling flags of the remaining descriptors as the second flag; Determine whether the descriptors in the descriptor chain are for sequential read and write or random read and write; When the descriptors in the descriptor chain are for sequential read and write, configure the channel scheduling switches of all the descriptors in the descriptor chain as the first state through the CPU; When the descriptors in the descriptor chain are for random read and write, configure the channel scheduling switches of all the descriptors in the descriptor chain as the second state through the CPU. According to some embodiments of the present invention, the descriptor reader includes an entry register, an acquisition module, and a status register group; obtaining the descriptor chain sent by the descriptor reader through the descriptor queue includes: The CPU writes the head address of the descriptor chain to the entry register, configures an identification number for the descriptor chain through the entry register, and identifies the identification number to each descriptor of the descriptor chain; The acquisition module reads multiple descriptors in the descriptor chain from the system cache according to the head address and sends them to the descriptor queue; The status register group records the completion status of each descriptor chain and each descriptor within each descriptor chain. According to some embodiments of the present invention, the descriptor includes an OPCODE pointer, access unit information, flash memory particle address information, system cache address, hardware control information, and address information of the next descriptor, and the hardware control information includes a channel scheduling switch and a channel scheduling flag. According to some embodiments of the present invention, after the task scheduler sequentially reads the descriptors in the descriptor queue and determines whether there are other descriptors with the same access unit information as the current descriptor that have uncompleted access tasks in the pending waiting area, it further includes: If there are access tasks of other descriptors with the same access unit information as the current descriptor that are uncompleted in the pending waiting area, the task scheduler reads the next descriptor in the descriptor queue as the current descriptor, and repeats this step until there are no other descriptors with the same access unit information as the current descriptor that have uncompleted access tasks in the pending waiting area. According to some embodiments of the present invention, after the task scheduler determines whether the channel scheduling switch of the current descriptor is in the first state, it further includes: When the channel scheduling switch of the current descriptor is in the second state, the task scheduler sends a second signal to the pending waiting area to enable the pending waiting area to periodically query the task completion status of other descriptors in the pending waiting area from the execution unit; The task scheduler schedules the current descriptor to the task parser, and the task parser parses the current descriptor to form a control instruction; The execution unit performs an access operation on the flash memory particle according to the control instruction; When the execution time exceeds the preset time, the current descriptor is stored in the pending waiting area, the task parser pauses parsing the subsequent tasks of the current descriptor, and returns to the step of the task scheduler sequentially reading the descriptors in the descriptor queue according to the descriptor order and determining whether there are access tasks of other descriptors with the same access unit information as the current descriptor that are uncompleted in the pending waiting area. When the descriptors in the suspension waiting area meet the suspension exit conditions, the suspension waiting area notifies the task scheduler. When the task scheduler is idle, the descriptors in the suspension waiting area are rescheduled for subsequent parsing and execution until the tasks of the descriptors are completed. According to some embodiments of the present invention, the task scheduler schedules the current descriptor to the task parser, and the task parser parses the current descriptor to form control instructions, including: The task scheduler looks up the corresponding task sequence from the OPCODE table according to the OPCODE pointer of the current descriptor, and sends the task sequence and the current descriptor to the task parser; The task parser parses the current descriptor and determines whether the task sequence is of the DMA start type, suspension waiting type, FCU instruction type or end type; If the type of the task sequence is the DMA start type, the task parser parses the current descriptor to generate an RDMA or WDMA start instruction; Alternatively, if the type of the task sequence is the suspension waiting type, the task parser stores the current descriptor in the suspension waiting area and suspends the subsequent parsing actions of the current descriptor; Alternatively, if the type of the task sequence is the FCU instruction type, the task parser generates an instruction for accessing the flash memory particles according to the parameters and command sets in the task read command table; Alternatively, if the type of the task is the end type, the task parser generates an instruction for updating the descriptor status to a specified position in the system cache and ends the parsing task of the entire descriptor.

[0007] On the other hand, a flash memory controller according to an embodiment of the present invention includes a descriptor queue, a task scheduler, a task parser, an execution unit, and a suspension waiting area. The flash memory controller is used to execute the method for accessing a flash memory cell based on a descriptor as described above.

[0008] On the other hand, a flash memory control system according to an embodiment of the present invention includes a flash memory controller, a descriptor reader, a CPU, a bus, and a system cache. The bus is respectively connected to the flash memory controller, the descriptor reader, the CPU, and the system cache. The descriptor reader is connected to the flash memory controller. The flash memory control system is used to execute the method for accessing a flash memory cell based on a descriptor as described above.

[0009] On the other hand, according to an embodiment of the present invention, a computer storage medium stores computer-executable instructions for causing a computer to execute the method for accessing a flash memory cell based on a descriptor as described above.

[0010] The method for accessing a flash memory cell based on a descriptor, a flash memory controller, a system, and a storage medium according to an embodiment of the present invention have at least the following beneficial effects: By configuring a channel scheduling switch for the descriptor, the flash memory controller can determine whether the descriptor chain belongs to sequential read / write or random read / write through the channel scheduling switch, and adopt different access methods according to the requirements of sequential read / write and random read / write scenarios, so that the method can realize seamless switching between parallel operations and serial operations. By adding the technology of channel scheduling control, when there are multiple descriptor chains in the descriptor queue at the same time, and multiple descriptor chains have both sequential read / write and random read / write, the flash memory controller supports both parallel operations and out-of-order completion of descriptors for all CEs / LUNs; supports both serial operations and sequential completion of descriptors for all CEs / LUNs; also supports parallel operations and out-of-order completion of descriptors for some CEs / LUNs, and serial operations and sequential completion of descriptors for another part of CEs / LUNs. In this way, no matter what the operation type and operation combination are, the flash memory controller can handle them, and each module of the flash memory controller can work in a pipeline, improving the working efficiency of the flash memory controller.

[0011] The additional aspects and advantages of the present invention will be partly given in the following description, partly will become obvious from the following description, or will be understood through the practice of the present invention. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and / or additional aspects and advantages of the present invention will become obvious and easy to understand from the description of the embodiments in conjunction with the following drawings, in which: Figure 1 is a schematic structural diagram of a flash memory control system according to an embodiment of the present invention; Figure 2 is a schematic structural diagram of a descriptor according to an embodiment of the present invention; Figure 3 is a schematic structural diagram of a descriptor chain according to an embodiment of the present invention; Figure 4 is a schematic structural diagram of a descriptor reader and a flash memory controller according to an embodiment of the present invention; Figure 5 is a flowchart of steps of a method for accessing a flash memory cell based on a descriptor according to an embodiment of the present invention; Figure 6 is a schematic diagram of a specific process of a method for accessing a flash memory cell based on a descriptor according to an embodiment of the present invention. DETAILED DESCRIPTION

[0013] This section will describe in detail specific embodiments of the present invention. Preferred embodiments of the present invention are shown in the accompanying drawings. The function of the drawings is to supplement the description in the text part of the specification, enabling people to intuitively and vividly understand each technical feature and the overall technical solution of the present invention. However, it should not be construed as a limitation on the protection scope of the present invention.

[0014] In the description of the present invention, the meaning of "a number of" is one or more, the meaning of "a plurality of" is two or more, and understandings such as "greater than", "less than", "exceeding", etc. do not include the recited number, while understandings such as "above", "below", "within", etc. include the recited number. If there is a description of "first" and "second", it is only for the purpose of distinguishing technical features and cannot be construed as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features or implicitly indicating the sequence relationship of the indicated technical features.

[0015] In the description of the present invention, unless otherwise clearly defined, terms such as "setting", "installing", "connecting", etc. should be understood in a broad sense, and those skilled in the art can reasonably determine the specific meanings of the above terms in the present invention in combination with the specific content of the technical solution.

[0016] eMMC: Embedded Multi Media Card, an embedded multimedia card, is a standard specification for embedded memory established by the MMC Association, mainly targeting products such as mobile phones or tablets. eMMC is an embedded, non-volatile storage system, which mainly consists of flash memory, an access method for flash memory cells based on descriptors, and an eMMC protocol interface, etc. It defines the physical architecture, access interface, and protocol of the storage system based on the embedded multimedia card, and has the advantages of small size, low power consumption, large capacity, etc., and is very suitable as a storage medium for electronic devices such as smart phones, tablets, and mobile Internet devices.

[0017] UFS: Universal Flash storage, a flash storage specification designed for use in consumer electronic products such as digital cameras and smart phones. Its design goal is to develop a unified format for flash memory cards, which can reduce the confusion of consumers about various memory card formats on the market and the use of different memory card adapters while providing high data transfer speed and stability.

[0018] SSD: Solid State Disk, a solid-state drive, also known as a solid-state disk, is a hard disk made of an array of solid-state electronic storage chips.

[0019] Nand Flash: Flash refers to flash memory, which is a type of non-volatile memory that can be electrically erased and programmed quickly. From a chip technology perspective, Flash can be divided into two major categories: Nor Flash and Nand Flash. Nand Flash memory is a type of Flash memory that uses a non-linear macrocell mode internally, providing a cheap and effective solution for the implementation of solid-state large-capacity memory. Nand Flash memory has advantages such as a large capacity and a fast rewrite speed, making it suitable for storing large amounts of data. Therefore, it has been increasingly widely used in the industry, such as in embedded products including digital cameras, MP3 player memory cards, and small-sized USB flash drives.

[0020] OPCODE: Operation Code, which is used to describe the part of the machine code in a machine language instruction that specifies a certain operation to be performed. The instruction format and specification that make up the OPCODE are specified by the processor.

[0021] CE / LUN information: CE / LUN information refers to the CE and LUN information of the flash memory particles to be accessed that needs to be specified in the descriptor. Each Nand Flash can have multiple CEs (Chip Enable units), and each CE can have multiple LUNs (Logical Unit Number. A LUN is the smallest independent unit in the flash memory that can execute commands and report its own status).

[0022] SRAM: Static Random-Access Memory, which is a type of random-access memory. As long as this memory remains powered on, the data stored in it can be constantly maintained.

[0023] DDR: Double Data Rate, double data rate synchronous dynamic random access memory.

[0024] An embodiment of the present application proposes a method for accessing flash memory cells based on descriptors. A number of descriptor chains sent by a descriptor reader are obtained through a descriptor queue; the task scheduler sequentially reads the descriptors according to the order of the descriptors in the descriptor queue, and determines whether there are unfinished access tasks of other descriptors with the same access unit information as the current descriptor in the pending waiting area; if not, the task scheduler determines whether the channel scheduling switch of the current descriptor is in the first state; if so, the task scheduler sends a signal to the pending waiting area to cause the pending waiting area to pause querying the task completion status of other descriptors in the pending waiting area from the execution unit at regular intervals; the task scheduler schedules the current descriptor to the task parser, and the task parser parses the current descriptor to form a control instruction; the execution unit performs an access operation on the flash memory particles according to the control instruction; the next descriptor with the same identification number as the current descriptor in the descriptor queue is obtained as the current descriptor, and the step of scheduling the current descriptor to the task parser by the task scheduler to cause the task parser to parse the current descriptor to form a control instruction is returned, until the access tasks of all the descriptors in the descriptor chain are completed. By configuring a channel scheduling switch for the descriptor, the flash memory controller can determine whether the descriptor chain belongs to sequential read / write or random read / write through the channel scheduling switch, and adopt different access methods according to the requirements of sequential read / write and random read / write scenarios, so that the method can realize seamless switching between parallel operation and serial operation. By adding the technology of channel scheduling control, when there are multiple descriptor chains in the descriptor queue at the same time, and multiple descriptor chains have both sequential read / write and random read / write, the flash memory controller supports parallel operation and out-of-order completion of descriptors of all CEs / LUNs; it also supports serial operation and sequential completion of descriptors of all CEs / LUNs; it also supports parallel operation and out-of-order completion of descriptors of some CEs / LUNs, and serial operation and sequential completion of descriptors of another part of CEs / LUNs. In this way, no matter what the operation type and operation combination are, the flash memory controller can handle them, and each module of the flash memory controller can work in a pipeline, improving the working efficiency of the flash memory controller.

[0025] The following refers to Figures 1 to 6 to elaborate in detail the method for accessing flash memory cells based on descriptors, the flash memory controller and system, and the storage medium according to the embodiments of the present invention.

[0026] As Figure 1 shown, an embodiment of the present application proposes a flash memory control system, which includes: a flash memory controller 100, a descriptor reader 200, a CPU 300, a bus 400, and a system cache 500. The bus 400 is respectively connected to the flash memory controller 100, the descriptor reader 200, the CPU 300, and the system cache 500, and the descriptor reader 200 is connected to the flash memory controller 100.

[0027] It should be noted that the flash memory control system may include multiple flash memory controllers 100, and each flash memory controller 100 is respectively used to access and control the corresponding flash memory cells (Nand). The CPU 300 is used to create descriptors and concatenate multiple descriptors into a descriptor chain. It should be noted that a descriptor is a data structure constructed by the software layer through the CPU 300 to describe the access tasks to the flash memory cells (Nand), such as the erasure of a Block (Block: a block, the smallest erasure unit of the flash memory, and the flash memory is composed of multiple Blocks) and the read and write of Nand Pages, etc. (Page: a page, the smallest unit that can be read and written in the flash memory, and a Block contains multiple Pages). Any common access operation can be implemented by one descriptor or multiple descriptors, and the software creates different descriptors in a flexible way to adapt to various scenario requirements. After the CPU 300 creates a descriptor, it writes the descriptor into the system cache 500 through the bus 400 (the controller chips of eMMC and UFS types can use SRAM as the system cache, and SSDs can also use DDR as the system cache), and writes the start address of the descriptor chain composed of multiple descriptors into the descriptor reader 200.

[0028] As Figure 2 shown, in some embodiments of the present application, a descriptor is composed of multiple fields, including an OPCODE pointer, access unit information (hereinafter referred to as CE / LUN information), flash memory die address information (i.e., Nand Flash address), system cache address, hardware control information, and the address information of the next descriptor. The hardware control information includes a channel scheduling switch and a channel scheduling flag. Among them, the OPCODE pointer is the index number of the OPCODE table to be introduced below, and the task scheduler of the flash memory controller 100 will look up the corresponding task sequence from the OPCODE table according to this pointer and schedule and send it to the subsequent modules for parsing and execution. The CE / LUN information refers to the CE and LUN information of the flash memory die that needs to be specified in the descriptor to be accessed. The Nand Flash address means that the descriptor also needs to specify the address of the flash memory die to be accessed (Block, Page address, etc.). The system cache address means that the descriptor needs to specify the system cache address. For example, for the read operation of Nand Flash, the hardware needs to move the data read from a certain Page of the flash memory die to the destination address of the system cache. The hardware control information of the descriptor is used to guide the hardware to execute flexibly in the way required by the software to meet the needs of different application scenarios; in the present application, the hardware control information includes a channel scheduling switch and a channel scheduling flag, and the functions of the channel scheduling switch and the channel scheduling flag will be described below. As Figure 3As shown, descriptors usually appear in the form of a descriptor chain, which includes multiple descriptors. Therefore, the location of the next descriptor in the system cache is also specified in the descriptor.

[0029] As Figure 4 shown, in some embodiments of the present application, the descriptor reader 200 includes an Entry register, a Fetch module, and a Status register group. Among them, after the CPU 300 creates a descriptor chain, it writes the starting address of the descriptor chain into the Entry register; the Fetch module reads each descriptor in the descriptor chain into the flash controller 100 according to the starting address. The Entry register configures an identification number for the descriptor chain as the ID of the descriptor chain. The identification number of the subsequent descriptor chain can be incremented by 1 based on the identification number of the current descriptor chain, or other rules can be used to configure the corresponding identification number for each descriptor chain. The Status register group is used to represent the completion status of each descriptor in the descriptor chain and the completion status of the entire descriptor chain. The CPU 300 can obtain the execution status of each descriptor chain and each descriptor by reading the Status register group.

[0030] As Figure 4 shown, in some embodiments of the present application, the flash controller 100 is composed of a front-end module and a back-end module. The front-end module is used for task scheduling and parsing of descriptors, generating control instructions, and then sending the control instructions to the back-end module for execution. It can be understood that the front-end module is the control center, and the back-end module is the execution unit. The front-end module sends control instructions to control and direct the operation of the back-end module. Specifically, the front-end module includes a descriptor queue, a task scheduler, a task parser, a suspension waiting area, etc., and the back-end module includes an execution unit. Among them, after the descriptor reader 200 reads the descriptor chain from the system cache 500, it first sends it to the descriptor queue to wait. This queue can store multiple descriptor chains, providing room for the task scheduler to achieve parallel access to multiple CE / LUNs or serial access to a single CE / LUN. The task scheduler selects descriptors that meet the scheduling conditions from the descriptor queue when it is idle, and schedules them out and sends them to the task parser for parsing. The generated control instructions after parsing are sent to the corresponding hardware units (FCU, WDMA, RDMA) of the execution unit for execution. Among them, FCU refers to the Flash Control Unit, WDMA refers to Write DMA, and RDMA refers to Read DMA.

[0031] The task scheduler relies on the OPCODE table to complete its work. The OPCODE table stores a large number of different combinations of task sequences for use when the software creates descriptors. The OPCODE pointer in each descriptor points to a specific task sequence in the OPCODE table to implement different access operations on the flash memory.

[0032] When the task parser parses and generates control instructions sent to the execution unit, it usually needs to complete the work with the assistance of the command table. The parsed and generated instructions include access operations on Nand chips through the FCU and Nand IO (such as sending commands, addresses, and performing data read / write operations, erasing, and status queries), start instructions for RDMA and WDMA, and instructions for updating the descriptor status to the system cache, etc.

[0033] For a descriptor, multiple control commands are generated after its parsing, and not every control command can be executed immediately. Some control commands require a relatively long execution time. For example, a certain control command requires RDMA to read a sufficient amount of data from the system cache to the internal cache of the subsequent module. During the execution of this control command, the Nand IO will be in the busy state. If we keep waiting for this descriptor to be parsed and executed completely and then parse and execute other descriptors, the execution efficiency will be low. To improve the utilization rate and access efficiency of the Nand IO, in the example of this application, a suspension waiting area is also designed in the front-end module. Taking full advantage of the characteristic that different CEs / LUNs of the Nand Flash chip can be accessed in parallel, after the control instructions that need to wait for the execution result for a long time are sent to the subsequent module, the subsequent task parsing actions of this descriptor are suspended. After the task parser notifies the suspension waiting area to record the current execution status of the CE / LUN, the suspension exit waiting condition, the current position of the task sequence in the OPCODE table, etc., it releases the resources to execute the scheduling and parsing work of descriptors under other CEs / LUNs, thus realizing the parallel access to different CEs / LUNs of the Nand Flash chip and improving the utilization efficiency of the NandIO. When the subsequent module feeds back a signal that meets the suspension exit condition to the suspension waiting area, the suspended descriptor tasks under the corresponding CE / LUN can then be scheduled again and sent to the task parser to continue parsing and execution. It should be noted that the method of parallel access for different CEs / LUNs is applicable to the scenario of random read / write. If it is a sequential read / write scenario, consecutive multiple instructions for the same CE / LUN need to be executed in sequence and are not allowed to be interrupted by other CEs / LUNs in the middle, and the above method of parallel access for multiple CEs / LUNs is not applicable to the sequential read / write scenario.

[0034] Therefore, the embodiment of this application provides an access method for flash memory cells based on descriptors that is applicable to both sequential read / write and random read / write, as Figure 5As shown, the method includes the following steps: Step S100: Obtain a number of descriptor chains sent by the descriptor reader 200 through the descriptor queue; Step S200: Sequentially read the descriptors through the task scheduler according to the descriptor order in the descriptor queue, and determine whether there are unfinished access tasks of other descriptors with the same access unit information as the current descriptor in the pending waiting area; Step S300: If not, determine whether the channel scheduling switch of the current descriptor is in the first state through the task scheduler; Step S400: If so, send a signal to the pending waiting area through the task scheduler to cause the pending waiting area to suspend periodically querying the task completion status of other descriptors in the pending waiting area from the execution unit; Step S500: Schedule the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction; Step S600: Execute the access operation on the flash memory particles according to the control instruction through the execution unit.

[0035] It should be noted that since the descriptor chain is constructed by the CPU 300, before step S100 obtains a number of descriptor chains sent by the descriptor reader 200 through the descriptor queue, steps S10 - S40 are also included: Step S10: Create descriptors through the CPU, concatenate multiple descriptors into a descriptor chain, and configure the channel scheduling flag of the last descriptor in the descriptor chain as the first flag, and configure the channel scheduling flags of the remaining descriptors as the second flag; Step S20: Determine whether the descriptors in the descriptor chain are sequential read / write or random read / write; Step S30: When the descriptors in the descriptor chain are sequential read / write, configure the channel scheduling switches of all descriptors in the descriptor chain as the first state through the CPU; Step S40: When the descriptors in the descriptor chain are random read / write, configure the channel scheduling switches of all descriptors in the descriptor chain as the second state through the CPU.

[0036] Specifically, after the CPU 300 creates a descriptor, it writes the descriptor into the system cache 500 through the bus 400 and writes the head address of the descriptor chain composed of multiple descriptors into the descriptor reader 200. At the same time, in order to facilitate the task scheduler of the subsequent flash memory controller 100 to determine whether all descriptors of the current descriptor chain have completed the access task, in this application, a field of channel scheduling flag is added to the hardware control information of the descriptor. The channel scheduling flag of the last descriptor of the descriptor chain is configured as the first flag, and the channel scheduling flags of the remaining descriptors are configured as the second flag. For example, the channel scheduling flag of the last descriptor can be set to 0, and the channel scheduling flags of the remaining descriptors can be set to 1. Of course, the first flag and the second flag can also be set to other symbols. When the task scheduler schedules a descriptor, it reads the value of the channel scheduling flag of the descriptor. If the channel scheduling flag is 1, it means that there are still descriptors in the current descriptor chain that have not completed the access task; if the channel scheduling flag is 0, it means that all descriptors of the current descriptor chain have completed the access task. In addition, in order to distinguish whether the descriptor belongs to the scenario of sequential read / write or random read / write in the future, in this application, a field of channel scheduling switch is added to the hardware control information of the descriptor. By the switch state of the channel scheduling switch, the scenario of sequential read / write and the scenario of random read / write are distinguished. If all descriptors of the descriptor chain have the same access unit information (CE / LUN information) and belong to the scenario of sequential read / write, the CPU 300 will configure the channel scheduling switches of all descriptors of the descriptor chain to the first state (for example, set to the open state); if all descriptors of the descriptor chain have different CE / LUN information and belong to the scenario of random read / write, the CPU 300 will configure the channel scheduling switches of all descriptors of the descriptor chain to the second state (for example, set to the closed state).

[0037] In some embodiments of the present application, the above step S100: obtaining several descriptor chains sent by the descriptor reader 200 through the descriptor queue further includes the following three steps: Step S110: writing the head address of the descriptor chain into the entry register through the CPU 300 and configuring an identification number for the descriptor chain through the entry register; Step S120: reading out multiple descriptors in the descriptor chain from the system cache 500 according to the head address by the acquisition module and sending them to the descriptor queue; Step S130: recording the completion status of each descriptor chain and each descriptor in each descriptor chain through the status register group.

[0038] After the CPU 300 creates a descriptor chain, it writes the starting address of the descriptor chain into an entry register; the acquisition module reads each descriptor in the descriptor chain into the descriptor queue of the flash memory controller 100 according to the starting address. The entry register configures an identification number for the descriptor chain. The status register group is used to represent the completion status of each descriptor in the descriptor chain and the completion status of the entire descriptor chain. By reading the status register group, the CPU 300 can learn the execution status of each descriptor chain and each descriptor.

[0039] In the above step S200, after the descriptor queue acquires the descriptors of the descriptor chain, the task scheduler sequentially reads each descriptor in the order of the descriptors in the descriptor queue. When reading each descriptor, the task scheduler determines whether there is an unfinished access task of other descriptors with the same CE / LUN information as the current descriptor in the pending waiting area of the flash memory controller 100. If so, the task scheduler cannot schedule the current descriptor temporarily. It needs to continue reading the next descriptor in the descriptor queue as the current descriptor through the task scheduler and repeat the above judgment process until a descriptor is obtained for which there is no access task of other descriptors with the same CE / LUN in the pending waiting area. If there is no step of unfinished access task of other descriptors with the same access unit information as the current descriptor in the pending waiting area, the above step S300 is executed. At this time, the task scheduler determines whether the channel scheduling switch of the current descriptor is in the first state. If so, it means that all descriptors of the descriptor chain where the current descriptor is located belong to the sequential read / write scenario. At this time, the task scheduler sends a signal to the pending waiting area to make the pending waiting area pause querying the task completion status of other descriptors in the pending waiting area from the execution unit regularly, and then starts to schedule the current descriptor to the task parser, so that the task parser parses the current descriptor to form a control instruction, and the execution unit executes the access operation on the flash memory particles according to the control instruction. When the access operation of the current descriptor is completed, since this descriptor chain belongs to the sequential read / write scenario, the task scheduler schedules the next descriptor with the same identification number (indicating belonging to the same descriptor chain) as the current descriptor until the access operations of all descriptors in this descriptor chain are completed in order. It should be noted that in the sequential read / write scenario, even if the access time of a certain descriptor is too long, the task of this descriptor is not placed in the pending waiting area, but the access task of the next descriptor is carried out after the access operation of this descriptor is completed. Therefore, it is necessary to make the pending waiting area pause querying the task completion status of other descriptors in the pending waiting area from the execution unit regularly.

[0040] As Figure 6 shown, in some embodiments of the present application, after the above step S300, the following five steps are further included: When the channel scheduling switch of the current descriptor is in the second state, a second signal is sent to the suspended waiting area through the task scheduler, enabling the suspended waiting area to periodically query the task completion status of other descriptors in the suspended waiting area from the execution unit; The current descriptor is scheduled to the task parser through the task scheduler, enabling the task parser to parse the current descriptor to form a control instruction; The execution unit executes the access operation on the flash memory particles according to the control instruction; When the execution time exceeds the preset time, the current descriptor is stored in the suspended waiting area, the task parser suspends parsing the subsequent tasks of the current descriptor, and returns to step S200; When the descriptors in the suspended waiting area meet the suspended exit conditions, the suspended waiting area notifies the task scheduler. When the task scheduler is idle, the descriptors in the suspended waiting area are rescheduled for subsequent parsing and execution work until the tasks of the descriptors are completed.

[0041] Specifically, when the channel scheduling switch of the current descriptor is in the second state, it indicates that all descriptors in the descriptor chain where the descriptor is located belong to the random read / write scenario. At this time, the task scheduler sends a signal to the suspended waiting area to enable the suspended waiting area to periodically query the task completion status of other descriptors in the suspended waiting area from the execution unit, and then starts to schedule the current descriptor to the task parser, enabling the task parser to parse the current descriptor to form a control instruction. According to the control instruction, the execution unit performs an access operation on the flash memory particles. It should be noted that in the random read / write scenario, the descriptors in the descriptor chain may have different CE / LUN information, and descriptors with different CE / LUN information can be accessed in parallel. Therefore, if the execution time of a certain descriptor is too long and exceeds the preset time, the current descriptor will be stored in the suspended waiting area, causing the task parser to pause parsing the subsequent tasks of the current descriptor and return to step S200, enabling the task scheduler to continue reading the next descriptor in the order of the descriptors in the descriptor queue and determining whether there are access tasks for other descriptors in the suspended waiting area that have the same access unit information as the next descriptor and are not completed. If not, the scheduling and parsing operations of the next descriptor can be executed. If so, continue to read the next descriptor. When the descriptors in the suspended waiting area meet the suspended exit condition, the suspended waiting area notifies the task scheduler. When the task scheduler is idle, the descriptors in the suspended waiting area are rescheduled to perform subsequent parsing and execution work until the tasks of the descriptors are completed. In the random read / write scenario, when the execution time of a descriptor is too long, the subsequent tasks of the descriptor are placed in the suspended waiting area and wait until the execution unit completes the current task of the descriptor, and then the subsequent tasks of the descriptor are scheduled out of the suspended waiting area; therefore, it is necessary to periodically query the task completion status of other descriptors in the suspended waiting area from the execution unit through the suspended waiting area so that the descriptors that meet the suspended exit condition can be rescheduled.

[0042] According to the access method for flash memory cells based on descriptors in the embodiments of the present application, the specific operation process is as Figure 6As shown, by configuring a channel scheduling switch and a channel scheduling flag for a descriptor, it can be known whether the descriptor chain belongs to sequential read / write or random read / write. According to the requirements of sequential read / write and random read / write scenarios, different access methods are adopted, enabling seamless switching between parallel operations and serial operations. By adding the technology of channel scheduling control, when there are multiple descriptor chains in the descriptor queue at the same time, and some of the descriptor chains are for sequential read / write and some are for random read / write, the flash memory controller 100 supports both all CE / LUN parallel operations and out-of-order completion; and supports all CE / LUN serial operations and sequential completion; and also supports partial CE / LUN parallel operations and out-of-order completion, while the other part of CE / LUN serial operations and sequential completion. In this way, regardless of the operation type and operation combination, the flash memory controller 100 can handle it, and each module of the flash memory controller 100 can work in a pipeline, improving the working efficiency of the flash memory controller 100.

[0043] The following uses a specific example to illustrate in detail the scheduling, parsing, and execution process of the descriptor by the flash memory controller 100. It should be noted that the following is only an exemplary illustration and not a specific limitation of the present invention.

[0044] In the front-end module of the flash memory controller 100, descriptors sent by the descriptor reader 200 are received through a descriptor queue. This queue can store multiple descriptors, providing room for the task scheduler to achieve parallel access to multiple CE / LUNs.

[0045]

[0046] Table 1 Descriptor Queue Case Please refer to Table 1, which shows a case of one of the descriptor queues. The descriptor queue for storing descriptors can adopt a circular queue design scheme to implement the push (enqueue) and pop (dequeue) operations of descriptors, as well as queue management. For example, the relationship between the physical positions of the cache units pointed to by the head / tail pointers is used to determine the emptiness and fullness of the queue. When a new descriptor is pushed in, the tail pointer (tail pointer) is automatically incremented by 1. When a descriptor is popped out, the head pointer (head pointer) is automatically incremented by 1. It should be noted that if the descriptor at a certain position has completed all scheduling and parsing (i.e., the status is done), but it is not in the unit pointed to by the head pointer and does not meet the condition for popping, it must wait for the previous descriptors to be all popped out before it can be popped. For example, in the case of Table 1, the descriptor at physical position 5 is already in the done state, but since the physical position of the unit pointed to by the head pointer is 3, this descriptor does not meet the condition for being popped.

[0047] Descriptor queues are generally scheduled and executed by the task scheduler in the order from the head to the tail, i.e., first come, first served. However, out-of-order scheduling and execution can be achieved in some cases (random read / write scenarios). Each LUN under each CE belongs to the smallest storage unit that performs NandFlash access operations. Storage units under the same CE / LUN cannot be accessed out of order and can only be executed sequentially. However, descriptors for accessing storage units under different CE / LUNs can be scheduled out of order to achieve parallel access, thereby improving the utilization rate of Nand IO. For example, the descriptor pointed to by the head pointer in Table 1 (physical position 3) is in the running state (being scheduled) at this time. During parsing and execution, it encounters a situation where it needs to wait for a long time for the feedback result from the subsequent module. Therefore, this descriptor will be registered in the pending waiting area of the previous module and the subsequent parsing actions will be suspended. At this time, if the task scheduler is idle, it will look for candidates that meet the scheduling conditions (pending state) in the next unit (physical position 4) of the descriptor queue. However, in the case, the access objects of the descriptor at physical position 4 and the descriptor pointed to by the head pointer both belong to the same CE / LUN and do not meet the scheduling conditions. The task scheduler continues to search downward. The descriptor at physical position 5 is in the done state. Continuing to search downward, the descriptor at physical position 6 is in the pending state, and the CE / LUN of the access object is different from the previous descriptors and can be scheduled out for parsing.

[0048] As mentioned above, each descriptor has an OPCODE pointer. After a candidate descriptor is scheduled out in the descriptor queue of the previous module, the task scheduler will read a series of task sequences from the corresponding position in the OPCODE table according to this pointer for parsing and execution.

[0049]

[0050] Table 2. Virtual Case of OPCODE Table Table 2 is a virtual case of an OPCODE table. Each unit or multiple units can construct a complete task sequence. For example, there is a task sequence at each of the positions pointed to by pointers 3 and 4, with different lengths. The task sequence at the position with the OPCODE pointer 5 occupies two units.

[0051] We take the case where the OPCODE pointer is 3 to illustrate how a descriptor is scheduled for execution. The assumed task sequence stored is AA -> BB -> 20 -> CC -> FF. In this virtual case, AA represents that RDMA needs to read data from system cache 500 into the internal cache of the subsequent module. Since this takes a relatively long time, BB represents that the task sequence of the current descriptor needs to be registered in the pending waiting area until the subsequent module feedbacks that RDMA has read enough data into the internal cache. During this waiting period, the task scheduler can schedule other descriptors for execution to improve parallelism. When the data reading is completed, the task scheduler continues to read out the task represented by 20 and send it to the task parser for parsing. Assume this task represents controlling the FCU of the subsequent module to access the Nand Flash chip through Nand IO. The task parser parses and generates control instructions by looking up the content at the position pointed to by 20 in the command table and combining the content of the current descriptor, and then sends them to the FCU. This instruction represents sending the data in the internal cache to a certain page of the Nand Flash in the command mode specified in the command table. CC represents registering in the pending waiting area again until the Nand Flash chip returns a completion signal. Since this waiting time is long, other descriptor scheduling and parsing are allowed again in the middle. FF represents that all tasks of the descriptor are completed, and a control instruction is sent to the WDMA of the subsequent module. The WDMA needs to write the status of the descriptor to the specified position in the system cache.

[0052]

[0053] Table 3 Case of the data structure in the pending waiting area Table 3 shows a case of the data structure in the pending waiting area. The storage unit under each CE / LUN combination records whether it is in a pending state, the exit condition after suspension (waiting event), whether the exit condition is met, and the position in the OPCODE table where it pauses when suspended. When the task parser encounters a task sent by the task scheduler indicating a suspension action, it finds the corresponding unit in the pending waiting area according to the CE / LUN value, sets the "status" to "pending", and records the "exit condition after suspension", such as waiting for the RB signal to be ready, or waiting for RDMA to read enough data into the internal cache, or other conditions. Set "whether the exit condition is met" to "NO", and record the position in the OPCODE table where the task sequence is suspended, including the OPCODE pointer and the offset within the current unit.

[0054] After a period of waiting, the subsequent module returns a standard signal indicating that the exit condition for the suspended wait is satisfied. The "Whether the exit condition is satisfied" of the corresponding unit in the suspended wait area is set to "YES". The task scheduler will reschedule the suspended descriptor task when it is idle and continue to execute according to the position recorded in the suspended wait area.

[0055]

[0056] Table 4 Command Representation Intent Table 4 is the command representation intent, which is used to generate instructions sent to the FCU of the execution unit. If the task sent by the task scheduler is to parse and generate FCU instructions, this task is the CMD pointer at this time, and the data content at the corresponding position of this pointer will be read from the CMD table. The latter is various parameters and CMD SET. The task parser parses according to the following several types: 1) DMA start type: Read the system cache address and other contents in the descriptor to parse and generate RDMA or WDMA start instructions; 2) Suspended wait type: No instructions are generated. According to CE / LUN, find the corresponding unit in the suspended wait area to register the suspended state, record the exit wait condition and the suspended position of the task sequence; 3) FCU instruction type: The task itself is the command table pointer. According to the pointer, read the corresponding parameters and command sets in the command table, and at the same time read the descriptor content to generate FCU instructions according to the register configuration; 4) End type: Generate an instruction for updating the descriptor state to the specified address in the system cache and end the entire descriptor task.

[0057] On the other hand, based on the method for accessing flash memory cells based on descriptors in the above embodiments, the present invention also proposes a flash memory controller, as Figure 4 shown, the flash memory controller includes: a descriptor queue, a task scheduler, a task parser, an execution unit, and a suspended wait area. The flash memory controller is used to execute the method for accessing flash memory cells based on descriptors described in the above embodiments.

[0058] On the other hand, based on the method for accessing flash memory cells based on descriptors in the above embodiments, the present invention also proposes a computer storage medium, and the storage medium stores computer-executable instructions, and the computer-executable instructions are used to cause a computer to execute the method for accessing flash memory cells based on descriptors described in the above embodiments. Although specific embodiments are described herein, those of ordinary skill in the art will recognize that many other modifications or alternative embodiments are also within the scope of the present disclosure. For example, any one of the functions and / or processing capabilities described in connection with a particular device or component can be performed by any other device or component. Additionally, although various exemplary implementations and architectures have been described in accordance with embodiments of the present disclosure, those of ordinary skill in the art will recognize that many other modifications to the exemplary implementations and architectures described herein are also within the scope of the present disclosure.

[0059] Certain aspects of the present disclosure have been described above with reference to block diagrams and flowcharts of systems, methods, systems, and / or computer program products according to exemplary embodiments. It should be understood that one or more blocks in the block diagrams and flowcharts, and combinations of blocks in the block diagrams and flowcharts, can be implemented respectively by executing computer-executable program instructions. Similarly, according to some embodiments, some of the blocks in the block diagrams and flowcharts may not need to be executed in the order shown, or may not need to be executed at all. Additionally, additional components and / or operations beyond those shown in the blocks of the block diagrams and flowcharts may be present in certain embodiments.

[0060] Accordingly, the blocks in the block diagrams and flowcharts support combinations of means for performing the specified functions, combinations of elements or steps for performing the specified functions, and means for program instructions for performing the specified functions. It should also be understood that each block in the block diagrams and flowcharts, and combinations of blocks in the block diagrams and flowcharts, can be implemented by a special purpose hardware computer system that performs a particular function, element, or step, or by a combination of special purpose hardware and computer instructions.

[0061] The program modules, applications, etc. described herein may include one or more software components, including, for example, software objects, methods, data structures, etc. Each such software component may include computer-executable instructions that, in response to execution, cause at least a portion of the functions described herein (e.g., one or more operations of the exemplary methods described herein) to be performed.

[0062] Software components can be coded in any of a variety of programming languages. An exemplary programming language can be a low-level programming language, such as an assembly language associated with a specific hardware architecture and / or operating system platform. Software components including assembly language instructions may need to be converted by an assembler into executable machine code before being executed by the hardware architecture and / or platform. Another exemplary programming language can be a higher-level programming language, which can be portable across multiple architectures. Software components including a higher-level programming language may need to be converted by an interpreter or compiler into an intermediate representation before execution. Other examples of programming languages include, but are not limited to, macro languages, shell or command languages, job control languages, scripting languages, database query or search languages, or report writing languages. In one or more exemplary embodiments, software components containing instructions in one of the above examples of programming languages can be directly executed by an operating system or other software components without first being converted into another form.

[0063] Software components can be stored as files or other data storage constructs. Software components with similar types or related functions can be stored together in, for example, a specific directory, folder, or library. Software components can be static (e.g., pre-set or fixed) or dynamic (e.g., created or modified at execution time).

[0064] The embodiments of the present invention have been described in detail above with reference to the accompanying drawings. However, the present invention is not limited to the above embodiments, and various changes can be made without departing from the spirit of the present invention within the knowledge of those of ordinary skill in the art.

Claims

1. A method for accessing flash memory cells based on descriptors, characterized in that, Applied to a flash memory controller, the flash memory controller includes a descriptor queue, a task scheduler, a task parser, an execution unit, and a pending waiting area, and the method includes: Obtaining a plurality of descriptor chains sent by a descriptor reader through the descriptor queue; each descriptor chain includes a plurality of descriptors, each descriptor includes access unit information and a channel scheduling switch. When the descriptor chain is for sequential read and write, the channel scheduling switch is in a first state, and the access unit information of all the descriptors in the descriptor chain is the same. When the descriptor chain is for random read and write, the channel scheduling switch is in a second state; Sequentially reading the descriptors in the descriptor queue through the task scheduler, and determining whether there are unfinished access tasks of other descriptors with the same access unit information as the current descriptor in the pending waiting area; If not, determining, through the task scheduler, whether the channel scheduling switch of the current descriptor is in the first state; If so, sending a signal to the pending waiting area through the task scheduler to cause the pending waiting area to suspend periodically querying the task completion status of other descriptors in the pending waiting area from the execution unit; Scheduling the current descriptor to the task parser through the task scheduler, so that the task parser parses the current descriptor to form a control instruction; Performing an access operation on the flash memory particles according to the control instruction through the execution unit.

2. The method for accessing a flash memory cell based on a descriptor according to claim 1, wherein Each descriptor further includes a channel scheduling flag. Before obtaining the descriptor chain sent by the descriptor reader through the descriptor queue, it further includes: Creating descriptors through the CPU, concatenating a plurality of the descriptors into a descriptor chain, and configuring the channel scheduling flag of the last descriptor in the descriptor chain as a first flag, and configuring the channel scheduling flags of the remaining descriptors as second flags; Determining whether the descriptors in the descriptor chain are for sequential read and write or random read and write; When the descriptors in the descriptor chain are for sequential read and write, configuring the channel scheduling switches of all the descriptors in the descriptor chain as the first state through the CPU; When the descriptors in the descriptor chain are for random read and write, configuring the channel scheduling switches of all the descriptors in the descriptor chain as the second state through the CPU.

3. The access method to a flash memory cell based on a descriptor according to claim 2, wherein The descriptor reader includes an entry register, an acquisition module, and a status register group. Obtaining the descriptor chain sent by the descriptor reader through the descriptor queue includes: Writing the starting address of the descriptor chain into the entry register through the CPU, and configuring an identification number for the descriptor chain through the entry register, and identifying the identification number to each descriptor in the descriptor chain; Reading a plurality of the descriptors in the descriptor chain from the system cache according to the starting address through the acquisition module, and sending them to the descriptor queue; Recording the completion status of each descriptor chain and each descriptor in each descriptor chain through the status register group.

4. The access method to the flash memory cell based on the descriptor according to claim 1, wherein The descriptor includes an OPCODE pointer, access unit information, flash memory particle address information, system cache address, hardware control information, and address information of the next descriptor. The hardware control information includes a channel scheduling switch and a channel scheduling flag.

5. The access method to the flash memory cell based on descriptors according to claim 1, characterized in that, After the task scheduler sequentially reads the descriptors in the descriptor queue and determines whether there are other descriptors with the same access unit information as the current descriptor that have unfinished access tasks in the pending waiting area, it further includes: If there are access tasks of other descriptors with the same access unit information as the current descriptor that are unfinished in the pending waiting area, the task scheduler reads the next descriptor in the descriptor queue as the current descriptor, and repeats this step until there are no other descriptors with the same access unit information as the current descriptor that have unfinished access tasks in the pending waiting area.

6. The access method for flash memory cells based on descriptors according to claim 1, wherein After the task scheduler determines whether the channel scheduling switch of the current descriptor is in the first state, it further includes: When the channel scheduling switch of the current descriptor is in the second state, the task scheduler sends a second signal to the pending waiting area to enable the pending waiting area to periodically query the task completion status of other descriptors in the pending waiting area from the execution unit; The task scheduler schedules the current descriptor to the task parser, enabling the task parser to parse the current descriptor to form a control instruction; The execution unit performs an access operation on the flash memory particle according to the control instruction; When the execution time exceeds the preset time, the current descriptor is stored in the pending waiting area, the task parser pauses parsing the subsequent tasks of the current descriptor, and returns to the step of the task scheduler sequentially reading the descriptors according to the descriptor order in the descriptor queue and determining whether there are access tasks of other descriptors with the same access unit information as the current descriptor that are unfinished in the pending waiting area; When the descriptors in the pending waiting area meet the pending exit condition, the pending waiting area notifies the task scheduler. When the task scheduler is idle, the descriptors in the pending waiting area are rescheduled for subsequent parsing and execution work until the tasks of the descriptors are completed.

7. The access method to the flash memory cell based on the descriptor according to claim 1, wherein The task scheduler schedules the current descriptor to the task parser, enabling the task parser to parse the current descriptor to form a control instruction, including: The task scheduler looks up the corresponding task sequence from the OPCODE table according to the OPCODE pointer of the current descriptor, and sends the task sequence and the current descriptor to the task parser; The task parser parses the current descriptor and determines whether the task sequence is of the DMA start type, pending waiting type, FCU instruction type, or end type; If the type of the task sequence is the DMA start type, the task parser parses the current descriptor to generate an RDMA or WDMA start instruction; Alternatively, if the type of the task sequence is the pending wait type, the task parser stores the current descriptor in the pending wait area and suspends the subsequent parsing actions of the current descriptor; Alternatively, if the type of the task sequence is the FCU instruction type, the task parser reads the parameters and command sets in the task command table and generates instructions for accessing the flash memory particles according to the parameters and command sets; Alternatively, if the type of the task is the end type, the task parser generates instructions for updating the descriptor status to a specified position in the system cache and ends the entire descriptor parsing task.

8. A flash memory controller, characterized in that, Comprising: a descriptor queue, a task scheduler, a task parser, an execution unit, and a pending wait area, wherein the flash memory controller is configured to execute the method for accessing flash memory cells based on descriptors according to any one of claims 1-7.

9. A flash memory control system, characterized in that, Comprising: a flash memory controller, a descriptor reader, a CPU, a bus, and a system cache according to claim 8, wherein the bus is respectively connected to the flash memory controller, the descriptor reader, the CPU, and the system cache, the descriptor reader is connected to the flash memory controller, and the flash memory control system is configured to execute the method for accessing flash memory cells based on descriptors according to any one of claims 1-7.

Images