Integrated circuit bus system, data processing method and programmable logic unit

Abstract

The present application discloses an integrated circuit bus system, a data processing method and a programmable logic unit, which relate to the technical field of storage devices. The system includes a host, a programmable logic unit, a switch unit and a slave connected via a bus. If the processing module in the programmable logic unit detects that the slave receives a signal and does not respond within a predetermined time, it sends an abnormal signal to the host to cause the host to stop accessing the data. If the processing module in the programmable logic unit detects that the cumulative number of times the slave does not respond reaches a first preset cumulative number, it disconnects and re-enables the slave so that the slave can return to a normal state. If the target slave does not respond, the programmable logic unit promptly sends an abnormal signal to the host to prompt the host to stop accessing the data, thereby preventing the host from falling into a deadlock state. If the cumulative number of times the slave does not respond reaches a preset cumulative number, the programmable logic unit controls the switch unit to disconnect and enable the slave power supply after disconnection, thereby facilitating the slave to return to a normal state.

Description

Technical Field

[0001] The present application relates to the technical field of centralized storage devices, and in particular to an integrated circuit bus system, a data processing method applied to the integrated circuit bus system, and a programmable logic unit. Background Art

[0002] In centralized storage devices, a backup battery unit (BBU) typically provides temporary power to the entire device during data backups in the event of an unexpected power outage. The central processing unit (CPU) uses the I2C bus (Inter-Integrated Circuit Bus) to monitor and control the BBU's version information, charge and discharge, and other functions. Due to the complex connection path between the motherboard where the CPU resides and the power board where the BBU resides, and the hot-swappable nature of the BBU and power board, the I2C bus connecting the CPU to the BBU often experiences various abnormalities, leading to bus deadlocks and data loss during system backups.

[0003] Deadlock failures include deadlocks of slave devices such as BBU units, as well as deadlocks of the CPU control end. There is no effective recovery method for CPU deadlocks, and the only way to recover is to restart the CPU, but this carries the risk of service interruption. Summary of the Invention

[0004] The present application provides an integrated circuit bus system, a data processing method applied to the integrated circuit bus system, and a programmable logic unit, so as to at least solve the problem in the related art of lacking an effective solution to deal with host deadlock and slave deadlock.

[0005] The present application provides an integrated circuit bus system, comprising: a host, a programmable logic unit, a switch unit, and a slave, wherein the programmable logic unit includes a processing module, and the host and the programmable logic unit, the programmable logic unit and the switch unit, and the switch unit and the slave are all connected via an integrated circuit bus. If the processing module in the programmable logic unit detects that the slave has received a signal and has not responded within a predetermined time, the processing module sends an abnormal signal to the host to cause the host to stop accessing the data. If the processing module in the programmable logic unit detects that the cumulative number of times the slave has not responded reaches a first preset cumulative number, the processing module disconnects and re-enables the slave so that the slave returns to a normal state.

[0006] Optionally, the programmable logic unit also includes a shaping module and a sampling module. The shaping module is used to perform hysteresis comparison on the received integrated circuit bus signal. If the integrated circuit bus signal is higher than the signal upper limit value, it outputs a high level; if the integrated circuit bus signal is lower than the signal lower limit value, it outputs a low level. The sampling module is used to store the sampling value of the signal processed by the shaping module in a shift register, and when the sampling values ​​are the same for multiple consecutive times, the shift register is updated and determined to be a valid level. The sampling frequency of the sampling module is a preset multiple of the integrated circuit bus clock frequency.

[0007] Optionally, the processing module is further configured to detect the signal status from the host, jump to the next state if the combination of the serial data signal and the serial clock signal meets the start condition, and enter the end state if the combination meets the end condition.

[0008] Optionally, the programmable logic unit further includes a latch module, and the latch module is used to store the serial data signal in a latch register.

[0009] Optionally, the processing module is further configured to: detect the signal received from the latch register; if the serial data signal received from the latch register is abnormal within a clock cycle, the programmable logic unit stops signal forwarding.

[0010] Optionally, the processing module is further configured to: in a data routing state, if a slave address is matched, establish a connection between a bus signal line of the corresponding slave and an output signal line of the latch register.

[0011] Optionally, the processing module is further used to: if it is detected that the low level duration of the serial clock signal on the slave side exceeds a first preset time, forcibly pull up the serial clock signal for a preset number of pulses to generate an end condition, and record an error log; in the ACK return phase, if the low level duration of the serial data signal on the slave side exceeds a second preset time, forcibly pull up the serial data signal to generate an end condition, and record an error log, and the first preset time is greater than the second preset time.

[0012] Optionally, the processing module is further configured to: if the cumulative number of times that the slave device fails to respond reaches a second preset cumulative number, isolate the address of the slave device and upload device fault information to the host device.

[0013] Optionally, the processing module is further configured to: in the address matching stage, set a preset list of slave addresses, wherein the slave addresses in the preset list of slave addresses are allowed to be accessed.

[0014] Optionally, the programmable logic unit is further configured to: control the slave power supply to be enabled if it is detected that the slave power supply is valid; and control the switch unit to be closed if the slave power supply is successfully enabled.

[0015] Optionally, the switch unit includes a plurality of electrically connected MOS devices.

[0016] Optionally, the host is a controller, the slave is a backup battery unit, and the programmable logic unit is a complex programmable logic unit.

[0017] Optionally, there is one master and multiple slaves.

[0018] The present application also provides a data processing method applied to an integrated circuit bus system, comprising: receiving an integrated circuit bus signal sent by a host, and sending the integrated circuit bus signal to a slave after performing predetermined processing on the signal; judging whether the slave responds to the received signal within a predetermined time; if the slave does not respond within the predetermined time, sending an abnormal signal to the host so that the host stops the data access; if the cumulative number of times the slave does not respond reaches a first preset cumulative number, disconnecting the connection with the slave and re-enabling the slave so that the slave returns to a normal state.

[0019] Optionally, predetermined processing is performed on the integrated circuit bus signal, including: shaping the integrated circuit bus signal, the shaping step including performing hysteresis comparison on the integrated circuit bus signal, outputting a high level if the integrated circuit bus signal is higher than the signal upper limit value, and outputting a low level if the integrated circuit bus signal is lower than the signal lower limit value; sampling the signal after the shaping process, and storing the sampled value in a shift register, and updating the shift register when the sampled value is the same for multiple consecutive times and determining it as a valid level.

[0020] Optionally, the integrated circuit bus signal includes a serial data signal and a serial clock signal. After sampling the signal after the shaping processing, storing the sampling value in the shift register, and updating the shift register when the sampling value is the same for multiple consecutive times and determining it to be a valid level, the method also includes: storing the serial data signal in a latch register; matching the address in the serial data signal with the address in the preset list of slave addresses, and if the match is successful, connecting the bus signal line of the corresponding slave to the output signal line of the latch register.

[0021] Optionally, the method further includes: if the cumulative number of times that the slave device fails to respond reaches a second preset cumulative number, isolating the address of the slave device and uploading device fault information to the host.

[0022] Optionally, the method further includes: controlling the slave power supply to be enabled if it is detected that the presence signal of the slave is valid, wherein a level of the presence signal line is a preset level indicating that the presence signal is valid.

[0023] Optionally, the method further includes: if it is detected that the low level duration of the serial clock signal on the slave side exceeds a first preset time, forcibly pulling up the serial clock signal for a preset number of pulses to generate an end condition, and recording an error log; in the ACK return phase, if the low level duration of the serial data signal on the slave side exceeds a second preset time, forcibly pulling up the serial data signal to generate an end condition, and recording an error log, and the first preset time is greater than the second preset time.

[0024] The present application also provides a programmable logic unit, including: a receiving module, used to receive an integrated circuit bus signal sent by a host, and send the integrated circuit bus signal to a slave after performing predetermined processing on the integrated circuit bus signal; a judging module, used to judge whether the slave responds to the received signal within a predetermined time; a sending module, used to send an abnormal signal to the host if the slave does not respond within the predetermined time, so that the host stops the data access; a disconnecting module, used to disconnect the connection with the slave if the cumulative number of times the slave does not respond reaches a first preset cumulative number, and re-enable the slave so that the slave returns to a normal state.

[0025] Through the present application, due to the addition of a programmable logic unit and a MOS circuit on the slave side, if the target slave does not respond, the programmable logic unit promptly sends a NACK (Not Acknowledge) signal to the host, prompting the host to stop data access, thereby avoiding the host from waiting for a long time and falling into a deadlock state. Moreover, if the cumulative number of times the slave does not respond reaches a preset cumulative number, the programmable logic unit controls the MOS circuit to disconnect, and after disconnection, enables the slave power supply to facilitate the slave to return to normal state. Therefore, it is possible to solve the technical problem that the I2C bus connecting the CPU (host) to the slave (including the BBU unit) often has various abnormal scenarios that cause the bus to deadlock, resulting in data loss when the system is performing data backup, thereby achieving the technical effect of effectively dealing with host deadlock and slave deadlock. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0027] Figure 1A schematic diagram of the structure of an integrated circuit bus system provided in an embodiment of the present application;

[0028] Figure 2 A schematic diagram of the structure of another integrated circuit bus system provided in an embodiment of the present application;

[0029] Figure 3 A schematic diagram of the structure of a programmable logic unit provided in an embodiment of the present application;

[0030] Figure 4 A flowchart of a data processing method applied to an integrated circuit bus system provided in an embodiment of the present application;

[0031] Figure 5 Flowchart of the slave address preset list mechanism provided in the embodiment of the present application;

[0032] Figure 6 Schematic diagram of the I2C bus control system provided in an embodiment of the present application;

[0033] Figure 7 A schematic diagram of the internal functional modules of a complex programmable logic unit provided in an embodiment of the present application;

[0034] Figure 8 Schematic diagram of the I2C bus control system and method provided in an embodiment of the present application;

[0035] Figure 9 A schematic diagram of the I2C bus control system and method flow chart provided in an embodiment of the present application;

[0036] Figure 10 The SCL low level detection flow chart provided in the embodiment of the present application;

[0037] Figure 11 This is a flow chart of SDA low level detection provided in an embodiment of the present application;

[0038] Figure 12 A structural block diagram of a programmable logic unit provided in an embodiment of the present application.

[0039] The above drawings include the following reference numerals:

[0040] 01. Integrated circuit bus system; 10. Host; 20. Programmable logic unit; 30. Switch unit; 40. Slave; 201. Processing module; 202. Shaping module; 203. Sampling module; 204. Latch module. DETAILED DESCRIPTION

[0041] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments of this application, all other embodiments obtained by ordinary technicians in this field without making any creative work are within the scope of protection of this application.

[0042] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0043] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0044] The embodiment of the present application provides an integrated circuit bus system, such as Figure 1 As shown, the integrated circuit bus system 01 includes a host 10, a programmable logic unit 20, a switch unit 30, and a slave 40. The programmable logic unit 20 includes a processing module 201. The host 10 and the programmable logic unit 20, the programmable logic unit 20 and the switch unit 30, and the switch unit 30 and the slave 40 are all connected via an integrated circuit bus. If the processing module in the programmable logic unit detects that the slave receives a signal and does not respond within a predetermined time, it sends an abnormal signal to the host to cause the host to stop accessing the data. If the processing module in the programmable logic unit detects that the cumulative number of times the slave does not respond reaches a first preset cumulative number, it disconnects and re-enables the slave so that the slave returns to a normal state.

[0045] Specifically, an integrated circuit bus system includes a host, a programmable logic device (PLD), a switch unit, and slaves. These components are interconnected via the integrated circuit bus (IC) I2C, forming a multi-layered communication structure. The PLD serves as a hub for the integrated circuit bus system, responsible not only for signal processing and logic control but also for monitoring the status of slaves. Specifically, the PLD includes a processing module capable of detecting the slave's response after receiving a signal. If the processing module detects that the slave fails to respond (i.e., a NACK or no acknowledgement) within a predetermined time after receiving a signal, it sends an exception signal to the host, causing the host to immediately terminate the current data access to avoid unnecessary resource waste and potential system errors. If the slave fails to respond for a cumulative number of times exceeding a first predetermined number, this indicates a potential problem with the slave. In this case, the processing module of the PLD disconnects the slave and attempts to restore normal operation by re-enabling the slave. In this embodiment, if a slave fails to respond more than three times, hardware repair is performed on the slave device. This involves disconnecting the link between the slave and the programmable logic unit (PLD), re-enabling the slave's power supply, and attempting to restore normal operation. This process involves electrical isolation and restarting the slave device, aiming to eliminate potential faults and restore normal communication capabilities. The slave device can include a battery backup unit (BBU), an I2C expansion device, a GPIO (General-Purpose Input / Output) expansion device, a temperature sensor, or any other device controlled by the host CPU.

[0046] Through this mechanism, the integrated circuit bus system can proactively respond to unresponsive or abnormal slave devices, protecting the host from errors while attempting to repair the slaves, ensuring stable operation and data integrity of the entire I2C bus communication network. Compared to traditional I2C bus control systems, this design significantly enhances system robustness and fault recovery capabilities by introducing programmable logic units and intelligent response monitoring and repair logic. It is particularly suitable for applications requiring high reliability and fault tolerance, such as servers and storage devices.

[0047] Furthermore, if Figure 2As shown, the programmable logic unit 20 further includes a shaping module 202 and a sampling module 203. The shaping module is used to perform hysteresis comparison on the received integrated circuit bus signal. If the integrated circuit bus signal is higher than the upper limit of the signal, a high level is output; if the integrated circuit bus signal is lower than the lower limit of the signal, a low level is output. The sampling module is used to store the sampling value of the signal processed by the shaping module in a shift register, and when the sampling values ​​are the same for multiple consecutive times, the shift register is updated and determined to be a valid level. The sampling frequency of the sampling module is a preset multiple of the integrated circuit bus clock frequency.

[0048] Specifically, the shaping module is a signal preprocessing component within the programmable logic unit (PLU). Its primary task is to ensure that signals received from the I2C bus meet specific logic level standards. The shaping module achieves this function through hysteresis. When the received signal level exceeds the upper limit, the output is high; conversely, when the received signal level falls below the lower limit, the output is low. This hysteresis allows the shaping module to eliminate noise interference during signal transmission, ensuring the stability and reliability of the input signal.

[0049] The sampling module converts the shaped signal into a digital signal and stores it in a shift register. The sampling module operates at a preset multiple of the I2C bus clock frequency. This ensures that the sampling frequency accurately captures every change in the bus signal, avoiding data loss or errors caused by a mismatch between the sampling rate and the signal rate.

[0050] When the sampling module detects that the sampled values ​​are identical multiple times in a row, indicating that the signal has stabilized at a specific level (high or low), it updates the shift register to reflect the latest signal state and determines that state as a valid level. This process helps ensure data accuracy and integrity. Even if there are certain fluctuations or interference during signal transmission, the true state of the signal can be confirmed through continuous sampling.

[0051] The combination of the shaping and sampling modules provides two layers of protection for I2C bus signal processing within the programmable logic unit (PLU). First, the shaping module ensures signal stability and eliminates noise interference. Second, the sampling module ensures accurate signal conversion and storage through precise sampling and continuous level verification. This signal preprocessing and sampling mechanism is crucial for maintaining the reliability and accuracy of I2C bus communication, especially in environments with poor signal transmission quality or potential interference. Through the shaping and sampling modules, the programmable logic unit can more efficiently process and manage I2C bus signals, providing a more stable data transmission environment for the entire integrated circuit bus system, enhancing overall system performance and user experience.

[0052] Furthermore, the processing module is also used to detect the signal status from the host, jump to the next state if the combination of the serial data signal and the serial clock signal meets the start condition, and enter the end state if the combination meets the end condition.

[0053] Specifically, the processing module monitors I2C bus signals from the host, primarily the serial data signal (SDA) and the serial clock signal (SCL). Monitoring signal states ensures that data transmission and processing occur at the correct time between the sender and receiver. Based on the signal state detection, the processing module determines whether the current communication should transition to the next state or enter the end state according to preset rules or conditions. I2C bus communication can be understood using a state machine model, where different signal combinations correspond to different states, such as the start state, data transmission state, response state, and end state.

[0054] When the combination of the serial data signal and the serial clock signal meets the start condition, it indicates that one party (usually the host) is ready to begin or continue data transmission. Upon recognizing this condition, the processing module triggers the system to transition to the next state, allowing further data transmission. Conversely, if the signal combination indicates that communication should end, meaning that the end condition is met (for example, the host sends a stop signal), the processing module recognizes this signal combination and switches the system to the end state, halting the current data transmission process.

[0055] The processing module not only detects signal states but also automatically adjusts system behavior based on these states. This automated state transition control eliminates manual intervention, improves system response speed and efficiency, and reduces the likelihood of errors. State detection and control mechanisms are key to efficient and reliable I2C bus communication. Through the processing module's intelligent judgment, it automatically responds to the start, resume, and end of communication, ensuring smooth data transmission. It also rapidly responds to abnormal situations, such as retrying communication or entering fault isolation mode, thereby improving system robustness and fault tolerance.

[0056] Further, see Figure 3 The programmable logic unit 20 further includes a latch module 204, which is used to store the serial data signal in a latch register.

[0057] Specifically, the latch module is responsible for capturing and storing the serial data signal SDA on the I2C bus at specific points in time. In I2C communication, data is transmitted bit by bit under the control of the serial clock signal SCL. The latch module triggers a latch operation on the falling edge of each clock cycle, capturing the current data line voltage state and storing it in a latch register. This is because data validity is determined on the falling edge of the serial clock signal, and the signal on the data line may change before and after the falling edge. Therefore, the serial data signal must be latched at the falling edge. The latch register is a storage unit that temporarily stores the serial data signal captured by the latch module. As the clock cycle progresses, the contents of the latch register are continuously updated until the entire byte (or the required data length) of data is captured. This data can then be read and interpreted by the processing module for subsequent communication processing or error checking.

[0058] During the implementation, the latch module is first initialized and its operating parameters are set, including the address of the latch register and the latch's opening and closing timing signals. This initialization ensures that the latch module can correctly respond to subsequent signal changes and prepares for data latching. Simultaneously with the receipt of the serial data signal, the programmable logic unit simultaneously detects the serial clock signal. This is because in the I2C bus protocol, data sampling and latching typically occur on the rising edge of the clock signal, making it crucial to accurately capture clock signal changes. The received serial data signal is shaped to remove jitter and ensure signal clarity and stability. The shaped serial data signal is sampled on the rising edge of the serial clock signal, a stable point in data transmission. Sampling is the process of reading the current signal level to determine the actual data value (0 or 1). After sampling, the latch module stores the sampled serial data signal in the latch register, locking the sampled value of the serial data signal on the rising edge of the clock signal. The latch register can be considered a temporary data storage container, ensuring that the data is not altered by external interference during subsequent processing. The latch module will continuously latch the data of each sampling point according to the rhythm of the clock signal until the entire data byte is completely collected and latched.

[0059] By employing latch modules, the programmable logic unit (PLU) can capture serial data signals at the most critical moments of each clock cycle, thus avoiding data errors caused by signal instability or transmission delays. This ensures the stability and consistency of communication data in both time and space, reducing data distortion and misinterpretation, especially in high-speed communication scenarios. The introduction of latch modules significantly improves the data processing capability and transmission reliability of integrated circuit bus systems. It ensures that data can be accurately captured and processed even in complex communication environments, even in the presence of noise and interference. This has a direct positive impact on building high-performance, high-reliability communication systems.

[0060] Furthermore, the processing module is further configured to detect the signal received from the latch register; if the serial data signal received from the latch register is abnormal within a clock cycle, the programmable logic unit stops forwarding the signal.

[0061] Specifically, the processing module is also responsible for detecting the data signal received from the latch register. The latch register captures and stores the state of the serial data signal SDA on the falling edge of each clock cycle. This data is then read and analyzed by the processing module. Within a complete clock cycle, the processing module checks the signal stored in the latch register to determine whether there is any irregular or unexpected behavior. Anomalies in the serial data signal include sudden changes in the signal level, long periods of unchanged signal level, or changes that are inconsistent with other signals. These all indicate data errors or communication failures. If the processing module detects an abnormal state of the serial data signal within a certain clock cycle, such as an unexpected flip in the data bit or a continuous invalid level, it automatically takes action to prevent the abnormal data from being forwarded to the slave. The above mechanism is a system self-protection mechanism designed to avoid abnormal slave responses or system-level errors caused by erroneous data transmission.

[0062] By immediately stopping the forwarding of abnormal signals, the processing module can effectively contain potential data errors and prevent them from spreading throughout the system. This is crucial to the integrity of I2C bus communications, especially in data-sensitive applications such as storage devices and data processing centers, where ensuring accurate data transmission is a fundamental requirement of system design. This mechanism not only improves data transmission quality but also enhances the robustness of the entire integrated circuit bus system. Even in harsh electromagnetic environments or when transient faults occur in the communication link, the system can quickly identify and respond, avoiding the risk of long-term data errors or system crashes.

[0063] Furthermore, the processing module is further configured to: in a data routing state, if a slave address is matched, establish a connection between a bus signal line of the corresponding slave and an output signal line of the latch register.

[0064] Specifically, the data routing state refers to the stage in which the system is preparing to send data to a specific slave. The start of this state indicates that the host has sent the slave address and is waiting for the processing module of the programmable logic unit (PLD) to perform an address match to determine the target of the data transmission. After receiving the slave address sent by the host, the processing module compares it with a preset slave address list, which contains the address information of all slaves and is used to identify and verify the communication target. If the processing module identifies a successful address match, that is, it has found the slave corresponding to the address requested by the host, it proceeds to the next step. Once the slave address is successfully matched, the processing module establishes a connection between the bus signal line and the latch register output signal line. In other words, the slave's I2C bus interface is directly connected to the latch register output within the programmable logic unit (PLD), allowing data to flow from the latch register to the slave, completing the data transmission. This process ensures the correct flow of data to the slave.

[0065] In the data routing state, the processing module controls the connection of signal lines to enable data transmission from the master to the slaves. The latch register acts as a data buffer and stabilizer during this process, ensuring the integrity and accuracy of data during transmission. Through precise address matching and dynamic connection of signal lines, the processing module ensures that data is sent only to the correct slaves, improving communication efficiency and enhancing system security by preventing data from being received by unauthorized slaves.

[0066] Furthermore, the above-mentioned processing module is also used to: if it is detected that the low-level duration of the serial clock signal on the slave side exceeds the first preset time, forcibly pull up the above-mentioned serial clock signal for a preset number of pulses to generate an end condition, and record an error log; in the ACK return phase, if the low-level duration of the serial data signal on the above-mentioned slave side exceeds the second preset time, forcibly pull up the above-mentioned serial data signal to generate an end condition, and record an error log, and the above-mentioned first preset time is greater than the above-mentioned second preset time.

[0067] Specifically, the processing module continuously monitors the status of the slave's serial clock signal, SCL. If it detects that the serial clock signal remains low for longer than a first preset time (set according to the communication protocol and system requirements), this indicates that the slave controller has failed to properly release the clock signal, resulting in a bus deadlock or communication anomaly. In this case, the processing module forcibly pulls the serial clock signal high for a preset number of pulses to simulate a normal clock signal end condition, thereby breaking the deadlock and restoring normal bus communication. This mechanism prevents prolonged communication stagnation and avoids degradation of overall system performance.

[0068] During the ACK return phase, the processing module also monitors the state of the serial data signal SDA on the slave side. If the low-level state of the serial data signal continues for more than the second preset time, it indicates that the slave has failed to release the data line within the specified time, resulting in signal abnormality or communication blockage. Similarly, the processing module will force the serial data signal to be pulled high to simulate the normal end condition of the data signal to ensure that the bus can continue subsequent communication operations. The first preset time is greater than the second preset time because the abnormal response to the clock signal usually needs to be faster to avoid long-term system stagnation, while the abnormal response to the data signal can be slightly more relaxed under the premise of ensuring data integrity.

[0069] During the above process, the processing module also records the corresponding error log. The error log contains detailed information about the signal anomaly, such as the time of occurrence, the type of abnormal signal (clock signal or data signal), its duration, and the response measures taken. Error logs are crucial for subsequent problem analysis, troubleshooting, and system optimization. They provide a detailed record of system operating status, helping to quickly locate the root cause of the problem and take effective measures to repair or optimize it.

[0070] By introducing these signal anomaly detection and response mechanisms, as well as error logging, the processing module not only responds to communication anomalies in real time, ensuring communication stability and continuity, but also enhances system robustness and maintainability. Even in the event of hardware failures, software errors, or external interference, the system can quickly resume normal operation through self-recovery mechanisms, and error logging provides a basis for subsequent problem analysis.

[0071] Furthermore, the processing module is further configured to: if the cumulative number of times that the slave device fails to respond reaches a second preset cumulative number, isolate the address of the slave device and upload device fault information to the host device.

[0072] Specifically, the processing module continuously monitors the slave's response. If the slave fails to provide the expected response (acknowledgement or data signal) in consecutive communication attempts, the processing module will record the cumulative number of non-responses to help identify possible problems with the slave, such as software failures, hardware damage, or power supply issues. When the cumulative number of non-responses from the slave reaches a second preset cumulative number, further system response is triggered. The second preset cumulative number is set based on system stability and fault tolerance, and is intended to avoid making drastic system adjustments due to occasional communication failures. For example, if the second preset cumulative number is set to 5 times, this means that the slave must fail to respond for 5 consecutive times before the isolation mechanism is triggered.

[0073] When a slave fails to respond for a second preset number of times, the processing module isolates the slave's address from the current I2C communication network, effectively disconnecting it physically or logically from the bus. Address isolation is a crucial measure to prevent further deterioration of system communications and protect other normally functioning slaves. In addition to physical isolation, the processing module also transmits device failure information from the slave to the host, typically in the form of an interrupt or a specific data packet. This allows the host to identify abnormalities in the status of a specific slave on the network and implement appropriate fault handling strategies, such as reconfiguring the communication network, activating a backup slave, or notifying the system administrator for maintenance.

[0074] By detecting and responding to the cumulative number of unresponsiveness, timely isolation of faulty slaves and uploading of fault information are achieved. This not only improves the overall stability of the system and reduces the risk of communication interruption due to single slave failure, but also enhances the system's maintainability and fault diagnosis capabilities, enabling the system to respond to equipment failures within the network more intelligently and efficiently.

[0075] Furthermore, the processing module is further configured to: in the address matching stage, set a preset list of slave addresses, and the slave addresses in the preset list of slave addresses are allowed to be accessed.

[0076] Specifically, in I2C bus communication, before each communication begins, the host sends a slave address signal to specify the destination slave for this communication. The processing module enters the address matching phase, which receives and parses the slave address sent by the host, and then compares it with the system's internal slave address list. The slave address preset list lists all slave addresses that are allowed to be accessed. The slave address preset list can be defined during system initialization or dynamically updated at runtime to reflect the current system configuration and security policy. The existence of the slave address preset list ensures that only compliant slave addresses are recognized and responded to.

[0077] During the address matching phase, the processing module checks whether the slave address sent by the master is present in a preset list of slave addresses. If the address matches, meaning the slave address is within the preset list, the processing module allows communication to proceed. Otherwise, communication is blocked to prevent unauthorized access or malicious attacks. This security mechanism is particularly important for protecting the system from unauthorized access, especially in communication environments involving sensitive data or critical services.

[0078] By implementing a preset list of slave addresses, the processing module can effectively control which slaves can and cannot be accessed. This not only strengthens system security by preventing unlisted devices from intervening in communications and posing a threat, but also improves system controllability. The preset list of slave addresses provides a flexible access control strategy for the system. The preset list of slave addresses can be adjusted based on actual needs, such as adding new slave addresses, removing retired slave addresses, and even temporarily disabling certain slaves for maintenance or upgrades. This dynamic adjustment capability enables the system to adapt to changing environments and maintain efficient communication and operation.

[0079] Furthermore, the programmable logic unit is further configured to: control the slave power supply to be enabled if it is detected that the slave power supply is valid; and control the switch unit to be closed if the slave power supply is enabled successfully.

[0080] Specifically, the programmable logic unit continuously monitors and evaluates the slave's presence signal, which is a signal indicating whether the slave is ready to communicate. If the presence signal is detected to be valid, that is, the slave is ready and able to respond to communication requests, the programmable logic unit will proceed to the next step. Based on the validity of the presence signal, the programmable logic unit sends a power enable signal to the slave through its GPIO pin. The purpose of this signal is to activate the slave's power supply so that it can receive and process communication data at the physical level. If the power enable is successful, that is, the slave confirms receipt and responds to the power enable signal, the programmable logic unit will continue with the subsequent communication control process.

[0081] After confirming that the slave device has successfully enabled power, the programmable logic unit further controls the closure of the switch unit. Closing the switch unit establishes a physical communication link between the master and slave, allowing data to be transferred between them over the I2C bus. If power is not successfully enabled or the in-position signal is invalid, the programmable logic unit does not close the switch unit, thus protecting the system from sending data to an unprepared slave device, potentially preventing electrical damage or communication errors.

[0082] Through this mechanism, the programmable logic unit not only implements sophisticated power management, ensuring that slave devices receive power only when they need it, saving energy and reducing unnecessary hardware loss, but also enhances communication security by preventing the opening of communication links to unauthorized or unprepared slaves. This automated control process for power enablement and switching unit closure simplifies system integration, automatically adjusting slave device status based on communication needs without manual intervention, significantly improving communication efficiency and the overall automation level of the system.

[0083] Furthermore, the switch unit includes a plurality of electrically connected MOS devices.

[0084] MOS devices here refer to metal-oxide-semiconductor field-effect transistors (MOSFETs). Their low on-resistance, high switching speed, and excellent current control characteristics make them ideal switching elements. In particular, in bus communication systems that require frequent state switching, MOS devices can quickly respond to control signals from programmable logic units, efficiently opening and closing communication channels.

[0085] MOS devices can be connected in series and / or in parallel. A series configuration can increase voltage handling capability. For example, in high-voltage applications, connecting multiple MOS devices in series can share the high voltage, reducing stress on individual devices and improving overall system reliability. A parallel configuration can increase current carrying capacity, ensuring stable operation of the switch unit in high-current applications. The specific connection method will depend on the system design requirements and electrical specifications.

[0086] By using MOS devices as switching elements, integrated circuit bus systems enable refined power management and communication control. Programmable logic units (PLUs) can control the on and off states of MOS devices by varying their gate voltages, enabling dynamic management of communication links. For example, this can disconnect a slave device's power supply when it's offline, reducing unnecessary energy consumption; or rapidly terminate the link in the event of a communication anomaly, preventing electrical overload or data conflicts. The use and combination of MOS devices provides a high degree of flexibility in system design. Designers can flexibly select the number and connection method of MOS devices based on the current and voltage requirements of the specific application, achieving the optimal balance between performance and cost. This also facilitates system expansion and upgrades. For example, if additional communication links are needed, the number of MOS devices and the corresponding control logic can be increased without significantly modifying the existing circuit design. In short, the configuration of multiple electrically connected MOS devices not only meets the power management and signal isolation requirements of the communication process, but also enhances the system's scalability and adaptability, making it suitable for a variety of complex and diverse application scenarios.

[0087] Furthermore, the host is a controller, the slave is a backup battery unit, and the programmable logic unit is a complex programmable logic unit CPLD (Complex Programmable Logic Device).

[0088] Specifically, the host is the controller, meaning it's the device responsible for overall coordination and management. It's responsible for initiating communication requests, executing read and write operations, and managing and maintaining the communication protocol. In an I2C bus system, the controller (or host) is the central processing unit (CPU), responsible for controlling interactions with multiple slave devices to retrieve data, send commands, or query status.

[0089] The slave device is a battery backup unit (BBU), a component commonly found in servers, network equipment, and high-end computers. It provides emergency power in the event of a primary power failure, maintaining critical system functions. Communication between the programmable logic unit and the BBU is crucial because it ensures the system can quickly switch to backup power in the event of a primary power failure or other abnormal situation, ensuring data security and system operation.

[0090] The PLU is a complex programmable logic unit (CPLU), a highly integrated and powerful programmable logic device capable of implementing complex digital circuit logic functions such as signal processing, control algorithms, and communication protocols. The PLU not only serves as an I2C bus relay but also handles important logic control tasks such as signal shaping, sampling, latching, protocol parsing and exception handling, as well as switch unit control and slave power enable.

[0091] Designating the master as the controller, the slave as the battery backup unit, and specifying the programmable logic unit as a complex programmable logic unit (CPLU)—this system design is targeted at high-availability scenarios such as centralized storage devices or data centers. The PLU's high performance and flexibility ensure efficient and reliable communication between the controller and the battery backup unit, enabling rapid response in emergencies such as power failures, ensuring data integrity and system stability. Furthermore, the use of the PLU simplifies system design and maintenance, enabling hardware logic adjustments through software programming, improving system maintainability and upgrade potential.

[0092] Furthermore, there is one master and multiple slaves.

[0093] In a configuration with one master and multiple slaves, the master serves as the system's control center, responsible for initiating communications, coordinating data exchange, managing slave status, and overseeing the execution of communication protocols. In this application, the master establishes a connection with the programmable logic unit via the I2C bus, and then indirectly communicates with multiple slaves through the programmable logic unit, ensuring unified and orderly system communication.

[0094] Slaves can be distributed throughout the system, each with specific functions or tasks, such as data storage, sensor data acquisition, signal amplification, and power management. In this application, these slaves include different battery backup units, connected to the programmable logic unit via their own I2C bus, which manages communication with the master.

[0095] The programmable logic unit acts as a bridge between a host and multiple slaves. It not only handles the communication between the host and a specific slave, but is also responsible for dynamically adjusting the communication link according to the status of the slave (such as the presence signal and power enable signal), thereby achieving effective management and communication control of multiple slaves.

[0096] The configuration of one master with multiple slaves provides excellent scalability and flexibility. As system requirements grow, the number of slaves can be increased by simply expanding the number of GPIO pins and other resources in the programmable logic unit, without having to change the master's structure or logic. This flexibility allows the system to adapt to different scales and complexities.

[0097] The embodiment of the present application also provides a data processing method applied to an integrated circuit bus system, such as Figure 4 As shown, the method includes the following steps:

[0098] Step S401, receiving an integrated circuit bus signal sent by a host, performing predetermined processing on the integrated circuit bus signal, and then sending the signal to a slave;

[0099] Specifically, it receives integrated circuit bus signals from the host. These signals can be data read requests, data write instructions, or other types of control signals. After receiving the signal, it processes it according to its internal logic and pre-defined processing flow. This includes signal shaping to ensure signal integrity, sampling to ensure accurate signal reading, and protocol parsing to ensure compliance with the I2C bus communication protocol and avoid communication errors. After processing, it forwards the signal to the target slave device, initiating the slave's response process.

[0100] Step S402, determining whether the slave responds to the received signal within a predetermined time;

[0101] Specifically, the slave's response is monitored within a predetermined time window (predetermined time). This time window is set based on the I2C bus communication protocol and the slave's response speed. It is used to determine whether the slave has responded to the master's communication request within a reasonable timeframe. If a slave response signal is detected within the predetermined timeframe, the slave is considered to have successfully responded to the master's communication request. Conversely, if no response signal is detected, the exception handling process begins.

[0102] Step S403: If the slave does not respond within the predetermined time, an abnormal signal is sent to the host to cause the host to stop accessing the data.

[0103] Specifically, if a slave device fails to respond within a predetermined time, it sends an exception signal to the master. This signal informs the master that the slave device's failure to respond is due to a communication link problem, a slave device failure, or other reasons. Upon receiving the exception signal, the master device halts data access, avoiding continued data transmission to the unresponsive slave device and preventing potential communication errors and resource waste.

[0104] Step S404: If the cumulative number of times that the slave does not respond reaches a first preset cumulative number, disconnect the slave and re-enable the slave so that the slave returns to a normal state.

[0105] Specifically, if the cumulative number of unresponsive slaves reaches a preset threshold (a first preset cumulative number), the communication connection with the slave is disconnected, indicating a problem with the slave that requires diagnosis or repair. After disconnection, the slave is re-enabled and an attempt is made to restore its state. The re-enabling process includes sending a specific power-enable signal, executing an initialization sequence, or performing other fault recovery procedures to help the slave return to normal operating state. Re-enabling the slave provides it with an opportunity to restore its communication capabilities. If the slave successfully recovers, the communication link is re-established, and the slave can resume normal system communication.

[0106] The data processing method of the embodiment of the present application significantly enhances the communication stability and fault recovery capability of the integrated circuit bus system, especially the I2C bus system. By receiving and processing the signal of the host, the accuracy and integrity of the data are ensured, thereby optimizing the communication efficiency. The slave response monitoring mechanism can detect communication anomalies in a timely manner, and by sending an abnormal signal to the host, immediately terminate invalid data access, thereby avoiding the waste of system resources and possible accumulation of communication errors. When the cumulative number of times the slave does not respond exceeds a preset threshold, the connection with the slave is automatically disconnected and an attempt is made to re-enable. This mechanism can not only effectively isolate the faulty slave and prevent it from affecting the overall communication of the system, but also provide the possibility of automatic recovery of the slave state, greatly improving the self-repair capability and high availability of the system.

[0107] Furthermore, the integrated circuit bus signal is subjected to predetermined processing, including: performing shaping processing on the integrated circuit bus signal, the shaping processing step including performing hysteresis comparison on the integrated circuit bus signal, outputting a high level if the integrated circuit bus signal is higher than the upper limit value of the signal, and outputting a low level if the integrated circuit bus signal is lower than the lower limit value of the signal; sampling the signal after the shaping processing, and storing the sampled value in a shift register, and updating the shift register when the sampled values ​​are the same for multiple consecutive times and determining it as a valid level.

[0108] Specifically, the purpose of signal shaping is to ensure signal quality and make it less susceptible to noise or interference during transmission. Hysteresis comparator requires the signal to exceed a certain range before changing the output state. This prevents the signal from frequently jumping under the influence of noise and improves signal stability. If the IC bus signal is above the upper signal limit, the shaping process adjusts it to a high level; conversely, if the IC bus signal is below the lower signal limit, it is adjusted to a low level. This mechanism ensures that even slight signal distortion during transmission can be corrected to a standard level range, thereby ensuring signal recognizability and communication accuracy.

[0109] The shaped signal is then sampled, and the sampled values ​​are sequentially stored in a shift register. If the values ​​of multiple consecutive samples are the same, it means that the signal has remained at a relatively stable level for a period of time. At this time, the contents of the shift register are updated, and the corresponding level is considered valid. This mechanism filters out brief signal fluctuations or noise, identifying only those level changes that last longer and represent the true signal state, thereby improving signal processing accuracy and communication reliability.

[0110] Shaping effectively reduces signal distortion and noise interference, ensuring signal transmission quality and integrity. Sampling combined with continuous value determination accurately identifies the true state of the signal, ensuring accurate data reading even in complex and dynamic communication environments. This processing significantly improves the communication efficiency and stability of integrated circuit bus systems.

[0111] Furthermore, the above-mentioned integrated circuit bus signal includes a serial data signal and a serial clock signal. After sampling the signal after the above-mentioned shaping processing, and storing the sampling value in the shift register, and updating the above-mentioned shift register when the above-mentioned sampling values ​​are the same for multiple consecutive times and determining them to be a valid level, the above-mentioned method also includes: storing the above-mentioned serial data signal in a latch register; matching the address in the above-mentioned serial data signal with the address in the preset list of slave addresses, and if the match is successful, connecting the bus signal line of the corresponding slave to the output signal line of the above-mentioned latch register.

[0112] Specifically, after signal shaping and sampling, and after determining the valid level of the sampled value, the serial data signal is stored in a latch register. The latch register captures and holds the signal state during a clock cycle until the next clock cycle. This is crucial for subsequent data processing, as the latch register ensures that the data remains unchanged while being read or processed, improving data consistency and predictability.

[0113] Communication in the I2C bus system is address-based, with each slave having a unique address. Later in the signal processing phase, the serial data signal stored in the latch register is parsed to extract the slave address information contained therein. This address information is then compared with a preset list of slave addresses to determine the identity of the target slave. The preset list of slave addresses is a database of all possible slave addresses. By matching the addresses in the signal, the target slave can be quickly located. If the address match is successful—that is, the slave address specified in the serial data signal matches an address in the preset list of slave addresses—the corresponding slave is selected for communication. Specifically, the bus signal line of the selected slave is connected to the output signal line of the latch register, preparing for data read and write operations.

[0114] The use of latch registers further ensures data integrity and consistency based on the results of signal shaping and sampling processing, preventing the impact of transient changes during data transmission on communication. The address matching mechanism ensures that the host can accurately identify and select the correct slave for communication, reducing communication delays and errors and improving communication efficiency. Combined with signal shaping and sampling processing, address matching further enhances the communication reliability of the I2C bus system, effectively filtering out noise and avoiding communication failures caused by address resolution errors.

[0115] Furthermore, the method further includes: if the cumulative number of times that the slave device fails to respond reaches a second preset cumulative number, isolating the address of the slave device and uploading device fault information to the host.

[0116] Specifically, if the cumulative number of slave failures reaches a higher warning threshold, namely the second preset cumulative number, this indicates that the slave may have a serious communication failure or hardware issue, requiring further measures to prevent it from impacting the entire system. In this case, further communication attempts will be discontinued, and its address will be isolated. This means that in subsequent communication polling cycles, the slave's address will be ignored by the system and will not be selected by the master for data access or control command transmission. This measure avoids continued attempts to contact a faulty or abnormal slave, reducing unnecessary communication overhead and preventing potential communication conflicts or erroneous commands from impacting the system. In addition to address isolation, slave fault information is also uploaded to the master. This information includes the slave's ID, fault type (e.g., communication failure), and the number of abnormal responses. Upon receiving this information, the master can perform higher-level error handling based on the fault information, such as logging the fault, activating a backup slave, or executing a fault recovery procedure. This process ensures timely response and management of faults, improving the overall stability and resilience of the system.

[0117] By setting a second preset cumulative count, a more conservative yet effective strategy can be adopted after initial recovery attempts fail, preventing the failure of a single slave from impacting the normal operation of the entire system. The slave address isolation mechanism reduces ineffective communication attempts with a faulty slave, optimizes the allocation of communication resources, and improves system communication efficiency and overall performance. Uploading fault information enables the host to conduct more detailed analysis and recording of slave failures, facilitating subsequent fault diagnosis, equipment maintenance, and the execution of fault recovery procedures, thereby enhancing the system's self-healing capabilities and maintenance efficiency.

[0118] Furthermore, the method further includes: controlling the power supply of the slave device to be enabled if it is detected that the presence signal of the slave device is valid, wherein a level of the presence signal line is a preset level indicating that the presence signal is valid.

[0119] Specifically, the presence signal indicates whether a slave is in a communicative state. It is transmitted via a dedicated signal line (the presence signal line). The level of the presence signal line is continuously monitored to determine whether the slave is online and ready to receive or respond to communication requests. When the level of the presence signal line reaches a preset level, the signal is valid, indicating that the slave is in a communicative state. The preset level is set based on the slave's hardware characteristics and communication protocol requirements, and serves as a logical basis for distinguishing whether a slave is online. When the slave's presence signal is detected to be valid, the slave's power enable signal is controlled, allowing the slave to receive data or perform other communication operations. The power enable signal typically controls the slave's power supply, ensuring that its power is activated only when the slave is online and ready to communicate, thereby avoiding unnecessary energy consumption. The above mechanism ensures a logical connection between the slave's presence signal and the power enable signal. The slave's power is activated only when it is in a communicative state, and is otherwise shut down. This not only enhances the accuracy of slave status management but also improves system energy efficiency and security.

[0120] By detecting the presence signal and controlling the slave power supply accordingly, the system precisely manages the slave's status, ensuring that only online slaves can participate in communication and avoiding ineffective communication attempts with offline slaves. The power-enable control mechanism prevents unnecessary slave power supply, reducing energy waste. Ensuring consistency between the slave's presence status and its power supply status prevents communication issues caused by unstable or abnormal power supply conditions, improving overall system stability and security.

[0121] Furthermore, the above method also includes: if it is detected that the low level duration of the serial clock signal on the slave side exceeds the first preset time, forcibly pulling up the above serial clock signal for a preset number of pulses to generate an end condition, and recording an error log; in the ACK return phase, if the low level duration of the serial data signal on the slave side exceeds the second preset time, forcibly pulling up the above serial data signal to generate an end condition, and recording an error log, and the above first preset time is greater than the above second preset time.

[0122] Specifically, I2C bus communication relies on a serial clock signal to synchronize data transmission. If the serial clock signal on the slave side is detected to remain low for longer than a first preset time, it indicates that the slave controller has failed to release the clock signal normally, resulting in a bus deadlock or communication anomaly. In this case, the serial clock signal is forced high for a preset number of pulses to simulate the normal end condition of the clock signal, thereby breaking the deadlock and restoring normal bus communication. This mechanism can prevent long-term communication stagnation and avoid a decline in overall system performance.

[0123] The ACK (Acknowledgement) signal is a feedback signal used in I2C communication to confirm data reception. It is typically issued by the slave after data transmission is complete. If the serial data signal remains low for longer than a second preset time during the slave's response phase, this indicates that the slave failed to release the data line within the specified time, resulting in a signal anomaly or communication blockage. In this case, the serial data signal is forced high to simulate a normal end condition for the data signal, ensuring that the bus can continue subsequent communication operations. The first preset time is longer than the second preset time because a faster response to clock signal anomalies is generally required to avoid prolonged system stagnation, while a slightly more relaxed response to data signal anomalies can be achieved while ensuring data integrity.

[0124] In both of the above cases, regardless of whether intervention is taken due to anomalies in the serial clock or serial data signals, a detailed error log is recorded. The error log includes detailed information about the signal anomaly, such as the time of occurrence, the type of abnormal signal (clock or data), its duration, and the response measures taken. Error logs are crucial for subsequent problem analysis, troubleshooting, and system optimization. They provide a detailed record of system operating status, helping to quickly locate the root cause of the problem and take effective repair or optimization measures.

[0125] By forcibly pulling the signal high to generate an end condition, communication can be proactively intervened and restored, shortening downtime and mitigating the negative impact of data loss or communication failures. Error logs provide troubleshooting clues, helping to quickly locate problems and implement targeted system repairs, improving system availability and maintenance efficiency. This ensures timely action when signal anomalies occur, preventing prolonged unstable communication links and enhancing the robustness and anti-interference capabilities of I2C bus communication.

[0126] Through the description of the above implementation methods, those skilled in the art can clearly understand that the method according to the above embodiment can be implemented by means of software plus the necessary general hardware platform, and of course it can also be implemented by hardware, but in many cases the former is a better implementation method.

[0127] In I2C communication, the clock signal is typically generated by the master, but slaves are allowed to extend the current clock cycle by pulling down the serial clock signal (SCL) when receiving or processing data. This process is called clock stretching. CPLDs can be designed with dynamic clock stretching control, automatically adjusting the clock stretching duration based on the actual responsiveness of the slave. For example, if the CPLD detects a slow slave response, it can allow longer clock stretching to ensure the slave has sufficient time to process data and avoid data transmission errors.

[0128] The CPLD monitors I2C bus communication and dynamically adjusts the communication rate based on real-time communication conditions, such as signal quality and slave device response speed. When poor communication quality or limited slave device processing power is detected, the CPLD automatically reduces the transmission rate to minimize communication errors. Conversely, when communication conditions are favorable, the CPLD increases the rate to accelerate data transmission and improve system efficiency. This adaptive adjustment mechanism ensures stable and efficient I2C bus communication under various operating environments.

[0129] The integrated circuit bus system of the present application and the data processing method applied thereto are described below through a specific embodiment.

[0130] This application adds a programmable logic unit between the CPU host and the slave, thereby recovering from slave deadlock and avoiding CPU-side host deadlock, significantly improving the reliability of the I2C bus and ensuring the stable operation of electronic equipment.

[0131] This application includes the following key components and corresponding functions:

[0132] The master, acting as the controller of the I2C bus control system, connects its I2C signals to the CPLD's GPIO pins. It has a retry mechanism when accessing slave data. Upon receiving a NACK signal, it automatically re-initiates data access. If a NACK signal is still received after three retries, the address is isolated and a device error is reported. This prevents persistent issues caused by a single communication anomaly.

[0133] The switch unit consists of multiple electrically connected MOS devices, which together form a MOS circuit. This MOS circuit serves as the switching link between the CPLD and the slave device and is controlled by the CPLD's GPIO. When the CPLD detects the slave device is present and powered, the link is reconnected. When the repair mechanism is triggered, the link is disconnected and reconnected, ensuring timely communication link connection and providing the necessary electrical isolation for slave device repair operations.

[0134] Slave: As a slave device in the I2C bus control system, its power enable signal and presence signal are connected to the CPLD's GPIO pins. The CPLD controls the activation of the power enable signal based on the slave presence signal detected, achieving precise control of the slave's power supply and ensuring that the slave is not incorrectly powered when not in the presence state.

[0135] CPLD: As the transfer station of the I2C bus control system, it undertakes the core signal processing and logic control functions. Two of its GPIOs are connected to the host I2C bus, and the other two GPIOs are connected to the slave I2C bus. Using the Verilog hardware description language, it implements several important functions:

[0136] Shaping Module: Implementing a Schmitt trigger in Verilog language, this module performs hysteresis comparison on the input I2C signal to eliminate signal noise. Setting the upper limit parameter HYSTERESIS_HIGH and the lower limit parameter HYSTERESIS_LOW ensures a stable and reliable input signal by outputting a high level when the input signal exceeds the upper limit and a low level when it falls below the lower limit.

[0137] Sampling Module: This module samples the signal at a high frequency, four times the I2C clock frequency, and stores the sampled values ​​in a shift register. The register is updated and considered valid only when three consecutive sampled values ​​are identical. This ensures the accuracy and stability of the sampling results, providing a reliable basis for subsequent signal processing.

[0138] Latch module: On the rising edge of I2C's SCL, the SDA signal is placed in the latch register to buffer the I2C signal and provide a stable signal source for protocol analysis and exception handling.

[0139] Processing module: including protocol analysis submodule and exception handling submodule, which performs comprehensive protocol analysis on the latched I2C signal, covering multiple important states such as START / STOP status detection, protocol filtering, address matching, data routing, signal forwarding and error detection. Specifically:

[0140] In terms of START / STOP state detection, the signal state from the host is strictly detected. When the combination of SCL and SDA meets the START condition, it immediately jumps to the next state; and when the combination meets the STOP condition, it quickly enters the STOP state to ensure that the state transition during the communication process is accurate.

[0141] During the abnormal signal analysis phase, the signal from the latch is carefully tested. If the SDA signal exhibits unexpected behavior, such as a continuously low or high level within a clock cycle, it is considered an abnormal signal. In this case, the CPLD returns an ACK signal and does not forward the signal, effectively preventing the abnormal signal from propagating on the bus and potentially interfering with other devices.

[0142] During the address matching phase, a preset list of slave addresses is set. When the address sent by the host is a legal address, the address signal is forwarded to the slave; otherwise, if the address is illegal, the CPLD sends a NACK signal to the host and records a detailed error log, providing key information for subsequent troubleshooting. The flowchart of the slave address preset list mechanism can be found in Figure 5 .

[0143] In the data routing state, once the slave address is matched, the connection between the I2C signal line of the corresponding slave and the latch output signal line is immediately established to ensure the accurate establishment of the data transmission path and the correct transmission of data.

[0144] In the signal forwarding state, the address and data bits in the latch register are accurately sent to the corresponding slave device. If the target slave device does not respond, the CPLD promptly sends a NACK signal to the host, prompting the host to stop data access, avoiding the host from waiting for a long time and falling into a deadlock state.

[0145] In the error detection phase, the SDA and SCL signals are tested for low-level timeouts:

[0146] Once it detects that the SCL low level on the slave side lasts for more than 35ms, the CPLD decisively forces the SCL signal to be pulled high for 9 pulses, generates a STOP condition, and records the corresponding error log; if the SCL low level does not time out, communication continues normally, ensuring the normal periodic changes of the SCL signal and maintaining smooth communication.

[0147] For the SDA signal, if it is continuously low during the data bit stage, it is considered normal communication; however, during the ACK return stage, if the SDA low level lasts for more than 4ms, the CPLD will force the SDA signal to be high, generate a STOP condition, and record an error record to prevent the abnormal continuous low level state of the SDA signal from affecting the entire communication system.

[0148] When a slave device experiences an error for the first time, the system records an alarm status. If the number of errors exceeds three, the slave device hardware is repaired, that is, the link between the control slave and the CPLD is disconnected, and the slave device power is re-enabled to try to restore the slave device to normal operation. If the number of errors on a slave device exceeds five, the device address is isolated to prevent the faulty slave from further affecting the entire I2C bus system, ensuring system reliability and stability.

[0149] Specifically, if Figure 6 As shown, the integrated circuit bus system of the present application is composed of a host, a complex programmable logic unit (CPLD), a switch unit, and a slave. The switch unit includes multiple electrically connected MOS devices, and the multiple electrically connected MOS devices form a MOS circuit. The host's I2C signal is connected to the GPIO pin of the CPLD. The MOS circuit serves as a switch link between the CPLD and the slave and is controlled by the GPIO of the CPLD. The power enable signal and the in-position signal of the slave are connected to the GPIO pin of the CPLD. The CPLD controls the activation of the power enable signal based on the detection result.

[0150] CPLD is the core transfer station of the system, and its internal functional modules are as follows Figure 7As shown in the figure, the shaping module uses a Schmitt trigger to perform hysteresis comparison on the input I2C signal to eliminate noise. The sampling module samples the signal at a frequency four times that of the I2C clock to ensure sampling accuracy. The latch module latches the SDA signal into the register on the rising edge of SCL. The processing module includes a protocol parsing submodule and an exception handling submodule. The protocol parsing and exception handling submodules are responsible for performing a series of protocol parsing and exception handling operations on the latched signal.

[0151] When the host sends data to the slave, the signal is shaped, sampled, latched, and processed by the CPLD before entering the protocol parsing submodule and the exception handling submodule. First, the START state is detected to confirm the start of communication; then the signal is filtered by protocol, and the address is matched. If the address match is successful, the data routing state is entered to establish a slave signal line connection; then, in the signal forwarding state, the data is sent to the corresponding slave. If an abnormality occurs during the process, such as no response from the slave or a low-level signal timeout, the CPLD processes it according to the corresponding rules, such as sending a NACK signal, recording an error log, forcibly pulling up the signal to generate a STOP condition, etc., and triggering the hardware repair mechanism when necessary to control the MOS circuit to disconnect the link and re-enable the slave power supply, or to isolate the faulty slave address. The schematic diagram of the I2C bus control system and method can be found in Figure 8 .

[0152] In practical applications, an I2C bus system including multiple slaves is used as an example to describe the operation process of this application in detail. Figure 9 .

[0153] Assume that the system has three slaves with addresses 0x50, 0x51, and 0x52. The CPLD internally presets the slave addresses to 0x50, 0x51, and 0x52.

[0154] When the host needs to read data from slave 0x50, it sends a data frame containing the slave address 0x50 and the read command via the I2C bus. The host's I2C signal is transmitted to the CPLD via its GPIO pins. The CPLD's shaping module first processes the incoming I2C signal, eliminating signal noise using a Schmitt trigger. For example, if the I2C signal experiences slight fluctuations during transmission due to line interference or other factors, the shaping module can smooth these fluctuations, ensuring that subsequent processing modules receive a stable signal.

[0155] Next, the sampling module samples the signal at a frequency four times that of the I2C clock. Assuming the I2C clock frequency is 100kHz, the sampling module's sampling frequency is 400kHz. The sampled values ​​are stored in a shift register. Only when three consecutive sample values ​​are identical is the register updated and considered a valid level. This effectively avoids misjudgments caused by occasional signal glitches.

[0156] On the rising edge of the I2C SCL signal, the latch module latches the SDA signal into the latch register. Subsequently, the protocol parsing and exception handling submodules begin operation. First, a START state check is performed to confirm that the host has initiated a new communication request. The signal is then filtered to check whether the data frame complies with the I2C protocol specification. During the address matching phase, the master's address 0x50 is compared with the preset list of slave addresses. If a match is found, the data routing state is entered, connecting the I2C signal line 0x50 of the slave to the latch output signal line.

[0157] In the signal forwarding state, the CPLD sends the address bits and read command data bits in the latch register to slave 0x50. After receiving the address and command, slave 0x50 returns the corresponding data. If slave 0x50 responds normally, the data is forwarded back to the host through the CPLD, completing a successful read operation.

[0158] If slave 0x50 fails to respond due to a fault and does not send an acknowledgment signal to the CPLD within the specified time, the CPLD detects this and sends a NACK signal to the host. Upon receiving this signal, the host stops accessing the data. The CPLD then records the slave's error count. If the error count for slave 0x50 reaches three, the CPLD triggers a hardware repair mechanism, controlling the MOS circuit to disconnect the link with slave 0x50 and re-enable the power supply to slave 0x50. After power is restored, slave 0x50 performs a reset and initialization operation, attempting to resume normal operation. After a period of time, the CPLD attempts to establish a connection with slave 0x50 again. If the connection is successful and communication is normal, the device is allowed to communicate with the CPLD again. If the error count for slave 0x50 increases further, exceeding five, the CPLD isolates the device address 0x50 and stops sending data access requests to it. The CPLD also reports the device's fault information to the host for subsequent maintenance.

[0159] To detect the presence of a slave, the CPLD monitors the slave's presence signal line in real time. For example, when the presence signal line of slave 0x51 is high, the CPLD determines that the slave is present. It then turns on the slave's power enable signal, providing power to slave 0x51, enabling it to operate normally and participate in I2C bus communications. If the presence signal line is low, the CPLD does not turn on the power enable signal, preventing ineffective power supply to an absent slave.

[0160] During the communication process, the CPLD continuously performs error detection. Figure 10 This is the SCL low-level detection flow chart. Taking the SCL signal detection as an example, if the slave's SCL low level persists for more than 35ms, the CPLD immediately forces the SCL signal high for nine pulses, generating a STOP condition, terminating the current abnormal communication process, and recording an error log. This prevents the entire I2C bus from being blocked due to a persistent low SCL signal on the slave, which could affect the communication of other normal slaves.

[0161] See also Figure 11 For the SDA signal, if it remains low during the data bit transmission phase, it is considered normal communication, such as when the slave is sending data. However, if the SDA low level persists for more than 4ms during the ACK return phase, the CPLD will force the SDA signal high, generating a STOP condition and logging an error. This helps to promptly handle abnormal, sustained low-level SDA signals during the ACK phase, ensuring accurate and timely communication.

[0162] CPLDs can integrate intelligent fault detection capabilities that not only detect anomalies in I2C bus signals (such as sustained high or low states), but also identify more complex issues such as abnormal slave response patterns and sudden changes in communication traffic. Once a fault is detected, the CPLD immediately records the fault information and takes appropriate action based on pre-defined fault handling strategies.

[0163] After detecting a fault, the CPLD can perform a series of preset automatic recovery operations, such as resetting the I2C bus, retrying communication, and switching to a backup slave, to minimize the fault's impact on the system. For recoverable faults, such as momentary signal interference, the automatic recovery mechanism can quickly restore communication, eliminating manual intervention and improving the system's self-healing capabilities.

[0164] The embodiment of the present application also provides a programmable logic unit, such as Figure 12As shown, the programmable logic unit includes a receiving module 100, a judging module 200, a sending module 300, and a disconnecting module 400. The receiving module is used to receive an integrated circuit bus signal sent by the host, and send the integrated circuit bus signal to the slave after performing predetermined processing on the signal; the judging module is used to determine whether the slave responds to the received signal within a predetermined time; the sending module is used to send an abnormal signal to the host if the slave does not respond within the predetermined time, causing the host to stop the current data access; and the disconnecting module is used to disconnect the slave if the cumulative number of times the slave does not respond reaches a first preset cumulative number, and re-enable the slave so that the slave returns to a normal state.

[0165] The above embodiments significantly enhance the communication stability and fault recovery capability of the integrated circuit bus system, especially the I2C bus system. By receiving and processing the host's signal, the accuracy and integrity of the data are ensured, thereby optimizing the communication efficiency. The slave response monitoring mechanism can detect communication anomalies in a timely manner, and by sending an abnormal signal to the host, immediately terminate invalid data access, thereby avoiding the waste of system resources and possible accumulation of communication errors. When the cumulative number of times the slave does not respond exceeds a preset threshold, the connection with the slave is automatically disconnected and an attempt is made to re-enable it. This mechanism can not only effectively isolate the faulty slave and prevent it from affecting the overall communication of the system, but also provides the possibility of automatic recovery of the slave state, greatly improving the self-repair capability and high availability of the system.

[0166] Furthermore, the receiving module includes a shaping submodule and a sampling submodule. The shaping submodule is used to perform shaping processing on the integrated circuit bus signal, wherein the shaping processing step includes performing hysteresis comparison on the integrated circuit bus signal, outputting a high level if the integrated circuit bus signal is higher than the upper limit of the signal, and outputting a low level if the integrated circuit bus signal is lower than the lower limit of the signal; the sampling submodule is used to sample the signal after the shaping processing and store the sampled values ​​in a shift register. If the sampled values ​​are the same multiple times in a row, the shift register is updated and determined to be a valid level.

[0167] Shaping effectively reduces signal distortion and noise interference, ensuring signal transmission quality and integrity. Sampling combined with continuous value determination accurately identifies the true state of the signal, ensuring accurate data reading even in complex and dynamic communication environments. This processing significantly improves the communication efficiency and stability of integrated circuit bus systems.

[0168] Furthermore, the integrated circuit bus signal includes a serial data signal and a serial clock signal, and the programmable logic unit further includes a storage module and a matching module. The storage module is configured to sample the signal after the shaping process and store the sampled values ​​in a shift register. After the shift register is updated and determined to be at a valid level multiple times when the sampled values ​​are identical, the serial data signal is stored in a latch register. The matching module is configured to match the address in the serial data signal with an address in a preset list of slave addresses. If a match is successful, the bus signal line of the corresponding slave is connected to the output signal line of the latch register.

[0169] The use of latch registers further ensures data integrity and consistency based on the results of signal shaping and sampling processing, preventing the impact of transient changes during data transmission on communication. The address matching mechanism ensures that the host can accurately identify and select the correct slave for communication, reducing communication delays and errors and improving communication efficiency. Combined with signal shaping and sampling processing, address matching further enhances the communication reliability of the I2C bus system, effectively filtering out noise and avoiding communication failures caused by address resolution errors.

[0170] Furthermore, the programmable logic unit further includes an isolation module for isolating the address of the slave and uploading device fault information to the host if the cumulative number of times the slave fails to respond reaches a second preset cumulative number.

[0171] By setting a second preset cumulative count, a more conservative yet effective strategy can be adopted after initial recovery attempts fail, preventing the failure of a single slave from impacting the normal operation of the entire system. The slave address isolation mechanism reduces ineffective communication attempts with a faulty slave, optimizes the allocation of communication resources, and improves system communication efficiency and overall performance. Uploading fault information enables the host to conduct more detailed analysis and recording of slave failures, facilitating subsequent fault diagnosis, equipment maintenance, and the execution of fault recovery procedures, thereby enhancing the system's self-healing capabilities and maintenance efficiency.

[0172] Furthermore, the programmable logic unit further includes a control module for controlling the slave power supply to be enabled if it is detected that the presence signal of the slave is valid, wherein the presence signal line level being a preset level indicates that the presence signal is valid.

[0173] By detecting the presence signal and controlling the slave power supply accordingly, the system precisely manages the slave's status, ensuring that only online slaves can participate in communication and avoiding ineffective communication attempts with offline slaves. The power-enable control mechanism prevents unnecessary slave power supply, reducing energy waste. Ensuring consistency between the slave's presence status and its power supply status prevents communication issues caused by unstable or abnormal power supply conditions, improving overall system stability and security.

[0174] Furthermore, the programmable logic unit further includes a first pull-up module and a second pull-up module. The first pull-up module is configured to forcibly pull the serial clock signal high for a preset number of pulses to generate an end condition and record an error log if it detects that the low-level duration of the serial clock signal on the slave side exceeds a first preset time; and the second pull-up module is configured to forcibly pull the serial data signal high to generate an end condition and record an error log if the low-level duration of the serial data signal on the slave side exceeds a second preset time during the ACK return phase, wherein the first preset time is greater than the second preset time.

[0175] By forcibly pulling the signal high to generate an end condition, communication can be proactively intervened and restored, shortening downtime and mitigating the negative impact of data loss or communication failures. Error logs provide troubleshooting clues, helping to quickly locate problems and implement targeted system repairs, improving system availability and maintenance efficiency. This ensures timely action when signal anomalies occur, preventing prolonged unstable communication links and enhancing the robustness and anti-interference capabilities of I2C bus communication.

[0176] For the description of the features in the embodiments corresponding to the programmable logic unit, reference can be made to the relevant description of the embodiments corresponding to the data processing method applied to the integrated circuit bus system, which will not be repeated here.

[0177] An embodiment of the present application also provides an electronic device, including a memory and a processor, wherein the memory stores a computer program, and the processor is configured to run the computer program to execute the steps of any of the above-mentioned data processing method embodiments applied to an integrated circuit bus system.

[0178] An embodiment of the present application further provides a computer-readable storage medium storing a computer program, wherein the computer program is configured to execute the steps of any of the above-mentioned data processing method embodiments applied to an integrated circuit bus system when run.

[0179] In an exemplary embodiment, the computer-readable storage medium may include, but is not limited to, various media that can store computer programs, such as a USB flash drive, a read-only memory (ROM), a random access memory (RAM), a mobile hard disk, a magnetic disk, or an optical disk.

[0180] An embodiment of the present application further provides a computer program product, which includes a computer program. When the computer program is executed by a processor, the steps of any of the above-mentioned data processing method embodiments applied to an integrated circuit bus system are implemented.

[0181] An embodiment of the present application also provides another computer program product, including a non-volatile computer-readable storage medium, the non-volatile computer-readable storage medium storing a computer program, and when the computer program is executed by a processor, implementing the steps of any of the above-mentioned data processing method embodiments applied to an integrated circuit bus system.

[0182] Professionals may further appreciate that the units and algorithm steps of each example described in conjunction with the embodiments disclosed herein can be implemented in electronic hardware, computer software, or a combination of the two. In order to clearly illustrate the interchangeability of hardware and software, the above description has generally described the components and steps of each example according to their functions. Whether these functions are performed in hardware or software depends on the specific application and design constraints of the technical solution. Professionals and technicians may use different methods to implement the described functions for each specific application, but such implementation should not be considered beyond the scope of this application.

[0183] The above is a detailed introduction to an integrated circuit bus system, a data processing method applied to an integrated circuit bus system, and a programmable logic unit provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is only used to help understand the method and core idea of ​​the present application. It should be pointed out that for ordinary technicians in this technical field, without departing from the principles of the present application, several improvements and modifications can be made to the present application, and these improvements and modifications also fall within the scope of protection of the claims of the present application.

Claims

1. An integrated circuit bus system, characterized in that: include: A host, a programmable logic unit, a switch unit, and a slave, wherein the programmable logic unit includes a processing module, the host and the programmable logic unit, the programmable logic unit and the switch unit, and the switch unit and the slave are connected via an integrated circuit bus, the host is a central processing unit, and the slave includes a backup battery unit; If the processing module in the programmable logic unit detects that the slave has received a signal and has not responded within a predetermined time, it sends an abnormal signal to the host so that the host stops accessing the data. If the processing module in the programmable logic unit detects that the cumulative number of times the slave has not responded reaches a first preset cumulative number, it disconnects and re-enables the slave so that the slave returns to a normal state.

2. The integrated circuit bus system according to claim 1, wherein: The programmable logic unit also includes a shaping module and a sampling module. The shaping module is used to perform hysteresis comparison on the received integrated circuit bus signal. If the integrated circuit bus signal is higher than the signal upper limit value, it outputs a high level; if the integrated circuit bus signal is lower than the signal lower limit value, it outputs a low level. The sampling module is used to store the sampling value of the signal processed by the shaping module in a shift register, and when the sampling values ​​are the same for multiple consecutive times, the shift register is updated and determined to be a valid level. The sampling frequency of the sampling module is a preset multiple of the integrated circuit bus clock frequency.

3. The integrated circuit bus system according to claim 1, wherein: The processing module is further configured to detect the signal state from the host, jump to the next state if the combination of the serial data signal and the serial clock signal meets the start condition, and enter the end state if the combination meets the end condition.

4. The integrated circuit bus system according to claim 1, wherein: The programmable logic unit further includes a latch module, which is used to store the serial data signal in a latch register.

5. The integrated circuit bus system according to claim 4, wherein: The processing module is further configured to detect the signal received from the latch register, and if the serial data signal received from the latch register is abnormal within a clock cycle, the programmable logic unit stops signal forwarding.

6. The integrated circuit bus system according to claim 4, wherein: The processing module is further configured to: in a data routing state, if a slave address is matched, establish a connection between the bus signal line of the corresponding slave and the output signal line of the latch register.

7. The integrated circuit bus system according to claim 1, wherein: The processing module is further configured to: If it is detected that the low level duration of the serial clock signal on the slave side exceeds a first preset time, the serial clock signal is forcibly pulled high for a preset number of pulses to generate an end condition, and an error log is recorded; In the ACK return phase, if the low level duration of the serial data signal on the slave side exceeds a second preset time, the serial data signal is forced to be pulled high to generate an end condition and an error log is recorded. The first preset time is greater than the second preset time.

8. The integrated circuit bus system according to claim 1, wherein: The processing module is further configured to: if the cumulative number of times that the slave device fails to respond reaches a second preset cumulative number, isolate the address of the slave device and upload device fault information to the host device.

9. The integrated circuit bus system according to claim 1, wherein: The processing module is further configured to: in the address matching stage, set a preset list of slave addresses, wherein the slave addresses in the preset list of slave addresses are allowed to be accessed.

10. The integrated circuit bus system according to claim 1, wherein: The programmable logic unit is further configured to: control the slave power supply to be enabled if it is detected that the slave power supply is valid; and control the switch unit to be closed if the slave power supply is enabled successfully.

11. The integrated circuit bus system according to any one of claims 1 to 10, characterized in that: The switch unit includes a plurality of electrically connected MOS devices.

12. The integrated circuit bus system according to any one of claims 1 to 10, characterized in that: The host is a controller, the slave is a backup battery unit, and the programmable logic unit is a complex programmable logic unit.

13. The integrated circuit bus system according to any one of claims 1 to 10, characterized in that: There is one master and multiple slaves.

14. A data processing method applied to an integrated circuit bus system, characterized in that: include: Receiving an integrated circuit bus signal sent by the host, and sending the integrated circuit bus signal to the slave after a predetermined process, the host is a central processing unit, the slave includes a backup battery unit; determining whether the slave responds to the received signal within a predetermined time; If the slave does not respond within the predetermined time, an abnormal signal is sent to the host to cause the host to stop the data access; If the slave device does not respond for a cumulative number of times reaching a first preset cumulative number of times, the connection with the slave device is disconnected, and the slave device is re-enabled so that the slave device returns to a normal state.

15. The data processing method according to claim 14, characterized in that: Performing predetermined processing on the integrated circuit bus signal, comprising: performing a shaping process on the integrated circuit bus signal, wherein the shaping process comprises performing a hysteresis comparison on the integrated circuit bus signal, outputting a high level if the integrated circuit bus signal is higher than an upper signal limit, and outputting a low level if the integrated circuit bus signal is lower than a lower signal limit; The signal after the shaping process is sampled, and the sampling value is stored in a shift register. When the sampling value is the same for multiple times, the shift register is updated and determined to be a valid level.

16. The data processing method according to claim 15, characterized in that: The integrated circuit bus signal includes a serial data signal and a serial clock signal. After sampling the signal after the shaping process, storing the sampled value in a shift register, and updating the shift register when the sampled values ​​are the same for multiple consecutive times and determining that the shift register is at a valid level, the method further includes: Storing the serial data signal in a latch register; The address in the serial data signal is matched with the address in the preset list of slave addresses. If the match is successful, the bus signal line of the corresponding slave is connected to the latch register output signal line.

17. The data processing method according to claim 14, characterized in that: The method further comprises: If the cumulative number of times that the slave device does not respond reaches a second preset cumulative number, the address of the slave device is isolated and device fault information is uploaded to the host.

18. The data processing method according to claim 14, characterized in that: The method further comprises: If it is detected that the presence signal of the slave is valid, the power supply of the slave is controlled to be enabled, wherein the level of the presence signal line is a preset level, which indicates that the presence signal is valid.

19. The data processing method according to claim 14, wherein: The method further comprises: If it is detected that the low level duration of the serial clock signal on the slave side exceeds a first preset time, the serial clock signal is forcibly pulled high for a preset number of pulses to generate an end condition, and an error log is recorded; In the ACK return phase, if the low level duration of the serial data signal on the slave side exceeds a second preset time, the serial data signal is forced to be pulled high to generate an end condition and an error log is recorded. The first preset time is greater than the second preset time.

20. A programmable logic unit, characterized in that: include: A receiving module for receiving an integrated circuit bus signal sent by the host, and sending the integrated circuit bus signal to the slave after performing predetermined processing, the host is a central processing unit, and the slave includes a backup battery unit; a judging module, configured to judge whether the slave responds to the received signal within a predetermined time; A sending module, configured to send an abnormal signal to the host to stop the data access if the slave does not respond within the predetermined time; The disconnection module is configured to disconnect the slave device and re-enable the slave device so that the slave device returns to a normal state if the cumulative number of times the slave device fails to respond reaches a first preset cumulative number of times.

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