PCB design method and device, equipment and storage medium

Abstract

The invention provides a PCB design method and device, equipment and a storage medium, and the method comprises the steps: determining a target lamination layer in an original PCB inner layer; wherein the target lamination is other wiring layers except a high-density wiring layer, a grounding layer and a power supply layer in the original PCB inner layer; generating a first lamination layer of a first daughter card in a new PCB based on the top layer and the power supply layer of the original PCB and the target lamination layer; generating a second lamination layer of a second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; generating a false layer in the new PCB; and generating the new PCB based on the first lamination layer, the second lamination layer and the false layer. Through the technical scheme of the invention, the space required by wiring can be reduced, and the compatibility of the connector is improved.

Description

Technical Field

[0001] This application relates to the technical field of PCB design, and in particular, to a PCB design method, apparatus, device, and storage medium. Background Art

[0002] In the related art, the design of the staggered arrangement of the high-density press-fit connectors on the bottom layer and the SMT (Surface Mount Technology) connectors on the top layer of the PCB is relatively simple, but it will impose limitations on the wiring space and the selection of connectors, and changing the arrangement method between the above connectors requires a re-design of the PCB. Summary of the Invention

[0003] This application aims to solve at least one of the technical problems in the related art to some extent.

[0004] In a first aspect, this application provides a PCB design method, which includes: determining a target stack in the inner layer of the original PCB; where the target stack is other wiring layers in the inner layer of the original PCB except for the high-density wiring layer, the ground layer, and the power layer; generating a first stack of a first sub-card in the new PCB based on the top layer, the power layer, and the target stack of the original PCB; generating a second stack of a second sub-card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; generating a dummy layer in the new PCB; and generating the new PCB based on the first stack, the second stack, and the dummy layer.

[0005] In an implementation, the generating a first stack of a first sub-card in the new PCB based on the top layer, the power layer, and the target stack of the original PCB includes: generating a first inner layer of the first stack based on the power layer in the original PCB; correspondingly generating corresponding second inner layers on both sides of the first inner layer based on the target stack; generating a first outer layer of the first stack based on the top layer of the original PCB; where the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long lines and metal layers on the top layer of the original PCB.

[0006] In an implementation, the generating a second stack of a second sub-card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB includes: generating a third inner layer of the second stack; generating fourth inner layers corresponding to the high-density wiring layer in the second sub-card on both sides of the third inner layer; generating a second outer layer of the second stack based on the bottom layer of the original PCB; where the second outer layer includes a second signal layer and a third signal layer, the second signal layer is used to arrange the short lines on the bottom layer of the original PCB, and the third signal layer is used to arrange the long lines on the bottom layer of the original PCB.

[0007] In an alternative implementation, the method further includes: obtaining the number of first high-density pins of the high-density connector in the original PCB and the design requirements, as well as the device information of the available high-density connectors of the new PCB; selecting a candidate high-density connector from the available high-density connectors based on the design requirements and the device information; selecting a target high-density connector from the candidate high-density connectors based on the number of first high-density pins; obtaining the number of second high-density pins of the target high-density connector; in response to the number of first high-density pins being less than the number of second high-density pins, obtaining the number of first differential signal pairs in the number of first high-density pins and the number of second differential signal pairs in the number of second high-density pins, and generating a fifth inner layer on both sides of the third inner layer based on the difference between the number of first differential signal pairs and the number of second differential signal pairs.

[0008] In one implementation, the total thickness of the first daughter card is less than a preset first thickness threshold; wherein, the first thickness threshold is determined according to the length of the non-plated holes corresponding to the hard disk connector of the original PCB.

[0009] In one implementation, the total thickness of the second daughter card is less than a preset second thickness threshold; wherein, the second thickness threshold is determined according to the pin length of the high-density connector at the bottom layer of the original PCB.

[0010] In a second aspect, the present application provides a PCB design device, the device includes: a first processing module, configured to determine a target stack in the inner layer of the original PCB; wherein, the target stack is other wiring layers in the inner layer of the original PCB except for the high-density wiring layer, the ground layer and the power layer; a second processing module, configured to generate a first stack of the first daughter card in the new PCB based on the top layer, the power layer and the target stack of the original PCB; a third processing module, configured to generate a second stack of the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; a fourth processing module, configured to generate a dummy layer in the new PCB; a fifth processing module, configured to generate the new PCB based on the first stack, the second stack and the dummy layer.

[0011] In one implementation, the second processing module is configured to: generate a first inner layer of the first stack based on the power layer in the original PCB; generate corresponding second inner layers on both sides of the first inner layer based on the target stack; generate a first outer layer of the first stack based on the top layer of the original PCB; wherein, the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long lines and metal layers on the top layer of the original PCB.

[0012] In one implementation, the third processing module is configured to: generate a third inner layer of the second stack; on both sides of the third inner layer, generate fourth inner layers corresponding to the high-density wiring layer in the second daughter card; generate a second outer layer of the second stack based on the bottom layer of the original PCB; wherein, the second outer layer includes a second signal layer and a third signal layer, the second signal layer is used to arrange short lines on the bottom layer of the original PCB, and the third signal layer is used to arrange long lines on the bottom layer of the original PCB.

[0013] In an alternative implementation, the third processing module is further configured to: obtain the first high-density pin logarithm and design requirements of the high-density connector in the original PCB, and the device information of the available high-density connectors of the new PCB; based on the design requirements and the device information, select candidate high-density connectors from the available high-density connectors; select a target high-density connector from the candidate high-density connectors based on the first high-density pin logarithm; obtain the second high-density pin logarithm of the target high-density connector; in response to the first high-density pin logarithm being less than the second high-density pin logarithm, obtain the first differential signal logarithm in the first high-density pin logarithm and the second differential signal logarithm in the second high-density pin logarithm, and based on the difference between the first differential signal logarithm and the second differential signal logarithm, generate a fifth inner layer on both sides of the third inner layer.

[0014] In one implementation, the total thickness of the first daughter card is less than a preset first thickness threshold; wherein, the first thickness threshold is determined according to the length of the non-plated holes corresponding to the hard disk connector of the original PCB.

[0015] In one implementation, the total thickness of the second daughter card is less than a preset second thickness threshold; wherein, the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

[0016] In a third aspect, the present application provides an electronic device, including: at least one processor; and a memory communicatively connected to the at least one processor; wherein, the memory stores instructions executable by the at least one processor, and when the instructions are executed by the at least one processor, the at least one processor is enabled to execute the PCB design method as described in the first aspect.

[0017] In a fourth aspect, the present application provides a computer-readable storage medium for storing instructions, which when executed, implement the method as described in the first aspect.

[0018] In a fifth aspect, the present application provides a computer program product, including a computer program, which when executed by a processor, implements the steps of the PCB design method as described in the first aspect.

[0019] The PCB design method, device, equipment, and storage medium provided by this application can generate new stack-ups corresponding to the first daughter card and the second daughter card in the new PCB based on the stack-ups in the original PCB, so as to obtain a new PCB that can support the overlapping placement of high-density connectors at the bottom layer and hard disk connectors at the top layer. It can reduce the space required for wiring and improve the compatibility with connectors.

[0020] Additional aspects and advantages of this application will be given in part in the following description, become apparent in part from the following description, or be understood through the practice of this application. Description of the Drawings

[0021] The above and / or additional aspects and advantages of this application will become apparent and be easily understood from the following description of the embodiments in conjunction with the drawings, where: Figure 1 is a schematic flowchart of a PCB design method provided by an embodiment of this application; Figure 2 is a schematic flowchart of another PCB design method provided by an embodiment of this application; Figure 3 is a schematic flowchart of yet another PCB design method provided by an embodiment of this application; Figure 4 is an example diagram of connector library information provided by an embodiment of this application; Figure 5 is an example diagram of a PCB design solution provided by an embodiment of this application; Figure 6 is an example diagram of pin parameters provided by an embodiment of this application; Figure 7 is a schematic structural diagram of a PCB design device provided by an embodiment of this application; Figure 8 is a schematic structural diagram of an electronic device provided by an embodiment of this application. Detailed Embodiments

[0022] The embodiments of this application will be described in detail below. The examples of the embodiments are shown in the drawings, where the same or similar reference numerals denote the same or similar elements or elements with the same or similar functions throughout. The embodiments described below with reference to the drawings are exemplary and are intended to explain this application and should not be construed as a limitation of this application.

[0023] In the design of a high-density storage backplane, the conventional solution is to arrange high-density press-fit connectors for connecting the control board on the bottom layer, and SMT surface-mount connectors for connecting hard disks on the top layer. Since it is necessary to avoid the vertical overlap interference between the vias of the press-fit connectors and the pads of the surface-mount connectors in the design, a method of staggering the placement of the two types of connectors is usually adopted. Although this layout can prevent the pins of the two-sided connectors from overlapping vertically and simplify the PCB design process, it also compresses the available space for backplane layout and wiring, increases the wiring difficulty, and limits the area of the backplane heat dissipation opening, which is not conducive to heat dissipation. At the same time, it restricts the selection of connectors, affecting the design flexibility and performance expansion.

[0024] The following describes the PCB design method and device according to the embodiments of the present application with reference to the accompanying drawings.

[0025] Please refer to Figure 1 , Figure 1 which is a schematic flowchart of a PCB design method provided by an embodiment of the present application. As Figure 1 shown, the method may include but is not limited to the following steps: Step S101: Determine the target stack in the original PCB inner layer.

[0026] Among them, in the embodiments of the present application, the above-mentioned original PCB may be a PCB with a multi-layer mixed-pressure laminated structure.

[0027] Among them, the target stack is other wiring layers in the original PCB inner layer except for the high-density wiring layer, the ground layer, and the power layer.

[0028] Exemplarily, obtain the high-density area wiring conditions of all the wiring layers (i.e., non-GND layers and non-power layers) in the original PCB, and determine the wiring layer without wiring in the high-density area as the target stack.

[0029] Step S102: Generate the first stack of the first daughter card in the new PCB based on the top layer, the power layer, and the target stack of the original PCB.

[0030] It can be understood that the first stack of the first daughter card includes multiple stacks.

[0031] Exemplarily, retain the top layer, the power layer, and the target stack of the original stack, transfer the conductive structure of the top layer to the newly created signal layer, and generate the corresponding ground layer according to the design specifications to generate the first stack of the first daughter card in the new PCB.

[0032] Step S103: Generate the second stack of the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB.

[0033] It can be understood that the second stack of the second daughter card includes multiple stacks.

[0034] Exemplarily, the bottom layer and the high-density wiring layer of the original PCB are retained, the bottom conductive structure is transferred to the newly created signal layer, and the corresponding ground layer is generated according to the design specifications to generate the second stack of the second daughter card.

[0035] Step S104: Generate a dummy layer in the new PCB.

[0036] Wherein, in the embodiment of the present application, the above-mentioned dummy layer is a stack for adjusting the thickness and impedance of the new PCB, and has no circuit functions such as signal transmission.

[0037] Exemplarily, the dummy layer in the new PCB can be generated according to actual design requirements.

[0038] Exemplarily, the above-mentioned dummy layer is at least one.

[0039] Exemplarily, a dummy layer is generated between the first daughter card and the second daughter card, and a low-flowing prepreg is used to prevent the glue from flowing into the holes when the first daughter card and the second daughter card are pressed together.

[0040] Step S105: Generate a new PCB based on the first stack, the second stack, and the dummy layer.

[0041] Exemplarily, the first stack of the first daughter card, the second stack of the second daughter card, and the dummy layer are integrated to obtain a new PCB. The starting layer and the ending layer of the high-density connector pins are set as the bottom layer of the new PCB, and the starting layer and the ending layer of the hard disk connector NPTH (Non-Plated Through Hole) pins are set as the top layer of the new PCB. Then, the stacks are renamed according to the actual arrangement of the stacks, the corresponding relationship between the original PCB stacks and the new PCB stacks is recorded, the traces and copper foils are exported layer by layer from the original PCB, and then the exported document is edited, the layer where each element is located is modified, and then imported into the new PCB layer by layer.

[0042] In an alternative implementation, the pins of the press-fit connector can be used as a reference to establish a no-wiring area within a preset range (for example, 40 mil).

[0043] In an alternative implementation, a limit can be set for the minimum distance between through holes and blind holes. For example, 30 mil.

[0044] In an alternative implementation, the wiring and vias that do not conform to the rules can be modified according to the violation coordinate positions marked in the design rule check report to optimize the new PCB.

[0045] It should be noted that the new PCB obtained by any embodiment of the present application can support the overlapping placement of the high-density connector at the bottom layer and the hard disk connector at the top layer.

[0046] By implementing the embodiments of the present application, new stacks corresponding to the first daughter card and the second daughter card in the new PCB can be generated respectively based on the stack in the original PCB, so as to obtain a new PCB that can support the overlapping placement of the high-density connector at the bottom layer and the hard disk connector at the top layer, thereby reducing the space required for wiring and improving the compatibility with the connectors.

[0047] In some embodiments, new stacks corresponding to the top layer, the power layer, and the target stack of the original PCB can be generated respectively, so as to obtain the first stack corresponding to the first daughter card. As an example, please refer to Figure 2 , Figure 2 which is a schematic flowchart of another PCB design method provided by the embodiments of the present application. As shown in Figure 2 , the method may include but is not limited to the following steps: Step S201: Determine the target stack in the inner layer of the original PCB.

[0048] In the embodiments of the present application, step S201 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0049] Step S202: Generate the first inner layer of the first stack based on the power layer in the original PCB.

[0050] Among them, in the embodiments of the present application, the above-mentioned first inner layer can be the middle layer of the first daughter card.

[0051] Exemplarily, based on the number of power layers in the original PCB, generate the corresponding number of power layers as the middle layer in the first stack of the first daughter card.

[0052] Step S203: Generate corresponding second inner layers on both sides of the first inner layer corresponding to the target stack.

[0053] Exemplarily, take the first inner layer as the middle layer and generate second inner layers corresponding to the target stack on both sides of the first inner layer.

[0054] It should be noted that the above-mentioned second inner layer may include a signal layer corresponding to the target stack and a ground layer corresponding to the signal layer.

[0055] Step S204: Generate the first outer layer of the first stack based on the top layer of the original PCB.

[0056] Among them, the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long lines and metal layers on the top layer of the original PCB.

[0057] Exemplarily, the top layer of the original PCB in the first stack corresponds to the new top layer, and a first signal layer is newly generated. This first signal layer is used to arrange the long lines and metal layers of the top layer of the original PCB. The new top layer and the first signal layer form the outer layer of the first stack.

[0058] Step S205: Generate the second stack of the second sub-card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB.

[0059] In the embodiments of the present application, step S205 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0060] Step S206: Generate a dummy layer in the new PCB.

[0061] In the embodiments of the present application, step S206 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0062] Step S207: Generate the new PCB based on the first stack, the second stack, and the dummy layer.

[0063] In the embodiments of the present application, step S207 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0064] By implementing the embodiments of the present application, new stacks corresponding to the top layer, the power layer, and the target stack of the original PCB can be generated respectively, so as to obtain the first stack corresponding to the first sub-card, and then combined with the new stack corresponding to the second sub-card to obtain a new PCB that can support the overlapping placement of the high-density connector at the bottom layer and the hard disk connector at the top layer. It can reduce the space required for wiring and improve the compatibility with the connector.

[0065] In one implementation, new stacks corresponding to the bottom layer and the high-density wiring layer of the original PCB can be generated respectively as the second stack of the second sub-card. As an example, please refer to Figure 3 , Figure 3 which is a schematic flow chart of another PCB design method provided by the embodiments of the present application. As shown in Figure 3 , the method may include but is not limited to the following steps: Step S301: Determine the target stack in the inner layer of the original PCB.

[0066] In the embodiments of the present application, step S301 can be implemented in any one of the embodiments of the present application. The embodiments of the present application do not make any limitations in this regard and will not be elaborated further.

[0067] Step S302: Generate the first stack-up of the first daughter card in the new PCB based on the top layer, power layer, and target stack-up of the original PCB.

[0068] In the embodiments of the present application, step S302 can be implemented in any one of the ways in the various embodiments of the present application. The embodiments of the present application do not limit this and will not elaborate further.

[0069] Step S303: Generate the third inner layer of the second stack-up.

[0070] Exemplarily, the above-mentioned third inner layer can be the middle layer of the second daughter card.

[0071] Exemplarily, generate at least one ground layer as the middle layer of the second stack-up.

[0072] Step S304: Generate the fourth inner layer corresponding to the high-density wiring layer in the second daughter card on both sides of the third inner layer.

[0073] Exemplarily, use the third inner layer as the middle layer and generate the fourth inner layer corresponding to the high-density wiring layer on both sides of the third inner layer.

[0074] It should be noted that the above-mentioned fourth inner layer can include a signal layer corresponding to the high-density wiring layer and a ground layer corresponding to the signal layer.

[0075] Step S305: Generate the second outer layer of the second stack-up based on the bottom layer of the original PCB.

[0076] Among them, in the embodiments of the present application, the above-mentioned second outer layer includes a second signal layer and a third signal layer. The second signal layer is used to arrange the short lines on the bottom layer of the original PCB, and the third signal layer is used to arrange the long lines on the bottom layer of the original PCB.

[0077] Exemplarily, split the bottom layer of the original PCB into a second signal layer and a third signal layer. The second signal layer is used to arrange the short lines on the bottom layer of the original PCB, and the third signal layer is used to arrange the long lines on the bottom layer of the original PCB.

[0078] Step S306: Generate a dummy layer in the new PCB.

[0079] In the embodiments of the present application, step S306 can be implemented in any one of the ways in the various embodiments of the present application. The embodiments of the present application do not limit this and will not elaborate further.

[0080] Step S307: Generate the new PCB based on the first stack-up, the second stack-up, and the dummy layer.

[0081] In the embodiments of the present application, step S307 can be implemented in any one of the ways in the various embodiments of the present application. The embodiments of the present application do not limit this and will not elaborate further.

[0082] By implementing the embodiments of the present application, new stacks corresponding to the bottom layer and the high-density wiring layer of the original PCB can be generated respectively as the second stack of the second daughter card, so as to combine the second daughter card with the first daughter card to obtain a new PCB that can support the overlapping placement of the high-density connector at the bottom layer and the hard disk connector at the top layer. This can reduce the space required for wiring and improve the compatibility with connectors.

[0083] In one implementation, the above method may further include the following steps: Step A1: Obtain the first high-density pin pair number and design requirements of the high-density connector in the original PCB, and the device information of the available high-density connectors of the new PCB.

[0084] Among them, in the embodiments of the present application, the above design requirements may include but are not limited to the data transfer rate.

[0085] Exemplarily, to obtain the design requirements, after reading the design file of the original PCB, retrieve and output the models and corresponding quantities of all high-density connectors at the bottom layer, and obtain the device information of the available high-density connectors that can be used currently. Among them, the device information may include but is not limited to the model, available quantity, data transfer rate, and number of pin pairs.

[0086] In some embodiments, the device information of the high-density connectors stored in the device library may be obtained as the device information of the available high-density connectors.

[0087] Exemplarily, please refer to Figure 4 , Figure 4 which is an example diagram of the connector library information provided by the embodiments of the present application. As Figure 4 shown, the part number, pin length, signal rate, number of pin pairs of the available high-density connectors, the part number of the hard disk connector, and the corresponding NPTH pin length can be stored in different columns of the table. This table can be connected to the device library to be updated and maintained in real time according to the situation of the connectors in the device library, ensuring the accuracy and comprehensiveness of the connector library information and improving the design efficiency of the new PCB.

[0088] Step A2: Select candidate high-density connectors from the available high-density connectors based on the design requirements and device information.

[0089] Exemplarily, taking the design requirement including the data transfer rate requirement as an example, select candidate high-density connectors that meet the data transfer rate requirement from the available high-density connectors based on the data transfer rate supported by the available high-density connectors.

[0090] Step A3: Select target high-density connectors from the candidate high-density connectors based on the first high-density pin pair number.

[0091] Exemplarily, a high-density connector with the number of differential pairs exactly the same as the number of the first high-density pin pairs is preferentially selected as the target high-density connector; if a high-density connector with the number of differential pair rows the same as the number of the first high-density pin pairs is used as the target high-density connector; again, a high-density connector with the number of differential pairs less than the number of the first high-density pin pairs is selected as the target high-density connector to improve the utilization rate of high-density devices.

[0092] Step A4: Obtain the second high-density pin pairs of the target high-density connector.

[0093] Exemplarily, according to the part number of the target high-density connector, look up in the Figure 4 shown table to obtain the second high-density pin pairs of the target high-density connector.

[0094] In some embodiments, the number of signals required to be routed on all high-density connectors in the original PCB can be obtained, and the number of signals is divided by the second high-density pin pairs to obtain the number of high-density connectors in the new PCB.

[0095] Step A5: In response to the first differential signal pairs in the first high-density pin pairs being less than the second differential signal pairs in the second high-density pin pairs, generate a fifth inner layer on both sides of the third inner layer based on the difference between the first differential signal pairs and the second differential signal pairs.

[0096] Exemplarily, in response to the first differential signal pairs in the first high-density pin pairs being less than the second differential signal pairs in the second high-density pin pairs, generate the same number of signal layers and the same number of ground layers as the above difference on both sides of the middle layer of the second daughter card.

[0097] By implementing the embodiments of the present application, the high-density connector can be re-selected according to the design requirements of the PCB and the device information of the available connectors, and the new PCB can be adjusted according to the selection result. The new PCB is made more in line with the actual production requirements, and the usability of the new PCB in industrial production is improved.

[0098] In one implementation, the total thickness of the first daughter card is less than a preset first thickness threshold; wherein, the first thickness threshold is determined according to the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

[0099] Exemplarily, the thickness of each stack of the first daughter card can be adjusted so that the total thickness of the first daughter card is less than the preset first thickness threshold.

[0100] Exemplarily, the above first thickness threshold can be 1.1 times the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

[0101] Exemplarily, according to the part number of the hard disk connector, in such as Figure 4Look up in the table shown to obtain the NPTH pin length corresponding to this part number.

[0102] In some embodiments, the total thickness of the second daughter card is less than a preset second thickness threshold; wherein, the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

[0103] Exemplarily, the thickness of each stack of the second daughter card can be adjusted so that the total thickness of the second daughter card is less than the preset second thickness threshold.

[0104] Exemplarily, the above-mentioned second thickness threshold can be 1.1 times the pin length of the high-density connector on the bottom layer of the original PCB.

[0105] Exemplarily, according to the part number of the high-density connector, look up in the table as shown in Figure 4 to obtain the corresponding pin length of this part number.

[0106] The PCB design method provided by the present application will be described exemplarily in combination with specific embodiments as follows: As an example, please refer to Figure 5 , Figure 5 which is an example diagram of a PCB design solution provided by an embodiment of the present application. As shown in Figure 5 , taking the 14-layer stack commonly used in storage devices as an example, the stack of the original PCB is divided into two upper and lower daughter cards (i.e., the aforementioned first daughter card and second daughter card). The upper daughter card takes the power layer of the original PCB stack as the intermediate layer, retains the top layer of the original PCB stack, adds Ly6_Signal (Layer 6_Signal Layer) for arranging the long lines and metal layers on the top layer of the original PCB, and counts the routing conditions of the high-density areas of all routing layers (i.e., non-GND and non-power layers). The routing layers without routing in the high-density area are symmetrically added to both sides of Ly3_Pwr (Layer 3_Power Layer) and Ly4_Pwr (Layer 4_Power Layer), and determine whether additional routing layers are needed according to the routing requirements. If all routing layers are routed in the high-density area, the upper daughter card will maintain the Figure 5 6-layer board shown.

[0107] The routing layers of the original PCB with routing in the high-density area (taking Ly3_signal (Layer 3_Signal Layer), Ly5_signal (Layer 5_Signal Layer), Ly10_signal (Layer 10_Signal Layer), Ly12_signal (Layer 12_Signal Layer) as examples) are adjusted to the lower daughter card. At the same time, the bottom layer of the original PCB stack is split into Ly7_Signal (Layer 7_Signal Layer) and Ly18_Signal layer (Layer 18_Signal Layer) of the new PCB, which are used to route the short lines and long lines on the bottom layer of the original stack respectively; Let the number of pinpairs of the high-density connector on the original PCB be denoted as X1*Y1 (indicating that this high-density connector has Y1 columns, and each column can carry X1 pairs of differential signals), and the number of pinpairs of the high-density connector on the new PCB be denoted as X2*Y2. If X1 < X2, then symmetrically add X1 - X2 signal layers and X1 - X2 GND layers on both sides of Ly12_Gnd and Ly13_Gnd. Add a dummy layer between the upper daughter card and the lower daughter card, and use a low-flow prepreg to prevent resin from flowing into the holes when the upper and lower daughter cards are laminated.

[0108] After that, modify the device packaging. Exemplarily, please refer to Figure 6 , Figure 6 which is an example diagram of pin parameters provided by an embodiment of the present application. As Figure 6 shown, after selecting the pins to be modified, enter the parameter configuration interface. If the pins to be modified are top-layer NPTH pins, set the parameter options of all layers from the Ly6_signal layer (the sixth layer - signal layer) and below to None; if the pins to be modified are bottom-layer high-density device pins, set the parameter options of all layers from the top layer to the Ly6_signal layer (including the Ly6_signal layer) to None.

[0109] Please refer to Figure 7 , Figure 7 which is a schematic structural diagram of a PCB design device provided by an embodiment of the present application. As Figure 7 shown, the device 700 includes: a first processing module 701, configured to determine a target stack-up in the inner layer of the original PCB; wherein, the target stack-up is other wiring layers in the inner layer of the original PCB except for the high-density wiring layer, the ground layer, and the power layer; a second processing module 702, configured to generate a first stack-up of the first daughter card in the new PCB based on the top layer, the power layer, and the target stack-up of the original PCB; a third processing module 703, configured to generate a second stack-up of the second daughter card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; a fourth processing module 704, configured to generate a dummy layer in the new PCB; a fifth processing module 705, configured to generate a new PCB based on the first stack-up, the second stack-up, and the dummy layer.

[0110] In one implementation, the second processing module 702 is configured to: generate a first inner layer of the first stack-up based on the power layer in the original PCB; correspondingly generate corresponding second inner layers on both sides of the first inner layer based on the target stack-up; generate a first outer layer of the first stack-up based on the top layer of the original PCB; wherein, the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long lines and metal layers on the top layer of the original PCB.

[0111] In one implementation, the third processing module 703 is configured to: generate a third inner layer of the second stack; on both sides of the third inner layer, generate fourth inner layers corresponding to the high-density wiring layers in the second daughter card; generate a second outer layer of the second stack based on the bottom layer of the original PCB; wherein, the second outer layer includes a second signal layer and a third signal layer, the second signal layer is used to arrange the short lines of the bottom layer of the original PCB, and the third signal layer is used to arrange the long lines of the bottom layer of the original PCB.

[0112] In an alternative implementation, the third processing module 703 is further configured to: obtain the first high-density pin pair number and design requirements of the high-density connector in the original PCB, and the device information of the available high-density connectors of the new PCB; based on the design requirements and device information, select candidate high-density connectors from the available high-density connectors; select a target high-density connector from the candidate high-density connectors based on the first high-density pin pair number; obtain the second high-density pin pair number of the target high-density connector; in response to the first high-density pin pair number being less than the second high-density pin pair number, obtain the first differential signal pair number in the first high-density pin pair number and the second differential signal pair number in the second high-density pin pair number, and based on the difference between the first differential signal pair number and the second differential signal pair number, generate a fifth inner layer on both sides of the third inner layer.

[0113] In one implementation, the total thickness of the first daughter card is less than a preset first thickness threshold; wherein, the first thickness threshold is determined according to the length of the non-plated holes corresponding to the hard disk connectors of the original PCB.

[0114] In one implementation, the total thickness of the second daughter card is less than a preset second thickness threshold; wherein, the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

[0115] Through the device according to the embodiments of the present application, new stacks corresponding to the first daughter card and the second daughter card in the new PCB can be respectively generated based on the stacks in the original PCB, so as to obtain a new PCB that can support the overlapping placement of the high-density connector on the bottom layer and the hard disk connector on the top layer. It can reduce the space required for wiring and improve the compatibility with connectors.

[0116] It should be noted that the foregoing explanation of the embodiments of the PCB design method also applies to the PCB design device of this embodiment, and will not be elaborated here.

[0117] To implement the above embodiments, the present application also proposes an electronic device. Please refer to Figure 8 , Figure 8 is a schematic structural diagram of the electronic device provided by the embodiments of the present application. As Figure 8As shown, the electronic device 800 includes: a processor 801, and a memory 802 communicatively connected to the processor 801; the memory 802 stores computer-executable instructions; the processor 801 executes the computer-executable instructions stored in the memory to implement the method provided in the foregoing embodiments.

[0118] To implement the foregoing embodiments, the present application further provides a computer-readable storage medium storing computer-executable instructions that, when executed by a processor, are used to implement the method provided in the foregoing embodiments.

[0119] To implement the foregoing embodiments, the present application further provides a computer program product including a computer program that, when executed by a processor, implements the method provided in the foregoing embodiments.

[0120] Wherein, in the description of the present application, unless otherwise specified, " / " means "or". For example, A / B may represent A or B; herein, "and / or" is merely a description of the association relationship of associated objects, indicating that there can be three relationships. For example, A and / or B may represent: A exists alone, A and B exist simultaneously, and B exists alone.

[0121] In the description of the foregoing embodiments, the descriptions with reference to the terms "one embodiment", "some embodiments", "example", "specific example", or "some examples", etc., mean that the specific features, structures, materials, or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present application. In this specification, the schematic descriptions of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials, or characteristics described may be combined in a suitable manner in any one or more embodiments or examples. In addition, without conflict, those skilled in the art may combine and combine the different embodiments or examples described in this specification and the features of different embodiments or examples.

[0122] In addition, the terms "first" and "second" are only used for descriptive purposes and cannot be construed as indicating or implying relative importance or implicitly specifying the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include at least one of the features. In the description of the present application, "a plurality of" means at least two, such as two, three, etc., unless otherwise specifically defined.

[0123] Any process or method description represented in a flowchart or otherwise described herein can be understood to represent a module, segment, or portion of code including one or more executable instructions for implementing a customized logical function or process. The scope of the preferred embodiments of the present application includes additional implementations, where functions may be executed in a manner substantially simultaneous or in a reverse order according to the functions involved, rather than in the order shown or discussed, which should be understood by those skilled in the art to which the embodiments of the present application pertain.

[0124] The logic and / or steps represented in a flowchart or otherwise described herein, for example, can be considered as a sequenced list of executable instructions for implementing a logical function, and can be embodied specifically in any computer-readable medium for use by or in connection with an instruction execution system, apparatus, or device, such as a computer-based system, a system including a processor, or other systems that can fetch and execute instructions from the instruction execution system, apparatus, or device. For the purposes of this specification, a "computer-readable medium" can be any device that can contain, store, communicate, propagate, or transport a program for use by or in connection with an instruction execution system, apparatus, or device. More specific examples (a non-exhaustive list) of the computer-readable medium include the following: an electrical connection portion with one or more wirings (electronic device), a portable computer diskette (magnetic device), a random access memory (RAM), a read-only memory (ROM), an erasable programmable read-only memory (EPROM or flash memory), an optical fiber device, and a portable compact disc read-only memory (CDROM). Additionally, the computer-readable medium can even be paper or other suitable media on which a program can be printed, as the program can be obtained electronically, for example, by optically scanning the paper or other media, followed by editing, interpretation, or other appropriate processing as necessary, and then stored in a computer memory.

[0125] It should be understood that various parts of the present application can be implemented by hardware, software, firmware, or a combination thereof. In the above-described embodiments, multiple steps or methods can be implemented by software or firmware stored in a memory and executed by a suitable instruction execution system. For example, if implemented in hardware, as in another embodiment, any one or a combination of the following techniques well known in the art can be used: discrete logic circuits having logic gate circuits for implementing logical functions on data signals, application specific integrated circuits having appropriate combinational logic gate circuits, programmable gate arrays (PGAs), field programmable gate arrays (FPGAs), and the like.

[0126] Those of ordinary skill in the art can understand that all or part of the steps carried out in the methods of the above embodiments can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. When the program is executed, it includes one or a combination of the steps of the method embodiments.

[0127] In addition, in each of the embodiments of the present application, the functional units can be integrated in a processing module, or each unit can exist physically alone, or two or more units can be integrated in a module. The above integrated module can be implemented in the form of hardware or in the form of a software functional module. When the integrated module is implemented in the form of a software functional module and sold or used as an independent product, it can also be stored in a computer-readable storage medium.

[0128] The storage medium mentioned above can be a read-only memory, a magnetic disk, an optical disc, etc. Although the embodiments of the present application have been shown and described above, it can be understood that the above embodiments are exemplary and should not be construed as limiting the present application. Those of ordinary skill in the art can make changes, modifications, substitutions, and variations to the above embodiments within the scope of the present application.

Claims

1. A PCB design method, characterized in that, Including: Determine a target stack-up in the inner layer of the original PCB; wherein, the target stack-up is other wiring layers in the inner layer of the original PCB except for the high-density wiring layer, the ground layer, and the power layer; Generate a first stack-up of the first sub-card in the new PCB based on the top layer, the power layer, and the target stack-up of the original PCB; Generate a second stack-up of the second sub-card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; Generate a dummy layer in the new PCB; Generate the new PCB based on the first stack-up, the second stack-up, and the dummy layer.

2. The method according to claim 1, wherein The generating a first stack-up of the first sub-card in the new PCB based on the top layer, the power layer, and the target stack-up of the original PCB includes: Generate a first inner layer of the first stack-up based on the power layer in the original PCB; Correspondingly generate corresponding second inner layers on both sides of the first inner layer based on the target stack-up; Generate a first outer layer of the first stack-up based on the top layer of the original PCB; wherein, the first outer layer includes a first signal layer, and the first signal layer is used to arrange the long lines and metal layers on the top layer of the original PCB.

3. The method according to claim 1, characterized in that, The generating a second stack-up of the second sub-card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB includes: Generate a third inner layer of the second stack-up; Generate fourth inner layers corresponding to the high-density wiring layer in the second sub-card on both sides of the third inner layer; Generate a second outer layer of the second stack-up based on the bottom layer of the original PCB; wherein, the second outer layer includes a second signal layer and a third signal layer, the second signal layer is used to arrange the short lines on the bottom layer of the original PCB, and the third signal layer is used to arrange the long lines on the bottom layer of the original PCB.

4. The method according to claim 3, characterized in that The method further includes: Obtain the first high-density pin pair number and design requirements of the high-density connector in the original PCB, and the device information of the available high-density connector of the new PCB; Select a candidate high-density connector from the available high-density connectors based on the design requirements and the device information; Select a target high-density connector from the candidate high-density connectors based on the first high-density pin pair number; Obtain the second high-density pin pair number of the target high-density connector; In response to the first high-density pin pair number being less than the second high-density pin pair number, obtain the first differential signal pair number in the first high-density pin pair number and the second differential signal pair number in the second high-density pin pair number, and generate a fifth inner layer on both sides of the third inner layer based on the difference between the first differential signal pair number and the second differential signal pair number.

5. The method according to claim 1, characterized in that, The total thickness of the first sub-card is less than a preset first thickness threshold; wherein, the first thickness threshold is determined according to the length of the non-plated hole corresponding to the hard disk connector of the original PCB.

6. The method according to claim 1, wherein The total thickness of the second sub-card is less than a preset second thickness threshold; wherein, the second thickness threshold is determined according to the pin length of the high-density connector on the bottom layer of the original PCB.

7. A PCB design device, characterized in that, Including: A first processing module, configured to determine a target stack in the original inner layer of the PCB; wherein, the target stack is other wiring layers in the original inner layer of the PCB except for the high-density wiring layer, the grounding layer, and the power layer; A second processing module, configured to generate a first stack of a first sub-card in the new PCB based on the top layer, the power layer, and the target stack of the original PCB; A third processing module, configured to generate a second stack of a second sub-card in the new PCB based on the bottom layer and the high-density wiring layer of the original PCB; A fourth processing module, configured to generate a dummy layer in the new PCB; A fifth processing module, configured to generate the new PCB based on the first stack, the second stack, and the dummy layer; 8. An electronic device, characterized in that, Comprising: A processor, and a memory communicatively connected to the processor; The memory stores computer-executable instructions; The processor executes the computer-executable instructions stored in the memory to implement the method according to any one of claims 1 to 6.

9. A computer-readable storage medium, characterized in that, Computer-executable instructions are stored in the computer-readable storage medium, and when the computer-executable instructions are executed by a processor, they are used to implement the method according to any one of claims 1 to 6.

10. A computer program product, characterized in that, Comprising a computer program, which when executed by a processor implements the method according to any one of claims 1 to 6.

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