Boolean operation method based on flash memory addressable memory

Abstract

The invention relates to the technical field of memories, and discloses a Boolean operation method based on a flash memory addressable memory. The two flash memory units M1 and M2 form a CAM unit for logical operation of n input variables, and threshold voltages Vth1 and Vth2 stored in the M1 and the M2 are used for representing the input variables X1, X2,..., Xn-1; the search voltages Vs1 and Vs2 applied by the grid electrodes of the M1 and the M2 are used for representing an input variable Xn, so that logic operation is realized; various logical operations are realized on one CAM unit according to a corresponding mapping rule through different mappings from an input variable logic value to a characteristic value of the CAM unit and mapping from a state of a matching line ML to an output result. According to the method, the reconfigurability and functionality of the CAM are improved.

Description

Technical Field

[0001] The present invention relates to a method for implementing full - scale Boolean operations on a content - addressable memory to implement highly reconfigurable logic gates, thereby greatly improving circuit integration, and belongs to the field of memory technology. Background Art

[0002] In traditional computing architectures, the energy - efficiency bottleneck has promoted the rapid development of in - memory computing (CIM, Computing In Memory) technology. This technology directly performs logical calculations in the memory array by using data as input parameters of the memory, completely eliminating the physical transfer requirement of data between the processor and the memory. The content - addressable memory (CAM, Content - Addressable Memory) adopts a "data - addressing" rather than a traditional "address - addressing" working mode and can match multiple rows of data in parallel. Therefore, it is very suitable for large - scale, low - latency, and energy - efficient in - memory computing operations.

[0003] A content - addressable memory based on non - volatile memory (NVM, Non - Volatile Memory) only requires two storage units to form a CAM unit, and the stored data can be retained for a long time. In contrast, a traditional content - addressable memory based on SRAM (Static Random Access Memory) requires six MOS transistors to form a CAM unit. In addition, due to the multi - value storage characteristic of NVM, an NVM - based CAM can implement MCAM (Multi - bit CAM), while an SRAM - based CAM can only implement BCAM (Binary CAM), or implement TCAM (Ternary CAM) by combining two CAM units. Therefore, the NVM - based CAM has advantages in terms of storage density, area consumption, etc.

[0004] Logic gate circuits are the core architecture of modern digital systems. The implementation of traditional CMOS (Complementary Metal Oxide Silicon) - based digital logic gates requires multiple MOS transistors. For example, a basic NOT gate requires two transistors, a two - input NAND gate and a NOR gate require four transistors, and more complex arithmetic logics need to be implemented by cascading multiple basic gate circuits. For example, an AND logic operation can be implemented by cascading a NOT gate after a NAND gate. A large number of MOS transistors will lead to large area overhead, power consumption, and timing alignment problems.

[0005] Therefore, a solution to reduce power consumption and improve circuit integration is very necessary. Summary of the Invention

[0006] In view of the complex structure of traditional logic operation circuits and the single function of traditional CAM units (Content Addressable Memory), the present invention provides a Boolean operation method based on a flash addressable memory, which can implement full-scale Boolean logic operations, realize highly reconfigurable logic gates, greatly improve the circuit integration, and at the same time, this method can be extended to multi-valued operations.

[0007] The Boolean operation method based on a flash addressable memory of the present invention adopts the following technical solutions:

[0008] Two flash memory cells M1 and M2 form a CAM unit (Content Addressable Memory unit). For the logic operation of n input variables, the threshold voltages Vth1 and Vth2 stored in M1 and M2 are used to represent the input variables X1, X2, …, Xn-1; the search voltages Vs1 and Vs2 applied to the gates of M1 and M2 are used to represent the input variable Xn, so as to realize the logic operation. Different types of logic operations result in different mapping rules for the input variables. Through different mappings of the logical values of the input variables to the characteristic values of the CAM unit, and then through the mapping of the state of the match line ML (Matchline) to the output result, various logic operations can be realized on a CAM unit according to the corresponding mapping rules, including binary logic operations (only 2 variables, such as AND, NAND, OR, NOR, XOR, XNOR, IMP, RIMP, NIMP, and RNIMP, etc.) and multi-valued logic operations (with multiple variables, such as AND, NAND, OR, NOR, XOR, XNOR).

[0009] The mapping rule of input variable 1 for the binary logic operation is that when Vth1 = Vlow and Vth2 = Vhigh, it means that input variable 1 is logic 0, otherwise it means that input variable 1 is logic 1, where Vlow < Vhigh.

[0010] The mapping rule of input variable 2 for the binary logic operation is:

[0011]

[0012]

[0013] When the logic operation is an AND (AND gate) logic operation: if the value of input variable 2 is logic 0, then the search voltages Vs1 = Vs2 = Vhigh are applied; if the value of input variable 2 is logic 1, then the search voltages Vs1 = Vhigh and Vs2 = Vlow are applied. When and only when the values of input variables 1 and 2 are both logic 1, the match line ML (Matchline) will always remain high level, that is, it means that the operation result is logic 1, otherwise the voltage of ML will drop rapidly, indicating that the operation result is logic 0.

[0014] The mapping process of the binary logical operation is as follows:

[0015] First, program the threshold voltages of each storage cell according to the value of input variable 1 to be calculated;

[0016] Second, apply voltage to each search line SL according to the value of input variable 2. If the calculation result of a certain CAM cell is 1, then the CAM cell is matched; otherwise, the CAM cell is mismatched, resulting in the discharge of the match line ML.

[0017] In the above mapping process:

[0018] The calculation result of the CAM cell is expressed by the following formula:

[0019]

[0020] The Sum value represents the number of calculated values of 1 in the calculation results of one row, that is, the number of matched CAM cells; the serial number N CAM represents the number of CAM cells loaded on one ML; the serial number i represents the i-th CAM cell in one row; xi1 and xi2 respectively represent the two storage cells in the i-th CAM cell; represents the adopted logical operation method (such as AND, NAND, OR, NOR, XOR, XNOR, IMP, RIMP, NIMP, RNIMP, etc.).

[0021] The situation of the discharge of the match line ML is expressed by the following formula:

[0022] VML = A × exp(-DR × t) + C;

[0023] where VML represents the voltage value of the match line ML; t represents the discharge time; A, DR, and C are fitting parameters, DR represents the discharge rate of the match line ML, and DR is proportional to the number N of mismatched CAM cells; "--" represents the negative sign.

[0024] The relationship between the discharge rate DR of the match line ML and the number N of mismatched CAM cells is expressed by the following formula:.

[0025] DR = J × N + K;

[0026] where J and K are fitting constants.

[0027] The relationship between the number Sum of matched CAM cells and the number N of mismatched CAM cells is expressed by the following formula:

[0028] Sum = N CAM -N;

[0029] where N CAM represents the number of CAM cells in one row.

[0030] Implementing various logical operations on a single CAM cell. For AND, NAND, OR, and NOR logical operations, when mapping n input variables, the n-bit input variables are represented by X1, X2, …, Xn respectively. Among them, X1, X2, …, Xn-1 are represented by the threshold voltages of the memory cells. Assuming that the decimal value corresponding to the binary number formed by X1X2…Xn-1 is i, then there is:

[0031] V th1 = V i-1 ,

[0032]

[0033] Xn is represented by the voltage applied to the search line SL. The mapping is shown in the following table, where V0 < V1 < V2 < … < V2^(n-1)-1;

[0034] Mapping rules for input variable n when implementing AND, NAND, OR, and NOR logical operations on n input variables

[0035]

[0036]

[0037] Implementing various logical operations on a single CAM cell. For XOR and XNOR logical operations, when mapping n input variables, the n-bit input variables are represented by X1, X2, …, Xn respectively. Among them, X1, X2, …, Xn-1 are represented by the threshold voltages of the memory cells. Reorder the binary codes of X1, X2, …, Xn-1: where the value of Xn-1 takes the first 2 n-1 bits of the Thue-Morse sequence, the value of Xn-2 cycles as 0, 1, 0, 1, …, the value of Xn-3 cycles as 0, 0, 1, 1, 0, 0, 1, 1, …, and so on. The value of X1 cycles as 2 n-3 zeros, 2 n-3 ones; in this order, the binary number formed by the i-th X1X2…Xn-1 is mapped to the CAM cell, and there is the following expression:

[0038] V th1 = V i-1 ,

[0039]

[0040] Xn is represented by the voltage applied to the search line SL. The mapping rules are shown in the following table, where V0 < V1 < V2 < … < V2^(n-1)-1;

[0041] Mapping rules of input variable n when the n-input variable implements XOR and XNOR logic operations

[0042]

[0043] The present invention does not require any physical structure adjustment to the CAM structure. Various logic operations can be realized only by changing the mapping, including full binary Boolean logic operations and six (AND, NAND, OR, NOR, XOR, XNOR) multi-valued logic operations.

[0044] Based on the physical characteristics of the CAM cell, the present invention does not require changing the CAM array structure. Through the combination of the threshold voltage of the storage cell and the input search voltage, full binary Boolean logic operations are realized in the CAM structure, expanding the function of the CAM and greatly improving the reconfigurability of the CAM. It is applicable to various non-volatile memories, not only applicable to NOR flash memories, but also applicable to non-volatile memories such as memristors, phase change memories, and ferroelectric memories. Brief Description of the Drawings

[0045] Figure 1 It is a schematic diagram of a CAM cell based on NOR flash memory.

[0046] Figure 2 Taking the logic operation of two input variables as an example, it shows a schematic diagram of the calculation process of the logic operation in a row of CAM cells.

[0047] Figure 3 Taking the logic operation of two input variables as an example, it shows a schematic diagram of the discharge rate under different mismatch numbers in a row of CAM cells. Detailed Embodiment

[0048] The Boolean operation method based on the flash memory addressable memory of the present invention can complete logic operations and realize full (16 kinds) Boolean operations based on the CAM cells of NVM by reconstructing the functional mapping relationship of the storage cells, without any change in the circuit structure. A CAM cell usually consists of 2 storage cells, that is, the present invention can use 2 storage cells to realize the functions of various logic gates, thereby saving area and improving the circuit integration degree.

[0049] The basic characteristic of the CAM cell is that the device is non-conductive and the match line ML remains high (i.e., "match") if and only if the search voltages applied to the two search lines SL (Search Line) are both less than or equal to the threshold voltage Vth of the storage cell. As long as the search level of ≥1 search line is greater than Vth, the device conducts and the match line ML discharges rapidly, which is "mismatch". Therefore, various logical operations, including AND, NAND, OR, NOR, XOR, XNOR, etc., can be implemented on a single CAM cell through different mappings of the logical values of the input variables to the characteristic values of the CAM cell and then through the mapping of the state of the match line ML to the output result.

[0050] Taking the NOR flash memory as an example for illustration, that is, a CAM cell consists of two NOR flash memory cells M1 and M2, as Figure 1 shown. For binary logical operations, the threshold voltages Vth1 and Vth2 stored in M1 and M2 are used to represent input variable 1: when Vth1 = Vlow and Vth2 = Vhigh, it means that input variable 1 is logic 0, and vice versa, it means that input variable 1 is logic 1, where Vlow < Vhigh. The search voltages Vs1 and Vs2 applied to the gates of M1 and M2 are used to represent input variable 2. To achieve different logical functions, different mapping methods are required for input variable 2. The specific mapping rules are shown in Table 1 below.

[0051] Table 1 Mapping rules for input variable 2 to implement full Boolean operations with two input variables

[0052]

[0053]

[0054] Taking the AND operation (logical AND operation) as an example, if the value of input variable 2 is logic 0, then the search voltages Vs1 = Vs2 = Vhigh are applied; if the value of input variable 2 is logic 1, then the search voltages Vs1 = Vhigh and Vs2 = Vlow are applied. If and only if the values of both input variables 1 and 2 are logic 1, the match line ML will always remain high, which means that the operation result is logic 1; otherwise, the voltage of the match line ML will drop rapidly, indicating that the operation result is logic 0. This Boolean logic operation method can also be extended to multiple input variables.

[0055] Figure 2Taking a binary operation as an example, the mapping process of the logical operation proposed by the present invention is shown. First, the threshold voltages of each storage unit are programmed according to the value of the input variable 1 to be calculated; secondly, each search line SL is pressurized according to the value of the input variable 2. If the calculation result of a CAM unit is 1, then the CAM unit is matched, otherwise the CAM unit is mismatched, resulting in the discharge of the match line ML. The calculation result Sum can be expressed by the following formula:

[0056]

[0057] The value of Sum represents the number of calculation values of 1 in the calculation results of a row, that is, the number of matched CAM units. The serial number i indicates that this is the i-th CAM unit in a row. N CAM represents the number of CAM units in a row. xi1 and xi2 respectively represent the two storage units in the i-th CAM unit. represents the adopted logical operation method (such as AND, NAND, OR, NOR, XOR, XNOR, IMP, RIMP, NIMP, RNIMP, etc.).

[0058] Due to the characteristics of the CAM unit, the discharge rate of the match line ML is different under different numbers of mismatches. The discharge situation of the match line ML over time can be expressed by the following formula:

[0059] VML = A × exp(-DR × t) + C;

[0060] where VML represents the voltage value of the match line ML, t represents the discharge time, and A, DR, and C are fitting parameters, where the discharge rate DR of the match line ML is proportional to the number N of mismatched CAM units.

[0061] Figure 3 The discharge rate of the match line ML under different numbers N of mismatched CAM units is given:

[0062] DR = J × N + K;

[0063] where J and K are fitting constants; specifically:

[0064] DR = 2.78×10 7 ×N + 3.14×10 7 .

[0065] Therefore, the present invention obtains DR from VML, and further the value of N can be obtained.

[0066] Sum = N CAM -N;

[0067] The above formula illustrates the relationship between Sum and N, where N CAM represents the number of CAM units in a row.

[0068] In summary, through VML in the present invention, the AND (logical AND) calculation result of a row can be obtained through conversion. The implementation methods of other Boolean logic operations are similar to this.

[0069] Taking advantage of the multi-value storage characteristic of NVM, a CAM cell can represent multi-bit data. Based on this characteristic, by further expanding the above mapping scheme, various logic operations of multiple input variables can be implemented on a single CAM cell.

[0070] For multi-variable logic operations, they can be implemented by utilizing the multi-value storage characteristic of CAM cells. The following Table 2-1 and Table 2-2 give the mapping rules of input variables when implementing AND, NAND, OR, and NOR logic operations for four input variables. Among them, the values of input variables X1, X2, and X3 in Table 2-1 are represented by the threshold voltage of the storage cell, and the mapping method is independent of the type of logic operation. The value of X4 is represented by the voltage applied to the search line SL, and the mapping method changes with different logic operations. Among them, V0 < V1 < V2 < … < V7.

[0071] Table 2-1 Mapping rules of input variables X1, X2, and X3 for quaternary AND, NAND, OR, and NOR logic operations

[0072]

[0073] Table 2-2 Mapping rules of input variable X4 for quaternary AND, NAND, OR, and NOR logic operations

[0074]

[0075] Thus, the mapping methods of AND, NAND, OR, and NOR logic operations can be further expanded to n input variables: represent n-bit input variables with X1, X2, …, Xn respectively, where X1, X2, …, Xn-1 are represented by the threshold voltage of the storage cell. Assume that the decimal corresponding to the binary number formed by X1X2…Xn-1 is i, then there is:

[0076] V th1 =V i-1 ,

[0077]

[0078] Xn is represented by the voltage applied to the search line SL, and the mapping method is shown in the following Table 3. Among them, V0 < V1 < V2 < … < V2^(n-1)-1.

[0079] Table 3 Mapping rules of input variable n for implementing AND, NAND, OR, and NOR logic operations with n input variables

[0080]

[0081] Table 4-1 and Table 4-2 below give the mapping rules of input variables when implementing XOR and XNOR logic operations with four input variables. Among them, the values of input variables X1, X2, and X3 are represented by the threshold voltages of memory cells, and the mapping method is independent of the type of logic operation. The value of X4 is represented by the pressurization value of SL, and the mapping method changes with the type of logic operation. Among them, V0 < V1 < V2 < … < V7.

[0082] Table 4-1 Mapping Rules of Input Variables X1, X2, and X3 When Implementing XOR and XNOR Logic Operations with Four Input Variables

[0083]

[0084] Table 4-2 Mapping Rules of Input Variable X4 When Implementing XOR and XNOR Logic Operations with Four Input Variables

[0085]

[0086] The mapping methods of XOR and XNOR logic operations can be further extended to n (n > 2) input variables: represent the n-bit input variables with X1, X2, …, Xn respectively, where X1, X2, …, Xn-1 are represented by the threshold voltages of memory cells. Here, for the convenience of expression, it is necessary to reorder the binary codes of X1X2…Xn-1: among them, the value of Xn-1 takes the first 2 n-1 bits of the Thue-Morse sequence, the value of Xn-2 cycles according to 0, 1, 0, 1, …, the value of Xn-3 cycles according to 0, 0, 1, 1, 0, 0, 1, 1, …, and so on. The value of X1 cycles according to 2 n-3 zeros and 2 n-3 ones. In this order, the binary number formed by the i-th X1X2…Xn-1 is mapped to the CAM cell, and there is the following expression:

[0087] V th1 = V i-1 ,

[0088]

[0089] Xn is represented by the pressurization value of the search line SL, and the mapping method is shown in Table 5 below. Among them, V0 < V1 < V2 < … < V2^(n-1)-1.

[0090] Table 5 Mapping Rules of Input Variable n When Implementing XOR and XNOR Logic Operations with n Input Variables

[0091]

[0092] In summary, the mapping method can implement various logical operations. When implementing all binary Boolean logical operations and multi - variable AND, NAND, OR, NOR operations, different types of operations for the same input variables can be achieved only by changing the pressure on the search line SL. When implementing multi - variable XOR and XNOR operations, the operations need to be carried out according to the corresponding mapping rules.

Claims

1. A Boolean operation method based on a flash-addressable memory, characterized in that: Two flash memory cells M1 and M2 form a CAM cell. For the logical operation of n input variables, the threshold voltages Vth1 and Vth2 stored in M1 and M2 are used to represent the input variables X1, X2, …, Xn-1; the search voltages Vs1 and Vs2 applied to the gates of M1 and M2 are used to represent the input variable Xn, so as to implement the logical operation; if the type of logical operation is different, the mapping rule of the input variables will change accordingly; through the different mappings of the logical values of the input variables to the characteristic values of the CAM cell, and then through the mapping of the state of the match line ML to the output result, various logical operations, including binary logical operations and multi-valued logical operations, are implemented on a CAM cell according to the corresponding mapping rules.

2. The Boolean operation method based on a flash memory addressable memory according to claim 1, characterized in that: The mapping rule of input variable 1 for the binary logical operation is that when Vth1 = Vlow and Vth2 = Vhigh, it means that input variable 1 is logic 0, otherwise it means that input variable 1 is logic 1, where Vlow < Vhigh.

3. The Boolean operation method based on a flash memory addressable memory according to claim 1, wherein: The mapping rule of input variable 2 for the binary logical operation is:

4. The Boolean operation method based on flash addressable memory according to claim 1, characterized in that: When the logical operation is the AND logical operation: if the value of input variable 2 is logic 0, then the search voltages Vs1 = Vs2 = Vhigh are applied; if the value of input variable 2 is logic 1, then the search voltages Vs1 = Vhigh and Vs2 = Vlow are applied; if and only if the values of input variables 1 and 2 are both logic 1, the match line ML will always remain high level, that is, it means that the operation result is logic 1, otherwise the voltage of ML will drop rapidly, indicating that the operation result is logic 0.

5. The Boolean operation method based on flash-addressable memory according to claim 1, characterized in that: The mapping process of the binary logical operation is: First, program the threshold voltages of each storage cell according to the value of input variable 1 to be calculated. Secondly, apply voltage to each search line SL according to the value of input variable 2. If the calculation result of a certain CAM cell is 1, then the CAM cell matches, otherwise the CAM cell mismatches, resulting in the discharge of the match line ML.

6. The Boolean operation method based on a flash-addressable memory according to claim 5, characterized in that: The calculation result of the CAM cell is expressed by the following formula: The Sum value represents the number of calculated values of 1 in the calculation results of a row, that is, the number of matching CAM cells; serial number N CAM represents the number of load CAM cells on an ML; The serial number i indicates that this is the i-th CAM cell in a row; xi1 and xi2 respectively represent the two storage cells in the i-th CAM cell. Indicates the logical operation method adopted.

7. The Boolean operation method based on a flash memory addressable memory according to claim 5, characterized in that: The situation of the discharge of the match line ML is expressed by the following formula: VML = A × exp(-DR × t) + C; Where VML represents the voltage value of the match line ML; t represents the discharge time; A, DR, and C are fitting parameters, DR represents the discharge rate of the match line ML, and DR is proportional to the number N of mismatched CAM cells; "--" represents the negative sign; The relationship between the discharge rate DR of the match line ML and the number N of mismatched CAM cells is expressed by the following formula: DR = J × N + K; Where J and K are fitting constants.

8. The Boolean operation method based on a flash addressable memory according to claim 5, characterized in that: The relationship between the number Sum of the matched CAM cells and the number N of the mismatched CAM cells is expressed by the following formula: Sum=N CAM -N; Where N CAM represents the number of CAM cells in a row.

9. The Boolean operation method based on a flash-addressable memory according to claim 1, characterized in that: When implementing various logical operations on a CAM cell, for the AND, NAND, OR, and NOR logical operations, when mapping n input variables, X1, X2, …, Xn are used to represent n-bit input variables respectively, where X1, X2, …, Xn-1 are represented by the threshold voltages of the storage cells. Assuming that the decimal corresponding to the binary number formed by X1X2…Xn-1 is i, then there is: V th1 = V i-1 , Xn is represented by the pressure value of the search line SL, and the mapping is shown in the following table, where V0 < V1 < V2 < … < V2^(n - 1) - 1; Mapping rules for the input variable n when the n-input variables perform AND, NAND, OR, and NOR logical operations 10. The Boolean operation method based on a flash-addressable memory according to claim 1, wherein: Implementing various logical operations on a CAM cell. For XOR and XNOR logical operations, when mapping n input variables, the n-bit input variables are represented by X1, X2, …, Xn respectively. Among them, X1, X2, …, Xn-1 are represented by the threshold voltages of the memory cells, and the binary codes of X1, X2, …, Xn-1 are reordered: where the value of Xn-1 takes the first 2 n-1 bits of the Thue-Morse sequence, the value of Xn-2 cycles as 0, 1, 0, 1, …, the value of Xn-3 cycles as 0, 0, 1, 1, 0, 0, 1, 1, …, and so on. The value of X1 cycles as 2 n-3 zeros and 2 n-3 ones arranged in sequence. In this order, the binary number formed by the i-th X1X2…Xn-1 is mapped to the CAM cell, and the following expression is obtained: V th1 = V i-1 , Xn is represented by the pressure value of the search line SL, and the mapping rules are shown in the following table, where V0 < V1 < V2 < … < V2^(n - 1) - 1; Mapping rules for the input variable n when the n-input variables perform XOR and XNOR logical operations

Images