A low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm
By optimizing the segmented processing and mantissa multiplication of the floating-point multiplier using a logarithmic approximation algorithm, the problems of hardware complexity and high resource consumption of the floating-point multiplier are solved, achieving low power consumption, low latency and high efficiency in computation.
Patent Information
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- UNIV OF ELECTRONICS SCI & TECH OF CHINA
- Filing Date
- 2026-03-17
- Publication Date
- 2026-05-29
AI Technical Summary
Existing floating-point multipliers have complex hardware circuits, consume a lot of hardware resources, and result in excessive power consumption and hardware overhead.
A low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm is adopted. By replacing the mantissa multiplier in the traditional floating-point multiplier with a segmented processing module, a truncation compensation multiplier based on probability statistics, and a dynamic truncation multiplier based on logarithmic approximation, approximate calculations are performed to optimize hardware overhead and power consumption.
It effectively reduces hardware overhead and power consumption, lowers latency, and optimizes accuracy, making it suitable for low-power, low-latency, low-cost, fault-tolerant applications.
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Figure CN122111370A_ABST
Abstract
Description
Technical Field
[0001] This invention belongs to the field of integrated circuit technology, and in particular relates to a low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm. Background Technology
[0002] As transistor sizes approach their physical limits, Moore's Law and Dennard's scaling law gradually fail, voltage cannot be reduced proportionally, and the power density of integrated circuits surges. Simultaneously, the explosive growth of computationally intensive applications such as artificial intelligence, digital signal processing, and big data leads to a dramatic increase in power consumption due to high-performance circuit systems. Excessive power consumption causes devices to overheat, affecting circuit performance and even damaging components. Therefore, low-power design of integrated circuits has become a hot topic in both industry and academia. Some applications have a certain degree of error tolerance; for example, in multimedia processing, images and audio are limited by human perception thresholds, and slight loss of accuracy is difficult to detect. Approximate computing techniques, a computing paradigm that sacrifices controllable accuracy for optimized computational performance, energy efficiency, and resource usage, have become a key direction for integrated circuit design in the post-Moore's Law era.
[0003] Floating-point numbers are a commonly used data format, widely employed in fields such as artificial intelligence and digital signal processing. Compared to fixed-point numbers, floating-point numbers offer a larger data range and higher precision. However, floating-point multiplication involves more complex hardware circuitry and consumes significant hardware resources. As the most basic arithmetic unit in a circuit system, the performance and power consumption of the multiplier play a decisive role in the overall energy efficiency of the circuit. Unlike fixed-point multiplication, which directly performs operations on the data as a whole, floating-point multiplication involves five separate steps: preprocessing, sign bit manipulation, mantissa multiplication, exponentiation, result normalization, and rounding. The preprocessing and mantissa multiplication steps account for a large portion of the hardware overhead and are the main sources of power consumption for the multiplier. The preprocessing module is primarily for handling denormalized numbers and requires a leading 1 detection circuit, shifters, and subtractors. Mantissa multiplication requires fixed-point multiplication of the mantissa portion, necessitating the use of numerous compressors to process the partial product array. Therefore, approximate calculation techniques are used to process floating-point multipliers, thereby optimizing circuit parameters such as area, power consumption, and delay, and achieving a balance between hardware overhead and accuracy. Summary of the Invention
[0004] The purpose of this invention is to provide a low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm, so as to solve the technical problem that the hardware circuit of floating-point multiplication is complex and consumes a lot of hardware resources in the prior art.
[0005] To solve the above-mentioned technical problems, the specific technical solution of the present invention is as follows:
[0006] A low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm is provided. The multiplier includes a sign bit operation module, a segmentation processing module, a truncation compensation multiplier based on probability statistics, a dynamic truncation multiplier based on logarithmic approximation, a mantissa adder, an exponent adder, an exponent update module, a normalization module, and a special value processing module.
[0007] The input to the segmented processing module is the mantissa M of the multiplier. B The output is the high-weight segment M of the mantissa of the multiplier. BH And the low-weight segment M of the mantissa of the multiplier BL Recombination M with hidden bit 1 BL ;
[0008] The probability-based truncated compensated multiplier consists of an array multiplier with four rows of partial products: PP1, PP2, PP3, and PP4. The partial product array of the array multiplier is truncated from columns 0 to 37, resulting in PP1 as the truncated partial product. k PP2 k PP3 k PP4 k The partial product array's compressed tree consists of two levels. The first level contains six 4-2 compressors and one full adder. The second level is a 7-bit ripple carry adder.
[0009] High-weight segmentation M of the mantissa portion of the input multiplier based on probability statistics for truncating and compensating the multiplier. BH Recombination of the mantissa of the multiplicand and the hidden 1: 1+M A The output is the first part of the product M. P1 ;
[0010] The dynamic truncated multiplier based on logarithmic approximation consists of two MUXs and one logarithmic adder. The input to the dynamic truncated multiplier is the mantissa of the multiplicand and the recombined 1+M of the hidden bit 1. A Low-weight segmentation of the mantissa of the multiplier and recombination of hidden bit 1 1+M BL Output the second part of the product M P2 ;
[0011] The mantissa adder consists of a single 10-bit adder; the input is the first part of the product M. P1 The product of the second part M P2 The output is the product of the third part, M. P3 .
[0012] Furthermore, the recombination of the mantissa portion of the multiplicand and the hidden bit 1 is 1+M. A Low-weight segmentation of the mantissa of the multiplier and recombination of hidden bit 1 1+M BLInput the first MUX; the first MUX is used to determine the multiplicand's mantissa M. A The size of the highest weight bit, and the low-weight segment M of the mantissa of the multiplier. BL Perform selective shifting; if the mantissa M of the multiplicand... A If the multiplier is greater than or equal to 0.5, then the low-weight segment M of the mantissa of the multiplier... BL Shift left by one bit, otherwise leave unchanged; the first MUX output temporary value M before truncating the mantissa of the logarithmic approximation multiplier. BL-t-pr The mantissa M of the multiplicand A M is the temporary value of the multiplicand before truncation of the mantissa in the logarithmic approximation. A-t-pre The temporary value M before truncation of the logarithmic approximation multiplier. BL-t-pr Input the second MUX, which is a temporary value M before the mantissa of the multiplicand is truncated based on the logarithmic approximation. A-t-pre The size of the highest weight bit, the temporary value M before truncating the mantissa of the logarithmic approximation multiplicand. A-t-pre The temporary value M before truncation of the sum of the approximate multiplier and the mantissa B-t-pre Selective dynamic truncation is performed on the two operands. If the logarithm approximates the temporary value M of the multiplicand before truncation... A-t-pre If the value is less than 0.5, the lower 14 bits are truncated without bias, leaving the upper 9 bits, and a fixed value of 1 is set in the least significant bit for compensation; otherwise, the lower 14 bits are directly truncated, leaving the upper 9 bits. The second MUX outputs the truncated mantissa portion M of the multiplicand. A-t The truncated part M of the multiplier BL-t A logarithmic adder is used for the truncated mantissa M of the multiplicand. A-t The truncated part M of the multiplier BL-t The product of the two parts, M, is summed and output as the second part. P2 .
[0013] Furthermore, the normalization module normalizes and rounds the third part of the product, ultimately obtaining the mantissa M of the product. P .
[0014] Furthermore, the exponent adder inputs the exponent portion E of the multiplicand. A The exponential part of the multiplier E B Perform addition and output the temporary exponent E. temp .
[0015] Furthermore, the exponent update module updates the mantissa M of the product. P When it exceeds 2, the temporary index E temp After updating the exponent, we finally obtain the exponent part E of the product. P .
[0016] Furthermore, the special value processing module adds an approximation processing for non-standard numbers, directly approximating non-standard numbers as 0.
[0017] Furthermore, the sign bit operation module includes one XOR gate; the input of the XOR gate is the sign part S of the multiplicand. A The sign part S of the multiplier B The output is the signed part S of the product. P .
[0018] Compared with the prior art, the present invention has the following beneficial technical effects:
[0019] 1) The proposed low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm effectively reduces hardware overhead and lowers circuit power consumption and latency by approximating the floating-point preprocessing and mantissa multiplier components. The logarithmic approximation multiplier achieves low-weight segmented computation at low cost and limits the maximum error loss. Simultaneously, the truncated and compensated multiplier ensures the computational accuracy of the mantissa multiplication's highly effective partial product array. This invention is suitable for implementing low-power, low-latency, and low-cost fault-tolerant applications.
[0020] 2) Compared with traditional precise floating-point multipliers, this invention significantly improves accuracy and optimizes circuit area, power consumption, and delay. Furthermore, compared with other approximate floating-point multiplier designs, this invention achieves a better balance between hardware overhead and accuracy.
[0021] 3) The low-power single-precision floating-point multiplier based on the logarithmic approximation algorithm of this invention is reconfigurable, allowing for reconfiguration design according to accuracy requirements and enabling fine-grained adjustment of accuracy. This invention is suitable for fault-tolerant applications with requirements for circuit delay and power consumption. Attached Figure Description
[0022] To more clearly illustrate the technical solutions in the embodiments of the present invention or the prior art, the drawings used in the description of the embodiments or the prior art will be briefly introduced below. Obviously, the drawings described below are some embodiments of the present invention. For those skilled in the art, other drawings can be obtained based on these drawings without creative effort.
[0023] Figure 1 This is a schematic diagram of a single-precision floating-point number format.
[0024] Figure 2 This is a schematic diagram of the circuit structure of a precise floating-point multiplier.
[0025] Figure 3 This is a schematic diagram of the circuit structure of the low-power single-precision floating-point multiplier based on the logarithmic approximation algorithm of the present invention.
[0026] Figure 4 This is a schematic diagram of the tail segmentation and recombination of the present invention.
[0027] Figure 5 This is a schematic diagram of the compressed tree of the truncated compensation array multiplier based on probability statistics of the present invention.
[0028] Figure 6 This is a schematic diagram of the circuit structure of the dynamic truncation multiplier based on logarithmic approximation of the present invention. Detailed Implementation
[0029] The technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings. Obviously, the described embodiments are only some embodiments of the present invention, and not all embodiments. Based on the embodiments of the present invention, all other embodiments obtained by those skilled in the art without creative effort are within the scope of protection of the present invention.
[0030] Figure 1 This is a schematic diagram of a single-precision floating-point number format. A single-precision floating-point number has a bit width of 32 bits, which includes a 1-bit sign part S, an 8-bit exponent part E, and a 23-bit mantissa part M.
[0031] Figure 2 This is a schematic diagram of the circuit structure of a precise floating-point multiplier. A E A and M A These correspond to the sign part, exponent part, and mantissa part of the multiplicand, respectively. B E B and M B These correspond to the sign part, exponent part, and mantissa part of the multiplier, respectively. The sign part S of the multiplicand... A The sign part S of the multiplier B The sign part S of the product is obtained through the XOR operation. P If the multiplicand or multiplier contains non-standard numbers, preprocessing is required to convert them to standard numbers. Preprocessing of the non-standard mantissa mainly involves detecting the most significant bit as 1 and performing a shift operation. Preprocessing of the exponent mainly involves subtracting the left-shifted value of the mantissa. The exponent E of the multiplicand... A The exponential part of the multiplier E B After exponent preprocessing, the exponent is input into an exponent adder for addition operations to obtain a temporary exponent E. temp The mantissa M of the multiplicand A After preprocessing the non-normal numbers, the mantissa M of the multiplicand is... A To determine if a number is non-standard, a temporary value M of the multiplicand before truncation is obtained by using a multiplexer (MUX). A-preThe mantissa M of the multiplier B After preprocessing the non-normal number, the mantissa M of the multiplier is... B To determine the non-standard number, a temporary value M of the multiplier before truncation is obtained by using a multiplexer (MUX). B-pre Temporary value M before truncating the mantissa of the multiplicand A-pre Temporary value M before truncation of the multiplier mantissa B-pre The input mantissa multiplier performs multiplication to obtain the product; the product is then normalized and rounded to finally obtain the mantissa part M of the product. P If the mantissa of the product is M P More than 2, for the temporary index E temp After updating the exponent, we finally obtain the exponent part E of the product. P In addition, if the multiplicand and multiplier contain special values, such as infinity (Inf) and not a number (NaN), the mantissa M of the product needs to be calculated. P The exponent part E of the product P Perform special value processing.
[0032] The circuit structure of the low-power single-precision floating-point multiplier based on the logarithmic approximation algorithm proposed in this invention is as follows: Figure 3 As shown, with Figure 2 The main difference between this and an accurate floating-point multiplier lies in the preprocessing and mantissa multiplication. In an accurate floating-point multiplier, the preprocessing of the exponent and mantissa consumes significant hardware resources to handle denormalized numbers. To reduce hardware resource overhead, this invention approximates the preprocessing by directly approximating denormalized numbers to 0 and placing them in a special value processing module. This approach significantly reduces hardware resource overhead without introducing large errors.
[0033] The core of this invention is to replace the mantissa multiplier in a precise floating-point multiplier by employing a hybrid precision operation that combines a probability-statistically based truncation-compensated multiplier with a probability-statistically based truncation-compensated multiplier. This invention uses the mantissa portion M of the multiplier... B The segmentation module obtains the high-weight segment M of the mantissa of the multiplier. BH And the low-weight segment M of the mantissa of the multiplier BL Recombination of hidden bit 1+M BL The low-weight segment M of the mantissa of the multiplier. BL Recombination of hidden bit 1+M BL The recombination of the mantissa of the multiplicand and the hidden 1 is 1+M A As input to a dynamically truncated multiplier based on logarithmic approximation. The high-weighted segment M of the mantissa of the multiplier. BHRecombination of the mantissa of the multiplicand and the hidden 1: 1+M A The input is used as the input to a probability-based truncated compensated multiplier. The outputs of the probability-based truncated compensated multiplier and the input are then processed by a mantissa adder. Since an approximation has been introduced, rounding is no longer necessary; only normalization is required. The subsequent process remains consistent with that of the exact multiplier.
[0034] like Figure 3 As shown, the low-power single-precision floating-point multiplier based on the logarithmic approximation algorithm proposed in this invention includes a sign bit operation module, a segmentation processing module, a truncation compensation multiplier based on probability statistics, a dynamic truncation multiplier based on logarithmic approximation, a mantissa adder, an exponent adder, an exponent update module, a normalization module, and a special value processing module.
[0035] The sign bit operation module includes one XOR gate. The input to the XOR gate is the sign part S of the multiplicand. A The sign part S of the multiplier B The output is the signed part S of the product. P .
[0036] The input to the segmented processing module is the mantissa M of the multiplier. B The output is the high-weight segment M of the mantissa of the multiplier. BH And the low-weight segment M of the mantissa of the multiplier BL Recombination M with hidden bit 1 BL .
[0037] The segmented processing module requires no logic gates, only wiring and constant level allocation, such as Figure 4 As shown. The input is the mantissa of the multiplier. The output is the high-weight segment M of the mantissa. BH The concatenation result of low-weight segments and constant 1 is 1+M. BL .
[0038] High-weight segmentation M of the mantissa portion of the input multiplier based on probability statistics for truncating and compensating the multiplier. BH Recombination of the mantissa of the multiplicand and the hidden 1: 1+M A The output is the first part of the product M. P1 .
[0039] The probability-statistic-based truncated compensated multiplier consists of an array of multipliers. The mantissa portion of the multiplier is divided into high-weight segments M. BH Recombination of the mantissa of the multiplicand and the hidden 1: 1+M A As input to this array multiplier, the output is the first partial product M. P1 Compressed trees of partial product arrays of truncated compensated multipliers based on probability statistics, such as... Figure 5As shown, the probability-statistic-based truncated compensated multiplier consists of an array multiplier with four rows of partial products: PP1, PP2, PP3, and PP4. The partial product array of the array multiplier is truncated from columns 0 to 37, resulting in PP1 as the truncated partial product. k PP2 k PP3 k PP4 k The partial product array's compression tree consists of two levels. The first level contains six 4-2 compressors and one full adder; the second level is a 7-bit ripple carry adder.
[0040] The dynamic truncation of the input multiplicand based on logarithmic approximation and the recombination of the mantissa portion and hidden 1 bits into 1+M is used. A Low-weight segmentation of the mantissa of the multiplier and recombination of hidden bit 1 1+M BL Output the second part of the product M P2 .
[0041] The dynamically truncated multiplier based on logarithmic approximation consists of two MUXs (multiplexers) and one logarithmic adder, such as... Figure 6 As shown. The recombination of the mantissa of the multiplicand and the hidden bit 1 is 1+M. A Low-weight segmentation of the mantissa of the multiplier and recombination of hidden bit 1 1+M BL Input the first MUX; the first MUX is used to determine the multiplicand's mantissa M. A The size of the highest weight bit, and the low-weight segment M of the mantissa of the multiplier. BL Perform selective shifting; if the mantissa M of the multiplicand... A If the multiplier is greater than or equal to 0.5, then the low-weight segment M of the mantissa of the multiplier... BL Shift left by one bit, otherwise leave unchanged. The first MUX output is the temporary value M before truncation of the logarithmic approximation multiplier. BL-t-pr The mantissa M of the multiplicand A M is the temporary value of the multiplicand before truncation of the mantissa in the logarithmic approximation. A-t-pre The temporary value M before truncation of the logarithmic approximation multiplier. BL-t-pr Input the second MUX, which is a temporary value M before the mantissa of the multiplicand is truncated based on the logarithmic approximation. A-t-pre The size of the highest weight bit, the temporary value M before truncating the mantissa of the logarithmic approximation multiplicand. A-t-pre The temporary value M before truncation of the sum of the approximate multiplier and the mantissa B-t-pre Selective dynamic truncation is performed on the two operands. If the logarithm approximates the temporary value M of the multiplicand before truncation... A-t-preIf the value is less than 0.5, the lower 14 bits are truncated without bias, leaving the upper 9 bits, and a fixed value of 1 is set in the least significant bit for compensation; otherwise, the lower 14 bits are directly truncated, leaving the upper 9 bits. The second MUX outputs the truncated mantissa portion M of the multiplicand. A-t The truncated part M of the multiplier BL-t A logarithmic adder is used for the truncated mantissa M of the multiplicand. A-t The truncated part M of the multiplier BL-t The product of the two parts, M, is summed and output as the second part. P2 That is, the logarithmic approximation product.
[0042] The mantissa adder consists of a single 10-bit adder. The input is the first part of the product M. P1 The product of the second part M P2 The output is the product of the third part, M. P3 .
[0043] The normalization module normalizes and rounds the product in the third part, ultimately obtaining the mantissa M of the product. P .
[0044] The exponent adder inputs the exponent part E of the multiplicand. A The exponential part of the multiplier E B Perform addition and output the temporary exponent E. temp .
[0045] The exponent update module updates the mantissa M of the product. P When it exceeds 2, the temporary index E temp After updating the exponent, we finally obtain the exponent part E of the product. P .
[0046] The special value processing module adds an approximation processing for non-standard numbers, directly approximating non-standard numbers as 0.
[0047] The following is the theoretical derivation of this invention: The mantissa multiplication of any set of normalized floating-point numbers can be expressed as... In the segmented processing module, the mantissa portion M of the multiplier... B The high-weighted segment M of the mantissa portion of the multiplier is segmented as a multiplier. BH And the low-weight segment M of the mantissa of the multiplier BL Then the mantissa multiplication can be converted to By simplification, we can obtain the following formula:
[0048]
[0049] In the above formula The low-weight segment M represents the mantissa of the multiplier.BL Adding a hidden 1 to the multiplication of the mantissa of the multiplicand. A characteristic of this multiplication is that the highest bit of both operands is always 1. Therefore, if a dynamic truncation multiplier based on logarithmic approximation is used, the leading 1 detection circuit is eliminated, thus avoiding additional hardware resource overhead. Logarithmic approximation multiplication replaces the original multiplication operation with an addition operation, effectively reducing hardware resource overhead. Another part... This represents the high-weight segment M of the mantissa of the multiplier. BH The mantissa M of the multiplicand A The hidden bit is multiplied, and a truncated compensated multiplier based on probability statistics is used for calculation. Considering that there are some overlapping bits between the calculation results of low-weight segments and high-weight segments, an approximation is also introduced in the truncated compensated multiplier based on probability statistics. The low effective partial product array of the truncated compensated multiplier based on probability statistics is truncated, and the compensation bit is set by probability statistics.
[0050] Figure 6 This is a schematic diagram of the circuit structure of a dynamically truncated multiplier based on logarithmic approximation, comprising three parts: operand preprocessing, dynamic truncation processing, and a logarithmic adder. Operand preprocessing is used to adjust the logarithmic approximation function. Considering that the error of the traditional logarithmic approximation multiplier exhibits a one-sided distribution and is relatively large, with a peak relative error of 11.1%, the approximate expression for the product of the traditional logarithmic approximation multiplier is as follows:
[0051]
[0052] in, Indicates product; Represents the exponent of the multiplicand; The exponent portion of the multiplier; Indicates the offset of a floating-point number; Represents the mantissa portion of the multiplicand; This represents the mantissa portion of the multiplier.
[0053] When the sum of the operands is less than 1, the exact value minus the approximate value equals the product of the operands, M. A ·M B This invention introduces bilateral error by adjusting the logarithmic approximation function. This is because the mantissa M of the multiplicand... A The mantissa M of the sum multiplier B If both are decimals less than 1, then their product M A ·M B It must be less than any one of these numbers. When the mantissa of the multiplicand is M A When the value is greater than or equal to 0.5, this invention adds an additional compensation term M to the logarithmic approximation. BAt this point, the expression for the new logarithmic approximation is as follows:
[0054]
[0055] At this point, the logarithmic approximation error As shown in the following formula. When the mantissa M of the multiplicand A Less than 0.5, the approximate value is smaller than the exact value; when the mantissa of the multiplicand is M A When the value is greater than or equal to 0.5, the approximate value is larger than the exact value. This is based on the mantissa M of the multiplicand. A The magnitude of the error introduces positive and negative errors, which are symmetrically distributed. Logarithmic approximation error. The size depends on the mantissa M of the multiplicand. A The absolute distance from 0.5, and the mantissa M of the multiplier. B The absolute size.
[0056]
[0057] in, This represents the logarithmic approximation error.
[0058] In this invention, due to the use of segmented processing, the low-weight segment M of the mantissa portion of the multiplier is... BL The maximum value is less than 2 -4 Therefore, the largest error is caused by the low-weight segment M of the mantissa of the multiplier. BL Maximum value limit.
[0059] In logarithmic addition, the least significant bit has a relatively small impact on precision, while the bit width of the addition operation has a significant impact on hardware overhead. Therefore, this invention employs a dynamic truncation scheme to process the operands. The truncated operand is the mantissa M of the multiplicand after truncation. A-t The truncated part M of the multiplier BL-t The truncated bit width is 9 bits. The temporary value M before truncating the mantissa of the logarithmic approximation multiplicand. A-t-pre When the value is greater than or equal to 0.5, the approximate value is larger than the precise value. In this case, direct truncation is used to reduce the approximation and ultimately reduce the error. However, when the logarithmic approximation uses a temporary value M before truncation of the multiplicand's mantissa... A-t-preWhen the value is less than 0.5, the approximate value is smaller than the precise value. Therefore, unbiased truncation is used, meaning the least significant bit retained after truncation is set to a fixed value of 1. When the least significant bit retained after truncation is 0, a certain positive compensation is applied to the approximate value. However, if the least significant bit retained after truncation was originally 1, then unbiased truncation will still result in a negative error, which will further amplify the negative error. Therefore, in logarithmic addition, this invention uses a temporary value M before truncating the mantissa of the logarithmic approximation multiplicand. A-t-pre When the value is less than 0.5, the carry signal of the least significant bit is set to 1. This enables the temporary value M to be used before the mantissa of the logarithmic approximation multiplicand is truncated. A-t-pre Cutoff compensation when less than 0.5, compensation value is 2. -9 The expression combining logarithmic approximation and dynamic truncation is as follows:
[0060]
[0061] in, This represents the truncated portion of the multiplicand. This represents the truncated portion of the multiplier.
[0062] Error function Err truncated by logarithmic addition T The expression is as follows. The temporary value M before truncating the mantissa of the logarithmic approximation multiplicand. A-t-pre When the value is less than 0.5, truncation will result in either a positive or negative error. The temporary value M before truncation of the multiplicand in a logarithmic approximation... A-t-pre The temporary value M before truncation of the sum of the approximate multiplier and the mantissa BL-t-pre The maximum negative error Err is obtained when every bit in the truncated region is 1. T-neg-max The maximum positive error Err is achieved when every bit in the truncated region is 0. T-pos-max Err T-pos-max Approximately equal to Err T-neg-max The probability of truncation leading to a positive error is three times that of logarithmic approximation, and the probability of it leading to a negative error is much greater than the probability of it leading to a positive error. Furthermore, in this case, the logarithmic approximation error... This will always lead to a negative error, so the positive error from the truncation can offset the negative error caused by the logarithmic approximation, thus improving accuracy. The temporary value M before truncation of the multiplicand's mantissa in the logarithmic approximation... A-t-pre When the value is greater than or equal to 0.5, truncation will only result in a negative error. In this case, the logarithmic approximation error... This will always result in a positive error. Therefore, the negative error of the truncation will cancel out the positive error caused by the logarithmic approximation, thereby improving accuracy.
[0063]
[0064] in, This represents the logarithmic addition truncation error.
[0065] Figure 5 This is a schematic diagram of a partial product array compressed tree based on a probability-statistical truncated compensated multiplier. The probability-statistical truncated compensated multiplier consists of an array multiplier with four rows of partial products: PP1, PP2, PP3, and PP4. The partial product array of the array multiplier is truncated from columns 0 to 37, resulting in PP1 as the truncated partial product. k PP2 k PP3 k PP4 k This partial product array's compression tree consists of two levels. The first level contains six 4-2 compressors and one full adder; the second level is a 7-bit ripple carry adder. To achieve a good balance between accuracy and hardware resource overhead, a high-weighted segmentation M is used in the mantissa of the multiplier. BH With 1+M A Column truncation is used in the multiplication calculation. Simultaneously, to reduce the mean error of the circuit, this invention employs a fixed-value compensation method. Assuming the multiplicand and multiplier are uniformly distributed, in the partial product array, each bit is composed of M... BH With 1+M A The corresponding bits are constructed using AND gates. Therefore, the probability that each bit in the partial product array is 1 is equal to M. BH With 1+M A The truncation compensation value is the product of the probabilities of each bit being 1. It equals the probability of each bit being 1 in the truncated array multiplied by its weight, and then summed. The expression for the compensation value C is as follows, which, after simplification and summation, is approximately equal to 2. -8 .
[0066]
[0067] in, This represents the compensation value.
[0068] The partial product array truncation error Err caused by partial product array truncation K Segment M by the high weight of the mantissa of the multiplier BH and the mantissa M of the multiplicand A The maximum negative error is determined when all parts of the truncated partial product array are 1. The maximum negative error E of the truncated partial product array is obtained by summing the truncated partial product arrays and subtracting the compensation value C. K-neg-max , approximately equal to 2 -7 +2 -8 The maximum negative error can only occur in the high-weight segment M of the mantissa of the multiplier. BH All bits of the multiplicand are 1, and the mantissa M of the multiplicand is... AThe case where all the least significant bits are 1 is generated, and the probability of this occurring is very small. The maximum positive error E of partial product array truncation. K-pos-max That is, the truncation compensation value C, which is 2. -8 .
[0069]
[0070] in, PP1, PP2, PP3, and PP4 represent the partial product errors of the partial product array. PP1, PP2, PP3, and PP4 represent the partial products of the four rows of the partial product array, respectively. k PP2 k PP3 k PP4 k These represent the partial products of the four rows that were truncated and retained.
[0071] The global error function Err of the approximate floating-point multiplier of this invention is equal to the logarithmic approximation error Err. LM Logarithmic addition truncation error Err T With partial product array truncation error Err K The sum of the three. Represented as follows:
[0072]
[0073] in, This indicates the overall error.
[0074] Maximum negative error Err neg-max M occurs in the mantissa of the multiplicand A Approaching 0.5, and the mantissa of the multiplier is M B When the value is close to 1, the error value is approximately equal to Simplified to a decimal, it is approximately 0.0449. The maximum positive error Err... pos-max M occurs in the mantissa of the multiplicand A Equal to 0.5, low-weight segment M of the mantissa of the multiplier BL When the truncated region is all 0 and the retained region is all 1, it is approximately equal to Simplified to a decimal, it is approximately 0.0341. The maximum negative error Err... neg-max and the maximum positive error Err pos-max Both are much smaller than the maximum error of a traditional logarithmic multiplier.
[0075] Experimental simulations show that the approximate floating-point multiplier proposed in this invention reduces area by 87.59%, power consumption by 83.56%, and latency by 72.03% compared to the accurate floating-point multiplier, with an error index relative to the error distance MRED of only 0.00320.
[0076] In summary, this invention approximates and optimizes floating-point multipliers in multiple aspects. Compared to traditional logarithmic approximation multipliers, the proposed approximate floating-point multiplier employs a piecewise mixed-precision architecture, where errors in each approximation step cancel each other out, resulting in a significant improvement in accuracy. Furthermore, this floating-point multiplier can be redesigned according to requirements, allowing for fine-grained adjustment of accuracy. Appropriately applying the approximate floating-point multiplier described in this invention to applications such as image processing and artificial intelligence can effectively reduce circuit area, power consumption, and latency while sacrificing a certain range of error.
[0077] Finally, it should be noted that the above embodiments are only used to illustrate the technical solutions of the present invention, and not to limit them; although the present invention has been described in detail with reference to the foregoing embodiments, those skilled in the art should understand that modifications can still be made to the technical solutions described in the foregoing embodiments, or equivalent substitutions can be made to some or all of the technical features; and these modifications or substitutions do not cause the essence of the corresponding technical solutions to deviate from the scope of the technical solutions of the embodiments of the present invention.
Claims
1. A low-power single-precision floating-point multiplier based on a logarithmic approximation algorithm, characterized in that, The multiplier includes a sign bit operation module, a segmentation processing module, a truncation compensation multiplier based on probability statistics, a dynamic truncation multiplier based on logarithmic approximation, a mantissa adder, an exponent adder, an exponent update module, a normalization module, and a special value processing module. The input to the segmented processing module is the mantissa M of the multiplier. B The output is the high-weight segment M of the mantissa of the multiplier. BH And the low-weight segment M of the mantissa of the multiplier BL Recombination M with hidden bit 1 BL ; The probability-based truncated compensated multiplier consists of an array multiplier with four rows of partial products: PP1, PP2, PP3, and PP4. The partial product array of the array multiplier is truncated from columns 0 to 37, resulting in PP1 as the truncated partial product. k PP2 k PP3 k PP4 k The partial product array's compression tree consists of two levels. The first level contains six 4-2 compressors and one full adder. The second level is a 7-bit ripple carry adder. High-weight segmentation M of the mantissa portion of the input multiplier based on probability statistics for truncating and compensating the multiplier. BH Recombination of the mantissa of the multiplicand and the hidden 1: 1+M A The output is the first part of the product M. P1 ; The dynamic truncated multiplier based on logarithmic approximation consists of two MUXs and one logarithmic adder. The input to the dynamic truncated multiplier is the mantissa of the multiplicand and the recombined 1+M of the hidden bit 1. A Low-weight segmentation of the mantissa of the multiplier and recombination of hidden bit 1 1+M BL Output the second part of the product M P2 ; The mantissa adder consists of a single 10-bit adder; the input is the first part of the product M. P1 The product of the second part M P2 The output is the product of the third part M. P3 .
2. The low-power single-precision floating-point multiplier based on logarithmic approximation algorithm according to claim 1, characterized in that, The recombination of the mantissa of the multiplicand and the hidden 1: 1+M A Low-weight segmentation of the mantissa of the multiplier and recombination of hidden bit 1 1+M BL Input the first MUX; the first MUX is used to determine the multiplicand's mantissa M. A The size of the highest weight bit, and the low-weight segment M of the mantissa of the multiplier. BL Perform selective shifting; if the mantissa M of the multiplicand... A If the value is greater than or equal to 0.5, then the low-weight segment M of the mantissa of the multiplier... BL Shift left by one bit, otherwise leave unchanged; the first MUX output temporary value M before truncating the mantissa of the logarithmic approximation multiplier. BL-t-pr The mantissa M of the multiplicand A M is the temporary value of the multiplicand before truncation of the mantissa in the logarithmic approximation. A-t-pre The temporary value M before truncation of the logarithmic approximation multiplier. BL-t-pr Input the second MUX, which is a temporary value M before the mantissa of the multiplicand is truncated based on the logarithmic approximation. A-t-pre The size of the highest weight bit, the temporary value M before truncating the mantissa of the logarithmic approximation multiplicand. A-t-pre The temporary value M before truncation of the sum of the approximate multiplier and the mantissa B-t-pre Selective dynamic truncation is performed on the two operands. If the logarithm approximates the temporary value M of the multiplicand before truncation... A-t-pre If the value is less than 0.5, the lower 14 bits are truncated without bias, leaving the upper 9 bits, and a fixed value of 1 is set in the least significant bit for compensation; otherwise, the lower 14 bits are directly truncated, leaving the upper 9 bits. The second MUX outputs the truncated mantissa portion M of the multiplicand. A-t The truncated part M of the multiplier BL-t A logarithmic adder is used for the truncated mantissa M of the multiplicand. A-t The truncated part M of the multiplier BL-t The product of the two parts, M, is summed and output as the second part. P2 .
3. The low-power single-precision floating-point multiplier based on logarithmic approximation algorithm according to claim 1, characterized in that, The normalization module normalizes and rounds the product in the third part, ultimately obtaining the mantissa M of the product. P .
4. The low-power single-precision floating-point multiplier based on logarithmic approximation algorithm according to claim 1, characterized in that, The exponent adder inputs the exponent part E of the multiplicand. A The exponential part of the multiplier E B Perform addition and output the temporary exponent E. temp .
5. The low-power single-precision floating-point multiplier based on logarithmic approximation algorithm according to claim 1, characterized in that, The exponent update module updates the mantissa M of the product. P When it exceeds 2, the temporary index E temp After updating the exponent, we finally obtain the exponent part E of the product. P .
6. The low-power single-precision floating-point multiplier based on logarithmic approximation algorithm according to claim 1, characterized in that, The special value processing module adds an approximation processing for non-standard numbers, directly approximating non-standard numbers as 0.
7. The low-power single-precision floating-point multiplier based on logarithmic approximation algorithm according to claim 1, characterized in that, The sign bit operation module includes one XOR gate; the input of the XOR gate is the sign part S of the multiplicand. A The sign part S of the multiplier B The output is the signed part S of the product. P .