Preparation method of multi-chip connection structure

Abstract

The invention belongs to the technical field of chips, and particularly relates to a preparation method of a multi-chip connection structure. The method comprises the following steps: coating a release layer and a bonding layer on a base material; the chip is provided with copper column salient points, the chip is temporarily bonded on the bonding layer, and the copper column salient points of the control part are embedded into the bonding layer; a plastic packaging layer is formed on the bonding layer and wraps the chip and the remaining copper column protruding points, and the chip and the plastic packaging layer jointly form a first module; peeling off the bonding layer, exposing the copper column salient points embedded into the bonding layer, depositing a non-metal dielectric material on the surface, with the copper column salient points, of the module I to modify the copper column salient points, enabling the two sides of the copper column salient points not to be exposed, and carrying out copper-copper bonding on the residual exposed surface of the copper column salient points and the TSV intermediate layer; and removing the redundant silicon substrate of the TSV intermediate layer to obtain a module II, constructing a complete RDL layer at the bottom of the module II, and manufacturing a bump on the surface of the complete RDL layer. According to the invention, the welding reliability, the signal integrity and the heat dissipation performance of the prepared multi-chip connection structure are improved.

Description

Technical Field

[0001] The present invention belongs to the field of chip technology, and particularly relates to a preparation method for a multi-chip connection structure. Background Art

[0002] In the prior art, uPads (micro-bumps) are usually electroplated on a TSV interposer (TSV interposer), such as micro-bumps made of Cu / Ni / Au alloy solder or Cu / Ni / SnAg alloy solder. Then, the chips are soldered to the TSV interposer by the Flip chip (flip chip) method, and then the chips are encapsulated.

[0003] The technical problems existing in such preparation are as follows: Welding reliability: The reliability problem of micro-bumps is becoming increasingly prominent, and defects such as poor soldering and cracks are likely to occur, affecting the long-term stability of the chips.

[0004] Signal integrity: As the signal frequency increases, the parasitic capacitance and inductance of micro-bumps and solder will affect signal integrity, restricting the data transmission rate.

[0005] Thermal management: The high thermal resistance of micro-bumps and solder will affect the heat dissipation performance of the chips. Summary of the Invention

[0006] Aiming at the deficiencies of the prior art, the purpose of the present invention is to provide a preparation method for a multi-chip connection structure.

[0007] To achieve the above object and other related objects, the present invention provides the following technical solutions: A preparation method for a multi-chip connection structure, comprising the following steps: Coat a release layer on a substrate, and coat an adhesive layer on the release layer; The chips include SOC Die and HBM Die, and there are copper pillar bumps on the chips. The chips are temporarily bonded to the adhesive layer, and a part of the copper pillar bumps are embedded in the adhesive layer; Form a plastic encapsulation layer on the adhesive layer. The plastic encapsulation layer wraps the chips and the remaining copper pillar bumps. The chips and the plastic encapsulation layer together form Module 1; Peel off the adhesive layer, and the copper pillar bumps embedded in the adhesive layer are exposed. Deposit a non-metallic dielectric material on the side of Module 1 with copper pillar bumps to modify the copper pillar bumps, so that both sides of the copper pillar bumps are no longer exposed. Bond the remaining exposed surfaces of the copper pillar bumps to the TSV interposer by copper-copper bonding (Cu-Cu bonding); Remove the excess silicon substrate of the TSV interposer to obtain Module 2. Construct a complete RDL layer on the bottom of Module 2, and fabricate bumps on the surface of the complete RDL layer.

[0008] It should be noted that in the above technical solution: 1) During plastic encapsulation, the plastic encapsulation layer only wraps a part of the copper pillar bumps of the chip, and the remaining part is embedded in the adhesive layer. In this way, the plastic encapsulation layer can protect the cylindrical surface of the copper pillar bumps, avoiding moisture erosion and metal migration. 2) After peeling off the adhesive layer, a non-metallic dielectric material is deposited to modify the copper pillar bumps, which can protect the cylindrical surface of the copper pillar bumps. 3) The remaining exposed surfaces of the copper pillar bumps are copper-copper bonded to the TSV interposer, which can also be regarded as the formation of copper-copper bonding between Module 1 and Module 2.

[0009] Regarding the copper-copper bonding technology adopted by the present invention, compared with the micro-bump welding method used in the traditional CoWoS-S process, it avoids problems such as uneven heating, depression or protrusion of the welded parts caused by solder or solder paste reflow welding, and improves the flatness and electrical connection reliability of the bonding interface. The preparation method of the present invention improves the welding reliability, signal integrity and heat dissipation performance.

[0010] In one embodiment, the steps of temporary bonding include: using a bonding machine to symmetrically arrange every two HBM Dies on both sides of an SOC Die, with the surfaces of the copper pillar bumps of the HBM Die and the SOC Die facing downwards and bonded to the adhesive layer, and controlling the depth of the copper pillar bumps embedded in the adhesive layer to be 2-3 μm; wherein, the total number of HBM Dies ≥ 2, and the total number of SOC Dies ≥ 1.

[0011] In one embodiment, there are copper pillar bumps on the metal pads of the SOC Die, the height of the copper pillar bumps is 4-8 μm, and the width of the copper pillar bumps is 5-25 μm; there are copper pillar bumps on the metal pads of the HBM Die, the height of the copper pillar bumps is 4-8 μm, and the width of the copper pillar bumps is 5-25 μm.

[0012] In one embodiment, the preparation method of the TSV interposer includes the following steps: Using an anisotropic etching process to make deep holes in the horizontal and vertical directions on the silicon substrate, and the vertical deep holes are connected through the horizontal deep holes; Deposit an insulating layer in the deep holes of the silicon substrate, deposit a barrier layer on the insulating layer, then deposit or not deposit a seed layer, electroplate and fill the metal material in the deep holes, and remove the excess metal material on the surface of the silicon substrate; then use the RDL process on the surface of the silicon substrate. Specifically, deposit an insulating material on the surface of the silicon substrate, then coat a photoresist on the insulating material, expose and develop to form an RDL circuit pattern, sputter deposit and / or electroplate metallic copper in the RDL circuit pattern to form an interconnection line, form an intermediate connection layer, and strip the photoresist to obtain the TSV interposer.

[0013] Further, when electroplating and filling a metal material in a deep hole, the metal material includes copper; when performing copper-copper bonding on the remaining exposed surface of the copper pillar bump and the TSV interposer, the exposed surface is bonded to the intermediate connection layer by copper-copper bonding.

[0014] In one embodiment, removing the redundant silicon substrate of the TSV interposer includes the following steps: Using a grinder to thin the thickness d1 of the redundant silicon substrate to 3 - 10 μm, then etching the bottom of the silicon substrate with an etching process to expose a part of the deep hole wrapped by the silicon substrate, the thickness of the deep hole exposed outside is 1 - 5 μm, then using the PECVD process to deposit a non-metallic dielectric material on both sides of the exposed deep hole, and then using the CMP process to planarize the bottom of the silicon substrate.

[0015] Optionally, the non-metallic dielectric material includes at least one of silicon nitride and silicon dioxide.

[0016] In one embodiment, constructing a complete RDL layer at the bottom of Module 2 includes the following steps: Forming a passivation layer at the bottom of Module 2, covering the passivation layer with a mask, exposing it, dissolving the passivation layer outside the mask, leaving a designed pattern on Module 2, sputtering a titanium and copper layer on the designed pattern to form a PVD layer, and the PVD layer and the remaining passivation layer constitute the first RDL layer; Forming a photoresist layer on the first RDL layer, covering the photoresist layer with a mask, exposing it, dissolving the photoresist layer outside the mask, leaving a designed pattern on the first RDL layer, electroplating copper on the designed pattern to form a conductive circuit; Removing the remaining photoresist, retaining the conductive circuit formed by electroplating, etching away the unnecessary conductive circuit, only retaining the conductive circuit connected to the PVD layer, creating a vacant gap after etching, and forming a protective layer in the gap, and the conductive circuit and the protective layer constitute the second RDL layer; The first RDL layer and the second RDL layer together constitute a complete RDL layer.

[0017] In one embodiment, the parameters of the temporary bonding include: the initial contact pressure is 0.5 - 1.0 MPa, the copper pillar bumps are in contact with the adhesive layer but not embedded; the pressure in the embedding stage is 2.5 - 3.5 MPa, and a part of the copper pillar bumps in the control part are embedded in the adhesive layer; the pressure holding time is 8 - 15 seconds.

[0018] In one embodiment, the encapsulation uses a molding compound, and the preparation of the molding compound includes the following steps: Mixing bisphenol F type epoxy resin and an active diluent evenly to obtain a resin mixture; Mixing large-size silica, small-size silica, and nanoparticles evenly to obtain a mixed powder; Slowly add the resin mixture into the mixed powder and stir to obtain a mixture; Add an antifoaming agent and a leveling agent to the mixture and stir to obtain a mixed solution; Slowly add a curing agent to the mixed solution, stir, and perform vacuum degassing to obtain a molding compound; Among them, the particle size of the large-size silica is 10 - 20 μm, the particle size of the small-size silica is 0.1 - 0.5 μm, and the reactive diluent includes a silicone oligomer.

[0019] Furthermore, by weight, the addition amount of the large-size silica is 50 - 70 parts, the addition amount of the small-size silica is 10 - 15 parts, and the addition amount of the nanoparticles is 1 - 10 parts.

[0020] Optionally, the particle size of the nanoparticles is 50 - 100 nm. The nanoparticles include α-phase nano silicon nitride particles.

[0021] The beneficial effects of the present invention are: The structure of the present invention has a higher transmission rate: Compared with traditional microbump welding, Cu-Cu bonding has lower resistance and inductance, enabling a higher data transmission rate.

[0022] The structure of the present invention has a higher I / O density: Cu-Cu bonding can achieve a smaller bonding pitch, thus supporting a higher I / O density.

[0023] The structure of the present invention has better reliability: Cu-Cu bonding has a higher bonding strength and better thermal cycling performance, improving the long-term reliability of the chip.

[0024] The structure of the present invention has better thermal performance: Cu-Cu bonding has a lower thermal resistance, which helps the chip dissipate heat.

[0025] Specifically, directly bond the exposed surface of the chip copper pillar bump to the intermediate connection layer of the TSV interposer. The TSV interposer does not need to additionally fabricate copper pillars or microbumps, simplifying the process flow, reducing the manufacturing cost, and at the same time improving the bonding accuracy and interconnection density.

[0026] Furthermore, in the plastic encapsulation step, the molding compound wraps the exposed copper pillar bumps, which not only serves as a protective material to prevent copper metal migration but also protects the side surfaces of the copper pillar bumps from oxidation, further enhancing the long-term reliability of the packaging structure.

[0027] After peeling off the adhesive layer, deposit silicon nitride and silicon dioxide on the exposed surface of the copper pillar bumps, forming a three-layer protection structure (plastic encapsulation layer, silicon nitride, silicon dioxide) on both sides of the copper pillar bumps, effectively protecting the side surfaces of the copper pillar bumps from oxidation and metal migration, while retaining the exposed surface of the copper pillar bumps for subsequent bonding.

[0028] In the RDL process, through multi-layer redistribution lines (the first RDL layer and the second RDL layer), the efficient reconstruction and distribution of circuits are achieved, significantly improving the flexibility of signal transmission and the integration density.

[0029] Furthermore, during the preparation of Module 1, the present invention also provides chip bonding parameters to ensure that the depth of the copper pillar bumps embedded in the adhesive layer is precisely controlled within 2 - 3 μm, avoiding the offset or uneven embedding of the copper pillar bumps caused by instantaneous high voltage, thereby improving the position stability and structural reliability of the chip during the plastic encapsulation process.

[0030] The present invention also provides a molding compound formulation to further improve the quality of the plastic encapsulation layer. The molding compound uses a bisphenol F-type epoxy resin with low viscosity and high reactivity, combined with an active diluent (siloxane oligomer), which reduces the viscosity of the resin system, improves fluidity, effectively fills small gaps and reduces bubble generation. An efficient defoaming agent and a leveling agent are added. The defoaming agent quickly eliminates bubbles during the mixing and potting processes, and the leveling agent improves fluidity and reduces surface defects, thereby ensuring that there are no bubble defects inside the plastic encapsulation layer, improving the mechanical strength and electrical performance of the encapsulation structure. Multi-stage composite fillers (large-size silica, small-size silica, and nano-sized silicon nitride particles) are used to optimize the packing density of the fillers, reduce the coefficient of thermal expansion, enhance the toughness and impact resistance of the molding compound, and further improve the reliability of the encapsulation structure. BRIEF DESCRIPTION OF THE DRAWINGS

[0031] To more clearly illustrate the technical solutions of the embodiments of the present invention, the following will briefly introduce the drawings required for the description of the embodiments. Obviously, the drawings in the following description are only some embodiments of the present invention. For those of ordinary skill in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0032] Figure 1 It is a schematic structural diagram of the steps for preparing Module 1 in Embodiment 1 of the present invention; Figure 2 It is a schematic structural diagram of the steps for preparing Module 1 in Embodiment 1 of the present invention; Figure 3 It is a schematic structural diagram of the steps for preparing Module 1 in Embodiment 1 of the present invention; Figure 4 It is a schematic structural diagram of the stripping step in Embodiment 1 of the present invention; Figure 5 It is a schematic structural diagram of the hybrid bonding step in Embodiment 1 of the present invention; Figure 6 It is a schematic structural diagram of the process step for exposing the bonding vias in Embodiment 1 of the present invention; Figure 7It is a schematic structural diagram of the RDL process step in Embodiment 1 of the present invention; Figure 8 It is a schematic structural diagram of the RDL process step in Embodiment 1 of the present invention; Figure 9 It is a schematic structural diagram of the bump process step in Embodiment 1 of the present invention; The markings in the figure are: 1. Substrate; 2. Release layer; 3. Adhesive layer; 4. SOC Die; 5. HBM Die; 6. Encapsulation layer; 7. Module 1; 8. Exposed surface; 9. TSV interposer; 10. Deep hole; 11. Intermediate connection layer; 12. Module 2; 13. PVD layer; 14. First RDL layer; 15. Conductive circuit; 16. Second RDL layer; 17. Complete RDL layer; 18. Bump.

[0033] Figures 1-9 Together they form a flowchart for preparing a multi-chip connection structure. Detailed implementation mode

[0034] The following further elaborates on the preparation method of the multi-chip connection structure proposed by the present invention in conjunction with the accompanying drawings and specific embodiments. According to the following description and claims, the advantages and features of the present invention will be clearer. It should be noted that the drawings are all in a very simplified form and use non-precise scales, only for conveniently and clearly assisting in explaining the purpose of the embodiments of the present invention.

[0035] In the description of the present invention, it should be noted that unless otherwise clearly specified and limited, the terms "connected" and "connected" should be understood in a broad sense. For example, it can be a fixed connection, a detachable connection, or an integral connection; it can be a mechanical connection or an electrical connection; it can be directly connected or indirectly connected through an intermediate medium, and it can also be the communication inside two components. It can be a wireless connection or a wired connection. For those of ordinary skill in the art, the specific meanings of the above terms in the present invention can be understood according to specific situations.

[0036] If not otherwise specified, the materials used in the embodiments can be easily obtained from commercial companies.

[0037] Hereinafter, the SOC (System on Chip) Die (bare chip) and HBM (High Bandwidth Memory) Die (bare chip) will be directly named in English without repeating the Chinese annotations. The chips (SOC Die and HBM Die) used in the present invention can be obtained by regular purchase, and their specific mechanisms are also well-known to those skilled in the art and will not be elaborated here.

[0038] The preparation method of the multi-chip connection structure refers to Figures 1-9, the specific steps are as follows: 1. Preparation of Module 1: Fabrication of the release layer 2 and the adhesive layer 3: Refer to Figure 1 , select a glass substrate as the base material 1, coat a layer of release material on the base material 1 to form the release layer 2, and coat a layer of adhesive material on the release layer 2 to form the adhesive layer 3. Among them, the release material includes but is not limited to photosensitive materials and thermal release tapes. The adhesive material includes but is not limited to chip temporary bonding materials and temporary adhesive films.

[0039] Select chips: Select chips, including SOC Die 4 and HBM Die 5. There are copper pillar bumps on the metal pads of SOC Die 4. The height of the copper pillar bumps is 4 - 8 μm, and the width is 5 - 25 μm. The copper pillar bumps of SOC Die 4 are electrically connected to the circuits inside SOC Die 4.

[0040] There are also copper pillar bumps on the metal pads of HBM Die 5. The height of the copper pillar bumps is 4 - 8 μm, and the width is 5 - 25 μm. To ensure a high production process yield, the height and width of HBM Die 5 need to be the same as those of SOC Die 4. The copper pillar bumps of HBM Die 5 are electrically connected to the circuits inside HBM Die 5.

[0041] Die bond: Refer to Figure 2 , use the die bonding process to temporarily bond HBM Die 5 and SOC Die 4 on the adhesive layer 3. The specific quantity and layout can be: use a bonder to symmetrically arrange every two HBM Die 5 on both sides of a SOC Die 4. The side with the copper pillar bumps of HBM Die 5 and SOC Die 4 faces down and is bonded to the adhesive layer 3. Control the depth of the copper pillar bumps embedded in the adhesive layer 3 to be 2 - 3 μm for subsequent encapsulation. Among them, the total number of HBM Die 5 ≥ 2, and the total number of SOC Die 4 ≥ 1.

[0042] Encapsulation: Refer to Figure 3 , use a molding compound to encapsulate HBM Die 5 and SOC Die 4, and form an encapsulation layer 6 on the adhesive layer 3. The encapsulation layer 6 contains HBM Die 5 and SOC Die 4. HBM Die 5, SOC Die 4, and the encapsulation layer 6 together constitute Module 1 7. During encapsulation, the molding compound also wraps the copper pillar bumps that are exposed and not embedded in the adhesive layer 3. The function is that the molding compound can be used as a protective material for the copper pillar bumps to avoid copper metal migration and can also protect the sides of the copper pillar bumps to prevent oxidation.

[0043] Grinding: This step is an optional step. Using the grinding process, the surface of the encapsulation layer 6 is ground and flattened using a precision grinder.

[0044] 2. Stripping: Refer to Figure 4 , strip the adhesive layer 3, and use the debonding process to remove the adhesive layer 3 connected to the module 1 7. Remove it according to the characteristics of the adhesive material, such as thermal sliding removal, laser depolymerization, or solvent-assisted stripping, and perform debonding according to the instructions of the adhesive material. After the adhesive layer 3 is removed, the corresponding release layer 2 and the substrate 1 are also removed. After the adhesive layer 3 is debonded, clean the surface of the module 1 7 to remove the residues of the debonding process, and dry it after cleaning.

[0045] After stripping the adhesive layer 3, the copper pillar bumps embedded in the adhesive layer 3 in the early stage are exposed, so that a part of the copper pillar bumps of the chip is inside the encapsulation layer 6 and a part is outside the encapsulation layer 6.

[0046] 3. Modify the copper pillar bumps of the chip: Refer to Figure 4 , deposit a non-metallic dielectric material on the side of the module 1 7 with copper pillar bumps to modify the copper pillar bumps. Using PECVD (Plasma Enhanced Chemical Vapor Deposition) technology, at the bottom of the encapsulation layer 6, that is, on the side with copper pillar bumps, first deposit silicon nitride (SiNx), and the deposition thickness of silicon nitride is 250 - 2000 Å. Deposit silicon dioxide (SiO2) on the silicon nitride, and the deposition thickness of SiO2 is 5000 - 30000 Å. Then use CMP (Chemical Mechanical Polishing) technology to grind the thickness of SiO2 to 3000 - 18000 Å. Among them, 1 Å = 1×10^(-10) meters.

[0047] After that, the two sides of the copper pillar bumps of the chip are no longer exposed, and there is a three-layer structure on both sides of the copper pillar bumps of the chip. From top to bottom, the first layer is the encapsulation layer 6, the second layer is silicon nitride, and the third layer is SiO2. Figure 4 Silicon nitride and SiO2 are not drawn in

[0048] The surface where the bottom of the copper pillar bump is located is not covered and is exposed. For the convenience of description, this place is named the exposed surface 8, and the structure of the exposed surface 8 is convenient for subsequent bonding.

[0049] 4. Hybrid bond: Refer to Figure 5, connect Module 1 7 and the TSV interposer 9. Specifically, take out the TSV interposer 9. The preparation method of the TSV interposer 9 is as follows: Use a dry etching process, that is, an anisotropic etching process, to fabricate deep holes 10 in the horizontal and vertical directions on the silicon substrate. The vertical deep holes 10 are connected through the horizontal deep holes 10. To accurately etch the deep holes 10 and avoid the etching of unnecessary sidewalls, the sidewalls can be passivated while etching. That is, first use plasma to etch a section of the deep hole 10 on the silicon substrate, and then use a passivation gas (such as silane gas) to deposit a thin insulating material, such as silicon dioxide, on the sidewalls of the deep hole 10 to form a passivation layer. Then switch the plasma to continue etching the next section of the deep hole 10 in a specific direction. In this way, it is also possible to maintain a sufficient etched hole diameter and depth.

[0050] To ensure that a passivation layer is formed in all the deep holes 10, after etching, deposit a thin insulating material, such as silicon dioxide, in the deep holes 10 of the silicon substrate to form an insulating layer. Deposit Ti (titanium) or TiN (titanium nitride) as a barrier layer on the insulating layer, and then electroplate and fill the metal material in the deep holes 10. The metal material is copper. If other metal materials are selected, a copper seed layer can be deposited on the barrier layer, and then electroplated and filled with the metal material.

[0051] Then, chemical mechanical polishing (CMP) is used to remove the excess metal material used for electroplating on the surface of the silicon substrate. Then, on the surface of the silicon substrate, using the RDL (Redistribution Layer) process, deposit an insulating material on the surface of the silicon substrate. The insulating material includes silicon nitride (SiNx), silicon dioxide, and NDC (silicon carbide thin film). Then, apply a photoresist on the insulating material, expose it with a lithography machine, and develop it to form an RDL circuit pattern. Sputter deposit and / or electroplate metallic copper in the RDL circuit pattern to fabricate interconnecting lines and form an intermediate connection layer 11. The intermediate connection layer 11 is electrically connected to the metal material in the deep holes 10. Subsequently, strip the photoresist and clean the excess residues. After the foregoing steps, the TSV interposer 9 is prepared.

[0052] Then, the exposed surface 8 of the chip copper pillar bump is connected to the intermediate connection layer 11 in a Cu-Cu bonding (copper-copper bonding) manner. Copper-copper bonding belongs to metal-metal bonding. Under certain bonding process conditions, copper atoms diffuse into each other to achieve interconnection bonding. Specifically: using a bonding machine, align the exposed surface 8 of the copper pillar bumps of the HBM Die 5 and the SOC Die 4 with the intermediate connection layer 11 of the TSV interposer 9, and interconnect the copper pillar bumps and the intermediate connection layer 11 through thermocompression bonding or low-temperature bonding. Among them, if thermocompression bonding is selected, the bonding parameters are 250-400 °C, 5-50 MPa, and 5-30 minutes under nitrogen protection. Copper atoms diffuse under high temperature and high pressure to form an intermetallic eutectic connection. If low-temperature bonding is selected, first use formic acid vapor or formic acid solution to pretreat the surface to be bonded to increase the surface roughness and reduce the bonding temperature, and then bond. The bonding parameters are 150-250 °C, 10-20 MPa, and 10-60 minutes.

[0053] It should be noted that in the prior art, in CoWoS-S (chip on a substrate wafer with a silicon interposer), the microbump (uBump) soldering method is usually used, and solder or solder paste is used to reflow solder the chip to the TSV interposer 9, which is prone to problems such as uneven heating, depression and protrusion of the welded parts. Different from the prior art, the present invention does not additionally fabricate copper pillars and microbumps on the TSV interposer 9. The present invention uses the intermediate connection layer 11 made of copper and the copper pillar bumps of the HBM Die 5 and the SOC Die 4 to achieve copper-copper bonding.

[0054] 5. Bonding Via Reveal (BVR) process: Refer to Figure 5 and Figure 6 , perform grinding, dry etching process, PECVD (Plasma Enhanced Chemical Vapor Deposition), and CMP (Chemical Mechanical Polishing) on the bottom of the TSV interposer 9. Through the foregoing processes, the excess silicon substrate at the bottom of the TSV interposer 9 can be ground off. If all the excess silicon substrate is directly removed by the grinding process, multiple problems are likely to occur, such as: 1) Cracks and fractures: Grinding, as a mechanical process, is likely to introduce local stress in brittle silicon materials, resulting in microcracks or edge fractures, reducing the structural integrity and long-term reliability. 2) Lattice damage: Grinding may damage the lattice structure of the silicon surface, forming a defective layer, affecting the carrier mobility, increasing the leakage current, and reducing the device performance. 3) Uneven thickness: Grinding is difficult to precisely control the removal amount of the silicon substrate, which may lead to inconsistent TSV heights, affecting the alignment and interconnection quality of three-dimensional integration.

[0055] The lateral and longitudinal deep hole 10 structures constructed in the previous step of this application are complex. To avoid the above problems, a single grinding process cannot be directly used to remove all the excess silicon substrate.

[0056] Therefore, a multi-process combination is adopted here to remove the redundant silicon substrate, specifically as follows: Use a grinding machine to grind the bottom of the silicon substrate, that is, the side not in contact with Module 7, and reduce the bottom thickness d1 of the silicon substrate to 3 - 10 μm. Here, d1 is the thickness from the deep hole 10 to the bottom surface of the silicon substrate. Then use the dry etching process to etch the bottom of the silicon substrate, exposing a part of the deep hole 10 wrapped by the silicon substrate. The thickness of the exposed part of the deep hole 10 is 1 - 5 μm. The purpose of this is to expose the copper electroplated in the deep hole 10.

[0057] Then use the PECVD (Plasma Enhanced Chemical Vapor Deposition) process to deposit silicon nitride (SiNx) on both sides of the exposed deep hole 10 first, and deposit silicon dioxide on the silicon nitride, so as to protect the copper electroplated in the deep hole 10, and both sides of it are no longer exposed.

[0058] Then use CMP (Chemical Mechanical Polishing) to planarize the bottom of the silicon substrate, removing the redundant copper and silicon dioxide.

[0059] After the above steps, all the redundant silicon substrates are removed, and a TSV interposer 9 with appropriate thickness is prepared. For the convenience of description, it is named Module 12.

[0060] 6. RDL (Redistribution Layer) process: Refer to Figure 7 and Figure 8 , and use the RDL process to rewire on the bottom of Module 12, specifically as follows: Glue coating: Coat polyimide (PI) on the bottom of Module 12 as a passivation layer to provide electrical insulation and mechanical protection.

[0061] Exposure: Use a mask to cover the passivation layer and expose it, and transfer the pattern designed on the mask to the passivation layer by using light.

[0062] Development: Use a developer to dissolve the passivation layer outside the mask, so as to leave the designed pattern on Module 12. Here, the developer includes TMAH (tetramethylammonium hydroxide) or other developers.

[0063] Physical Vapor Deposition (PVD): On the developed surface, sputter titanium (Ti) and copper (Cu) layers on the designed pattern to form a PVD layer 13. Here, titanium is used as an adhesion layer to prevent copper diffusion, and copper is used as an electroplating seed layer. In this way, the PVD layer 13 and the remaining passivation layer constitute the first RDL layer 14. The PVD layer 13 is electrically connected to the deep hole 10. Thus, the Figure 7 structure is obtained.

[0064] Then repeat the above steps: Glue application: Spin-coat photoresist on the surface of the first-layer RDL layer 14 to form a photoresist layer.

[0065] Second exposure: Cover the photoresist layer with a mask plate and expose it. Use light to transfer the designed pattern on the mask plate to the photoresist layer.

[0066] Second development: Dissolve the photoresist layer outside the mask plate with a developer, so as to leave the designed pattern on the first-layer RDL layer 14. Among them, the developer includes TMAH (tetramethylammonium hydroxide) or other developers.

[0067] Electroplating: On the surface after the second development, electroplate copper on the designed pattern to form a conductive circuit 15.

[0068] Desizing: Remove the excess photoresist with a chemical stripping solution, and retain the conductive circuit 15 formed by electroplating.

[0069] Etching: Etch away the unnecessary wire circuits 15, and only retain the conductive circuits 15 connected to the PVD layer 13. Vacant gaps will be generated after etching, and a protective material can be filled or coated in the gaps to form a protective layer. The protective material can be polyimide (PI) to ensure the reliability of the overall structure.

[0070] In this way, the conductive circuit 15 formed by electroplating and the protective layer constitute the second-layer RDL layer 16.

[0071] The first-layer RDL layer 14 and the second-layer RDL layer 16 together constitute the complete RDL layer 17, thus realizing the reconstruction and distribution of the circuit. In this way, the Figure 8 obtained structure.

[0072] 7. Bump process: Refer to Figure 9 , and use the C4 bump process to fabricate bumps 18 on the surface of the complete RDL layer 17. The bumps 18 need to be electrically connected to the complete RDL layer 17, that is, the bumps 18 are electrically connected to the conductive circuits 15, so as to realize the connection of the circuits.

[0073] In Example 1, when preparing Module 1 7, in the step of encapsulation molding, the molding compound also wraps the copper pillar bumps that are exposed and not embedded in the adhesive layer 3.

[0074] To achieve such a structure, it is necessary to control the depth of the chip embedded in the adhesive layer 3. Example 1 states that the depth of the copper pillar bumps embedded in the adhesive layer 3 is controlled to be 2 - 3 μm, which is convenient for subsequent encapsulation molding.

[0075] However, it is also necessary to control the parameters of chip bonding, as well as select the material of the molding compound and the parameters of encapsulation molding to ensure that no bubbles are generated in the encapsulation layer 6 and the chip will not be displaced by impact.

[0076] Therefore, these parameters are provided in the following examples.

[0077] Example 2 In this example, specific parameters for chip bonding are provided: Hierarchical control of bonding pressure: The initial contact pressure is 0.5 - 1.0 MPa to ensure that the copper pillar bumps contact but do not embed into the adhesive layer 3; The pressure during the embedding stage: 2.5 - 3.5 MPa, controlling the depth of the copper pillar bumps embedded into the adhesive layer 3 to be 2 - 3 μm; The pressure holding time: 8 - 15 seconds to avoid excessive deformation of the adhesive layer 3.

[0078] The rest is the same as in Example 1.

[0079] It should be noted that the hierarchical pressure can prevent the copper pillar bumps from shifting or being unevenly embedded due to instantaneous high pressure.

[0080] Example 3 In this example, a specific molding compound is provided. By weight, the preparation of the molding compound includes the following steps: Take 22 parts of bisphenol F type epoxy resin and 6 parts of reactive diluent and put them into a container, magnetically stir at 300 - 500 rpm for 15 - 20 minutes at room temperature, mix evenly to obtain a resin mixture.

[0081] Take 50 parts of large - sized silica with a particle size of 10 - 20 μm, 10 parts of small - sized silica with a particle size of 0.1 - 0.5 μm, and 2 parts of nanoparticles with a particle size of 50 - 100 nm. Add these three powders into a high - speed mixer and dry - mix for 5 - 10 minutes, mix evenly to obtain a mixed powder.

[0082] Slowly add the resin mixture to the mixed powder, stir while adding, disperse at 1000 - 1500 rpm for 10 - 15 minutes, gradually increase the rotation speed to 2000 - 2500 rpm, and continue to disperse for 15 - 20 minutes to obtain a mixture.

[0083] In the mixture, add 0.3 part of defoaming agent and 0.2 part of leveling agent in sequence, and continue to stir at a speed of 1500 rpm for 5 minutes to obtain a mixed solution. Among them, the defoaming agent can reduce the bubbles in the molding compound. The leveling agent can improve the fluidity of the molding compound.

[0084] Before use, slowly add 9.5 parts of modified amine curing agent to the mixed solution, stir at 1000 rpm for 10 minutes, and then perform vacuum degassing: under the condition of a vacuum degree of - 0.095 MPa, stir and degas at a speed of 800 rpm for 15 minutes to remove the bubbles in the mixture and obtain the molding compound.

[0085] In the above, the specific selection of raw materials used in this example is: Bisphenol F type epoxy resin: epoxy equivalent 160 - 180 g / eq, viscosity 3000 - 4000 cps (25℃), Taiwan South Asia NPEF-170 bisphenol F type epoxy resin can be selected; Reactive diluent: silicone oligomer, Evonik TEGOPREN®6875; Large-size silica: spherical, ADMAFINE®SO-E5, Admatechs; Small-size silica: spherical, Admatechs®SO-C3, Admatechs; Nanoparticles: α-phase nano silicon nitride particles (Si3N4), particle size 50 - 100 nm, silicon content 99%; Defoamer: BYK-A 530, BYK; Leveling agent: BYK-354, BYK; Modified amine curing agent: Huntsman Aradur 2958.

[0086] Furthermore, it is worth noting that (1) Resin system: Main resin: Bisphenol F type epoxy resin with low viscosity and high reactivity is used. Compared with traditional bisphenol A type epoxy resin, the selected bisphenol F type resin has lower viscosity, better fluidity and faster curing speed, which is beneficial to filling small gaps and reducing bubble generation.

[0087] Reactive diluent: A small amount of silicone oligomer with epoxy functional groups is added. The selected silicone oligomer can not only reduce the viscosity of the resin system and improve fluidity, but also react with epoxy resin to form a certain flexible silicone chain segment, improving the toughness and impact resistance of the molding compound.

[0088] (2) Multi-stage composite filler: Fillers with different sizes and functions are combined. The large-size silica is the large-size silica, used as the main filler, with a particle size of 10 - 20 μm and a weight fraction of 50 - 70 parts. It provides a low coefficient of thermal expansion and a high filling amount. The small-size silica is submicron spherical silica, with a particle size of 0.1 - 0.5 μm and a weight fraction of 10 - 15 parts. It fills the gaps between large particles, improves the packing density and reduces the viscosity. The nanoparticles are α-phase nano silicon nitride (Si3N4) particles, dispersed in the matrix, with high surface activity and forming strong chemical bonds with the matrix, thus improving the interfacial strength.

[0089] (3) Additives: The defoamer selects a highly efficient silicone defoamer, which can quickly eliminate the bubbles generated during mixing and potting. The leveling agent selects an acrylate leveling agent that can improve fluidity and reduce surface defects.

[0090] (4) Curing agent: Use a modified amine curing agent with low viscosity and high reactivity. This curing agent can cure quickly at a relatively low temperature, reducing shrinkage and stress during the curing process.

[0091] (5) The cured molding compound forms a multiphase composite structure: Continuous phase: A polymer network formed by crosslinking of epoxy resin, reactive diluent and curing agent.

[0092] Dispersed phase: Large-sized spherical silica particles are uniformly distributed in the matrix. Small-sized silica fills the voids between the large particles. Core-shell nanoparticles are dispersed in the matrix and form strong chemical bonds with the matrix.

[0093] Obviously, the above embodiments are merely examples given for clear illustration and are not limitations on the implementation manners. For those of ordinary skill in the art, other different forms of changes or modifications can be made based on the above description. It is not necessary and impossible to list all implementation manners here. And the obvious changes or modifications derived therefrom are still within the protection scope of the present invention.

Claims

1. A method for preparing a multi-chip connection structure, characterized in that, It includes the following steps: Coat a release layer on the substrate, and coat an adhesive layer on the release layer; The chip includes an SOC Die and an HBM Die. There are copper pillar bumps on the chip. Temporarily bond the chip to the adhesive layer, and control part of the copper pillar bumps to be embedded in the adhesive layer; Form a molding compound layer on the adhesive layer. The molding compound layer wraps the chip and the remaining copper pillar bumps. The chip and the molding compound layer together form Module 1; Peel off the adhesive layer, and the copper pillar bumps embedded in the adhesive layer are exposed. Deposit a non-metallic dielectric material on the side of Module 1 with copper pillar bumps to modify the copper pillar bumps, so that both sides of the copper pillar bumps are no longer exposed. Bond the remaining exposed surfaces of the copper pillar bumps to the TSV interposer by copper-copper bonding; Remove the excess silicon substrate of the TSV interposer to obtain Module 2. Construct a complete RDL layer on the bottom of Module 2, and fabricate bumps on the surface of the complete RDL layer.

2. The manufacturing method of the multi-chip connection structure according to claim 1, characterized in that The steps of temporary bonding include: using a bonder to symmetrically arrange every two HBM Dies on both sides of an SOC Die. The side of the copper pillar bumps of the HBM Die and the SOC Die faces downward and is bonded to the adhesive layer. Control the depth of the copper pillar bumps embedded in the adhesive layer to be 2 - 3μm; among them, the total number of HBM Dies ≥ 2, and the total number of SOC Dies ≥ 1.

3. The preparation method of the multi-chip connection structure according to claim 1, wherein, There are copper pillar bumps on the metal pads of the SOC Die. The height of the copper pillar bumps is 4 - 8μm, and the width of the copper pillar bumps is 5 - 25μm; there are copper pillar bumps on the metal pads of the HBM Die. The height of the copper pillar bumps is 4 - 8μm, and the width of the copper pillar bumps is 5 - 25μm.

4. The manufacturing method of the multi-chip connection structure according to claim 1, characterized in that, The preparation method of the TSV interposer includes the following steps: Use an anisotropic etching process to fabricate deep holes in the horizontal and vertical directions on the silicon substrate. The vertical deep holes are connected through the horizontal deep holes; Deposit an insulating layer in the deep holes of the silicon substrate, deposit a barrier layer on the insulating layer, and then deposit or not deposit a seed layer. Electroplate and fill a metal material in the deep holes, and remove the excess metal material on the surface of the silicon substrate; then use the RDL process on the surface of the silicon substrate. Specifically, deposit an insulating material on the surface of the silicon substrate, then coat a photoresist on the insulating material, expose, develop to form an RDL circuit pattern, sputter deposit and / or electroplate metallic copper in the RDL circuit pattern to form interconnecting lines, form an intermediate connection layer, and peel off the photoresist to obtain the TSV interposer.

5. The manufacturing method of the multi-chip connection structure according to claim 4, wherein, When electroplating and filling a metal material in the deep holes, the metal material includes copper; when bonding the remaining exposed surfaces of the copper pillar bumps to the TSV interposer by copper-copper bonding, this exposed surface is bonded to the intermediate connection layer by copper-copper bonding.

6. The manufacturing method of the multi-chip connection structure according to claim 1, characterized in that Removing the excess silicon substrate of the TSV interposer includes the following steps: Use a grinder to thin the thickness d1 of the excess silicon substrate to 3 - 10μm, and then use an etching process to etch the bottom of the silicon substrate to expose a part of the deep holes wrapped by the silicon substrate. The thickness of the deep holes exposed outside is 1 - 5μm. Then use the PECVD process to deposit a non-metallic dielectric material on both sides of the exposed deep holes, and then use the CMP process to planarize the bottom of the silicon substrate.

7. The manufacturing method of the multi-chip connection structure according to claim 1 or claim 6, characterized in that, The non-metallic dielectric material includes at least one of silicon nitride and silicon dioxide.

8. The manufacturing method of the multi-chip connection structure according to claim 1, characterized in that, Constructing a complete RDL layer on the bottom of Module 2 includes the following steps: A passivation layer is formed at the bottom of Module 2. A mask is used to cover the passivation layer, followed by exposure. The passivation layer outside the mask is dissolved, leaving a designed pattern on Module 2. A titanium and copper layer is sputtered on the designed pattern to form a PVD layer. The PVD layer and the remaining passivation layer constitute the first RDL layer; A photoresist layer is formed on the first RDL layer. A mask is used to cover the photoresist layer, followed by exposure. The photoresist layer outside the mask is dissolved, leaving a designed pattern on the first RDL layer. Copper is electroplated on the designed pattern to form a conductive circuit; The remaining photoresist is removed, leaving the conductive circuit formed by electroplating; The unnecessary conductive circuits are etched away, leaving only the conductive circuits connected to the PVD layer. Vacant voids are generated after etching, and a protective layer is formed in the voids. The conductive circuits and the protective layer constitute the second RDL layer; The first RDL layer and the second RDL layer together constitute the complete RDL layer.

9. The preparation method of the multi-chip connection structure according to claim 1, characterized in that, The parameters of the temporary bonding include: the initial contact pressure is 0.5 - 1.0 MPa, and the copper pillar bumps are in contact with the bonding layer but not embedded; the pressure during the embedding stage is 2.5 - 3.5 MPa, and the copper pillar bumps in the control part are embedded in the bonding layer; the holding pressure time is 8 - 15 seconds.

10. The manufacturing method of the multi-chip connection structure according to claim 1, wherein, The encapsulation uses a molding compound, and the preparation of the molding compound includes the following steps: Bisphenol F type epoxy resin and an active diluent are mixed evenly to obtain a resin mixture; Large-sized silica, small-sized silica, and nanoparticles are mixed evenly to obtain a mixed powder; The resin mixture is slowly added to the mixed powder and stirred to obtain a mixture; In the mixture, an antifoaming agent and a leveling agent are added and stirred to obtain a mixed solution; The curing agent is slowly added to the mixed solution, stirred, and degassed under vacuum to obtain the molding compound; Among them, the particle size of the large-sized silica is 10 - 20 μm, the particle size of the small-sized silica is 0.1 - 0.5 μm, and the active diluent includes a siloxane oligomer.

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