Semiconductor structure, forming method, packaging structure, device and electronic device
By setting the chip connection structure and protective layer on the chip bridge surface of the bridge chip, the problem of bridging chip is easily broken during the packaging process, and an efficient and low-cost packaging effect is achieved.
Patent Information
- Application Number
- CN202410084460.0
- Authority / Receiving Office
- CN · China
- Patent Type
- Applications(China)
- Current Assignee / Owner
- Filing Date
- 2024-01-19
- Publication Date
- 2025-07-22
AI Technical Summary
During the 2.5D packaging process, the bridge chip is prone to rupture due to its thin thickness, resulting in high packaging cost and low efficiency.
A chip connection structure and a protective layer are provided on the chip bridge surface of the bridge chip, and the protective layer covers the chip connection structure to prevent it from rupturing during the packaging process.
Improve packaging efficiency, reduce packaging costs, and keep the overall size of the packaging structure unchanged.
Smart Images
Figure CN120356887A_ABST
Abstract
Description
Technical Field
[0001] The present application relates to the field of semiconductor technology, and in particular, to a semiconductor structure, a forming method, a packaging structure, a device, and an electronic device. Background Art
[0002] As it becomes increasingly difficult to improve the semiconductor manufacturing process, the importance of advanced packaging technology has become more prominent and has become the key to continuing Moore's Law. Compared with traditional packaging technology, advanced packaging meets the market's requirements for high-performance, high-reliability, and low-cost electronic products to a certain extent.
[0003] 2.5D packaging is a relatively common advanced packaging technology. 2.5D packaging converts the connection between multiple chips and a printed circuit board into a "bridging" form. In 2.5D packaging, bridging chips are usually buried in the printed circuit board. The bridging chips serve as a bridge for connecting different chips and can achieve the connection between different chips. In related technologies, in order to reduce the size of the packaging structure, the thickness of the bridging chips is usually relatively thin. Therefore, during the packaging process, the bridging chips often break, which increases the packaging cost and reduces the packaging efficiency. Summary of the Invention
[0004] In order to solve the above technical problems, the present application provides a semiconductor structure, a forming method, a device, and an electronic device.
[0005] In a first aspect, an embodiment of the present application discloses a semiconductor structure, which includes:
[0006] A bridging chip having a chip bridging surface;
[0007] A chip connection structure disposed on the chip bridging surface, and the chip connection structure is used to bridge at least two preset chips;
[0008] A protective layer covering the chip connection structure, and one end of the chip connection structure away from the chip bridging surface exposes the surface of the protective layer.
[0009] In a second aspect, an embodiment of the present application discloses a method for forming a semiconductor structure, and the method includes:
[0010] Providing a bridging chip wafer; the bridging chip wafer has opposite first and second surfaces;
[0011] Forming a chip connection structure on the first surface;
[0012] Forming a protective layer on the first surface; the protective layer covers the chip connection structure;
[0013] Performing a grinding process on the second surface so that the remaining thickness of the bridging chip wafer is a preset thickness, obtaining a semiconductor structure.
[0014] In a third aspect, an embodiment of the present application discloses a packaging structure, and the packaging structure includes the semiconductor structure as described above.
[0015] In a fourth aspect, an embodiment of the present application discloses an electronic device, and the electronic device includes the packaging structure as described above.
[0016] In a fifth aspect, an embodiment of the present application discloses an electronic apparatus, and the electronic apparatus includes the electronic device as described above.
[0017] The technical solution provided by the embodiment of the present application has the following technical effects:
[0018] For the semiconductor structure, formation method, packaging structure, device, and electronic apparatus described in the embodiments of the present application, by providing a chip connection structure and a protective layer on the chip bonding surface of the bridging chip, on the one hand, bridging between different preset chips can be achieved, and on the other hand, protection of the bridging chip can be realized to prevent it from cracking during the packaging process, thereby improving the packaging efficiency and reducing the packaging cost. Description of the Drawings
[0019] To more clearly illustrate the technical solutions and advantages in the embodiments of the present application or the prior art, the following will briefly introduce the drawings required for the description of the embodiments or the prior art. Obviously, the drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, other drawings can be obtained based on these drawings without creative efforts.
[0020] Figure 1 It is a schematic diagram of a bridging chip mounter.
[0021] Figure 2 It is a schematic diagram of a semiconductor structure provided by an embodiment of the present application.
[0022] Figure 3 It is a schematic flowchart of a method for forming a semiconductor structure provided by an embodiment of the present application.
[0023] Figures 4 - 6 It is a schematic diagram of the structure during the formation process of a semiconductor structure provided by an embodiment of the present application.
[0024] Figure 7 It is a schematic diagram of a packaging structure provided by an embodiment of the present application.
[0025] The following is a supplementary description of the drawings:
[0026] 10 - Chip mounter; 11 - SMT tool; 12 - Material film; 13 - Ejector pin; 20 - Semiconductor structure; 210 - Bridging chip; 220 - Chip connection structure; 230 - Protective layer; 240 - Bridging chip wafer; 250 - Chip mounting mucosa; 30 - Printed circuit board; 40 - Wiring board; 50 - Preset chip. Detailed implementation mode
[0027] The technical solutions in the embodiments of the present application will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present application. Obviously, the described embodiments are only a part of the embodiments of the present application, rather than all the embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present application without creative efforts shall fall within the protection scope of the present application.
[0028] It should be noted that the "one embodiment" or "embodiment" mentioned in the specification of the embodiments of the present application refers to a specific feature, structure or characteristic that can be included in at least one implementation manner of the present application. It should be understood that in the specification and claims of the embodiments of the present application and the above-mentioned drawings, the orientation or positional relationship indicated by terms such as "upper", "lower", "top", "bottom", etc. is based on the orientation or positional relationship shown in the drawings, and is only for the convenience of describing the present application and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation, and therefore cannot be understood as a limitation of the present application. The terms "first" and "second" are only used for descriptive purposes, and cannot be understood as indicating or implying relative importance or implicitly indicating the quantity of the indicated technical features. Thus, the features defined with "first" and "second" may explicitly or implicitly include one or more of such features. Moreover, the terms "first", "second", etc. are used to distinguish similar objects and do not have to be used to describe a specific order or sequence. It should be understood that such data can be interchanged under appropriate circumstances so that the embodiments of the present application described herein can be implemented in an order other than those illustrated or described herein. In addition, in the description of this embodiment, unless otherwise specified, the meaning of "a plurality" is two or more. In addition, the terms "comprising" and "having" and any variations thereof are intended to cover non-exclusive inclusion. For example, a process, method, system or product that includes a series of steps or units does not have to be limited to those steps or units clearly listed, but may include other steps or units not clearly listed or inherent to these processes, methods, products or devices.
[0029] In order to make the purpose, technical solutions and advantages of the embodiments disclosed in the present application clearer and more understandable, the following further details the embodiments of the present application with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the embodiments of the present application and are not used to limit the embodiments of the present application.
[0030] At present, as semiconductor manufacturing processes are gradually approaching the physical limit, the importance of advanced packaging has become increasingly prominent. During 2.5D packaging, bridging chips can be used to connect different chips, thus achieving the effect of one plus one equals two. To achieve better packaging effects, the size of the bridging chips is getting larger and the thickness is getting thinner, which often leads to cracking of the bridging chips during chip mounting. Figure 1 is a schematic diagram of a bridging chip mounter, as Figure 1 shown. To facilitate the storage and use of bridging chips, bridging chips are usually adhered to a film. When mounting a bridging chip, the ejector pin 13 on the machine table will lift the bridging chip from the film to achieve film peeling of the bridging chip, and then the chip mounting tool 11 on the machine table can suck up the bridging chip from the film 12, thereby mounting it. During the above process, due to the large size and thin thickness of the bridging chip, it is very easy to crack.
[0031] In view of this, the embodiments of the present application provide a semiconductor structure 20, a forming method, a packaging structure, a device, and an electronic device. By providing a protective layer 230 on the chip bridging surface of the bridging chip 210, the bridging chip 210 is protected to prevent it from cracking during the packaging process, thereby improving the packaging efficiency and reducing the packaging cost.
[0032] Please refer to Figure 2 , Figure 2 is a schematic structural diagram of a semiconductor structure 20 provided by an embodiment of the present application. As Figure 2 shown, the semiconductor structure 20 includes a bridging chip 210. Optionally, the thickness of the bridging chip 210 is 30 μm to 50 μm, such as 30 μm, 32 μm, 34 μm, 36 μm, 38 μm, 40 μm, 42 μm, 44 μm, 46 μm, 48 μm, 50 μm, etc.
[0033] The bridging chip 210 has two opposite surfaces, and one of the surfaces is the chip bridging surface. In the packaging structure, the chip bridging surface is used to bridge different preset chips 50. A chip connection structure 220 is provided on the chip bridging surface, and the chip connection structure 220 is used to bridge at least two preset chips 50. The preset chips 50 bridged by the chip connection structure 220 can be the same type of chip, such as all being logic chips. The preset chips 50 bridged by the chip connection structure 220 can also be different types of chips, such as a system-on-chip (SOC) and a high-bandwidth memory (HBM), etc.
[0034] In the embodiments of the present application, as Figure 2As shown, the chip connection structure 220 arranged on the chip bridge surface can be a bump array formed by a plurality of bumps. The bumps in the bump array can be evenly distributed on the chip bridge surface according to a certain rule, such as evenly distributed on the chip bridge surface in a row-column corresponding manner, or randomly distributed on the chip bridge surface. The number and distribution of bumps in the bump array can be set according to actual needs and process conditions, and the embodiment of the present application does not impose too many restrictions on this. The bump is used to realize the electrical connection between the preset chip 50 and the bridge chip 210. Optionally, the material of the bump can be a composite of one or more of a variety of metals such as gold, silver, copper, titanium, aluminum, tin, etc. Optionally, the height of the bump can be 20μm to 40μm, such as 20μm, 22μm, 24μm, 26μm, 28μm, 30μm, 32μm, 34μm, 36μm, 38μm, 40μm, etc.
[0035] It should be noted that, in practical applications, due to the limitations of the processing technology, the actual height of the bumps in the bump array may have a certain dimensional tolerance.
[0036] In the embodiment of the present application, in order to prevent the bridge chip 210 from being broken during the packaging process, a protective layer 230 is also provided on the chip bridge surface. Figure 2 As shown, the protective layer 230 covers the chip bridge surface, and the chip connection structure 220 is wrapped in the protective layer 230. During the packaging process, the protective layer 230 can disperse the external force on the bridge chip 210, such as the external force applied to the bridge chip 210 by the top of the mounting machine, thereby preventing the bridge chip from breaking during the packaging process.
[0037] In order not to affect the connection between the bridge chip 210 and the preset chip 50, the top of the chip connection structure 220, that is, the end of the chip connection structure 220 away from the chip bridge surface, is exposed from the surface of the protective layer 230. Optionally, the chip connection structure 220 can be exposed to a certain height from the surface of the protective layer 230, or it can be flush with the surface of the protective layer 230.
[0038] The material of the protective layer 230 can be organic non-metal or inorganic non-metal. For example, plastic, resin, ceramic, etc. In practical applications, in order to reduce packaging costs, commonly used packaging materials can be used to make the protective layer 230, such as epoxy molding compound. Optionally, the thickness of the protective layer 230 can be 20μm to 40μm, such as 20μm, 22μm, 24μm, 26μm, 28μm, 30μm, 32μm, 34μm, 36μm, 38μm, 40μm, etc.
[0039] In some embodiments, in order to facilitate the storage of the bridging chip 210 and the chip mounting process during packaging, a chip mounting adhesive film 250 is provided on the surface of the bridging chip 210 opposite to the chip bridging surface. The bridging chip 210 can be adhered to the film or attached to the printed circuit board through the chip mounting adhesive film 250.
[0040] For the semiconductor structure 20 described in the embodiments of the present application, the protection of the semiconductor structure 20 can be achieved by providing a protective layer 230 on the chip bridging surface of the bridging chip 210, thereby avoiding the cracking of the semiconductor structure 20 during the packaging process. In addition, since the protective layer 230 is wrapped around the outside of the chip connection structure 220, the protective layer 230 does not actually increase the thickness of the semiconductor structure 20, so that while protecting the semiconductor structure 20, the size of the finally obtained packaging structure can be prevented from increasing.
[0041] The embodiments of the present application also provide a method for forming a semiconductor structure 20. Figure 3 It is a schematic flowchart of a method for forming a semiconductor structure 20 provided by the embodiments of the present application, as Figure 3 shown, the forming method may include:
[0042] S1. Provide a bridging chip wafer 240; the bridging chip wafer 240 has opposite first and second surfaces.
[0043] In the embodiments of the present application, when preparing the semiconductor structure 20, in order to improve the preparation efficiency, an uncut bridging chip wafer 240 can be used for preparation. The first surface of the bridging chip wafer 240 is the front side of the wafer, and the second surface is the back side of the wafer.
[0044] S3. Form a chip connection structure 220 on the first surface.
[0045] In the embodiments of the present application, after obtaining the bridging chip wafer 240, a chip connection structure 220 can be formed on the front side of the bridging chip wafer 240. In some embodiments, before forming the chip connection structure 220 on the front side of the bridging chip wafer 240, the bridging chip wafer 240 can also be subjected to cleaning, drying and other treatments.
[0046] As an optional implementation manner, when forming the chip connection structure 220 on the front side of the bridging chip wafer 240, a metal layer can be sputtered on the surface of the bridging chip wafer 240 first. Optionally, the material of the metal layer includes but is not limited to gold, silver, copper, etc. Then a photoresist layer is formed on the metal layer and lithography is performed to form an array structure, and finally a bump array is formed by electroplating.
[0047] S5. Form a protective layer 230 on the first surface; the protective layer 230 covers the chip connection structure 220.
[0048] In the embodiments of the present application, after the chip connection structure 220 is formed on the front surface of the bridge chip wafer 240, in order to prevent the bridge chip wafer 240 from cracking during subsequent processes such as lapping and slicing, a protective layer 230 can be formed on the front surface of the bridge chip wafer 240 first. In order to ensure that the protective layer 230 can better protect the chip wafer during subsequent processes, when forming the protective layer 230, the initially formed protective layer 230 can be appropriately thicker than the height of the chip connection structure 220 to wrap the chip connection structure 220. Optionally, the initially formed protective layer 230 can have a thickness of 40 μm to 400 μm, such as 40 μm, 80 μm, 120 μm, 160 μm, 200 μm, 240 μm, 280 μm, 320 μm, 360 μm, 400 μm, etc. In some embodiments, under process-permitted conditions, the thickness of the protective layer 230 can also be the same as the height of the chip connection structure 220 or slightly less than the height of the chip connection structure 220.
[0049] Figure 4 is a schematic structural diagram of the structure after the protective layer 230 is formed on the front surface of the bridge chip wafer 240 provided by the embodiments of the present application, as Figure 4 shown, the protective layer 230 covers the front surface of the bridge chip wafer and wraps the chip connection structure 220. The method of forming the protective layer 230 can be selected according to the material of the protective layer 230. As an example, when an epoxy molding compound is used to make the protective layer 230, an injection process can be used to form the protective layer 230 on the front surface of the bridge chip wafer 240.
[0050] In the embodiments of the present application, in the case where the protective layer 230 completely wraps the chip connection structure 220 therein, in order not to affect the function of the bridge chip 210, the protective layer 230 needs to be ground so that one end of the chip connection structure 220 away from the first surface, that is, the top end, exposes the surface of the protective layer 230. Figure 5 is a schematic structural diagram of the structure after the protective layer 230 is ground provided by the embodiments of the present application, as Figure 5 shown, after the protective layer 230 is ground, the top end of the chip connection structure 220 exposes the surface of the protective layer 230.
[0051] In practical applications, in order to ensure that the tops of all bumps in the chip connection structure 220 are exposed on the surface of the protective layer 230 and to ensure the consistency of the bump heights in the chip connection structure 220, when forming the chip connection structure 220, process control can be carried out according to a preset dimensional tolerance. For example, the height of the bumps in the chip connection structure 220 is designed to be 30 μm, and a 10% dimensional tolerance can be reserved when actually forming the bumps, that is, bumps with a height of 33 μm are formed. When grinding the protective layer 230, after the tops of the bumps are exposed on the surface of the protective layer 230, continue to grind the protective layer 230 and the tops of the bumps until the bumps with a height of the preset dimensional tolerance are ground off. That is, the remaining height of the bumps is the designed height, such as 30 μm in the above example. At this time, the consistency of the bump heights in the chip connection structure 220 can be ensured, thereby improving the reliability of the subsequent bridging of the chip 210 to the preset chip 50, and further improving the performance of the packaged electronic device. In addition, when the hardness of the material of the protective layer 230 is lower than the hardness of the material of the bumps, when the bumps and the protective layer 230 are ground simultaneously, the actual height of the protective layer 230 ground off will be slightly greater than that of the bumps, so it can be ensured that the protective layer 230 will not affect the connection between the bumps and the preset chip 50.
[0052] S7. Perform a grinding process on the second surface so that the remaining thickness of the bridging chip wafer 240 is the preset thickness, obtaining the semiconductor structure 20.
[0053] In the embodiments of the present application, since the bridging chip wafer 240 is usually relatively thick and cannot be directly cut to form the bridging chip 210, therefore, after the preparation of the protective layer 230 is completed, it is also necessary to grind and thin the second surface of the bridging chip wafer 240, that is, the back surface of the bridging chip wafer 240, so that its thickness meets the requirements. Specifically, perform a grinding process on the second surface so that the remaining thickness of the bridging chip wafer 240 is the preset thickness, obtaining the target bridging chip wafer 240. The thickness of the obtained target bridging chip wafer 240 is 30 μm to 50 μm.
[0054] After obtaining the target bridging chip wafer 240, the target bridging chip wafer 240 can be cut to obtain individual bridging chips 210 with chip connection structures 220 and protective layers 230 provided on their surfaces, that is, the above-mentioned semiconductor structure 20.
[0055] In some embodiments, after cutting the target bridging chip wafer 240, a chip-attaching adhesive film 250 can also be formed on the back surface of the obtained bridging chip 210, so as to facilitate its storage and use. Figure 6 It is a schematic structural diagram of another semiconductor structure 20 provided by the embodiments of the present application, as Figure 6As shown, a chip-attaching adhesive film 250 is provided on the surface of the bridging chip 210 opposite to the chip-bridging surface, facilitating the preservation of the bridging chip 210 and the chip-attaching process during packaging.
[0056] An embodiment of this application also provides a packaging structure. Figure 7 It is a schematic structural diagram of a packaging structure provided by an embodiment of this application. As Figure 7 shown, the packaging structure includes the semiconductor structure 20 as described above.
[0057] As Figure 7 shown, the packaging structure may include a printed circuit board 30, a wiring board 40, and at least two preset chips 50. Redistribution layers are provided on both the upper and lower surfaces of the wiring board 40. Among them, the redistribution layer on the lower surface of the wiring board 40 is connected to the printed circuit board 30 through metal bumps. The redistribution layer on the upper surface of the wiring board 40 is connected to at least two preset chips 50 through metal bumps.
[0058] As Figure 7 shown, the semiconductor structure 20 is also provided in the wiring board 40. Among them, the chip connection structure 220 in the semiconductor structure 20 can be connected to the metal wires in the wiring board 40, so as to lead out the pins of the chip connection structure 220 to the redistribution layer on the upper surface of the wiring board 40. The signal terminals of at least two preset chips 50 achieve signal intercommunication through the redistribution layer on the upper surface of the wiring board 40 and the bridging chip 210, thereby shortening the signal loss of communication between different preset chips 50 and improving the performance of the packaging structure.
[0059] The packaging structure described in the embodiment of this application is implemented based on 2.5D packaging technology. During the packaging process, since the bridging chip 210 is replaced by the semiconductor structure 20 as described above, the situation of the bridging chip 210 cracking during the chip-attaching process is avoided. Through actual test statistics, in the original packaging process, the fragmentation rate of the bridging chip 210 was about 50%. After using the semiconductor structure 20 to replace the original bridging chip 210, the fragmentation rate of the bridging chip 210 is almost 0 during packaging, greatly improving the yield and reliability of the bridging chip 210 in the 2.5D packaging process. In addition, since the semiconductor structure 20 as described above is only used to replace the original bridging chip 210, it can be compatible with the original 2.5D packaging process, that is, the packaging process can maintain the original advanced packaging process flow, and the equipment and materials used in the formation process of the semiconductor structure 20 as described above are all existing advanced packaging equipment and materials. Therefore, in the actual application process, using the semiconductor structure 20 as described above for packaging not only does not increase the packaging cost, but also reduces the packaging cost due to the decrease in the fragmentation rate of the bridging chip 210.
[0060] An embodiment of the present application also provides an electronic device, which includes the packaging structure described above.
[0061] The electronic device described in the embodiment of the present application can be an integrated circuit including multiple chips and can be used in various electronic devices. Since the electronic device includes the above packaging structure, and the packaging structure uses the above semiconductor structure 20 for packaging during packaging, it has advantages such as low cost and high performance.
[0062] An embodiment of the present application also provides an electronic device, which includes the electronic device described above.
[0063] The electronic device described in the embodiment of the present application can be any electronic product or device such as a smart phone, a desktop computer, a tablet computer, a laptop computer, a digital assistant, an augmented reality (AR) / virtual reality (VR) device, a smart voice interaction device, a smart home appliance, a smart wearable device, a vehicle-mounted terminal device, etc., or can also be any intermediate product including the above electronic device.
[0064] The electronic device described in the embodiment of the present application, since it includes the above electronic device, and the electronic device includes the above packaging structure, and the packaging structure uses the above semiconductor structure 20 for packaging during packaging, thus has advantages such as low cost and high performance.
[0065] It should be noted that: the above sequence of the embodiments of the present application is only for description and does not represent the superiority or inferiority of the embodiments. And the above specific embodiments of the present specification have been described. Other embodiments are within the scope of the appended claims. In some cases, the actions or steps recited in the claims can be performed in a different order than in the embodiments and still achieve the desired results. Additionally, the processes depicted in the figures do not necessarily require the specific order or sequential order shown to achieve the desired results. In certain embodiments, multitasking and parallel processing are also possible or may be advantageous.
[0066] Each embodiment in this specification is described in a progressive manner. The same or similar parts among the embodiments can be referred to each other, and the key point of each embodiment is to illustrate the differences from other embodiments. In particular, for the device embodiments, since they are basically similar to the method embodiments, the description is relatively simple, and the relevant parts can be referred to the partial description of the method embodiments.
[0067] Those of ordinary skill in the art can understand that all or part of the steps to implement the above embodiments can be completed by hardware, or can be completed by instructing relevant hardware through a program. The program can be stored in a computer-readable storage medium. The above-mentioned storage medium can be a read-only memory, a disk, an optical disc, or the like.
[0068] The above are only the preferred embodiments of the present application and are not intended to limit the present application. Any modifications, equivalent replacements, improvements, etc. made within the spirit and principle of the present application shall be included in the protection scope of the present application.
Claims
1. A semiconductor structure, characterized in that, The semiconductor structure includes: A bridging chip having a chip bridging surface; A chip connection structure disposed on the chip bridging surface, the chip connection structure being configured to bridge at least two preset chips; A protective layer covering the chip connection structure, and one end of the chip connection structure away from the chip bridging surface exposes the surface of the protective layer.
2. The semiconductor structure according to claim 1, wherein, The chip connection structure is a bump array.
3. The semiconductor structure according to claim 2, wherein, The material of the bumps includes at least one of gold, silver, and copper.
4. The semiconductor structure according to claim 1, wherein, The material of the protective layer is at least one of plastic, resin, and ceramic.
5. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The thickness of the protective layer is 20μm - 40μm.
6. The semiconductor structure according to any one of claims 1 to 4, characterized in that, The thickness of the bridging chip is 30μm - 50μm.
7. The semiconductor structure according to claim 1, wherein A chip-attaching mucosal film is disposed on the surface of the bridging chip opposite to the chip bridging surface.
8. A method for forming a semiconductor structure, characterized in that, Including: Providing a bridging chip wafer; the bridging chip wafer has opposite first and second surfaces; Forming a chip connection structure on the first surface; Forming a protective layer on the first surface; The protective layer covers the chip connection structure; Performing a grinding process on the second surface so that the bridging chip wafer remains a preset thickness to obtain the semiconductor structure.
9. The forming method according to claim 8, characterized in that, The performing a grinding process on the second surface so that the bridging chip wafer remains a preset thickness to obtain the semiconductor structure includes: Performing a grinding process on the second surface so that the bridging chip wafer remains a preset thickness to obtain a target bridging chip wafer; Performing a cutting process on the target bridging chip wafer to obtain the semiconductor structure.
10. An encapsulation structure, characterized in that Including the semiconductor structure according to any one of claims 1 to 7.
11. An electronic device, characterized in that, The electronic device includes the packaging structure according to claim 10.
12. An electronic device, characterized in that, The electronic device includes the electronic device according to claim 11.