Monolithic integrated device and preparation method thereof

Abstract

The invention provides a monolithic integrated device and a preparation method thereof. The monolithic integrated device comprises a substrate layer; a laser diode stack disposed on the substrate layer; the passivation layer covers the groove, and the groove is formed by partially etching from the depth direction of the laser diode lamination layer; and the high electron mobility transistor lamination layer is arranged on the laser diode lamination layer and is positioned on one side of the groove. The on-off control capability of the laser diode in a high-frequency, large-current and high-power application scene can be improved.

Description

Technical Field

[0001] The present disclosure relates to the field of semiconductor technologies, and more particularly, to a monolithic integrated device and a method for manufacturing the same. Background Art

[0002] In optical communication, optoelectronic integrated systems, and high-power application scenarios, as a light source, the performance of a laser diode directly affects the efficiency and stability of the entire system. However, traditional laser diode drive circuits are often implemented using discrete components, resulting in a large system volume, low integration, and high power consumption, making it difficult to meet the requirements of modern electronic devices for miniaturization, integration, and low power consumption. At the same time, in high-frequency, high-current, and high-power application scenarios, the switching control ability of the laser diode becomes a key factor restricting the system performance. Summary of the Invention

[0003] In view of this, the present disclosure provides a monolithic integrated device and a method for manufacturing the same.

[0004] One aspect of the present disclosure provides a monolithic integrated device, including:

[0005] A substrate layer;

[0006] A laser diode stack, disposed on the substrate layer;

[0007] A passivation layer, covering a groove obtained by partially etching the laser diode stack in the depth direction;

[0008] A high electron mobility transistor stack, disposed on the laser diode stack and located on one side of the groove.

[0009] According to an embodiment of the present disclosure, the laser diode stack includes a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer, and an upper contact layer, which are sequentially stacked on the substrate layer.

[0010] According to an embodiment of the present disclosure, the high electron mobility transistor stack includes a buffer layer, a channel layer, and a barrier layer, which are sequentially stacked on the laser diode stack, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

[0011] According to an embodiment of the present disclosure, the semiconductor laser further includes:

[0012] A back electrode layer, disposed under the substrate layer;

[0013] A front electrode layer, disposed on the laser diode stack, the passivation layer, and the high electron mobility transistor stack.

[0014] According to an embodiment of the present disclosure, the front electrode layer includes:

[0015] A drain, disposed on part of the high electron mobility transistor stack;

[0016] A gate, disposed on part of the high electron mobility transistor stack;

[0017] A source, disposed on the laser diode stack, the passivation layer, and part of the high electron mobility transistor stack.

[0018] According to an embodiment of the present disclosure, the semiconductor laser further includes:

[0019] A current spreading layer, disposed between the laser diode stack and the front electrode layer, on the other side of the groove.

[0020] According to an embodiment of the present disclosure, the semiconductor laser further includes:

[0021] A high reflection layer, located on one side of the laser diode stack and the high electron mobility transistor stack; and / or,

[0022] An antireflection layer, disposed opposite to the high reflection layer, on the other side of the laser diode stack and the high electron mobility transistor stack;

[0023] Wherein, a resonant cavity is formed between the high reflection layer and the antireflection layer.

[0024] Another aspect of the present disclosure provides a method for manufacturing a monolithic integrated device, characterized by including:

[0025] Preparing a laser diode stack on a substrate layer;

[0026] Partially etching from the depth direction of the laser diode stack to form a groove;

[0027] Preparing a passivation layer on the groove;

[0028] Preparing a high electron mobility transistor stack on one side of the groove and on the laser diode stack.

[0029] According to an embodiment of the present disclosure, the preparing the laser diode stack on the substrate layer includes:

[0030] Successively preparing a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer, and an upper contact layer on the substrate layer;

[0031] The preparing the high electron mobility transistor stack includes:

[0032] A buffer layer, a channel layer, and a barrier layer are sequentially stacked on the laser diode stack, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

[0033] According to an embodiment of the present disclosure, the method further includes:

[0034] A current spreading layer is fabricated on the other side of the groove and on the laser diode stack.

[0035] According to the embodiments of the present disclosure, a monolithic integrated voltage-controlled LD device can be realized, and the laser power output by the LD is controlled by the gate voltage, effectively improving the LD switching control ability in high-frequency, high-current, and high-power application scenarios. BRIEF DESCRIPTION OF THE DRAWINGS

[0036] Through the following description of the embodiments of the present disclosure with reference to the drawings, the above and other objects, features, and advantages of the present disclosure will become clearer. In the drawings:

[0037] Figure 1 Schematically shows a structural diagram of a monolithic integrated device according to an embodiment of the present disclosure;

[0038] Figure 2 Schematically shows a structural diagram of a monolithic integrated device according to another embodiment of the present disclosure;

[0039] Figure 3 Schematically shows a structural schematic diagram of an LD stack according to an embodiment of the present disclosure;

[0040] Figure 4 Schematically shows an equivalent circuit diagram of a monolithic integrated device provided according to an embodiment of the present disclosure;

[0041] Figure 5 Schematically shows a position diagram of the cavity surface coating according to an embodiment of the present disclosure;

[0042] Figure 6 Schematically shows a flowchart of a preparation method of a monolithic integrated device according to an embodiment of the present disclosure;

[0043] Figure 7A Schematically shows a flowchart of a preparation method of a monolithic integrated device according to another embodiment of the present disclosure;

[0044] Figure 7B Schematically shows a schematic diagram of a preparation method of a monolithic integrated device according to another embodiment of the present disclosure;

[0045] Figure 8A Schematically shows a flowchart of a preparation method of a monolithic integrated device according to still another embodiment of the present disclosure;

[0046] Figure 8BSchematic diagram showing a preparation method of a monolithic integrated device according to another embodiment of the present disclosure;

[0047] Description of reference numerals:

[0048] 1 - Substrate layer;

[0049] 2 - Stacked structure;

[0050] 21 - LD stack; 211 - Lower contact layer, 212 - Lower confinement layer, 213 - Lower waveguide layer, 214 - Pre - well layer, 215 - Active layer, 216 - Upper waveguide layer, 217 - Electron blocking layer, 218 - Upper confinement layer, 219 - Upper contact layer;

[0051] 22 - HEMT stack; 221 - Buffer layer, 222 - Channel layer, 223 - Two - dimensional electron gas layer, 224 - Barrier layer;

[0052] 3 - Current spreading layer;

[0053] 4 - Passivation layer;

[0054] 5 - Front - side electrode; 51 - Drain, 52 - Gate, 53 - Source;

[0055] 6 - Back - side electrode;

[0056] 7 - Cavity - surface coating; 71 - Anti - reflection layer; 72 - High - reflection layer. Detailed implementation manners

[0057] Hereinafter, embodiments of the present disclosure will be described with reference to the accompanying drawings. However, it should be understood that these descriptions are merely exemplary and are not intended to limit the scope of the present disclosure. In the following detailed description, for the sake of explanation, many specific details are set forth in order to provide a comprehensive understanding of the embodiments of the present disclosure. However, it is obvious that one or more embodiments can also be implemented without these specific details. In addition, in the following description, descriptions of well - known structures and technologies are omitted to avoid unnecessarily obscuring the concepts of the present disclosure.

[0058] The terms used herein are merely for describing specific embodiments and are not intended to limit the present disclosure. The terms "including", "comprising", etc. used herein indicate the presence of the described features, steps, operations, and / or components, but do not exclude the presence or addition of one or more other features, steps, operations, or components.

[0059] All terms used herein (including technical and scientific terms) have the meanings commonly understood by those skilled in the art, unless otherwise defined. It should be noted that the terms used herein should be interpreted as having a meaning consistent with the context of this specification and should not be interpreted in an idealized or overly rigid manner.

[0060] In the case of using expressions such as "at least one of A, B, and C, etc.", generally, it should be interpreted according to the meaning that those skilled in the art usually understand this expression (for example, "a system having at least one of A, B, and C" should include but not be limited to a system having only A, only B, only C, having A and B, having A and C, having B and C, and / or having A, B, and C, etc.).

[0061] Lasers are widely used in many fields such as laser display, laser TV, laser projector, communication, medical treatment, weapons, guidance, ranging, spectral analysis, cutting, precision welding, high-density optical storage, etc. According to different working media, lasers can be divided into types such as solid, gas, liquid, dye, and semiconductor; compared with other types of lasers, all-solid-state semiconductor lasers have the advantages of small volume, high efficiency, light weight, good stability, long life, and compact structure.

[0062] Group III nitrides represented by gallium nitride are direct-transition wide-bandgap semiconductors and are ideal materials for fabricating laser devices from the ultraviolet light band to the green light and even the red light band. The output power of a single nitride laser can reach the order of several watts. High-frequency switching control of it requires the use of complex and fragile external circuits, which not only increases the cost of the control system, reduces the life of the entire system, but also makes it difficult to achieve higher-frequency control. This greatly limits the application of nitride lasers in high-frequency, high-current, and high-power scenarios.

[0063] Figure 1 The structural diagram of a monolithic integrated device according to an embodiment of the present disclosure is schematically shown. Figure 2 The structural diagram of a monolithic integrated device according to another embodiment of the present disclosure is schematically shown.

[0064] As Figure 1 and Figure 2 shown, the monolithic integrated device includes: a substrate layer 1, a stacked structure 2, and a passivation layer 4. The stacked structure 2 includes a laser diode (LD) stack 21 and a high electron mobility transistor (HEMT) stack 22.

[0065] The laser diode stack 21 is disposed on the substrate layer 1. The passivation layer 4 covers the groove, and the groove is obtained by partially etching from the depth direction of the laser diode stack 21. The high electron mobility transistor stack 22 is disposed on the laser diode stack 21 and is located on one side of the groove.

[0066] The substrate 1 can be one of, but not limited to, a gallium nitride substrate, a silicon substrate, silicon carbide, a zinc oxide substrate, and a patterned substrate formed based on the above substrates. The substrate 1 can have a high level of n-type doping, and the dopant depends on the specific substrate. For example, the dopant for a gallium nitride substrate can be silicon, and the dopant for a silicon substrate can be phosphorus or antimony. The doping concentration can be in the range of 1×10 17 cm -3 ~1×10 20 cm -3 range, but not limited to this. In some embodiments, the n-type doping of the substrate 1 can form a good ohmic contact with the cathode 6 and the LD stack structure 21, provide a basic support for the LD stack 21, and serve as an excellent conductive path between the LD stack 21 and the cathode, providing sufficient electrons for the LD stack structure 21 to emit light.

[0067] In some embodiments, such as Figure 1 and Figure 2 shown, the monolithic integrated device further includes: a back electrode layer 6 and a front electrode layer 5. The back electrode layer 6 is disposed under the substrate layer 1. The front electrode layer 5 is disposed on the LD stack 21, the passivation layer 4, and the HEMT stack 22.

[0068] In some embodiments, such as Figure 1 and Figure 2 shown, the front electrode layer 5 includes: a drain 51, a gate 52, and a source 53. The drain 51 is disposed on a part of the HEMT stack 22. The gate 52 is disposed on a part of the HEMT stack 22. The source 53 is disposed on the LD stack 21, the passivation layer 4, and a part of the HEMT stack 22.

[0069] The drain 51 can be composed of one or more of Ni, Pt, Pd, Ti, Al, Cr, Ag, Au, etc., but not limited to this, and the thickness can be in the range of 50~5000 nm, but not limited to this.

[0070] The gate 52 is composed of one or more of a metal Schottky gate, a metal / insulating layer gate, and a metal / p-type semiconductor gate, but not limited to this. The metal in the gate 52 can be composed of one or more of Ni, Pt, Pd, Ti, Al, Cr, Ag, Au, etc., but not limited to this, and the thickness is 50~5000 nm. The insulating layer in the gate 52 can be composed of a single-layer film or a multi-layer film of materials such as oxides or nitrides of Si, Al, Zr, Ti, Nb, Ta, etc., but not limited to this, and the thickness can be in the range of 1~100 nm, but not limited to this. The p-type semiconductor in the gate 52 can be GaN, but not limited to this, and has p-type doping. The dopant can be selected as Mg, but not limited to this, and the doping concentration can be in the range of 1×10 19 cm -3 ~4×10 20 cm -3Within, but not limited to, the thickness can be 1 - 100 nm, but not limited to this.

[0071] The source electrode 53 can be an air - bridge structure, directly connecting the HEMT stack 22 and the current spreading layer 3 without contacting the passivation layer 4. The air - bridge structure can reduce the parasitic capacitance of the device and increase the switching frequency of the device. The source electrode 53 can be composed of one or more of Ni, Pt, Pd, Ti, Al, Cr, Ag, Au, etc., but not limited to this. The thickness can be within the range of 50 - 5000 nm, but not limited to this.

[0072] According to an embodiment of the present disclosure, the HEMT stack 22 is disposed on the upper LD stack 21. Above the HEMT stack 22, a drain electrode 51, a gate electrode 52, and a source electrode 53 are provided. The source electrode 53 extends to one side of the LD stack 21 and forms a good electrical contact with the current spreading layer 3, thereby being reused as the anode of the LD stack 21. By setting the voltage of the gate electrode 52, the depletion state of the two - dimensional electron gas layer 223 under the gate electrode 52 can be controlled, thereby controlling the current intensity between the drain electrode 51 and the source electrode 53, and further controlling the current intensity entering the LD stack structure from the source electrode 53, and regulating the output optical power.

[0073] It can be understood that, as Figure 2 shown, the HEMT stack 22 is disposed on the LD stack structure 21 whose at least part of the thickness is etched. The corresponding electrode setting method and control method are the same as those described above, and will not be elaborated here. The etching depth can be at least a part of the upper contact layer 219 and the upper confinement layer 218 of the LD stack 21. The present disclosure does not limit this, and those skilled in the art can set it according to actual needs.

[0074] In some embodiments, as Figure 1 and Figure 2 shown, the monolithic integrated device further includes a current spreading layer 3, which is disposed between the LD stack 21 and the front - side electrode layer 5 and on the other side of the groove. The current spreading layer 3 is used to form a good ohmic contact with the LD stack 21. At the same time, the relatively low resistivity of the current spreading layer 3 helps the holes injected from the source electrode 53 to be better diffused, thereby improving the uniformity of the current in the LD stack 21 and improving the working performance of the laser.

[0075] In some embodiments, the current spreading layer 3 can be composed of one or more of the transparent conductive materials ITO, IZO, ZnO and the metals Ni, Pt, Pd, Ti, Al, Cr, Ag, Au, etc., but not limited to this. The thickness can be 20 - 500 nm, but not limited to this.

[0076] It can be understood that the source electrode 53 extends onto the current spreading layer 3 and forms an ohmic contact with the current spreading layer 3, and is reused as the anode of the LD stack 21. The back electrode layer 6 disposed on the other side of the substrate 1 constitutes the cathode of the LD stack 21.

[0077] It can be understood that the passivation layer 4 covers at least the sidewalls of the LD stack structure 21, the sidewalls of the current spreading layer 3, and the sidewalls of the HEMT stack structure 22. The passivation layer 4 can protect the etched surface of the LD stack structure 21, reduce the influence of surface states on the light emission of the active layer 225, improve the light confinement ability, and enhance the device performance. The passivation layer 4 can also act as an insulating layer to prevent leakage current from the source electrode 53 to the LD stack structure 21. The passivation layer 4 can be a single-layer film or a multi-layer film composed of materials such as oxides or nitrides of Si, Al, Zr, Ti, Nb, Ta, etc., but is not limited thereto, and the thickness can be in the range of 50 - 2000 nm, but is not limited thereto.

[0078] Figure 3 Schematically shows a structural diagram of an LD stack according to an embodiment of the present disclosure.

[0079] As Figure 3 shown, the LD stack 21 includes a lower contact layer 211, a lower confinement layer 212, a lower waveguide layer 213, a pre-well layer 214, an active layer 215, an upper waveguide layer 216, an electron blocking layer 217, an upper confinement layer 218, and an upper contact layer 219 that are sequentially stacked on the substrate layer 1.

[0080] In some embodiments, the lower contact layer 211 can be selected from one or a combination of two or more of GaN, InGaN, and AlGaN, but is not limited thereto. The lower contact layer 211 can have n-type doping, and the dopant can be selected as Si, but is not limited thereto. The doping concentration can be in the range of 1×10 18 cm -3 ~1×10 20 cm -3 range, but is not limited thereto. The lower contact layer 211 is used to form a good ohmic contact with the substrate 1. The lower contact layer 211 can also be used as a stress release layer and a buffer layer to adjust the stress and dislocation density in the epitaxial layer, thereby providing a better growth environment for the active layer 215 in the LD stack structure 21 and improving the light emission efficiency, reliability, and lifetime of the device.

[0081] In some embodiments, the lower confinement layer 212 can be selected from one or a combination of two or more of GaN, InGaN, and AlGaN, but is not limited thereto, and has n-type doping. The dopant can be selected as Si, but is not limited thereto. The doping concentration can be in the range of 1×10 17 cm -3 ~1×10 19 cm -3 range, but is not limited thereto.

[0082] In some embodiments, the lower waveguide layer 213 may be selected from one or more combinations of GaN, InGaN, and AlGaN, but is not limited thereto. The lower waveguide layer 213 may be undoped or n-type doped, and the dopant may be selected as Si, but is not limited thereto, and the doping concentration may be in the range of 1×10 16 cm -3 ~1×10 18 cm -3 range, but is not limited thereto.

[0083] In some embodiments, the refractive index of the lower confinement layer 212 is lower than that of the lower waveguide layer 213. The lower confinement layer 212 and the lower waveguide layer 213 cooperate to form a total reflection interface for the signal light, thereby restricting the propagation of the optical signal in the waveguide layer and achieving an optical gain effect.

[0084] In some embodiments, the pre-well layer 214 may be selected from one or more combinations of GaN, InGaN, AlGaN, AlInN, and AlInGaN, but is not limited thereto. The pre-well layer 214 may also be omitted. The pre-well layer 214 may be undoped or n-type doped, and the dopant may be selected as Si, but is not limited thereto, and the doping concentration may be in the range of 1×10 16 cm -3 ~1×10 18 cm -3 range, but is not limited thereto. The pre-well layer 214 has a single quantum well structure or a multi-quantum well structure. Compared with the single quantum well structure, the multi-quantum well structure is easier to adjust the dislocations and stresses in the epitaxial layer, provides a better growth environment for the active layer 215, improves the material quality of the active layer 215, and thus brings good effects to the optoelectronic performance and structural performance of the laser.

[0085] In some embodiments, the active layer 215 may be selected from one or more combinations of GaN, InGaN, AlGaN, AlInN, and AlInGaN, but is not limited thereto. The active layer 215 has a single quantum well structure or a multi-quantum well structure. Compared with the single quantum well structure, the multi-quantum well structure has a higher carrier utilization rate, a higher luminous efficiency, and is easier to obtain sufficient gain to form lasing, thereby improving the output power and other optoelectronic performance of the laser.

[0086] In some embodiments, the upper waveguide layer 216 may be selected from one or more combinations of GaN, InGaN, and AlGaN, but is not limited thereto. The upper waveguide layer 216 may be undoped or p-type doped, and the dopant may be selected as Mg, but is not limited thereto, and the doping concentration may be in the range of 1×10 17 cm -3 ~1×10 19 cm -3 range, but is not limited thereto.

[0087] In some embodiments, the electron blocking layer 217 may be selected from one or more combinations of GaN, AlGaN, AlInN, and AlInGaN, but is not limited thereto, and has p-type doping. The dopant may be selected as Mg, but is not limited thereto. The doping concentration may be in the range of 1×10 18 cm -3 ~1×10 20 cm -3 range, but is not limited thereto. The electron blocking layer 217 is used to block electrons coming from the cathode of the laser through the active layer 215 and the upper waveguide layer 216, and avoid excessive consumption of holes injected from the source 53 through the current spreading layer 3, the upper contact layer 219, and the upper confinement layer 218. At the same time, the electron blocking layer 217 is disposed between the upper waveguide layer 216 and the upper confinement layer 218 to avoid excessive light absorption and light loss caused when the electron blocking layer 217 is disposed between the active layer 215 and the upper waveguide layer 216.

[0088] In some embodiments, the upper confinement layer 218 may be selected from one or more combinations of GaN, InGaN, and AlGaN, but is not limited thereto, and has p-type doping. The dopant may be selected as Mg, but is not limited thereto. The doping concentration may be in the range of 1×10 18 cm -3 ~1×10 20 cm -3 range, but is not limited thereto. The refractive index of the upper confinement layer 218 is lower than that of the upper waveguide layer 216. The upper waveguide layer 216, the electron blocking layer 217, and the upper confinement layer 218 cooperate to form a total reflection interface for the signal light, thereby restricting the propagation of the optical signal in the waveguide layer and achieving an optical gain effect.

[0089] In some embodiments, the upper contact layer 219 may be selected from one or more combinations of GaN, InGaN, and AlGaN, but is not limited thereto, and has p-type doping. The dopant may be selected as Mg, but is not limited thereto. The doping concentration may be in the range of 1×10 19 cm -3 ~4×10 20 cm -3 range, but is not limited thereto. The upper contact layer 219 is used to form a good ohmic contact with the current spreading layer 31, so as to better provide holes for the LD stack structure 21.

[0090] In some embodiments, the thickness of the lower contact layer 211 may be in the range of 10 to 500 nm, the thickness of the lower confinement layer 212 may be in the range of 100 to 3000 nm, the thickness of the lower waveguide layer 213 may be in the range of 20 to 500 nm, the thickness of the pre-well layer 214 may be in the range of 5 to 200 nm, the thickness of the active layer 215 may be in the range of 5 to 200 nm, the thickness of the upper waveguide layer 216 may be in the range of 20 to 500 nm, the thickness of the electron blocking layer 217 may be in the range of 5 to 200 nm, the thickness of the upper confinement layer 218 may be in the range of 100 to 2000 nm, and the thickness of the upper contact layer 219 may be in the range of 5 to 200 nm, but is not limited thereto.

[0091] In some embodiments, such as Figure 1 and Figure 2 shown, the HEMT stack 22 includes a buffer layer 221, a channel layer 222, and a barrier layer 224 stacked in sequence on the LD stack 21, and a two-dimensional electron gas layer 223 is formed between the channel layer 222 and the barrier layer 224.

[0092] In some embodiments, the buffer layer 221 may be selected from one or more combinations of GaN, AlN, AlGaN, InGaN, and AlInGaN, but is not limited thereto. The buffer layer 221 is used to adjust material properties such as dislocations and stresses in the epitaxial layer. The buffer layer 221 may also be a back barrier layer, which suppresses leakage current in the HEMT stack structure through a larger bandgap than the channel layer 222. The buffer layer 221 may also be a high-resistance layer, which suppresses leakage current through an extremely high resistance and has a high-resistance doping. The dopant may be selected from carbon, iron, manganese, magnesium, etc., but is not limited thereto, and the doping concentration may be in the range of 1×10 17 cm -3 ~5×10 20 cm -3 range, but is not limited thereto. The buffer layer 221 may also be omitted. For example, the upper contact layer 219 in the LD stack structure 21 may have p-type doping, and the upper confinement layer 218 may have p-type doping and may be AlGaN with a larger bandgap, so as to have a certain leakage current suppression ability.

[0093] In some embodiments, the channel layer 222 may be selected from GaN materials, but is not limited thereto.

[0094] In some embodiments, the barrier layer 224 may be selected from one or more combinations of AlN, AlGaN, InGaN, and AlInN, but is not limited thereto.

[0095] Optionally, the thickness of the buffer layer 221 may be in the range of 20 to 2000 nm, the thickness of the channel layer 222 may be in the range of 20 to 2000 nm, and the thickness of the barrier layer 224 may be in the range of 5 to 50 nm, but is not limited thereto.

[0096] It is understandable that the two-dimensional electron gas layer 223 refers to a thin layer of highly mobile and highly concentrated electrons generated at the heterojunction between different group III nitrides. The resistivity of the region where the two-dimensional electron gas layer 223 is located is relatively low, and the electron transmission condition is good.

[0097] The barrier layer 224 or the channel layer 222 forms a good ohmic contact with the drain 51. Different gates 52 can provide different electrical properties for the HEMT stack structure 22. By using a metal Schottky gate or a metal / insulating layer gate, a normally-on or depletion-mode HEMT can be formed. When the voltage applied to the gate 52 is 0, the two-dimensional electron gas layer 223 under the gate 52 still exists, and the HEMT stack structure 22 can still conduct normally. By using a metal / p-type semiconductor gate, a normally-off or enhancement-mode HEMT can be formed. When the voltage applied to the gate 52 is 0, the two-dimensional electron gas layer 223 under the gate 52 is depleted, and the HEMT stack structure 22 cannot conduct and is in a cut-off state. The source 53 forms a good ohmic contact with the barrier layer 224 or the channel layer 222. The source 53 forms a good ohmic contact with the current spreading layer 3.

[0098] Figure 4 Schematically shows an equivalent circuit diagram of a monolithic integrated device provided according to an embodiment of the present disclosure.

[0099] As Figure 4 shown, the LD stack 21 can be equivalent to an LD device in a monolithic integrated device, the HEMT stack 22 can be equivalent to a HEMT device in a monolithic integrated device, and the HEMT stack 22 drives the LD stack 21 to emit light. By using the HEMT stack 21 to drive the LD stack 22, without an additional driving unit, the volume of the integrated device can be effectively reduced, the parasitic resistance, inductance, and capacitance of the external circuit can be reduced, and the device performance and reliability can be improved.

[0100] Figure 5 Schematically shows a position diagram of the cavity surface coating according to an embodiment of the present disclosure.

[0101] As Figure 5 shown, the cavity surface coating 7 includes an antireflection layer 71 and a high-reflection layer 72. The high-reflection layer 72 is located on one side of the LD stack 21 and the HEMT stack 22. The antireflection layer 71 is disposed opposite to the high-reflection layer 72 and is located on the other side of the LD stack 21 and the HEMT stack 22. Among them, a resonant cavity is formed between the high-reflection layer 72 and the antireflection layer 71.

[0102] An antireflection layer 71 and a high-reflection layer 72 are respectively plated on the left and right sides of the substrate layer 1 and the stacked structure 2, which can adjust and enhance the performance of the laser, such as threshold voltage, slope efficiency, output power, etc. The antireflection layer 71 and the high-reflection layer 72 can also be omitted or at least one of them can be prepared. Among them, the cavity surface plated with the antireflection layer 71 is the laser output end face, and the cavity surface plated with the high-reflection layer 72 is the far end in the laser output direction.

[0103] The antireflection layer 71 can be composed of a single-layer film or a multi-layer film of materials such as oxides or nitrides of Si, Al, Zr, Ti, Nb, Ta, etc., but is not limited thereto, and the thickness can be 5 to 5000 nm, but is not limited thereto. The high-reflection layer 72 can be composed of a single-layer film or a multi-layer film of materials such as oxides or nitrides of Si, Al, Zr, Ti, Nb, Ta, etc., but is not limited thereto, and the thickness can be 5 to 5000 nm, but is not limited thereto.

[0104] The monolithic integrated device of LD and HEMT provided by the embodiments of the present disclosure may further include any structure known to those skilled in the art, and the embodiments of the present disclosure do not limit this.

[0105] The embodiments of the present disclosure do not limit the specific preparation process of the LD stacked layer 21 and the HEMT stacked layer 22, and those skilled in the art can set it according to actual needs. Exemplarily, several possible preparation processes and methods of the monolithic integrated device are introduced below. The present disclosure does not limit the specific preparation process and corresponding process parameters used in each process, and those skilled in the art can set them according to actual needs.

[0106] Figure 6 The flowchart of the preparation method of the monolithic integrated device according to the embodiments of the present disclosure is schematically shown.

[0107] As Figure 6 shown, the method includes operations S610 to S640.

[0108] In operation S610, a laser diode stacked layer is prepared on the substrate layer.

[0109] In operation S620, a groove is formed by partially etching from the depth direction of the laser diode stacked layer.

[0110] In operation S630, a passivation layer is prepared on the groove.

[0111] In operation S640, a high electron mobility transistor stacked layer is prepared on one side of the groove and on the laser diode stacked layer.

[0112] In some embodiments, preparing a laser diode stacked layer on the substrate layer includes: sequentially preparing a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer, and an upper contact layer on the substrate layer;

[0113] In some embodiments, the preparation of the high electron mobility transistor stack includes: a buffer layer, a channel layer, and a barrier layer sequentially stacked on the laser diode stack, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

[0114] In some embodiments, the method further includes: preparing a current spreading layer on the other side of the groove and on the laser diode stack.

[0115] In some embodiments, the method further includes: preparing a back electrode layer under the substrate layer; preparing a front electrode layer on the laser diode stack, the passivation layer, and the high electron mobility transistor stack. Among them, the drain is prepared on part of the high electron mobility transistor stack; the gate is prepared on part of the high electron mobility transistor stack; the source is prepared on the laser diode stack, the passivation layer, and part of the high electron mobility transistor stack.

[0116] In some embodiments, the method further includes: preparing a high-reflection layer on one side of the laser diode stack and the high electron mobility transistor stack; and / or, disposed opposite to the high-reflection layer, preparing an antireflection layer on the other side of the laser diode stack and the high electron mobility transistor stack; wherein, a resonant cavity is formed between the high-reflection layer and the antireflection layer.

[0117] Figure 7A Schematically shows a flowchart of a method for preparing a monolithic integrated device according to an embodiment of the present disclosure. Figure 7B Schematically shows a schematic diagram of a method for preparing a monolithic integrated device according to an embodiment of the present disclosure.

[0118] As Figure 7A shown, the method includes operations S11 to S19.

[0119] In operation S11, a substrate is obtained. As can be referred to Figure 7B in (a) shown, the setting manner of the substrate layer 1 can refer to the above embodiments and will not be elaborated here.

[0120] In operation S12, an LD stack 21 and a HEMT stack 22 are prepared on the upper surface of the substrate layer 1. As can be referred to Figure 7BAs shown in Fig. (b). Among them, the LD stack 21 includes a lower contact layer 211, a lower confinement layer 212, a lower waveguide layer 213, a pre-well layer 214, an active layer 215, an upper waveguide layer 216, an electron blocking layer 217, an upper confinement layer 218, and an upper contact layer 219; the HEMT stack 22 includes a buffer layer 221, a channel layer 222, and a barrier layer 224, and a two-dimensional electron gas layer 223 is formed between the channel layer 222 and the barrier layer 224. Optionally, the above LD stack 21 and HEMT stack 22 can be prepared by metal-organic chemical vapor deposition (MOCVD) or molecular beam epitaxy (MBE), but not limited thereto.

[0121] In operation S13, a part of the HEMT stack 22 in a partial region is etched to expose at least a part of the upper surface of the LD stack 21. Reference can be made to Figure 7B As shown in Fig. (c). The etching process may include a photolithography process and an etching process. Further, the photolithography process may include processes such as coating, baking, exposure, development, and resist stripping; the etching process may be a dry etching process, such as inductively coupled plasma dry etching (ICP) and reactive ion beam etching (RIE), but not limited thereto.

[0122] In operation S14, a current spreading layer 3 is prepared on at least a part of the region of the surface of the LD stack 21 away from the HEMT stack 22 to form a strip structure. Reference can be made to Figure 7B As shown in Fig. (d). This preparation process may include processes such as sputtering, evaporation, photolithography, corrosion, and etching. Among them, sputtering and evaporation can be used for the growth of the current spreading layer 3, photolithography can be used to set the mask shape, and corrosion and etching can be used to transfer the mask shape set by photolithography onto the current spreading layer 3. The strip structure is perpendicular to Figure 1 and Figure 2 the side shown in, and the present disclosure does not limit the specific dimensions, and those skilled in the art can set them according to actual needs. Optionally, the current spreading layer 3 can be prepared by MOCVD, physical vapor deposition (PVD), chemical vapor deposition (CVD), plasma-enhanced chemical vapor deposition (PECVD), or magnetron sputtering, but not limited thereto.

[0123] In operation S15, a part of the thickness of the LD stack 21 between the current spreading layer 3 and the HEMT stack 22 is etched. Reference can be made to Figure 7B As shown in Fig. (e). This etching process will form a ridge structure of the laser, and the ridge structure can enhance the light confinement ability of the laser. The width of the ridge structure affects the performance of the laser to a certain extent. The ridge structure is perpendicular to Figure 1 and Figure 2Regarding the side shown, the present disclosure does not limit the specific dimensions, and those skilled in the art can set them according to actual needs. The etching depth can be at least a certain depth of the LD stack 21 in this area, such as all the upper contact layers 219 and part of the upper confinement layer 218 in this area. The present disclosure does not limit the specific etching depth, and those skilled in the art can set it according to actual needs.

[0124] In operation S16, a passivation layer 4 is prepared on the surface of the LD stack 21 after etching and on the sidewalls of the adjacent LD stack 21, the sidewall of the current spreading layer 3, and the sidewall of the HEMT stack 22. Reference can be made to Figure 7B as shown in (f). The passivation layer 4 can protect the etched surface of the LD stack 21, reduce the influence of surface states on the light emission of the active layer 225, improve the light confinement ability, and enhance the device performance. The passivation layer 4 can also act as an insulating layer to prevent leakage from the source electrode 53 to the LD stack structure 21. Optionally, the passivation layer 4 can be prepared by PVD, CVD, PECVD, atomic layer deposition ALD, but not limited thereto.

[0125] In operation S17, front electrodes 5 are respectively prepared in partial areas on the surfaces of the LD stack 21 and the HEMT stack 22 to form a drain electrode 51, a gate electrode 52, and a source electrode 53. Reference can be made to Figure 7B as shown in (g). Since the types of electrodes are diverse, the electrodes can be prepared in multiple steps. Optionally, the drain electrode 51, the gate electrode 52, and the source electrode 53 can be prepared by magnetron sputtering, thermal evaporation, electron beam evaporation, but not limited thereto. Further, after the preparation of each metal electrode, an annealing treatment can be performed on it. After annealing, the metal electrode can form a good ohmic contact with the adjacent semiconductor material layer.

[0126] In operation S18, the back surface of the substrate layer 1 is thinned, and a back electrode 6 is prepared to form a cathode. Reference can be made to Figure 7B as shown in (h). By thinning the substrate layer 1, the series resistance can be effectively reduced, and the device performance can be improved. The back electrode 6 is prepared on the back surface of the thinned substrate layer 1, which can make the current injection of the LD stack 21 uniform, and can also effectively enhance the heat dissipation effect and improve the laser performance. The thinning process can adopt mechanical grinding and chemical mechanical polishing CMP, etc., including but not limited thereto. The thinning thickness can be at least part of the substrate thickness. The present disclosure does not limit the specific thinning thickness, and those skilled in the art can set it according to actual needs. The back electrode 6 can be prepared by magnetron sputtering, thermal evaporation, electron beam evaporation, but not limited thereto. After the electrode is prepared, an annealing treatment can also be performed on it. After annealing, the metal electrode can form a good ohmic contact with the adjacent semiconductor material layer.

[0127] In operation S19, at both ends of the LD stack 21, wafer cleavage or etching is performed to form the resonant cavity surfaces. Then, a high-reflection film and an anti-reflection film are deposited on the cavity surfaces to form the cavity surface coatings. The cavity surfaces are perpendicular to the strip structure formed in operation S14 and the ridge structure formed in operation S15, and at the same time, the cavity surfaces are perpendicular to the substrate 1, thus forming a ridge laser with a resonant cavity. Wafer cleavage utilizes the property that under the action of an external force, a crystalline substrate cracks along a certain crystal direction into a smooth plane due to the crystal structure; the cracked smooth plane is the cleavage plane, which is used as the resonant cavity surface of the laser in the present disclosure. The etching can be dry etching, and it should be ensured that the sidewalls formed by the etching are smooth and straight, otherwise it will increase the optical loss of the laser and reduce the output laser power. Optionally, the anti-reflection layer 71 and the high-reflection layer 72 can be prepared by PVD, CVD, PECVD, atomic layer deposition ALD, but not limited thereto.

[0128] Figure 8A Schematically shows a flowchart of a method for manufacturing a monolithic integrated device according to another embodiment of the present disclosure. Figure 8B Schematically shows a schematic diagram of a method for manufacturing a monolithic integrated device according to another embodiment of the present disclosure.

[0129] As Figure 8A shown, the manufacturing method includes operations S21 - S29.

[0130] In operation S21, a substrate is obtained. It can be referred to as shown in (a) of Figure 8B . The setting method of the substrate layer 1 can refer to the above embodiment and will not be elaborated here.

[0131] In operation S22, an LD stack 21 is fabricated on the upper surface of the substrate layer 1. It can be referred to as shown in (b) of Figure 8B . The LD stack 21 includes a lower contact layer 211, a lower confinement layer 212, a lower waveguide layer 213, a pre-well layer 214, an active layer 215, an upper waveguide layer 216, an electron blocking layer 217, an upper confinement layer 218, and an upper contact layer 219. The above LD stack 21 can be prepared by metal organic chemical vapor deposition MOCVD or molecular beam epitaxy MBE, but not limited thereto. This substrate setting method can grow the LD stack 21 and the HEMT stack 22 in two stages, so as to make full use of the growth advantages of different growth machines such as MOCVD and improve the performance and reliability of the monolithic integrated device.

[0132] Optionally, operation S21 and operation S22 can be combined into one operation, in which the substrate layer 1 is obtained and the LD stack 21 has been fabricated on the upper surface of the substrate layer 1. It can be referred to as shown in (b) of Figure 8B . This operation method can utilize the convenience of commercial laser epitaxial wafers, improve production efficiency, and reduce R & D costs.

[0133] In operation S23, at least a part of the LD stack 21 in a partial region is etched to form a strip structure. Reference can be made to Figure 8B as shown in (c) therein. The unetched strip portion will serve as the ridge structure of the laser, laterally restricting the optical field and increasing the injection current density. The strip region is perpendicular to Figure 1 and Figure 2 the side surfaces shown. The present disclosure does not limit the specific dimensions, and those skilled in the art can set them according to actual needs. The etching depth can be at least a certain depth of the LD stack 21 in this region, such as all of the upper contact layer 219 and part of the upper confinement layer 218 in this region. The present disclosure does not limit the specific etching depth, and those skilled in the art can set it according to actual needs. The etching process can include a photolithography process and an etching process. The etching process can be a dry etching process, such as inductively coupled plasma dry etching ICP and reactive ion beam etching RIE, but is not limited thereto.

[0134] In operation S24, a HEMT stack 22 is prepared in a partial region of the etched surface of the LD stack 21 away from the unetched surface of the LD stack 21. Reference can be made to Figure 8B as shown in (d) therein. The HEMT stack structure 22 includes a buffer layer 221, a channel layer 222, and a barrier layer 224, and a two-dimensional electron gas layer 223 is formed between the channel layer 222 and the barrier layer 224. Optionally, the growth of the HEMT stack 22 in the above region can be carried out by selective area epitaxy. The above HEMT stack 22 can be prepared by MOCVD or MBE, but is not limited thereto. Specifically, the selective area epitaxy can be achieved by covering a mask on a partial region of the surface of the LD stack 21. The mask can be a single-layer film or a multi-layer film composed of materials such as oxides or nitrides of Si, Al, Zr, Ti, Nb, Ta, etc., but is not limited thereto, and the corresponding thickness can be set by those skilled in the art according to actual needs.

[0135] In operation S25, a current spreading layer is prepared on the unetched surface of the LD stack 21. Reference can be made to Figure 8B as shown in (e) therein. The setting manner of the current spreading layer 3 can refer to the above embodiment and will not be elaborated here.

[0136] In operation S26, a passivation layer 4 is prepared on the surface of the etched LD stack 21 and the adjacent sidewalls of the LD stack 21, the sidewalls of the current spreading layer 3, and the sidewalls of the HEMT stack 22. Reference can be made to Figure 8B as shown in (f) therein. The setting manner of the passivation layer 4 can refer to the above embodiment and will not be elaborated here.

[0137] In operation S27, front electrodes 5 are respectively prepared in partial regions on the surfaces of the LD stack 21 and the HEMT stack 22 to form a drain 51, a gate 52, and a source 53. Reference can be made to Figure 8BAs shown in (g) of the figure. The arrangements of the drain 51, the gate 52, and the source 53 can be referred to the above embodiments, and will not be elaborated here. The source 53 is multiplexed as the anode of the LD stack 21.

[0138] In operation S28, the back surface of the substrate layer 1 is thinned, and a back electrode 6 is prepared to form a cathode. It can be referred to Figure 8B as shown in (h) of the figure. The arrangements of the thinned substrate layer 1 and the back electrode 6 can be referred to the above embodiments, and will not be elaborated here.

[0139] In operation S29, at both ends of the LD stack 21, wafer cleavage or etching is performed to form a resonant cavity surface, and a high-reflection film and an antireflection film are deposited on the cavity surface to form a cavity surface coating. The arrangements of forming the cavity surface and the coating can be referred to the above embodiments, and will not be elaborated here.

[0140] For the monolithic integrated device prepared by the above preparation method, the source 52 of the HEMT stack 22 and the anode of the LD stack 21 are multiplexed with each other, and a voltage-controlled LD device with monolithic integration can be realized. The current intensity between the source 52 and the drain 51 of the HEMT stack 22 can be controlled by a relatively small gate voltage, and then the laser power output by the LD can be controlled, which can effectively improve the LD switching control ability in high-frequency, high-current, and high-power application scenarios.

[0141] The embodiments of the present disclosure have been described above. However, these embodiments are for illustrative purposes only and are not intended to limit the scope of the present disclosure. Although the embodiments are described separately above, this does not mean that the measures in each embodiment cannot be used advantageously in combination. The scope of the present disclosure is defined by the appended claims and their equivalents. Without departing from the scope of the present disclosure, those skilled in the art can make various substitutions and modifications, and these substitutions and modifications should fall within the scope of the present disclosure.

Claims

1. A monolithic integrated device, characterized in that, Comprising: Substrate layer; Laser diode stack, disposed on the substrate layer; Passivation layer, covering the groove, the groove being obtained by partially etching in the depth direction of the laser diode stack; High electron mobility transistor stack, disposed on the laser diode stack and on one side of the groove.

2. The monolithic integrated device according to claim 1, wherein The laser diode stack includes a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer, and an upper contact layer sequentially stacked on the substrate layer.

3. The monolithic integrated device according to claim 1, characterized in that, The high electron mobility transistor stack includes a buffer layer, a channel layer, and a barrier layer sequentially stacked on the laser diode stack, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

4. The monolithic integrated device according to claim 1, characterized in that, The semiconductor laser further includes: Back electrode layer, disposed under the substrate layer; Front electrode layer, disposed on the laser diode stack, the passivation layer, and the high electron mobility transistor stack.

5. The monolithic integrated device according to claim 4, characterized in that, The front electrode layer includes: Drain, disposed on a part of the high electron mobility transistor stack; Gate, disposed on a part of the high electron mobility transistor stack; Source, disposed on the laser diode stack, the passivation layer, and a part of the high electron mobility transistor stack.

6. The monolithic integrated device according to claim 4, wherein, The semiconductor laser further includes: Current spreading layer, disposed between the laser diode stack and the front electrode layer and on the other side of the groove.

7. The monolithic integrated device according to claim 1, characterized in that, The semiconductor laser further includes: High reflection layer, located on one side of the laser diode stack and the high electron mobility transistor stack; and / or, Anti-reflection layer, disposed opposite to the high reflection layer and located on the other side of the laser diode stack and the high electron mobility transistor stack; Wherein, a resonant cavity is formed between the high reflection layer and the anti-reflection layer.

8. A method for preparing a monolithic integrated device, characterized in that, Comprising: Fabricating a laser diode stack on a substrate layer; Partially etching in the depth direction of the laser diode stack to form a groove; Fabricating a passivation layer on the groove; Fabricating a high electron mobility transistor stack on one side of the groove and on the laser diode stack.

9. The method for preparing a monolithic integrated device according to claim 8, characterized in that, The fabricating the laser diode stack on the substrate layer includes: Sequentially fabricating a lower contact layer, a lower confinement layer, a lower waveguide layer, a pre-well layer, an active layer, an upper waveguide layer, an electron blocking layer, an upper confinement layer, and an upper contact layer on the substrate layer; The fabricating the high electron mobility transistor stack includes: Sequentially fabricating a stacked buffer layer, a channel layer, and a barrier layer on the laser diode stack, and a two-dimensional electron gas layer is formed between the channel layer and the barrier layer.

10. The method for preparing the monolithic integrated device according to claim 9, characterized in that, The method further includes: Fabricating a current spreading layer on the other side of the groove and on the laser diode stack.

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