Common-mode voltage suppression method and device for hybrid power device type three-level inverter

Abstract

The present invention discloses a method and device for suppressing common-mode voltage in a hybrid power device-based three-level frequency converter. The method comprises comparing the amplitudes of sinusoidal signals of a three-phase given reference voltage to obtain the maximum, intermediate, and minimum values ​​of the sinusoidal signals of the three-phase given reference voltage; adding the maximum, intermediate, and minimum values ​​of the sinusoidal signals of the three-phase given reference voltage to an injected zero-sequence voltage to obtain the maximum, intermediate, and minimum values ​​of the three-phase modulated signal; and, based on the introduction of common-mode voltage suppression and midpoint potential balance, comparing the maximum, intermediate, and minimum values ​​of the three-phase modulated signal after the injection of the zero-sequence voltage with three carriers to generate switching signals, which act on the hybrid power device-based three-level frequency converter to achieve common-mode voltage suppression. The present invention can not only increase the service life of the frequency converter by reducing the common-mode voltage, but also reduce the midpoint potential fluctuation of the three-level frequency converter.

Description

Technical Field

[0001] The present invention belongs to the field of new energy drive and energy storage system control, and in particular relates to a method and device for suppressing common-mode voltage of a hybrid power device-type three-level inverter. Background Art

[0002] Three-level inverters have become a core technology in new energy, industrial drives, smart grids, and other fields due to their significant advantages in voltage rate of change, semiconductor losses, output harmonics, filter size, and lifecycle costs. With the advancement of silicon carbide devices and intelligent algorithms, their application scenarios are expanding, with a trend towards low-carbon and high-efficiency designs.

[0003] Among inverter switching devices, traditional IGBTs offer lower losses at low frequencies, such as 50Hz, and superior conduction characteristics at low frequencies and high currents. SiC MOSFETs, on the other hand, offer superior conduction characteristics at low currents and faster switching speeds, making them suitable for high-frequency applications. Three-level inverters with hybrid power devices replace IGBTs in the high-frequency switching portion with SiC MOSFETs to reduce losses, while using IGBTs in the low-frequency switching portion to lower costs. This hybrid device combination balances losses and costs for the three-level inverter. Furthermore, the hybrid power device design not only reduces the voltage stress on the devices but also increases the system's power density. Therefore, hybrid power device-based three-level inverters will become an important technology path for applications such as new energy vehicle electric drive systems and photovoltaic inverters. The high-frequency switching of inverter switching devices can cause large common-mode voltages, negatively impacting the system. In electric drive systems, bearing currents caused by common-mode voltages can shorten motor life. Furthermore, high-frequency common-mode voltage fluctuations can increase the risk of insulation degradation and breakdown. High common-mode voltages can distort the grid current waveform, reducing power quality. In three-level inverters, midpoint potential balance is also crucial. Fluctuations in midpoint potential can cause low-order harmonics in the output voltage, degrading power quality. When these fluctuations are large, some switching components may experience voltages exceeding their designed values, accelerating device aging or even breakdown, reducing reliability. Therefore, to ensure optimal operation of a three-level inverter with a hybrid power device combination, its modulation strategy must not only overcome the high common-mode voltage but also balance the midpoint potential.

[0004] The conventional dual-carrier PWM method (PDPWM) without common-mode voltage suppression uses two identically phased carriers to compare with a three-phase reference voltage signal to generate switching signals. Zero-sequence voltage injection achieves neutral-point potential balancing, but this approach fails to account for the negative impact of high common-mode voltage. While the prior art proposes a common-mode voltage suppression method with phase-reversal PWM (PODPWM), based on dual-carrier PWM, it suppresses common-mode voltage by avoiding fundamental vectors with large common-mode voltages and then achieves neutral-point potential balancing through zero-sequence voltage injection, the limitations of common-mode voltage suppression reduce the range of injected zero-sequence voltage. This results in poor controllability of neutral-point potential balancing under low-frequency modulation schemes and significant neutral-point potential fluctuations. Furthermore, most three-level inverter carrier modulation strategies often only consider a single optimization objective. However, for applications such as new energy electric drive systems and energy storage systems, not only must high common-mode voltage be overcome, but neutral-point voltage oscillation under different modulation schemes must also be addressed. Summary of the Invention

[0005] The present invention aims to provide a method and apparatus for common-mode voltage suppression in a hybrid power device-based three-level inverter, addressing the challenges of conventional three-level inverter control in achieving a balanced balance between common-mode voltage suppression, midpoint potential balance, and switching losses. This invention achieves common-mode voltage suppression and midpoint potential balance by constructing a third carrier based on conventional dual-carrier PWM and employing zero-sequence voltage injection. This constructed third carrier not only achieves common-mode voltage suppression but also expands the range of injected zero-sequence voltage, providing more zero-sequence voltage options for midpoint potential balance and improving midpoint potential control capabilities.

[0006] The technical solutions provided by the present invention are as follows:

[0007] In a first aspect, the present invention provides a method for suppressing common-mode voltage of a hybrid power device-type three-level inverter, wherein the method adopts a three-carrier PWM method, wherein the three-carrier PWM method is to construct a third carrier with an opposite phase and the same frequency as the upper carrier or the lower carrier on the basis of the dual-carrier PWM method; the method comprises:

[0008] Comparing the amplitudes of the sinusoidal signals of the three-phase given reference voltages to obtain the maximum value, the middle value and the minimum value of the sinusoidal signals of the three-phase given reference voltages;

[0009] The maximum value, the middle value and the minimum value of the three-phase given reference voltage sinusoidal signal are added to the injected zero-sequence voltage respectively to obtain the maximum value, the middle value and the minimum value of the three-phase modulated signal;

[0010] The injected zero-sequence voltage is obtained by: introducing a common-mode voltage suppression condition to obtain an injected zero-sequence voltage range; then introducing a midpoint potential balance condition to compare the actual midpoint current with a midpoint current reference value, and selecting the optimal injected zero-sequence voltage within the injected zero-sequence voltage range according to a zero-sequence voltage selection rule;

[0011] On the basis of introducing common-mode voltage suppression and midpoint potential balance, the maximum value, middle value and minimum value of the three-phase modulated signal are compared with the three carriers in the three-carrier PWM to generate switching signals, which act on the hybrid power device combined three-level inverter to achieve common-mode voltage suppression.

[0012] In one embodiment, the form and range of the constructed third carrier are: when the middle value of the three-phase modulated signal is positive, the form of the third carrier is an upper carrier with an inverted phase and the same frequency, ranging from 0 to 1; when the middle value of the three-phase modulated signal is negative, the form of the third carrier is a lower carrier with an inverted phase and the same frequency, ranging from -1 to 0.

[0013] In one embodiment, the steps of obtaining the injected zero-sequence voltage range by introducing common-mode voltage suppression condition restrictions include:

[0014] Compare the three carriers with the maximum, middle and minimum values ​​of the three-phase modulation signal to obtain the switching sequence of the three phases;

[0015] Avoid using large common-mode voltage basic vectors to ensure that the switching sequence meets the seven-segment type, and limit the duty cycle of the basic space vector of the switching sequence with low common-mode voltage.

[0016] Different switching sequences are obtained by judging the positive and negative values ​​of the intermediate values ​​of the three-phase modulation signal. According to the basic space vector duty cycle constraint conditions of the switching sequence, the maximum and minimum values ​​of the zero-sequence voltage under different signs of the intermediate values ​​of the three-phase modulation signal are calculated respectively, thereby obtaining the range of the injected zero-sequence voltage.

[0017] In one embodiment, the three carriers are compared with the maximum value, the middle value, and the minimum value of the three-phase modulation signal to obtain the three-phase switching sequence, and the specific steps include:

[0018] Compare the upper carrier wave with the maximum value, the lower carrier wave with the minimum value, and the constructed third carrier wave with the middle value;

[0019] When the middle value of the three-phase modulated signal is positive, the constructed third carrier range is from 0 to 1, and the switching sequence obtained after comparison is POP;

[0020] When the middle value of the three-phase modulated signal is negative, the constructed third carrier range is from -1 to 0, and the switching sequence obtained after comparison is ONO.

[0021] In one embodiment, in a switching sequence in which the intermediate value of the three-phase modulated signal is positive, in order to reduce the amplitude of the common-mode voltage and avoid using the large common-mode voltage basic vectors PPO, POP, and OPP while ensuring that the switching sequence is a seven-segment type, the duty cycle of the basic space vector of the switching sequence with low common-mode voltage is restricted, and the three-phase O state time relationship is obtained:

[0022] ,

[0023] Where, express Phase O state time, express Phase O state time, express Phase O state time, is the carrier period;

[0024] Calculate the O state time of the three phases based on the principle of volt-second balance equation , specifically:

[0025] ,

[0026] Where, Represents a three-phase modulated signal.

[0027] In one embodiment, the intermediate values ​​of the three-phase modulated signal are the maximum and minimum values ​​of the zero-sequence voltage under different signs, and the ranges of the injected zero-sequence voltage are:

[0028] At the middle value of the three-phase modulated signal When it is positive, the injected zero-sequence voltage The minimum and maximum values ​​of are:

[0029] ,

[0030] Where, , are the middle values ​​of the three-phase modulation signals is the zero-sequence voltage injected at the right time The minimum and maximum values ​​of 、 、 are the maximum, median and minimum values ​​of the given three-phase reference voltage sinusoidal signal, is the DC bus voltage;

[0031] Injected zero-sequence voltage Range The following relationship is satisfied:

[0032] ,

[0033] At the middle value of the three-phase modulated signal When it is negative, the injected zero-sequence voltage The minimum and maximum values ​​of are:

[0034] ,

[0035] Where, , are the middle values ​​of the three-phase modulation signals The injected zero-sequence voltage is negative The minimum and maximum values ​​of

[0036] Injected zero-sequence voltage Range The following relationship is satisfied:

[0037] ,

[0038] Among them, the maximum value, median value and minimum value of the three-phase given reference voltage sinusoidal signal are expressed as:

[0039] , , ,

[0040] ,

[0041] Where m is defined as the modulation index and θ is the phase position of the reference voltage vector.

[0042] In one embodiment, the method further introduces a midpoint potential balance condition constraint, compares the actual midpoint current with the midpoint current reference value, and selects the optimal injected zero-sequence voltage within the injected zero-sequence voltage range according to the zero-sequence voltage selection rule. The specific steps include:

[0043] According to Kirchhoff's voltage-current law, the DC side midpoint voltage deviation is closed-loop regulated by the PI controller to generate a midpoint current reference value;

[0044] The relationship between the average value of the actual midpoint current in a single carrier cycle and the injected zero-sequence voltage is simplified to a first-order function relationship;

[0045] Calculate the average value of the actual midpoint current corresponding to the maximum and minimum values ​​of the zero-sequence voltage;

[0046] The injected zero-sequence voltage interval is selected according to the positive or negative middle value of the three-phase modulation signal, and the average value of the actual midpoint current corresponding to the maximum and minimum values ​​of the zero-sequence voltage is compared with the midpoint current reference value. A zero-sequence voltage selection rule is formulated to select the optimal injected zero-sequence voltage.

[0047] In one embodiment, the relationship between the average value of the actual midpoint current in a single carrier cycle and the injected zero-sequence voltage is simplified to a first-order function relationship based on the following: Average value satisfy:

[0048] ,

[0049] Where, 、 and Respectively represent phase 、 and Current;

[0050] The O state time of the three phases , j = max, mid and min, substitute the midpoint current Average value The average midpoint current after zero-sequence voltage injection is obtained from the formula:

[0051] ,

[0052] in: , ,

[0053] Where, is the injected zero-sequence voltage, is the coefficient of the first-order function, is a first-order function in the zero-sequence voltage The midpoint current is 0, is the middle value of the three-phase modulation signal, is the DC bus voltage.

[0054] In one embodiment, the injected zero-sequence voltage interval is selected based on the positive or negative value of the middle value of the three-phase modulated signal, and the average value of the actual midpoint current corresponding to the maximum and minimum values ​​of the zero-sequence voltage is compared with the midpoint current reference value, a zero-sequence voltage selection rule is formulated, and the optimal injected zero-sequence voltage is selected. The specific steps include:

[0055] The middle value of the three-phase modulated signal The maximum and minimum values ​​when it is positive are 、 , the middle value of the three-phase modulation signal The maximum and minimum values ​​when negative are 、 ;

[0056] Will 、 、 、 The actual midpoint current corresponding to the four special zero-sequence voltages The average values ​​of 、 、 、 ;

[0057] exist and When the middle value of the three-phase modulation signal is is positive, and the zero-sequence voltage selection rule is:

[0058] when The optimal injection zero sequence voltage is selected based on the following: The special zero-sequence voltage corresponding to the closest actual midpoint current is used as the optimal injected zero-sequence voltage;

[0059] when When the midpoint current and the injected zero-sequence voltage are first-order functions, the special zero-sequence voltage 、 and its corresponding midpoint current 、 Calculate an optimal zero-sequence voltage , that is, the optimal injected zero-sequence voltage exist 、 and Select from among: ;

[0060] exist and When the middle value of the three-phase modulation signal is is negative, the zero-sequence voltage selection rule is:

[0061] when The optimal injection zero sequence voltage is selected based on the following: The special zero-sequence voltage corresponding to the closest actual midpoint current is used as the optimal injected zero-sequence voltage;

[0062] when When the midpoint current and the injected zero-sequence voltage are first-order functions, the special zero-sequence voltage 、 and its corresponding midpoint current 、 Calculate an optimal zero-sequence voltage , that is, the optimal injected zero-sequence voltage exist 、 and Select from: ;

[0063] exist and When the middle value of the three-phase modulation signal is Is positive or negative, the zero sequence voltage selection rule is:

[0064] when and When the optimal injected zero sequence voltage is selected, the basis for selecting is: 、 、 、 The midpoint current corresponding to the four special zero-sequence voltages is closest to the midpoint current reference value The special zero-sequence voltage of is used as the optimal injected zero-sequence voltage; when and When selecting As the zero-sequence voltage for optimal injection;

[0065] when and When selecting As the zero-sequence voltage for optimal injection;

[0066] when and When the intermediate value of the three-phase modulation signal Is positive or negative, the middle value of the three-phase modulation signal to be judged In the positive and negative of the previous carrier cycle, that is, The positive and negative and Select from;

[0067] when For positive time, select As the zero-sequence voltage for optimal injection;

[0068] when When it is negative, select As the optimal injected zero-sequence voltage; that is, the optimal injected zero-sequence voltage exist 、 、 、 、 and Select from; among them, is the middle value of the three-phase modulation signal of the previous carrier cycle, and k is the number of carrier cycles.

[0069] The present invention also provides a hybrid power device type three-level inverter common mode voltage suppression device, used to implement the above hybrid power device type three-level inverter common mode voltage suppression method, the device adopts a three-carrier PWM, the three-carrier PWM form is based on the dual-carrier PWM to construct a third carrier with an opposite phase and the same frequency as the upper carrier or the lower carrier; the device includes:

[0070] A three-phase reference voltage amplitude comparison module is used to compare the amplitudes of the sinusoidal signals of the three-phase given reference voltages and obtain the maximum, middle and minimum values ​​of the sinusoidal signals of the three-phase given reference voltages;

[0071] A three-phase modulation signal acquisition module is used to add the maximum value, middle value and minimum value of the three-phase given reference voltage sinusoidal signal to the injected zero-sequence voltage respectively to obtain the maximum value, middle value and minimum value of the three-phase modulation signal;

[0072] The three-carrier PWM comparison module is used to compare the maximum, intermediate, and minimum values ​​of the three-phase modulated signal with the three carriers in the three-carrier PWM, based on the introduction of common-mode voltage suppression and midpoint potential balance, to generate switching signals, which act on the hybrid power device combined three-level inverter to achieve common-mode voltage suppression;

[0073] The injected zero-sequence voltage is obtained by the following modules: an injected zero-sequence voltage range calculation module based on common-mode voltage suppression, which is used to obtain the injected zero-sequence voltage range by introducing common-mode voltage suppression condition restrictions;

[0074] A midpoint current reference value acquisition module is used to calculate the midpoint current reference value for achieving midpoint potential balance by introducing a PI controller;

[0075] The optimal injected zero-sequence voltage selection module based on midpoint balance is used to compare the actual midpoint current with the midpoint current reference value by introducing the midpoint potential balance condition restriction, and select the optimal injected zero-sequence voltage within the injected zero-sequence voltage range according to the zero-sequence voltage selection rule.

[0076] Beneficial effects of the present invention: 1. The present invention adopts a hybrid IGBT and SiC MOSFET device combination, replacing the high-frequency IGBT switch part with a SiC MOSFET device to reduce losses, and using IGBT in the low-frequency switch part to reduce costs. The hybrid device combination is used to balance the losses and costs of the three-level inverter. In addition, the design of the hybrid power device combination not only reduces the voltage stress on the device, but also improves the power density of the system. The present invention adopts a seven-segment switching sequence with a small number of switching times, which can further reduce switching losses in the hybrid device combination three-level inverter.

[0077] 2. The present invention suppresses common-mode voltage and mid-point potential fluctuations by combining three-carrier PWM and zero-sequence voltage injection. By constructing a third carrier on the basis of the traditional dual-carrier, it is possible to avoid using a large common-mode voltage vector while expanding the range of injected zero-sequence voltage, providing more optimal zero-sequence voltage options for mid-point potential balance. This method not only increases the service life of the inverter by reducing the common-mode voltage, but also reduces the mid-point potential fluctuations of the three-level inverter, effectively solving the problem of traditional three-level inverter control in terms of common-mode voltage suppression, mid-point potential balance, and current harmonic suppression.

[0078] 3. The midpoint potential balancing method for optimal zero-sequence voltage selection employed in this invention not only effectively reduces low-frequency fluctuations in the midpoint potential under steady-state conditions, but also accelerates the dynamic recovery of the DC bus voltage under external influences. Furthermore, this method can reduce the size of the DC bus capacitor, further reducing the cost of hybrid power device-based inverters, minimizing the impact of midpoint balancing on the DC bus capacitor, and increasing its service life.

[0079] 4. The present invention selects four specific zero-sequence voltages based on the state of the three-phase modulation signal, calculates the corresponding real-time midpoint current, and simultaneously calculates two optimal zero-sequence voltages based on the first-order functional relationship between the zero-sequence voltage and the midpoint current. This method achieves midpoint potential balance across the entire zero-sequence voltage range of common-mode voltage suppression by selecting from the six zero-sequence voltages based on the state of the three-phase modulation signal, effectively simplifying the calculation process of the injected zero-sequence voltage for midpoint potential balance.

[0080] 5. This invention utilizes a carrier-based PWM method combined with zero-sequence voltage injection to achieve multi-objective optimization, avoiding the cumbersome vector selection and duty cycle calculation required by traditional SVPWM methods to achieve common-mode voltage and midpoint potential balance. This reduces system complexity and computational effort, and can be extended to modulation strategies for multilevel topologies by simply varying the number and form of carriers within the existing method. BRIEF DESCRIPTION OF THE DRAWINGS

[0081] The accompanying drawings, as part of this disclosure, are provided to provide a further understanding of the present invention. The exemplary embodiments of the present invention and their descriptions are intended to explain the present invention but are not intended to limit the present invention. The common-mode voltage suppression method for a hybrid power device-based three-level inverter of the present invention is hereinafter referred to as 3CBPWM.

[0082] Figure 1 A flow chart of a common-mode voltage suppression method for a hybrid power device-type three-level inverter provided by one embodiment of the present invention;

[0083] Figure 2A topological diagram of a three-level inverter combining hybrid power devices provided in one embodiment of the present invention;

[0084] Figure 3 This is a common-mode voltage suppression principle diagram of a three-carrier PWM system according to an embodiment of the present invention. Figure 3 (a) is the middle value of the three-phase modulation signal This is the schematic diagram of positive common-mode voltage suppression. Figure 3 (b) is the middle value of the three-phase modulation signal This is the schematic diagram of negative common-mode voltage suppression;

[0085] Figure 4 The optimal injected zero-sequence voltage selection flow chart based on the midpoint potential balance target is shown in the figure. Figure 4 (a) is and Optimal zero-sequence voltage selection diagram under ; Figure 4 (b) is and Optimal zero-sequence voltage selection diagram under ; Figure 4 (c) is and Optimal zero-sequence voltage selection diagram under ;

[0086] Figure 5 A control block diagram of a common-mode voltage suppression device for a hybrid power device-type three-level inverter provided by one embodiment of the present invention;

[0087] Figure 6 The comparison diagram of the injected zero-sequence voltage range of the traditional PDPWM, PODPWM and the 3CBPWM method proposed in this invention when the modulation index is 0.3, 0.6, 0.9 and 1.1 respectively. Figure 6 (a) is the modulation index m=0.3; Figure 6 Middle (b) is the modulation index m=0.6; Figure 6 Middle (c) is the modulation index m = 0.9; Figure 6 Middle (d) is the modulation index m = 1.1;

[0088] Figure 7 The figure is a comparison of the midpoint potential controllable range of PODPWM and the 3CBPWM method proposed in the present invention when the load power angle is 80 degrees and 45 degrees respectively. Figure 7 (a) is the controllable range of the midpoint potential of PODPWM when the load power angle is 80 degrees; Figure 7 (b) shows the controllable range of the midpoint potential of 3CBPWM when the load power angle is 80 degrees; Figure 7 (c) is the controllable range of the midpoint potential of PODPWM when the load power angle is 45 degrees; Figure 7(d) is the controllable range of the midpoint potential of 3CBPWM when the load power angle is 45 degrees;

[0089] Figure 8 This is a comparison chart of the experimental results of the phase a terminal voltage, common mode voltage, and phase a current of the traditional PDPWM, PODPWM, and the 3CBPWM method proposed in this invention under the conditions of modulation index m = 0.3, fundamental frequency 10 Hz, and load power factor = 0.327;

[0090] Figure 9 This is a comparison chart of the midpoint potential experimental results of the traditional PDPWM, PODPWM and the 3CBPWM method proposed in this invention under the conditions of modulation index m=0.3, fundamental frequency of 10Hz and load power factor=0.327;

[0091] Figure 10 This is a comparison of the experimental results of the a-phase terminal voltage, common-mode voltage, and a-phase current of the traditional PDPWM, PODPWM, and the 3CBPWM method proposed in this invention under the conditions of modulation index m = 0.5, fundamental frequency 20 Hz, and load power factor = 0.174;

[0092] Figure 11 This is a comparison chart of the midpoint potential experimental results of the traditional PDPWM, PODPWM and the 3CBPWM method proposed in this invention under the conditions of modulation index m=0.5, fundamental frequency of 20Hz and load power factor=0.174;

[0093] Figure 12 This is a comparison of the dynamic equilibrium time of the midpoint potential of the PODPWM method and the 3CBPWM method proposed in the present invention at a base frequency of 10 Hz, a load power factor of 0.327, and a modulation index m=0.3;

[0094] Figure 13 This is the load current FFT analysis comparison result of PODPWM and the 3CBPWM method proposed in this invention when the base frequency is 10Hz, the load power factor is 0.327, and the modulation index m=0.3. Figure 13 (a) is PODPWM, Figure 13 (b) shows the proposed 3CBPWM method.

[0095] It should be noted that these drawings and textual descriptions are not intended to limit the conceptual scope of the present invention in any way, but rather to illustrate the concept of the present invention for those skilled in the art by referring to specific embodiments. DETAILED DESCRIPTION

[0096] In order to make the purpose, technical solutions and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments will be clearly and completely described below in conjunction with the drawings in the embodiments of the present invention. The following embodiments are used to illustrate the present invention but are not used to limit the scope of the present invention.

[0097] In order to deepen the knowledge and understanding of the present invention, the technical solution of the present invention is further described below with reference to the accompanying drawings and specific embodiments.

[0098] like Figure 1 As shown, an embodiment of the present invention provides a common-mode voltage suppression method for a hybrid power device-type three-level inverter. The method adopts a three-carrier PWM. The three-carrier PWM is formed by constructing a third carrier with an opposite phase and the same frequency as the upper carrier or the lower carrier on the basis of the dual-carrier PWM. The method specifically includes the following steps:

[0099] Step S100: performing amplitude comparison on the sinusoidal signals of the three-phase given reference voltage to obtain the maximum value, the middle value and the minimum value of the sinusoidal signals of the three-phase given reference voltage.

[0100] Furthermore, the sinusoidal signal of the three-phase reference voltage , , Compare and obtain the maximum, middle and minimum values ​​of the three-phase reference voltage signal 、 and for:

[0101] , , ,

[0102] ,

[0103] Where m is defined as the modulation index, θ is the phase position of the reference voltage vector, is the DC bus voltage.

[0104] According to the calculation formula of the three-phase reference voltage sinusoidal signal, the sinusoidal signal , , are three sinusoidal signals with a difference of 120 degrees. By sorting the three-phase reference voltage signals, we can get is positive, is negative, Can be positive or negative.

[0105] In an optional embodiment, the form and range of the constructed third carrier are: when the middle value of the three-phase modulation signal is positive, the form of the third carrier is an upper carrier with an inverted phase and the same frequency, ranging from 0 to 1; when the middle value of the three-phase modulation signal is negative, the form of the third carrier is a lower carrier with an inverted phase and the same frequency, ranging from -1 to 0.

[0106] In an optional embodiment, the three-phase bridge arms of the hybrid power device combination type three-level inverter are all composed of a mixture of IGBT and SiC MOSFET devices, and the high-frequency switching part of the bridge arm is a SiC MOSFET device.

[0107] Figure 2 The topology diagram of a hybrid power device combined three-level inverter includes a DC bus power supply , upper and lower DC bus capacitors and , the A-phase bridge arm consists of power switching devices - Composition, of which 、 、 、 For IGBT device modules, and It is a SiC MOSFET device module, and the B-phase bridge arm consists of power switching devices - Composition, of which 、 、 、 For IGBT device modules, and It is a SiC MOSFET device module, and the C-phase bridge arm consists of power switching devices - Composition, of which 、 、 、 For IGBT device modules, and It is a SiC MOSFET device module, a three-phase AC filter and a three-phase AC power grid. Point O is the midpoint of the DC bus capacitor, and points a, b, and c are the AC output ends of the three-phase bridge arm.

[0108] Step S200: adding the maximum value, the middle value and the minimum value of the given three-phase reference voltage sinusoidal signal to the injected zero-sequence voltage respectively to obtain the maximum value, the middle value and the minimum value of the three-phase reference voltage sinusoidal signal.

[0109] Furthermore, the injected zero-sequence voltage is obtained by introducing a common-mode voltage suppression condition restriction to obtain the injected zero-sequence voltage range, and then by introducing a midpoint potential balance condition restriction, the actual midpoint current is compared with the midpoint current reference value, and the optimal injected zero-sequence voltage is selected within the injected zero-sequence voltage range according to the zero-sequence voltage selection rule.

[0110] In the embodiment of the present application, by introducing the common-mode voltage suppression condition restriction, the injected zero-sequence voltage range is obtained, and the specific steps include:

[0111] Step S210: Compare the three carriers with the maximum value, the middle value and the minimum value of the three-phase modulation signal respectively to obtain a three-phase switching sequence.

[0112] Furthermore, the three carriers are compared with the maximum value, the middle value and the minimum value of the three-phase modulation signal respectively to obtain the three-phase switching sequence. The specific steps include:

[0113] Compare the upper carrier wave with the maximum value, the lower carrier wave with the minimum value, and the constructed third carrier wave with the middle value;

[0114] The constructed third carrier is compared with the middle value of the three-phase modulation signal. When the middle value of the three-phase modulation signal is positive, the constructed third carrier range is 0 to 1, and the switching sequence obtained after comparison is POP; when the middle value of the three-phase modulation signal is negative, the constructed third carrier range is -1 to 0, and the switching sequence obtained after comparison is ONO.

[0115] Conventional SVPWM, which effectively achieves common-mode voltage suppression and midpoint potential balancing, often uses a nine-segment switching sequence. For example, virtual space vector PWM requires the synthesis of small and medium vectors from adjacent vectors to achieve midpoint potential balancing and common-mode voltage suppression. This process requires frequent switching states and is unsuitable for hybrid power device inverters. The carrier PWM employed in this invention uses a seven-segment switching sequence, resulting in fewer switching cycles and further reducing switching losses in hybrid power device three-level inverters.

[0116] Step S211: avoid using a large common mode voltage basic vector so that the switching sequence satisfies the seven-segment type, and at the same time limit the duty cycle of the basic space vector of the switching sequence with a low common mode voltage.

[0117] Furthermore, in the switching sequence with a positive intermediate value of the three-phase modulation signal, in order to reduce the amplitude of the common-mode voltage and avoid using the large common-mode voltage basic vectors PPO, POP, and OPP, while ensuring that the switching sequence is a seven-segment type, the duty cycle of the basic space vector of the switching sequence with a low common-mode voltage is restricted, and the three-phase O state time relationship is obtained:

[0118] ,

[0119] Where, express Phase O state time, express Phase O state time, express Phase O state time, is the carrier period.

[0120] like Figure 3 As shown, Figure 3 (a) is the middle value of the three-phase modulation signal This is the schematic diagram of positive common-mode voltage suppression. Figure 3 (b) is the middle value of the three-phase modulation signal The negative common-mode voltage suppression principle diagram is shown in Figure 2. Calculate the O state time of the three phases. (j=max, mid and min) represents the carrier period of phase j The interval of state O in half of the time. Calculate the O state time of the three phases according to the principle of volt-second balance equation , j = max, mid and min, specifically:

[0121] ,

[0122] Where, Represents a three-phase modulated signal.

[0123] Step S212: Different switching sequences are obtained by judging whether the intermediate value of the three-phase modulation signal is positive or negative, and the maximum and minimum values ​​of the zero-sequence voltage under different signs of the intermediate value of the three-phase modulation signal are calculated according to the basic space vector duty cycle restriction condition of the switching sequence, thereby obtaining the range of the injected zero-sequence voltage.

[0124] According to the restriction condition of introducing common mode voltage suppression, the injected zero sequence voltage can be obtained The following relationship is satisfied: ,

[0125] Depend on Figure 3 As can be seen from (a) and (b), the three-phase modulated signal satisfies the following relationship: ,

[0126] The injected zero-sequence voltage satisfies the following relationship: .

[0127] Furthermore, the middle value of the three-phase modulation signal is the maximum and minimum value of the zero-sequence voltage under different signs, and the range of the injected zero-sequence voltage is: the middle value of the three-phase modulation signal When it is positive, the injected zero-sequence voltage The maximum and minimum values ​​of are:

[0128] ,

[0129] Where, , are the middle values ​​of the three-phase modulation signals is the zero-sequence voltage injected at the right time The minimum and maximum values ​​of 、 、 are the maximum, median and minimum values ​​of the given three-phase reference voltage sinusoidal signal, is the DC bus voltage;

[0130] Injected zero-sequence voltage Range The following relationship is satisfied: ,

[0131] At the middle value of the three-phase modulated signal When it is negative, the injected zero-sequence voltage The maximum and minimum values ​​of are:

[0132] ,

[0133] Where, , are the middle values ​​of the three-phase modulation signals The injected zero-sequence voltage is negative The minimum and maximum values ​​of

[0134] Injected zero-sequence voltage Range The following relationship is satisfied: .

[0135] In the embodiment of the present application, by introducing the midpoint potential balance condition restriction, the actual midpoint current is compared with the midpoint current reference value, and the optimal injected zero-sequence voltage is selected within the injected zero-sequence voltage range according to the zero-sequence voltage selection rule. The specific steps include:

[0136] Step S220: According to Kirchhoff's voltage-current law, a PI controller is used to perform closed-loop regulation on the DC side midpoint voltage deviation to generate a midpoint current reference value.

[0137] According to Kirchhoff's law and voltage law, the midpoint current can be obtained The relationship between the upper and lower DC capacitor voltages satisfies:

[0138] ,

[0139] Where C is the capacitance of the upper and lower capacitors of the DC bus, is the voltage of the upper DC bus capacitor, is the voltage of the lower DC bus capacitor, is the difference between the upper and lower DC bus voltages.

[0140] Through analysis, we can see that adjusting The size of can achieve midpoint potential balance, Reference value It can be obtained by controlling the difference between the upper and lower DC bus voltages through a PI controller.

[0141] Step S221: simplifying the relationship between the average value of the actual midpoint current within a single carrier cycle and the injected zero-sequence voltage into a first-order function relationship.

[0142] Furthermore, the relationship between the average value of the actual midpoint current in a single carrier cycle and the injected zero-sequence voltage is simplified to a first-order function relationship based on the following: the midpoint current in a carrier cycle Average value satisfy:

[0143] ,

[0144] Where, 、 and Respectively represent phase 、 and Current;

[0145] The O state time of the three phases , j = max, mid and min, substitute the midpoint current Average value The average midpoint current after zero-sequence voltage injection is obtained from the formula:

[0146] ,

[0147] in: ,

[0148] ,

[0149] Where, is the injected zero-sequence voltage, is the coefficient of the first-order function, is a first-order function in the zero-sequence voltage The midpoint current is 0, is the middle value of the three-phase modulation signal, is the DC bus voltage.

[0150] From the above, it can be found that the actual average value of the midpoint current in a single carrier cycle is related to the injected zero-sequence voltage and the three-phase given reference voltage, and satisfies the first-order function relationship.

[0151] Step S222: Calculate the average value of the actual midpoint current corresponding to the maximum and minimum values ​​of the zero-sequence voltage.

[0152] Step S223: selecting an injected zero-sequence voltage interval according to the positive or negative value of the middle value of the three-phase modulation signal.

[0153] Step S224: Compare the average value of the actual midpoint current corresponding to the maximum and minimum values ​​of the zero-sequence voltage with the midpoint current reference value, formulate a zero-sequence voltage selection rule, and select the optimal injected zero-sequence voltage. Figure 4 As shown, Figure 4 (a) is and The optimal zero-sequence voltage selection diagram under Figure 4 (b) is and The optimal zero-sequence voltage selection diagram under Figure 4 (c) is and Optimal zero-sequence voltage selection diagram under .

[0154] The injected zero-sequence voltage From the calculation formula, it can be seen that the injected zero-sequence voltage under common-mode voltage suppression is a continuous range. The maximum and minimum values ​​when it is positive are 、 ,exist The maximum and minimum values ​​when negative are 、 , where there are countless zero-sequence voltages.

[0155] Will 、 、 、 Actual midpoint current of four special zero-sequence voltages The mean values ​​are defined as 、 、 、 .

[0156] exist and When the middle value of the three-phase modulation signal is is positive, and the zero-sequence voltage selection rule is:

[0157] when The optimal injection zero sequence voltage is selected based on the following criteria: The special zero-sequence voltage corresponding to the closest actual midpoint current is used as the optimal injected zero-sequence voltage;

[0158] when When the midpoint current and the injected zero-sequence voltage are first-order functions, the special zero-sequence voltage 、 and its corresponding midpoint current 、 Calculate an optimal zero-sequence voltage , that is, the optimal injected zero-sequence voltage exist 、 and Select from among:

[0159] ,

[0160] exist and When the middle value of the three-phase modulation signal is is negative, the zero-sequence voltage selection rule is:

[0161] when The optimal injection zero sequence voltage is selected based on the following: The special zero-sequence voltage corresponding to the closest actual midpoint current is used as the optimal injected zero-sequence voltage;

[0162] when When the midpoint current and the injected zero-sequence voltage are first-order functions, the special zero-sequence voltage 、 and its corresponding midpoint current 、 Calculate an optimal zero-sequence voltage , that is, the optimal injected zero-sequence voltage exist 、 and Select from:

[0163] ,

[0164] exist and When the middle value of the three-phase modulation signal is Is positive or negative, the zero sequence voltage selection rule is:

[0165] when and When the optimal injected zero sequence voltage is selected, the basis for selecting is: 、 、 、 The midpoint current corresponding to the four special zero-sequence voltages is closest to the midpoint current reference value The special zero-sequence voltage of is used as the optimal injected zero-sequence voltage;

[0166] when and When selecting As the zero-sequence voltage for optimal injection;

[0167] when and When selecting As the zero-sequence voltage for optimal injection;

[0168] when and When the intermediate value of the three-phase modulation signal Is positive or negative, the middle value of the three-phase modulation signal to be judged In the positive and negative of the previous carrier cycle, that is, The positive and negative and Select from;

[0169] when For positive time, select As the zero-sequence voltage for optimal injection;

[0170] when When it is negative, select As the optimal injected zero-sequence voltage; that is, the optimal injected zero-sequence voltage exist 、 、 、 、 and Select from; among them, is the middle value of the three-phase modulation signal of the previous carrier cycle, and k is the number of carrier cycles.

[0171] The optimal injected zero-sequence voltage is selected according to the midpoint potential balance condition, the state of the three-phase modulation signal and the optimal zero-sequence voltage selection rule to achieve midpoint potential balance.

[0172] Step S300: Based on the introduction of common-mode voltage suppression and midpoint potential balance, the maximum value, middle value and minimum value of the obtained three-phase modulated signal are compared with the three carriers to generate switching signals, which act on the hybrid power device combined three-level inverter.

[0173] Specifically, the upper carrier, the constructed third carrier and the lower carrier are compared with the maximum value, the middle value and the minimum value of the three-phase modulation signal respectively, the maximum value of the three-phase modulation signal is compared with the carrier in the range of 0 to 1, the middle value of the three-phase modulation signal is compared with the constructed inverted third carrier, and the minimum value of the three-phase modulation signal is compared with the carrier in the range of -1 to 0, and the hybrid power device combined three-level inverter is applied.

[0174] By constructing a third carrier based on the traditional dual-carrier PWM and adopting the zero-sequence voltage injection method to avoid the use of large common-mode voltage basic vectors, and selecting the optimal injected zero-sequence voltage within the zero-sequence voltage range of the common-mode voltage suppression condition to achieve mid-point potential balance, this method can not only increase the service life of the inverter by reducing the common-mode voltage, but also reduce the mid-point potential fluctuation of the three-level inverter, effectively solving the problem that traditional three-level inverter control is difficult to take into account in terms of common-mode voltage suppression, mid-point potential balance and current harmonic suppression.

[0175] like Figure 5 As shown, the present invention provides a hybrid power device type three-level inverter common mode voltage suppression device, the device adopts three-carrier PWM, the form of three-carrier PWM is to construct a third carrier with opposite phase and same frequency as the upper carrier or the lower carrier on the basis of dual-carrier PWM; the device includes: a three-phase reference voltage amplitude comparison module 1, a three-phase modulation signal acquisition module 2, a three-carrier PWM comparison module 3, an injection zero-sequence voltage range calculation module 4 based on common mode voltage suppression, a midpoint current reference value acquisition module 5, and an optimal injection zero-sequence voltage selection module 6 based on midpoint balance, wherein,

[0176] A three-phase reference voltage amplitude comparison module 1 is used to compare the amplitudes of the sinusoidal signals of the three-phase given reference voltages to obtain the maximum value, the middle value and the minimum value of the sinusoidal signals of the three-phase given reference voltages;

[0177] The three-phase modulation signal acquisition module 2 is used to add the maximum value, the middle value and the minimum value of the three-phase given reference voltage sinusoidal signal to the injected zero-sequence voltage respectively to obtain the maximum value, the middle value and the minimum value of the three-phase modulation signal;

[0178] The three-carrier PWM comparison module 3 is used to compare the maximum value, intermediate value and minimum value of the three-phase modulation signal with the three carriers in the three-carrier PWM on the basis of introducing common-mode voltage suppression and mid-point potential balance, generate switching signals, and act on the hybrid power device combined three-level inverter to achieve common-mode voltage suppression;

[0179] The injected zero-sequence voltage is obtained by the following modules:

[0180] An injection zero-sequence voltage range calculation module 4 based on common-mode voltage suppression is used to obtain an injection zero-sequence voltage range by introducing common-mode voltage suppression condition restrictions;

[0181] A midpoint current reference value acquisition module 5 is used to calculate a midpoint current reference value for achieving midpoint potential balance by introducing a PI controller;

[0182] The optimal injected zero-sequence voltage selection module 6 based on midpoint balance is used to compare the actual midpoint current with the midpoint current reference value by introducing the midpoint potential balance condition restriction, and select the optimal injected zero-sequence voltage within the injected zero-sequence voltage range according to the zero-sequence voltage selection rule.

[0183] Specifically, the three-phase reference voltage amplitude comparison module 1 compares the sinusoidal signal of the three-phase reference voltage , , Compare and obtain the maximum, middle and minimum values ​​of the three-phase reference voltage sinusoidal signal 、 and The three-carrier PWM comparison module 3 compares the three-phase reference voltage signal and the sum of the injected zero-sequence voltage with the three carriers to generate a switching signal, which acts on the hybrid power device combination three-level inverter 7. The hybrid power device combination three-level inverter 7 converts the switching signal into a target output voltage signal. The injection zero-sequence voltage range calculation module 4 based on common-mode voltage suppression calculates the maximum and minimum values ​​of the injected zero-sequence voltage by introducing the common-mode voltage suppression constraint, that is, avoiding the use of basic vectors with large common-mode voltage amplitudes and ensuring that the switching sequence is a seven-segment type. The midpoint current reference value acquisition module 5 obtains the reference value of the midpoint current by controlling the voltage difference between the upper and lower DC buses through a PI controller. The optimal injection zero-sequence voltage selection module 6 based on midpoint balance selects the optimal injection zero-sequence voltage based on the midpoint potential balance condition within the injection zero-sequence voltage range obtained in the injection zero-sequence voltage range calculation module 4 based on common-mode voltage suppression to achieve midpoint potential balance.

[0184] The present invention can be extended to the modulation strategy of multi-level topology by only changing the number and form of carriers based on the existing method. However, traditional three-level multi-objective optimization strategies, including model prediction and SVPWM, are often accompanied by the exponential growth of basic space vectors in multi-level topology, making the implementation of modulation in multi-level topology more difficult.

[0185] It should be noted that the hybrid power device-based three-level inverter common-mode voltage suppression device provided in the above embodiment, when executing the hybrid power device-based three-level inverter common-mode voltage suppression method, is only illustrated by the division of the above-mentioned functional modules. In actual applications, the above-mentioned functions can be assigned to different functional modules as needed, that is, the internal structure of the device can be divided into different functional modules to complete all or part of the functions described above. In addition, the hybrid power device-based three-level inverter common-mode voltage suppression device provided in the above embodiment and the hybrid power device-based three-level inverter common-mode voltage suppression method embodiment are based on the same concept. The implementation process is detailed in the hybrid power device-based three-level inverter common-mode voltage suppression method embodiment, and will not be repeated here.

[0186] The common mode voltage suppression method of the hybrid power device three-level inverter is referred to as 3CBPWM below. Figure 6 As shown, Figure 6 Figures (a), (b), (c), and (d) show the comparison results of the injected zero-sequence voltage ranges of conventional PDPWM, PODPWM, and the proposed 3CBPWM for modulation indices of 0.3, 0.6, 0.9, and 1.1, respectively. Of the three methods, conventional PDPWM has the widest injected zero-sequence voltage range, without considering the common-mode voltage reduction target, but does not suppress the common-mode voltage. Compared to PODPWM, the proposed 3CBPWM method significantly expands the injected zero-sequence voltage range under low-profile conditions. Because the proposed method's injected zero-sequence voltage range is wider than PODPWM's, it offers greater selectivity for zero-sequence voltage when performing zero-sequence injection to achieve midpoint potential balance, and its midpoint potential is more controllable.

[0187] like Figure 7 As shown, Figure 7 (a) and (b) show the comparison results of the midpoint potential controllable range of PODPWM and the proposed 3CBPWM under a load power angle of 80 degrees. Figure 7 (c) and (d) show the comparison results of the controllable range of the midpoint potential of PODPWM and the proposed 3CBPWM at a load power angle of 45 degrees. The comparison shows that the controllable range of the proposed method is greatly improved compared with the traditional PODPWM method at different power angles.

[0188] like Figure 8The experimental results for the phase a terminal voltage, common-mode voltage, and phase a current for the three methods, PDPWM, PODPWM, and the proposed 3CBPWM, are shown under conditions of a 10Hz base frequency, a load power factor of 0.327, and a modulation index m of 0.3. The figure shows that the peak-to-peak common-mode voltage of the traditional PDPWM method, which does not consider common-mode voltage suppression, is 361.2V, while that of PODPWM is 180.7V. The peak-to-peak common-mode voltage of the proposed 3CBPWM method is limited to 180.2V, effectively suppressing the common-mode voltage to one-sixth of the DC bus voltage.

[0189] like Figure 9 Figure 2 shows the experimental results of the midpoint potential of the three methods, PDPWM, PODPWM, and the proposed 3CBPWM, under conditions of a 10Hz base frequency, a load power factor of 0.327, and a modulation index m of 0.3. The figure shows that the PODPWM midpoint potential exhibits significant third-order ripple, with the maximum difference between the upper and lower DC bus capacitor voltages reaching 18.7V. However, the proposed 3CBPWM midpoint potential fluctuates within 4.2V, significantly reducing its fluctuation range compared to the PODPWM.

[0190] like Figure 10 The experimental results for the a-phase terminal voltage, common-mode voltage, and a-phase current for the three methods, PDPWM, PODPWM, and the proposed 3CBPWM, are shown under conditions of a 20Hz base frequency, a load power factor of 0.174, and a modulation index m of 0.5. The figure shows that the peak-to-peak common-mode voltage of the traditional PDPWM method, which does not consider common-mode voltage suppression, is 361.4V, while that of PODPWM is 180.8V. The peak-to-peak common-mode voltage of the proposed 3CBPWM method is limited to less than 180.5V, effectively suppressing the common-mode voltage to one-sixth of the DC bus voltage.

[0191] like Figure 11 As shown in the figure, the experimental results of the midpoint potential of the three methods, PDPWM, PODPWM, and the proposed 3CBPWM, are presented under the conditions of a fundamental frequency of 20Hz, a load power factor of 0.174, and a modulation index m of 0.5. As can be seen from the figure, the midpoint potential of PODPWM still has obvious third-order ripple, and the voltage difference between the upper and lower DC bus capacitors reaches a maximum of 24.4V. However, the midpoint potential of the proposed 3CBPWM fluctuates within 12.1V, which is significantly smaller than that of PODPWM.

[0192] like Figure 12The figure shows a comparison of the dynamic balancing time of the midpoint potential between PODPWM and the proposed 3CBPWM method at a base frequency of 10 Hz, a load power factor of 0.327, and a modulation index of 0.3. The upper and lower DC bus capacitor voltages are initially set to 320 V and 220 V. The figure shows that compared to PODPWM, the proposed 3CBPWM method reduces the balancing time from 0.035 s to 0.02 s, a reduction of approximately 40%.

[0193] like Figure 13 As shown in Figure 1, the load current FFT analysis comparison results of PODPWM and the proposed 3CBPWM method are given when the base frequency is 10Hz, the load power factor is 0.327, and the modulation index m=0.3. FFT stands for fast Fourier transform, where Figure 13 (a) is the PODPWM method, Figure 13 (b) shows the proposed 3CBPWM method. As can be seen from the figure, compared with PODPWM, the proposed 3CBPWM has smaller low-order harmonics.

[0194] The above experimental results show that the common-mode voltage suppression method and device of the hybrid power device type three-level inverter provided by the embodiments of the present invention can suppress the common-mode voltage of the three-level inverter to one-sixth of the DC bus voltage, and the midpoint potential fluctuation is small.

[0195] The technical features of the above embodiments can be combined arbitrarily. To make the description concise, not all possible combinations of the technical features in the above embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0196] The above-described embodiments merely illustrate several implementations of the present invention, and while their descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the present invention. It should be noted that a person skilled in the art would be able to make numerous variations and improvements without departing from the spirit of the present invention, all of which fall within the scope of protection of the present invention. Therefore, the scope of protection of the present invention shall be determined by the appended claims.

Claims

1. A method for suppressing common-mode voltage of a hybrid power device three-level inverter, characterized by: The method adopts three-carrier PWM. The three-carrier PWM is formed by constructing a third carrier with an opposite phase and the same frequency as the upper carrier or the lower carrier on the basis of the dual-carrier PWM. The form and range of the constructed third carrier are: when the middle value of the three-phase modulation signal is positive, the third carrier is in the form of the upper carrier with the opposite phase and the same frequency, and the range is 0 to 1; when the middle value of the three-phase modulation signal is negative, the third carrier is in the form of the lower carrier with the opposite phase and the same frequency, and the range is -1 to 0. The method includes: Comparing the amplitudes of the sinusoidal signals of the three-phase given reference voltages to obtain the maximum value, the middle value and the minimum value of the sinusoidal signals of the three-phase given reference voltages; The maximum value, the middle value and the minimum value of the three-phase given reference voltage sinusoidal signal are added to the injected zero-sequence voltage respectively to obtain the maximum value, the middle value and the minimum value of the three-phase modulated signal; The injected zero-sequence voltage is obtained by: introducing a common-mode voltage suppression condition to obtain an injected zero-sequence voltage range; then introducing a midpoint potential balance condition to compare the actual midpoint current with a midpoint current reference value, and selecting the optimal injected zero-sequence voltage within the injected zero-sequence voltage range according to a zero-sequence voltage selection rule; According to the zero-sequence voltage selection rule, the optimal injected zero-sequence voltage is selected. The specific steps include: The middle value of the three-phase modulated signal The maximum and minimum values ​​when it is positive are 、 , ， Where, , are the middle values ​​of the three-phase modulation signals is the zero-sequence voltage injected at the right time The minimum and maximum values ​​of 、 、 are the maximum, median and minimum values ​​of the three-phase given reference voltage sinusoidal signals, is the DC bus voltage; , , , the sinusoidal signal of the three-phase reference voltage , , for: ， Where m is defined as the modulation index and θ is the phase position of the reference voltage vector; The middle value of the three-phase modulated signal The maximum and minimum values ​​when negative are 、 ; ， Where, , are the middle values ​​of the three-phase modulation signals The injected zero-sequence voltage is negative The minimum and maximum values ​​of Will 、 、 、 The actual midpoint current corresponding to the four special zero-sequence voltages The average values ​​of 、 、 、 ; ， Where C is the capacitance of the upper and lower capacitors of the DC bus, is the voltage of the upper DC bus capacitor, is the voltage of the lower DC bus capacitor, is the difference between the upper and lower DC bus voltages; exist and When the middle value of the three-phase modulation signal is is positive, and the zero-sequence voltage selection rule is: when The optimal injection zero sequence voltage is selected based on the following: The special zero-sequence voltage corresponding to the closest actual midpoint current is used as the optimal injected zero-sequence voltage; the midpoint current reference value The difference between the upper and lower DC bus voltages is controlled by a PI controller; when When the midpoint current and the injected zero-sequence voltage are first-order functions, the special zero-sequence voltage 、 and its corresponding midpoint current 、 Calculate an optimal zero-sequence voltage , that is, the optimal injected zero-sequence voltage exist 、 and Select from among: ； exist and When the middle value of the three-phase modulation signal is is negative, the zero-sequence voltage selection rule is: when The optimal injection zero sequence voltage is selected based on the following: The special zero-sequence voltage corresponding to the closest actual midpoint current is used as the optimal injected zero-sequence voltage; when When the midpoint current and the injected zero-sequence voltage are first-order functions, the special zero-sequence voltage 、 and its corresponding midpoint current 、 Calculate an optimal zero-sequence voltage , that is, the optimal injected zero-sequence voltage exist 、 and Select from among: ； exist and When the middle value of the three-phase modulation signal is Is positive or negative, the zero sequence voltage selection rule is: when and When the optimal injected zero sequence voltage is selected, the basis for selecting is: 、 、 、 The midpoint current corresponding to the four special zero-sequence voltages is closest to the midpoint current reference value The special zero-sequence voltage of is used as the optimal injected zero-sequence voltage; when and When selecting As the zero-sequence voltage for optimal injection; when and When selecting As the zero-sequence voltage for optimal injection; when and When the intermediate value of the three-phase modulation signal Is positive or negative, the middle value of the three-phase modulation signal to be judged In the positive and negative of the previous carrier cycle, that is, The positive and negative and Select from; when For positive time, select As the zero-sequence voltage for optimal injection; when When it is negative, select As the optimal injected zero-sequence voltage; that is, the optimal injected zero-sequence voltage exist 、 、 、 、 and Select from; among them, is the median value of the three-phase modulation signal of the previous carrier cycle, and k is the number of carrier cycles; On the basis of introducing common-mode voltage suppression and midpoint potential balance, the maximum value, middle value and minimum value of the three-phase modulated signal are compared with the three carriers in the three-carrier PWM to generate switching signals, which act on the hybrid power device combined three-level inverter to achieve common-mode voltage suppression.

2. The common-mode voltage suppression method for a hybrid power device-based three-level inverter according to claim 1, characterized in that: The injected zero-sequence voltage range is obtained by introducing the common-mode voltage suppression condition restriction, and the specific steps include: Compare the three carriers with the maximum, middle and minimum values ​​of the three-phase modulation signal to obtain the switching sequence of the three phases; Avoid using large common-mode voltage basic vectors to ensure that the switching sequence meets the seven-segment type, and limit the duty cycle of the basic space vector of the switching sequence with low common-mode voltage. Different switching sequences are obtained by judging the positive and negative values ​​of the intermediate values ​​of the three-phase modulation signal. According to the basic space vector duty cycle constraint conditions of the switching sequence, the maximum and minimum values ​​of the zero-sequence voltage under different signs of the intermediate values ​​of the three-phase modulation signal are calculated respectively, thereby obtaining the range of the injected zero-sequence voltage.

3. The common-mode voltage suppression method for a hybrid power device-based three-level inverter according to claim 2, characterized in that: The three carriers are compared with the maximum value, the middle value and the minimum value of the three-phase modulation signal respectively to obtain the three-phase switching sequence. The specific steps include: Compare the upper carrier wave with the maximum value, the lower carrier wave with the minimum value, and the constructed third carrier wave with the middle value; When the middle value of the three-phase modulated signal is positive, the constructed third carrier range is from 0 to 1, and the switching sequence obtained after comparison is POP; When the middle value of the three-phase modulated signal is negative, the constructed third carrier range is from -1 to 0, and the switching sequence obtained after comparison is ONO.

4. The method for suppressing common-mode voltage of a hybrid power device-based three-level inverter according to claim 3, wherein: In the switching sequence with a positive intermediate value of the three-phase modulation signal, in order to reduce the amplitude of the common-mode voltage and avoid using the large common-mode voltage basic vectors PPO, POP, and OPP, while ensuring that the switching sequence is a seven-segment type, the duty cycle of the basic space vector of the switching sequence with a low common-mode voltage is restricted, and the three-phase O state time relationship is obtained: ， Where, express Phase O state time, express Phase O state time, express Phase O state time, is the carrier period; Calculate the O state time of the three phases based on the principle of volt-second balance equation , specifically: ， Where, Represents a three-phase modulated signal.

5. The method for suppressing common-mode voltage of a hybrid power device-type three-level inverter according to claim 4, characterized in that: The intermediate values ​​of the three-phase modulated signal are the maximum and minimum values ​​of the zero-sequence voltage under different signs, and the ranges of the injected zero-sequence voltage are: At the middle value of the three-phase modulated signal When it is positive, the injected zero-sequence voltage The maximum and minimum values ​​of are: ， Where, , are the middle values ​​of the three-phase modulation signals is the zero-sequence voltage injected at the right time The minimum and maximum values ​​of 、 、 are the maximum, median and minimum values ​​of the three-phase given reference voltage sinusoidal signals, is the DC bus voltage; Injected zero-sequence voltage Range The following relationship is satisfied: ， At the middle value of the three-phase modulated signal When it is negative, the injected zero-sequence voltage The maximum and minimum values ​​of are: ， Where, , are the middle values ​​of the three-phase modulation signals The injected zero-sequence voltage is negative The minimum and maximum values ​​of Injected zero-sequence voltage Range The following relationship is satisfied: ， Among them, the maximum value, median value and minimum value of the three-phase given reference voltage sinusoidal signal are expressed as: ， ， ， ， Where m is defined as the modulation index and θ is the phase position of the reference voltage vector.

6. The method for suppressing common-mode voltage of a hybrid power device-type three-level inverter according to claim 1 or 5, characterized in that: The method then introduces a midpoint potential balance condition restriction, compares the actual midpoint current with the midpoint current reference value, and selects the optimal injected zero-sequence voltage within the injected zero-sequence voltage range according to the zero-sequence voltage selection rule. The specific steps include: According to Kirchhoff's voltage-current law, the DC side midpoint voltage deviation is closed-loop regulated by the PI controller to generate a midpoint current reference value; The relationship between the average value of the actual midpoint current in a single carrier cycle and the injected zero-sequence voltage is simplified to a first-order function relationship; Calculate the average value of the actual midpoint current corresponding to the maximum and minimum values ​​of the zero-sequence voltage; The injected zero-sequence voltage interval is selected according to the positive or negative middle value of the three-phase modulation signal, and the average value of the actual midpoint current corresponding to the maximum and minimum values ​​of the zero-sequence voltage is compared with the midpoint current reference value. A zero-sequence voltage selection rule is formulated to select the optimal injected zero-sequence voltage.

7. The method for suppressing common-mode voltage of a hybrid power device-based three-level inverter according to claim 6, characterized in that: The basis for simplifying the relationship between the average value of the actual midpoint current in a single carrier cycle and the injected zero-sequence voltage into a first-order function relationship is: the midpoint current in a carrier cycle Average value satisfy: ， Where, 、 and Respectively 、 and Phase current; The O state time of the three phases , j = max, mid and min, substitute the midpoint current Average value The average midpoint current after zero-sequence voltage injection is obtained from the formula: ， in: , ， Where, is the injected zero-sequence voltage, is the coefficient of the first-order function, is a first-order function in the zero-sequence voltage The midpoint current is 0, is the middle value of the three-phase modulation signal, is the DC bus voltage.

8. A hybrid power device type three-level inverter common mode voltage suppression device, characterized by: A method for suppressing common-mode voltage of a hybrid power device-type three-level inverter according to any one of claims 1 to 7, wherein the device adopts a three-carrier PWM, wherein the three-carrier PWM is formed by constructing a third carrier with a phase opposite to that of the upper carrier or the lower carrier and the same frequency as the lower carrier on the basis of the dual-carrier PWM; the device comprises: A three-phase reference voltage amplitude comparison module is used to compare the amplitudes of the sinusoidal signals of the three-phase given reference voltages and obtain the maximum, middle and minimum values ​​of the sinusoidal signals of the three-phase given reference voltages; A three-phase modulation signal acquisition module is used to add the maximum value, middle value and minimum value of the three-phase given reference voltage sinusoidal signal to the injected zero-sequence voltage respectively to obtain the maximum value, middle value and minimum value of the three-phase modulation signal; The three-carrier PWM comparison module is used to compare the maximum, intermediate, and minimum values ​​of the three-phase modulated signal with the three carriers in the three-carrier PWM, based on the introduction of common-mode voltage suppression and midpoint potential balance, to generate switching signals, which act on the hybrid power device combined three-level inverter to achieve common-mode voltage suppression; The injected zero-sequence voltage is obtained by the following modules: An injection zero-sequence voltage range calculation module based on common-mode voltage suppression is used to obtain the injection zero-sequence voltage range by introducing common-mode voltage suppression condition restrictions; A midpoint current reference value acquisition module is used to calculate the midpoint current reference value for achieving midpoint potential balance by introducing a PI controller; The optimal injected zero-sequence voltage selection module based on midpoint balance is used to compare the actual midpoint current with the midpoint current reference value by introducing the midpoint potential balance condition restriction, and select the optimal injected zero-sequence voltage within the injected zero-sequence voltage range according to the zero-sequence voltage selection rule.

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