High-voltage high-precision window comparator circuit

Abstract

The invention discloses a high-voltage high-precision window comparator circuit, which comprises an input pair circuit, an offset correction circuit, a polarity change-over switch, a current digital-to-analog converter and an active load, and is characterized in that the input pair circuit is used for converting a differential voltage signal into a first differential current signal, and the offset correction circuit is used for correcting differential current mismatch of the input pair circuit; the polarity change-over switch is used for switching the polarity of the input pair circuit connected to the active load and outputting a third differential current signal, and the current digital-to-analog converter is used for setting a window voltage and outputting a fourth differential current signal. The active load is used for amplifying the difference value of the third differential current signal and the fourth differential current signal and converting the difference value into a first logic level, and window detection is achieved by comparing the first logic levels before and after polarity switching of the polarity switching switch. Window detection of voltage signals is achieved through the single comparator, high-voltage input and accurate window voltage control are supported, and the circuit can be widely applied to the field of integrated circuit design.

Description

Technical Field

[0001] The present invention relates to the field of analog integrated circuit design, and in particular to a high-voltage and high-precision window comparator circuit. Background Art

[0002] In a neural stimulator system, in order to avoid problems such as tissue electrolysis and electrode damage caused by residual charges on the electrodes, a charge balance circuit needs to be added. As neural stimulators evolve towards highly integrated multi-channel systems, the area of the electrodes continues to shrink, and the tolerance threshold of the tissue and electrodes for residual charges also continues to decline.

[0003] A window comparator is a key module in the charge balance circuit of a neural stimulator, which is used to detect whether the potential difference between the stimulating electrodes exceeds a safety window, so as to judge whether the accumulated residual charges exceed the tolerance threshold. For a highly integrated neural stimulator system, the window comparator in its charge balance circuit needs to meet the following performance requirements:

[0004] 1. Adapt to a high input common-mode voltage. Implantable stimulators usually use microelectrodes with high impedance, resulting in the common-mode potential of the motor voltage usually exceeding 5V. Therefore, the window comparator needs to be able to work properly under the condition of high input voltage. However, circuits based on low-voltage CMOS processes are difficult to directly meet this requirement.

[0005] 2. Achieve high-precision detection of residual voltage. In order to ensure high-precision charge balance, the window voltage of the window comparator needs to reach the millivolt level or even the sub-millivolt level. However, for a traditional window comparator implemented based on a dual-comparator structure, the accuracy of its window voltage is limited by the stability of the reference voltage and the offset of the comparator, and it is difficult to meet the strict requirements of implantable neural stimulators for charge balance. Summary of the Invention

[0006] In order to solve the above technical problems, the purpose of the present invention is to provide a high-voltage and high-precision window comparator circuit with high window voltage accuracy and supporting high-voltage input.

[0007] To achieve the above object, on the one hand, an embodiment of the present application provides a high-voltage and high-precision window comparator circuit, which includes an input pair circuit, an offset correction circuit, a polarity switching switch, a current digital-to-analog converter, and an active load. The input pair circuit, the offset correction circuit, and the polarity switching switch are all connected to a first internal node. The polarity switching switch, the current digital-to-analog converter, and the active load are all connected to a second internal node. The input pair circuit and the polarity switching switch are also both connected to the offset correction circuit. The input pair circuit is configured to convert an externally input differential voltage signal into a first differential current signal. The offset correction circuit is configured to correct the differential current mismatch of the input pair circuit. The polarity switching switch is configured to switch the polarity of the input pair circuit connected to the active load and output a third differential current signal. The current digital-to-analog converter is configured to set a window voltage and output a fourth differential current signal. The active load is configured to amplify the difference between the third differential current signal and the fourth differential current signal and convert it into a first logic level, and then, by comparing the first logic levels before and after the polarity switching of the polarity switching switch, window detection is achieved.

[0008] In some embodiments, the input pair circuit includes a first current source, a diode unit, a first field-effect transistor unit, and a second field-effect transistor unit. The first field-effect transistor unit is configured to input the differential voltage signal. The first current source, the diode unit, the second field-effect transistor unit, and the first internal node are all connected to the first field-effect transistor unit. The second field-effect transistor unit is also connected to the offset correction circuit. The diode unit is configured to limit the gate-source voltage of the first field-effect transistor unit within a safe range. The first field-effect transistor unit and the second field-effect transistor unit are configured to convert the differential voltage signal into the first differential current signal according to a reset signal output by the offset correction circuit.

[0009] In some embodiments, the offset correction circuit includes an offset sample-and-hold circuit and a discrimination correction circuit. The offset sample-and-hold circuit and the discrimination correction circuit are both connected to the first internal node. The offset sample-and-hold circuit is connected to the discrimination correction circuit. The discrimination correction circuit is configured to output a correction control voltage signal and a reset signal. The offset sample-and-hold circuit is configured to convert the first differential current signal into a differential output voltage according to the correction control voltage signal. The discrimination correction circuit is also configured to adjust the third differential current signal compensated to the input pair circuit by successive approximation according to the differential output voltage to correct the differential current mismatch of the input pair circuit.

[0010] In some embodiments, the offset sampling and holding circuit includes a third field effect transistor unit, a fourth field effect transistor unit, a fifth field effect transistor unit, a sixth field effect transistor unit, a seventh field effect transistor unit, and a plate capacitor unit. The third field effect transistor unit and the fourth field effect transistor unit are both connected to the first internal node. The third field effect transistor unit, the fourth field effect transistor unit, the sixth field effect transistor unit, and the seventh field effect transistor unit are all connected to the discrimination and correction circuit. The third field effect transistor unit, the fourth field effect transistor unit, and the plate capacitor unit are all connected to the fifth field effect transistor unit.

[0011] In some embodiments, the discrimination and correction circuit includes a low voltage comparator. The non-inverting input terminal and the inverting input terminal of the low voltage comparator are used to input the differential output voltage. The low voltage comparator is used to output a second logic level according to the differential output voltage.

[0012] In some embodiments, the discrimination and correction circuit further includes a clock generation and successive approximation controller. The output terminal of the low voltage comparator is connected to the input terminal of the clock generation and successive approximation controller. The input terminal of the offset sampling and holding circuit is connected to the output terminal of the clock generation and successive approximation controller. The clock generation and successive approximation controller is used to generate the correction control voltage signal and the reset signal according to an externally input clock voltage signal, and generate an M-bit binary control voltage signal according to the clock voltage signal and the second logic level.

[0013] In some embodiments, the discrimination and correction circuit further includes an M-bit current digital-to-analog converter. The input terminal of the M-bit current digital-to-analog converter is connected to the output terminal of the clock generation and successive approximation controller. The output terminal of the M-bit current digital-to-analog converter is connected to the first internal node. The M-bit current digital-to-analog converter is used to generate the third differential current signal according to the M-bit binary control voltage signal. The third differential current signal is used to correct the differential current mismatch of the input pair circuit.

[0014] In some embodiments, the polarity switching switch includes a first logic gate, a second logic gate, a third logic gate, and an eighth field effect transistor unit. The first input terminal of the first logic gate and the input terminal of the second logic gate are both used for inputting a polarity inversion control voltage signal. The second input terminal of the first logic gate and the second input terminal of the third logic gate are both used for inputting the reset signal output by the offset correction circuit. The output terminal of the second logic gate is connected to the first input terminal of the third logic gate. The output terminals of the first logic gate and the third logic gate are both connected to the eighth field effect transistor unit. The first internal node and the second internal node are both connected to the eighth field effect transistor unit.

[0015] In some embodiments, the current digital-to-analog converter includes a driving voltage generation module and a plurality of current steering units. Each current steering unit is connected to the driving voltage generation module, and each current steering unit is also connected to the second internal node. The driving voltage generation module and each current steering unit are used to set the window voltage according to the third differential current signal and the fourth differential current signal.

[0016] In some embodiments, the active load includes a cascode load, a third current source, a fourth current source, a bias voltage providing unit, and a logic gate unit. The cascode load, the third current source, and the fourth current source are all connected to the second internal node. The third current source, the fourth current source, the logic gate unit, and the bias voltage providing unit are all connected to the cascode load. The third current source and the fourth current source are used to provide a tail current for the cascode load. The cascode load is used to convert the difference between the third differential current signal and the fourth differential current signal into a voltage change. The bias voltage providing unit is used to provide a bias voltage for the cascode load. The logic gate unit is used to perform a level conversion on the voltage change to obtain the first logic level.

[0017] The beneficial effects of the present invention are as follows: A high-voltage and high-precision window comparator circuit of the present invention includes an input pair circuit, an offset correction circuit, a polarity switching switch, a current digital-to-analog converter, and an active load. The input pair circuit converts an externally input differential voltage signal into a first differential current signal. The offset correction circuit corrects the differential current mismatch of the input pair circuit. The polarity switching switch switches the polarity of the connection of the input pair circuit to the active load and outputs a third differential current signal. The current digital-to-analog converter sets the window voltage and outputs a fourth differential current signal. The active load amplifies the difference between the third differential current signal and the fourth differential current signal and converts it into a first logic level. Then, by comparing the first logic levels before and after the polarity switching of the polarity switching switch, window detection is achieved. By adopting an input pair circuit supporting high common-mode voltage, an offset correction circuit based on successive approximation logic, and a polarity switching switch, the window comparator circuit designed by the present invention realizes window detection of voltage signals by using a single comparator, and at the same time supports high-voltage input and precise window voltage control. BRIEF DESCRIPTION OF THE DRAWINGS

[0018] In order to more clearly illustrate the technical solutions in the embodiments of the present invention, the following introduces the drawings required to be used in the embodiments of the present invention. It should be understood that the drawings introduced below only facilitate the clear expression of some embodiments of the technical solutions in the present invention. For those skilled in the art, without creative efforts, other drawings can also be obtained based on these drawings.

[0019] Figure 1 It is a structural block diagram of a high-voltage and high-precision window comparator circuit provided by an embodiment of the present invention;

[0020] Figure 2 It is a circuit structure schematic diagram of an input pair circuit provided by an embodiment of the present invention;

[0021] Figure 3 It is a circuit structure schematic diagram of an offset correction circuit provided by an embodiment of the present invention;

[0022] Figure 4 It is a circuit structure schematic diagram of a polarity switching switch provided by an embodiment of the present invention;

[0023] Figure 5 It is a circuit structure schematic diagram of a current digital-to-analog converter provided by an embodiment of the present invention;

[0024] Figure 6 It is a circuit structure schematic diagram of an active load provided by an embodiment of the present invention;

[0025] Reference numerals: 1, input pair circuit; 2, offset correction circuit; 21, offset sampling and holding circuit; 22, discrimination and correction circuit; 221, low-voltage comparator; 222, clock generation and successive approximation controller; 223, M-bit current digital-to-analog converter; 3, polarity switching switch; 4, current digital-to-analog converter; 41, drive voltage generation module; 42, current steering unit; 5, active load; I b1 , first current source; I b3 , third current source; I b4 , fourth current source; G1, first logic gate; G2, second logic gate; G3, third logic gate; G4, fourth logic gate; G5, fifth logic gate. Detailed implementation manners

[0026] In order to make the objectives, technical solutions and advantages of the present application clearer, the present application will be further described in detail below with reference to the accompanying drawings and embodiments. It should be understood that the specific embodiments described herein are only used to explain the present application and are not used to limit the present application. When the following description refers to the accompanying drawings, unless otherwise indicated, the same numbers in different drawings represent the same or similar elements. The implementation manners described in the following exemplary embodiments do not represent all implementation manners consistent with the embodiments of the present application. They are only examples of devices and methods consistent with some aspects of the embodiments of the present application detailed in the appended claims.

[0027] It can be understood that the terms "first", "second", etc. used in the present application may be used herein to describe various concepts, but unless otherwise specified, these concepts are not limited by these terms. These terms are only used to distinguish one concept from another. For example, without departing from the scope of the embodiments of the present application, the first information may also be referred to as the second information, and similarly, the second information may also be referred to as the first information. Depending on the context, the words "if", "when" as used herein may be interpreted as "when...", "when...", or "in response to determining".

[0028] The terms "at least one", "a plurality of", "each", "any one", etc. used in the present application, at least one includes one, two or more than two, a plurality includes two or more than two, each refers to each of the corresponding plurality, and any one refers to any one of the plurality.

[0029] In a nerve stimulator system, in order to avoid problems such as tissue electrolysis and electrode damage caused by residual charges on the electrodes, a charge balancing circuit needs to be added. As nerve stimulators evolve towards highly integrated multi-channel systems, the area of the electrodes continues to shrink, and the tolerance thresholds of tissues and electrodes for residual charges also continue to decline.

[0030] The window comparator is a key module in the charge balancing circuit of a nerve stimulator, used to detect whether the potential difference between the stimulation electrodes exceeds the safety window, so as to determine whether the accumulated residual charge exceeds the tolerance threshold. For a highly integrated nerve stimulator system, the window comparator in its charge balancing circuit needs to meet the following performance requirements:

[0031] 1. Adapt to high input common-mode voltage. Implantable stimulators usually use microelectrodes with high impedance, resulting in the common-mode potential of the motor voltage usually exceeding 5V. Therefore, the window comparator needs to be able to work properly under the condition of high input voltage. However, circuits based on low-voltage CMOS technology are difficult to directly meet this requirement.

[0032] 2. Achieve high-precision residual voltage detection. To ensure the high precision of charge balancing, the window voltage of the window comparator needs to reach the millivolt level or even the sub-millivolt level. However, for traditional window comparators implemented based on the dual-comparator structure, the accuracy of their window voltage is limited by the stability of the reference voltage and the offset of the comparator, and it is difficult to meet the strict requirements of implantable nerve stimulators for charge balancing.

[0033] For this reason, the embodiments of the present invention propose a high-voltage and high-precision window comparator circuit, including an input pair circuit, an offset correction circuit, a polarity switching switch, a current digital-to-analog converter, and an active load. The external input differential voltage signal is converted into a first differential current signal through the input pair circuit, the differential current mismatch of the input pair circuit is corrected through the offset correction circuit, the polarity of the input pair circuit connected to the active load is switched through the polarity switching switch, and a third differential current signal is output. The window voltage is set through the current digital-to-analog converter, and a fourth differential current signal is output. The difference between the third differential current signal and the fourth differential current signal is amplified and converted into a first logic level through the active load, and then the window detection is realized by comparing the first logic levels before and after the polarity switching of the polarity switching switch. By adopting an input pair circuit supporting high common-mode voltage, an offset correction circuit based on successive approximation logic, and a polarity switching switch, the window comparator circuit designed by the present invention realizes the window detection of voltage signals by using a single comparator, and at the same time supports high-voltage input and precise window voltage control.

[0034] Refer to Figure 1 , Figure 1This is a structural block diagram of a high-voltage and high-precision window comparator circuit provided by an embodiment of the present invention. An embodiment of the present invention proposes a high-voltage and high-precision window comparator circuit, which includes an input pair circuit 1, an offset correction circuit 2, a polarity switching switch 3, a current digital-to-analog converter 4, and an active load 5. The input pair circuit 1, the offset correction circuit 2, and the polarity switching switch 3 are all connected to a first internal node. The polarity switching switch 3, the current digital-to-analog converter 4, and the active load 5 are all connected to a second internal node. The input pair circuit 1 and the polarity switching switch 3 are also both connected to the offset correction circuit 2. The input pair circuit 1 is used to convert an externally input differential voltage signal into a first differential current signal. The offset correction circuit 2 is used to correct the differential current mismatch of the input pair circuit 1. The polarity switching switch 3 is used to switch the polarity of the input pair circuit 1 connected to the active load 5 and output a third differential current signal. The current digital-to-analog converter 4 is used to set a window voltage and output a fourth differential current signal. The active load 5 is used to amplify the difference between the third differential current signal and the fourth differential current signal and convert it into a first logic level, and then realize window detection by comparing the first logic levels before and after the polarity switching of the polarity switching switch 3.

[0035] Specifically, the high-voltage and high-precision window comparator circuit proposed by an embodiment of the present invention includes an input pair circuit 1, an offset correction circuit 2, a polarity switching switch 3, a current digital-to-analog converter 4, and an active load 5. The input pair circuit 1 is used to convert a differential voltage into a differential current. The offset correction circuit 2 is used to reset the input pair circuit 1 and the polarity switching switch 3 and correct the differential current mismatch of the input pair circuit 1. The polarity switching switch 3 is used to switch the polarity of the output end of the input pair circuit 1 connected to the input end of the active load 5. The differential output current of the current digital-to-analog converter 4 is subtracted from the differential output current of the polarity switching switch 3 to set a window voltage. The active load 5 is used to amplify the difference between the third differential current signal output by the polarity switching switch 3 and the fourth differential current signal output by the current digital-to-analog converter 4 and convert it into a rail-to-rail first logic level, and finally realize window detection by comparing the first logic levels before and after the polarity switching of the polarity switching switch 3.

[0036] Referring to Figure 2 , Figure 2 This is a circuit structure schematic diagram of the input pair circuit provided by an embodiment of the present invention. Further, as an optional implementation manner, the input pair circuit 1 includes a first current source I b1 , a diode unit, a first field-effect transistor unit, and a second field-effect transistor unit. The first field-effect transistor unit is used to input a differential voltage signal. The first current source I b1, the diode unit, the second field effect transistor unit, and the first internal node are all connected to the first field effect transistor unit. The second field effect transistor unit is also connected to the offset correction circuit 2. The diode unit is used to limit the gate-source voltage of the first field effect transistor unit within a safe range. The first field effect transistor unit and the second field effect transistor unit are used to convert the differential voltage signal into a first differential current signal according to the reset signal output by the offset correction circuit 2.

[0037] In some alternative embodiments, the input pair circuit 1 includes two P-type high-voltage metal oxide semiconductor field effect transistors with the same channel length and the same width (field effect transistors M1 and M2, i.e., the first field effect transistor unit), two P-type high-voltage metal oxide semiconductor field effect transistors with the same channel length and the same width (field effect transistors M3 and M5), two N-type high-voltage metal oxide semiconductor field effect transistors with the same channel length and the same width (field effect transistors M4 and M6), ten Zener diodes with the same area (diodes D1, D2, D3, D4, D5, D6, D7, D8, D9, D 10 , i.e., the diode unit), and a high-voltage current source I b1 (i.e., the first current source). The field effect transistors M3, M5, M4, and M6 constitute the second field effect transistor unit.

[0038] Among them, the differential voltage signal includes the voltage signal V ip and the voltage signal V in , the first differential current signal includes the current signal I n1 and the current signal I p1 , the first internal node includes the internal node V x1 and the internal node V x2 . The gate of the field effect transistor M1 is the input terminal of the voltage signal V ip . The drain of the field effect transistor M1 is connected to the internal node V x1 as the output terminal of the differential current signal I n1 . The source and back gate of the field effect transistor M1 are connected. The gate of the field effect transistor M2 is the input terminal of the voltage signal V in . The drain of the field effect transistor M2 is connected to the internal node V x2 as the output terminal of the differential current signal I p1 . The source and back gate of the field effect transistor M2 are connected. The sources of the field effect transistors M1 and M2 are connected. The gates of the field effect transistors M3 and M5 are connected as the reset signal V rstbAt the input terminal, the drain of the field effect transistor M3 is connected to the gate of the field effect transistor M1, and the source of the field effect transistor M3 is connected to the back gate; the gate of the field effect transistor M4 is connected to the gate of the field effect transistor M6 as the reset signal V rst At the input terminal, the drain of the field effect transistor M4 is connected to the source of the field effect transistor M3, and the source of the field effect transistor M4 and the back gate are connected to the source and the back gate of the field effect transistor M6 as the reset reference signal V ref At the input terminal, the drain of the field effect transistor M5 is connected to the gate of the field effect transistor M2, the source of the field effect transistor M5 is connected to the back gate, and the drain of the field effect transistor M6 is connected to the source of the field effect transistor M5; the positive electrode of the diode D1 is connected to the negative electrode of the diode D2, the negative electrode of the diode D1 is connected to the gate of the field effect transistor M1, the positive electrode of the diode D2 is connected to the negative electrode of the diode D3, the positive electrode of the diode D3 is connected to the negative electrode of the diode D4, the positive electrode of the diode D4 is connected to the negative electrode of the diode D5, the positive electrode of the diode D5 is connected to the source of the field effect transistor M1, the positive electrode of the diode D6 is connected to the negative electrode of the diode D7, the negative electrode of the diode D6 is connected to the gate of the field effect transistor M2, the positive electrode of the diode D7 is connected to the negative electrode of the diode D8, the positive electrode of the diode D8 is connected to the negative electrode of the diode D9, the positive electrode of the diode D9 is connected to the negative electrode of the diode D 10 The negative electrode is connected, and the positive electrode of the diode D 10 The positive electrode is connected to the source of the field effect transistor M2; the input terminal of the high-voltage current source I b1 (i.e., the first current source) is connected to the high-voltage positive power supply voltage V DDH The output terminal of the high-voltage current source I b1 (i.e., the first current source) is connected to the sources of the field effect transistor M1 and the field effect transistor M2.

[0039] Specifically, the second field effect transistor unit of the input pair circuit 1 is used to set the gate voltages of the field effect transistor M1 and the field effect transistor M2 in the first field effect transistor unit to V rst When the reset signal V rstn is at a high level and the reset signal V ref is at a low level, at this time, the difference between the current signal I n1 output by the input pair circuit 1 and the current signal I p1 will be determined by the mismatch between the field effect transistor M1 and the field effect transistor M2. Therefore, the offset correction circuit 2 detects and compensates the current signal I n1 and the current signal I p1The difference between them will correct the mismatch between the field effect transistor M1 and the field effect transistor M2. The diode unit is used to clamp the gate-source voltages of the field effect transistor M1 and the field effect transistor M2 within the safe range specified by the process, even if the input voltage signals V ip and the voltage signal V in vary within the range of the negative power supply voltage V SS and the high-voltage positive power supply voltage V DDH , overvoltage will not occur between the gate and source of the field effect transistor M1 and the field effect transistor M2.

[0040] Referring to Figure 3 , Figure 3 is a schematic circuit diagram of the offset correction circuit provided by an embodiment of the present invention. Further, as an optional implementation manner, the offset correction circuit 2 includes an offset sampling and holding circuit 21 and a discrimination and correction circuit 22. The offset sampling and holding circuit 21 and the discrimination and correction circuit 22 are both connected to the first internal node. The offset sampling and holding circuit 21 is connected to the discrimination and correction circuit 22. The discrimination and correction circuit 22 is used to output a correction control voltage signal and a reset signal. The offset sampling and holding circuit 21 is used to convert the first differential current signal into a differential output voltage according to the correction control voltage signal. The discrimination and correction circuit 22 is further used to adjust the third differential current signal compensated to the input pair circuit 1 by successive approximation according to the differential output voltage to correct the differential current mismatch of the input pair circuit 1.

[0041] Specifically, the offset correction circuit 2 is composed of an offset sampling and holding circuit 21 and a discrimination and correction circuit 22. The offset sampling and holding circuit 21 is used to convert the first differential output current of the input pair circuit 1 in the reset state into a differential output voltage and sample and hold it. The discrimination and correction circuit 22 is used to adjust the current compensated to the output end of the input pair circuit 1 in a successive approximation manner according to the polarity of the differential output voltage of the offset sampling and holding circuit 21 to correct the differential current offset of the input pair circuit 1.

[0042] Referring to Figure 3 , further, as an optional implementation manner, the offset sampling and holding circuit 21 includes a third field effect transistor unit, a fourth field effect transistor unit, a fifth field effect transistor unit, a sixth field effect transistor unit, a seventh field effect transistor unit, and a plate capacitor unit. The third field effect transistor unit and the fourth field effect transistor unit are both connected to the first internal node. The third field effect transistor unit, the fourth field effect transistor unit, the sixth field effect transistor unit, and the seventh field effect transistor unit are all connected to the discrimination and correction circuit 22. The third field effect transistor unit, the fourth field effect transistor unit, and the plate capacitor unit are all connected to the fifth field effect transistor unit.

[0043] In some alternative embodiments, the offset sampling and holding circuit 21 includes two N-type high-voltage metal oxide semiconductor field effect transistors (field effect transistor M A1 and field effect transistor M A2 , i.e., the third field effect transistor unit), two N-type high-voltage metal oxide semiconductor field effect transistors with the same channel length and the same width (field effect transistor M A3 and field effect transistor M A4 , i.e., the fourth field effect transistor unit), two N-type low-voltage metal oxide semiconductor field effect transistors with the same channel length and the same width (field effect transistor M B1 and field effect transistor M B2 , i.e., the fifth field effect transistor unit), three N-type low-voltage metal oxide semiconductor field effect transistors with the same channel length and the same width (field effect transistor M C1 and field effect transistor M C2 and field effect transistor M C3 , i.e., the sixth field effect transistor unit), three P-type low-voltage metal oxide semiconductor field effect transistors with the same channel length and the same width (field effect transistor M D1 and field effect transistor M D2 and field effect transistor M D3 , i.e., the seventh field effect transistor unit), and four plate capacitors with the same area (plate capacitor C1, plate capacitor C2, plate capacitor C3, plate capacitor C4).

[0044] Among them, the calibration control voltage signal includes voltage signal V p1 , voltage signal V p1b , voltage signal V p2 , voltage signal V p3 , voltage signal V p3b , voltage signal V p4 , and voltage signal V p4b . The differential output voltage includes voltage signal V op and voltage signal V on . The gates of field effect transistor M A1 and field effect transistor M A2 are connected as the input terminal of voltage signal V p1 . The drains of field effect transistor M A1 and field effect transistor M A3 are connected to the internal node V x1 as the input terminal of current signal I n2 . The sources of field effect transistor M A1 and field effect transistor M A2 are connected. The source of field effect transistor M A1is connected to the back gate and the negative power supply voltage V SS The gate of the field-effect transistor M A2 is connected to the gate of the field-effect transistor M A3 as the input terminal of the voltage signal V p2 The drain of the field-effect transistor M A2 is connected to the drain of the field-effect transistor M A4 and the internal node V x2 is connected as the input terminal of the current signal I p2 The back gate of the field-effect transistor M A2 is connected to the negative power supply voltage V SS The source of the field-effect transistor M A3 is connected to the source of the field-effect transistor M A4 The back gate of the field-effect transistor M A3 is connected to the negative power supply voltage V SS The back gate of the field-effect transistor M A4 is connected to the negative power supply voltage V SS The gate and the drain of the field-effect transistor M B1 are connected to the source of the field-effect transistor M A1 The source and the back gate of the field-effect transistor M B1 are connected to the negative power supply voltage V SS The gate and the drain of the field-effect transistor M B2 are connected to the source of the field-effect transistor M A3 The source and the back gate of the field-effect transistor M B2 are connected to the negative power supply voltage V SS The gate of the field-effect transistor M C1 is connected to the voltage signal V p1b The source of the field-effect transistor M C1 is connected to the drain of the field-effect transistor M D1 and the upper plate of the plate capacitor C1 as the output terminal of the voltage signal V op The drain of the field-effect transistor M C1 is connected to the source of the field-effect transistor M D1 The source of the field-effect transistor M A1 is connected to the source of the field-effect transistor M C1 The back gate of the field-effect transistor M SS is connected to the negative power supply voltage V D1 The gate of the field-effect transistor M p1 is connected to the voltage signal V D1 The back gate of the field-effect transistor M DDL is connected to the low-voltage positive power supply voltage V C2 The gate of the field-effect transistor M p3b is connected to the voltage signal V C2The source of and the field - effect transistor M D2 The drain of is connected to the upper plate of the plate capacitor C2 as the voltage signal V on The output terminal of, the field - effect transistor M C2 The drain of the field - effect transistor M D2 The source of is connected to the source of the field - effect transistor M A1 The source of the field - effect transistor M C2 The back - gate of is connected to the negative power - supply voltage V SS The field - effect transistor M D2 The gate of is connected to the voltage signal V p3 The field - effect transistor M D2 The back - gate of is connected to the low - voltage positive power - supply voltage V DDL The field - effect transistor M C3 The gate of is connected to the voltage signal V p4b The field - effect transistor M C3 The source of the field - effect transistor M D3 The drain of is connected to the upper plate of the plate capacitor C3, the field - effect transistor M C3 The drain of the field - effect transistor M D3 The source of is connected to the source of the field - effect transistor M A1 The source of the field - effect transistor M C3 The back - gate of is connected to the negative power - supply voltage V SS The field - effect transistor M D3 The gate of is connected to the voltage signal V p4 The field - effect transistor M D3 The back - gate of is connected to the low - voltage positive power - supply voltage V DDL Connected; the negative plates of the plate capacitor C1, the plate capacitor C2, the plate capacitor C3, and the plate capacitor C4 are all connected to the negative power - supply voltage V SS The positive plate of the plate capacitor C4 is connected to the source of the field - effect transistor M A3 Connected.

[0045] Specifically, the principle of the offset sample - and - hold circuit 21 is as follows: When the input pair circuit 1 and the polarity switch 3 are reset, first, the voltage signal V p1 , the voltage signal V p3b and the voltage signal V p4b are set to high level, and the voltage signals V p1b , the voltage signal V p2 , the voltage signal V p3 and the voltage signal V p4 are set to low level. At this time, the current signals I x1 flowing in from the internal node V x2 and the internal node V n2 and the current signal I p2 will respectively flow through the field - effect transistor MB1 and the field effect transistor M B2 , the gate-source voltage of the field effect transistor M at this time is sampled on the plate capacitor C1 B1 ; then, the voltage signal V p1b , the voltage signal V p2 , the voltage signal V p3 and the voltage signal V p4b are set to high level, the voltage signals V p1 , the voltage signals V p3b and the voltage signals V p4 are set to low level. At this time, the current signals I x1 flowing in from the internal node V x2 and the current signals I n2 will flow through the field effect transistor M p2 and the field effect transistor M B2 respectively. The gate-source voltage of the field effect transistor M sampled in the first phase is maintained on the plate capacitor C1. The gate-source voltage of the field effect transistor M at this time is sampled on the plate capacitor C2 B1 ; finally, the voltage signals V B1 , the voltage signals V B1 and the voltage signals V p1 are set to high level, the voltage signals V p3b , the voltage signals V p4 and the voltage signals V p1b are set to low level. The gate-source voltage of the field effect transistor M sampled in the first phase is maintained on the plate capacitor C1. The gate-source voltage of the field effect transistor M sampled in the second phase is maintained on the plate capacitor C2. At this time, the difference between the voltage signals V p2 , the voltage signals V p3 and the voltage signals V p4b is the result of dividing the error between the current signals I B1 and the current signals I B1 by the transconductance of the field effect transistor M op and reflects the offset of the input to circuit 1. The functions of the plate capacitors C3 and C4 are to ensure that the load capacitances of the gates of the field effect transistors M on and the field effect transistors M n2 remain unchanged when the offset sampling and holding circuit 21 switches between phases, reducing the fluctuations of the voltage signals V p2 and the voltage signals V B1 at the beginning of sampling and making the voltage values sampled and held on the plate capacitors C1 and C2 more accurate. When the offset correction is completed, the voltage signals V B1 and the voltage signals V B2 are set to high level, the voltage signals V op and the voltage signals V on are set to low level, the voltage signals V p1b , the voltage signals V p3b and the voltage signals Vp4b is set to high level, and the voltage signal V p1 , the voltage signal V p2 , the voltage signal V p3 and the voltage signal V p4 are set to low level. The offset sampling and holding circuit 21 will cut off the connection with the input pair circuit 1 and the polarity switching switch 3, so it will not affect the operation of the window comparator.

[0046] Referring to Figure 3 , as a further optional embodiment, the discrimination and correction circuit 22 includes a low-voltage comparator 221. The non-inverting input terminal and the inverting input terminal of the low-voltage comparator 221 are used for inputting the differential output voltage, and the low-voltage comparator 221 is used to output a second logic level according to the differential output voltage.

[0047] Referring to Figure 3 , as a further optional embodiment, the discrimination and correction circuit 22 further includes a clock generation and successive approximation controller 222. The output terminal of the low-voltage comparator 221 is connected to the input terminal of the clock generation and successive approximation controller 222, and the input terminal of the offset sampling and holding circuit 21 is connected to the output terminal of the clock generation and successive approximation controller 222. The clock generation and successive approximation controller 222 is used to generate a correction control voltage signal and a reset signal according to the externally input clock voltage signal, and generate an M-bit binary control voltage signal according to the clock voltage signal and the second logic level.

[0048] Referring to Figure 3 , as a further optional embodiment, the discrimination and correction circuit 22 further includes an M-bit current digital-to-analog converter 223. The input terminal of the M-bit current digital-to-analog converter 223 is connected to the output terminal of the clock generation and successive approximation controller 222, and the output terminal of the M-bit current digital-to-analog converter 223 is connected to the first internal node. The M-bit current digital-to-analog converter 223 is used to generate a third differential current signal according to the M-bit binary control voltage signal, and the third differential current signal is used to correct the differential current mismatch of the input pair circuit 1.

[0049] In some optional embodiments, the discrimination and correction circuit 22 includes a low-voltage comparator 221, a clock generation and successive approximation controller 222, and an M-bit current digital-to-analog converter 223. Among them, the differential output voltage includes the voltage signal V op and the voltage signal V on . The non-inverting input terminal of the low-voltage comparator 221 is the input terminal of the voltage signal V op , and the inverting input terminal of the low-voltage comparator 221 is the input terminal of the voltage signal V on . By comparing the magnitudes of the voltage signal V op and the voltage signal V on , the second logic level V is determinedpol polarity. The clock generation and successive approximation controller 222 generates a correction control voltage signal (i.e., voltage signal V clk ), a reset signal (voltage signal V p1 ), voltage signal V p1b ), voltage signal V p2 ), voltage signal V p3 ), voltage signal V p3b ), voltage signal V p4 ), and voltage signal V p4b ) through logical operations according to the clock voltage signal V rst and the second logic level V rstb ). The M-bit binary control voltage signal is generated through successive approximation logical operations according to the clock voltage signal V clk and the second logic level V pol . The input end of the M-bit current digital-to-analog converter 223 is connected to the M-bit binary control voltage signal output by the clock generation and successive approximation controller 222. The positive output end and the negative output end are respectively connected to the internal node V x1 and the internal node V x2 to generate a third differential output current signal (i.e., current signal I p3 and current signal I n3 ) proportional to the input M-bit binary control voltage signal, canceling the error between the first differential output current signals (i.e., current signal I p1 and current signal I n1 ) when the input pair circuit 1 is reset. M is a natural number greater than or equal to 1.

[0050] Specifically, the principle of the discrimination and correction circuit 22 is as follows: First, the clock generation and successive approximation controller 222 sets the reset signal V rst to a high level and the reset signal V rstn to a low level, so that the current signals I p1 and I n1 output by the input pair circuit 1 are only related to the mismatch, and disconnects the connection of the polarity switching switch 3 between the first internal nodes (i.e., internal node V x1 and internal node V x2 ) and the second internal nodes (i.e., internal node V y1 and internal node V y2 ); then, the clock generation and successive approximation controller 222 outputs a periodic polyphase control voltage signal (i.e., voltage signal V p1 , voltage signal V p1b , voltage signal V p2 , voltage signal V p3 , voltage signal V p3b , voltage signal V p4and voltage signal V p4b ) mismatched sampling of the current signal I output by the input pair to circuit 1 p1 and current signal I n1 and convert it into voltage signal V on and voltage signal V op of the voltage difference; the low-voltage comparator 221 converts the voltage difference between voltage signal V on and voltage signal V op into a second logic level V pol and then sends it to the clock generation and successive approximation controller 222. The successive approximation logic adjusts the M-bit binary control voltage signal bit by bit starting from the highest bit. After each adjustment, a mismatch sampling will be performed again until the lowest bit of the M-bit binary control voltage signal is adjusted. In the kth successive approximation cycle, the (M - k + 1)th control signal will be set to 1 first. Then, if the second logic level V pol is high, the (M - k + 1)th control signal remains unchanged; if the second logic level V pol is low, the (M - k + 1)th control signal is set to 0. Both k and M are natural numbers greater than or equal to 1. The difference between the current signal I n3 output by the M-bit current digital-to-analog converter 223 and the current signal I p3 is proportional to the M-bit binary control voltage signal at the input end. Taking M equal to 3 as an example, when the logic of the control voltage signal is "100", the difference between the current signal I p3 and the current signal I n3 is zero; when the logic of the control voltage signal is "111", the difference between the current signal I p3 and the current signal I n3 is the positive maximum value; when the logic of the control voltage signal is "000", the difference between the current signal I p3 and the current signal I n3 is the negative minimum value.

[0051] Refer to Figure 4 , Figure 4Schematic diagram of the circuit structure of a polarity switching switch provided by an embodiment of the present invention. Further, as an optional implementation manner, the polarity switching switch 3 includes a first logic gate G1, a second logic gate G2, a third logic gate G3, and an eighth field effect transistor unit. The first input terminal of the first logic gate G1 and the input terminal of the second logic gate G2 are both used to input a polarity inversion control voltage signal. The second input terminal of the first logic gate G1 and the second input terminal of the third logic gate G3 are both used to input a reset signal output by the offset correction circuit 2. The output terminal of the second logic gate G2 is connected to the first input terminal of the third logic gate G3. The output terminals of the first logic gate G1 and the third logic gate G3 are both connected to the eighth field effect transistor unit. The first internal node and the second internal node are both connected to the eighth field effect transistor unit.

[0052] In some optional embodiments, the polarity switching switch 3 includes four N-type high-voltage metal oxide semiconductor field effect transistors with the same channel length and the same width (field effect transistor M7, field effect transistor M8, field effect transistor M9, field effect transistor M 10 , that is, the eighth field effect transistor unit), two NOR logic gates (the first logic gate G1, the second logic gate G3), and one NOT logic gate (the third logic gate G2).

[0053] Among them, the gate of the field effect transistor M7 and the gate of the field effect transistor M 10 are connected to the output terminal of the third logic gate G3. The drain of the field effect transistor M7 and the drain of the field effect transistor M9 are connected to the internal node V x1 . The source of the field effect transistor M7 and the source of the field effect transistor M8 are connected to the internal node V y1 . The back gate of the field effect transistor M7 is connected to the negative power supply voltage V SS . The gate of the field effect transistor M8 and the gate of the field effect transistor M9 are connected to the output terminal of the first logic gate G1. The drain of the field effect transistor M8 and the drain of the field effect transistor M 10 are connected to the internal node V x2 . The back gate of the field effect transistor M8 is connected to the negative power supply voltage V SS . The source of the field effect transistor M9 and the source of the field effect transistor M 10 are connected to the internal node V y2 . The back gate of the field effect transistor M9 is connected to the negative power supply voltage V SS . The back gate of the field effect transistor M 10 is connected to the negative power supply voltage V SS . The back gate of the field effect transistor M flipare connected. The second input terminal of the first logic gate G1 and the second input terminal of the third logic gate G3 are connected to the reset signal V rst are connected, and the output terminal of the second logic gate G2 and the first input terminal of the third logic gate G3 are connected.

[0054] Specifically, the principle of the polarity switching switch 3 is that the field effect transistor M7, the field effect transistor M 10 tube or the field effect transistor M8, the field effect transistor M9 tube are respectively turned on to change the polarity of the current digital-to-analog converter 4 and the active load 5 connected to the input pair circuit 1, so that the two output results of the comparator before and after the polarity switching reflect the information of the window detection. The difference between the fourth differential current signal (i.e., the current signal I p4 and the current signal I n4 ) output by the current digital-to-analog converter 4 sets the window voltage V window of the comparator. When the field effect transistor M7 and the field effect transistor M 10 are turned on, the condition for the output voltage of the comparator to jump from low level to high level is that the difference between the voltage signal V ip minus the voltage signal V in is greater than the window voltage V window ; when the field effect transistor M8 and the field effect transistor M9 are turned on, the condition for the output voltage of the comparator to jump from low level to high level is that the difference between the voltage signal V ip minus the voltage signal V in is less than -V window . Therefore, when the output levels of the comparator before and after the polarity switching are the same, it means that the difference between the voltage signal V ip and the voltage signal V in falls within the interval of [-V window , V window ; when the output levels of the comparator before and after the polarity switching are different and the comparator outputs a high level when the field effect transistor M7 and the field effect transistor M 10 are turned on, it means that the difference between the voltage signal V ip and the voltage signal V in is greater than the window voltage V window ; when the output levels of the comparator before and after the polarity switching are different and the comparator outputs a low level when the field effect transistor M7 and the field effect transistor M 10 are turned on, it means that the difference between the voltage signal V ip and the voltage signal V in is less than -V window .

[0055] Refer to Figure 5 , Figure 5Schematic diagram of the circuit structure of a current digital-to-analog converter according to an embodiment of the present invention. Further, as an optional implementation manner, the current digital-to-analog converter 4 includes a driving voltage generation module 41 and a plurality of current steering units 42. Each current steering unit 42 is connected to the driving voltage generation module 41, and each current steering unit 42 is also connected to the second internal node. The driving voltage generation module 41 and each current steering unit 42 are configured to set a window voltage according to a third differential current signal and a fourth differential current signal.

[0056] In some optional embodiments, the current digital-to-analog converter 4 includes one driving voltage generation module 41 and N current steering units 42. Among them, the fourth differential current signal includes a current signal I p4 and a current signal I n4 . The driving voltage generation module 41 is composed of a low-voltage current source I b2 and an N-type high-voltage metal oxide semiconductor field effect transistor M 11 . The gate and drain of the field effect transistor M 11 are connected to the output end of the low-voltage current source I b2 . The source and back gate of the field effect transistor M 11 are connected to the negative power supply voltage V SS ; the i-th current steering unit 42 among the N current steering units 42 is composed of an N-type low-voltage metal oxide semiconductor field effect transistor M Ei and two N-type low-voltage metal oxide semiconductor field effect transistors M Fi with the same channel length and width, and a field effect transistor M Gi . The ratio of the channel width to the channel length of the field effect transistor M Ei to the ratio of the channel width to the channel length of the field effect transistor M 11 is i:1. The ratio of the channel width to the channel length of the field effect transistor M Fi to the ratio of the channel width to the channel length of the field effect transistor M F1 is i:1. The ratio of the channel width to the channel length of the field effect transistor M Gi to the ratio of the channel width to the channel length of the field effect transistor M G1 is i:1. The gate of the field effect transistor M Ei is connected to the gate of the field effect transistor M 11 . The drain of the field effect transistor M Ei is connected to the source of the field effect transistor M Fi . The source and back gate of the field effect transistor M Ei are connected to the negative power supply voltage V SS . The gate of the field effect transistor M Fi is connected to the logic voltage signal V conbkis connected, and the drain of the field-effect transistor M Fi is connected to the internal node V y1 as the output terminal of the current signal I n4 ; the source of the field-effect transistor M Fi is connected to the source of the field-effect transistor M Gi ; the back gate of the field-effect transistor M Fi is connected to the negative power supply voltage V SS ; the gate of the field-effect transistor M Gi is connected to the logic voltage signal V conbk ; the drain of the field-effect transistor M Gi is connected to the internal node V y2 as the output terminal of the current signal I p4 ; the back gate of the field-effect transistor M Gi is connected to the negative power supply voltage V SS ; i ∈ [1, N], where both i and N are natural numbers greater than or equal to 1.

[0057] Specifically, the current digital-to-analog converter 4 is a current-steering digital-to-analog converter. Among them, for the k-th current-steering unit 42 in the N current-steering units 42, the drain-source current of the field-effect transistor M Ek is 2 11 times the drain-source current of the field-effect transistor M k . According to the logic levels of the voltage signal V conk and the voltage signal V conbk , only one of the field-effect transistor M Fk and the field-effect transistor M Gk is in the on state, so that a current of 2 k I b2 flows out of the internal node V y1 or the internal node V y2 . The difference between the current signal I n3 and the current signal I p3 is equivalent to the offset voltage at the input of the input pair circuit 1, which is the window voltage V window , where the window voltage V window is equal to the current signal I n3 minus the current signal I p3 divided by the transconductance of the field-effect transistor M1 and the field-effect transistor M2.

[0058] Referring to Figure 6 , Figure 6 is a schematic diagram of the circuit structure of the active load provided by an embodiment of the present invention. Further, as an optional embodiment, the active load 5 includes a cascode load, a third current source I b3 , and a fourth current source I b4, a bias voltage providing unit, and a logic gate unit, a cascode load, a third current source I b3 and a fourth current source I b4 are all connected to the second internal node. The third current source I b3 , the fourth current source I b4 , the logic gate unit, and the bias voltage providing unit are all connected to the cascode load. The third current source I b3 and the fourth current source I b4 are used to provide a tail current for the cascode load. The cascode load is used to convert the difference between the third differential current signal and the fourth differential current signal into a voltage change. The bias voltage providing unit is used to provide a bias voltage for the cascode load. The logic gate unit is used to perform a level conversion on the voltage change to obtain a first logic level.

[0059] In some alternative embodiments, the active load 5 includes two P-type low-voltage metal oxide semiconductor field effect transistors (field effect transistor M 12 , field effect transistor M 13 ) with the same channel length and the same width, one N-type low-voltage metal oxide semiconductor field effect transistor (field effect transistor M 14 ), two N-type low-voltage metal oxide semiconductor field effect transistors (field effect transistor M 15 , field effect transistor M 16 ) with the same channel length and the same width, four P-type low-voltage metal oxide semiconductor field effect transistors (field effect transistor M 17 , field effect transistor M 18 , field effect transistor M 19 , field effect transistor M 20 ), two non-logic gates (logic gate G4, logic gate G5, i.e., the logic gate unit), and three low-voltage current sinks (i.e., the third current source I b3 , the fourth current source I b4 , the fifth current source I b5 ).

[0060] Among them, the gate and drain of the field effect transistor M 12 are connected to the gate of the field effect transistor M 13 . The source and back gate of the field effect transistor M 12 are connected to the low-voltage positive power supply voltage V DDL . The drain of the field effect transistor M 13 is connected to the drain of the field effect transistor M 14 . The source and back gate of the field effect transistor M 13 are connected to the low-voltage positive power supply voltage V DDL . The source of the field effect transistor M 14The gate and drain of M are connected. 14 The source and back gate of M are connected to the negative power supply voltage V. SS The gate of M is connected to the gate of M. 15 The gate of M is connected to the gate of M. 16 The gate of M is connected to the gate of M. 14 The drain of M is connected to the drain of M. 15 The drain of M is connected to the drain of M. 17 The source of M is connected to the input terminal of the low - voltage current sink I. 15 The source of M is connected to the input terminal of the low - voltage current sink I. b3 The source of M is connected to the input terminal of the low - voltage current sink I. y1 The source of M is connected to the input terminal of the low - voltage current sink I. 15 The back gate of M is connected to the negative power supply voltage V. SS The back gate of M is connected to the negative power supply voltage V. 16 The drain of M is connected to the input terminal of the logic gate G4. 18 The drain of M is connected to the input terminal of the logic gate G4. 16 The source of M is connected to the input terminal of the low - voltage current sink I. b4 The source of M is connected to the input terminal of the low - voltage current sink I. y2 The source of M is connected to the input terminal of the low - voltage current sink I. 16 The back gate of M is connected to the negative power supply voltage V. SS The back gate of M is connected to the negative power supply voltage V. 17 The gate of M is connected to the gate of M. 18 The gate of M is connected to the gate of M. 12 The gate of M is connected to the gate of M. 17 The source of M is connected to the drain of M. 19 The source of M is connected to the drain of M. 17 The back gate of M is connected to the positive low - voltage power supply voltage V. DDL The back gate of M is connected to the positive low - voltage power supply voltage V. 18 The source of M is connected to the drain of M. 20 The source of M is connected to the drain of M. 18 The back gate of M is connected to the positive low - voltage power supply voltage V. DDL The back gate of M is connected to the positive low - voltage power supply voltage V. 19 The gate of M is connected to the drain of M. 20 The gate of M is connected to the drain of M. 17 The source and back gate of M are connected to the positive low - voltage power supply voltage V. 19 The source and back gate of M are connected to the positive low - voltage power supply voltage V. DDL The source and back gate of M are connected to the positive low - voltage power supply voltage V. 20 The source and back gate of M are connected to the positive low - voltage power supply voltage V. DDL The output terminal of the logic gate G4 is connected to the input terminal of the logic gate G5. The output terminal of the logic gate G5 is connected to the voltage signal V. out The low - voltage current sink I is connected. b3, low - voltage current sink I b4 and low - voltage current sink I b5 have their output terminals all connected to the negative power - supply voltage V SS The input terminal of low - voltage current sink I b5 is connected to the drain of field - effect transistor M 12 The current magnitudes of low - voltage current sinks I b3 and I b4 are the same as the current magnitude of low - voltage current source I b1 .

[0061] Specifically, the field - effect transistors M 15 、field - effect transistor M 16 、field - effect transistor M 17 、field - effect transistor M 18 、field - effect transistor M 19 、field - effect transistor M 20 of the active load 5 form a folded cascode load. The third current source I b3 and the fourth current source I b4 provide the tail current for the folded cascode structure, converting the difference in the currents flowing into the internal node V y1 and the internal node V y2 into the voltage change at the drains of field - effect transistors M 16 、field - effect transistor M 18 . The fifth current source I b5 and field - effect transistors M 12 、field - effect transistor M 13 、field - effect transistor M 14 constitute a bias - voltage providing unit. The bias - voltage providing unit provides bias voltages for the four cascode transistors of field - effect transistors M 15 、field - effect transistor M 16 、field - effect transistor M 17 、field - effect transistor M 18 so that they operate in the saturation region at DC. The two non - logic gates, logic gate G4 and logic gate G5, play the role of expanding the output voltage swing.

[0062] The structure and working principle of a high - voltage and high - precision window comparator circuit according to an embodiment of the present invention are described above. It can be recognized that the window comparator circuit designed by the present invention's embodiment by adopting an input pair circuit supporting a high common - mode voltage, an offset correction circuit based on successive - approximation logic, and a polarity - switching switch realizes the window detection of voltage signals by using a single comparator, and at the same time supports high - voltage input and precise window voltage control, and is applicable to the application of the charge - balance circuit in an implantable neural stimulator.

[0063] In the foregoing description of the present specification, the descriptions referring to terms such as "one embodiment", "another embodiment" or "certain embodiments" mean that the specific features, structures, materials or characteristics described in connection with the embodiment or example are included in at least one embodiment or example of the present invention. In the present specification, the schematic representations of the above terms do not necessarily refer to the same embodiment or example. Moreover, the specific features, structures, materials or characteristics described may be combined in any one or more embodiments or examples in a suitable manner.

[0064] Although the embodiments of the present invention have been shown and described, those of ordinary skill in the art can understand that various changes, modifications, substitutions and variations can be made to these embodiments without departing from the principles and spirit of the present invention, and the scope of the present invention is defined by the claims and their equivalents.

[0065] The above is a specific description of the preferred embodiment of the present invention, but the present invention is not limited to the embodiments. Those skilled in the art can also make various equivalent deformations or substitutions without departing from the spirit of the present invention, and these equivalent deformations or substitutions are all included in the scope defined by the claims of this application.

Claims

1. A high-voltage and high-precision window comparator circuit, characterized in that, It includes an input pair circuit, an offset correction circuit, a polarity switching switch, a current digital-to-analog converter, and an active load. The input pair circuit, the offset correction circuit, and the polarity switching switch are all connected to a first internal node. The polarity switching switch, the current digital-to-analog converter, and the active load are all connected to a second internal node. The input pair circuit and the polarity switching switch are also both connected to the offset correction circuit. The input pair circuit is used to convert an externally input differential voltage signal into a first differential current signal. The offset correction circuit is used to correct the differential current mismatch of the input pair circuit. The polarity switching switch is used to switch the polarity of the input pair circuit connected to the active load and output a third differential current signal. The current digital-to-analog converter is used to set a window voltage and output a fourth differential current signal. The active load is used to amplify the difference between the third differential current signal and the fourth differential current signal and convert it into a first logic level, and then realize window detection by comparing the first logic levels before and after the polarity switching of the polarity switching switch.

2. The high-voltage and high-precision window comparator circuit according to claim 1, wherein The input pair circuit includes a first current source, a diode unit, a first field effect transistor unit, and a second field effect transistor unit. The first field effect transistor unit is used to input the differential voltage signal. The first current source, the diode unit, the second field effect transistor unit, and the first internal node are all connected to the first field effect transistor unit. The second field effect transistor unit is also connected to the offset correction circuit. The diode unit is used to limit the gate-source voltage of the first field effect transistor unit within a safe range. The first field effect transistor unit and the second field effect transistor unit are used to convert the differential voltage signal into the first differential current signal according to the reset signal output by the offset correction circuit.

3. The high-voltage and high-precision window comparator circuit according to claim 1, characterized in that The offset correction circuit includes an offset sample and hold circuit and a discrimination and correction circuit. The offset sample and hold circuit and the discrimination and correction circuit are both connected to the first internal node. The offset sample and hold circuit is connected to the discrimination and correction circuit. The discrimination and correction circuit is used to output a correction control voltage signal and a reset signal. The offset sample and hold circuit is used to convert the first differential current signal into a differential output voltage according to the correction control voltage signal. The discrimination and correction circuit is also used to adjust the third differential current signal compensated to the input pair circuit by successive approximation according to the differential output voltage to correct the differential current mismatch of the input pair circuit.

4. A high-voltage and high-precision window comparator circuit according to claim 3, characterized in that The offset sampling and holding circuit includes a third field effect transistor unit, a fourth field effect transistor unit, a fifth field effect transistor unit, a sixth field effect transistor unit, a seventh field effect transistor unit, and a plate capacitor unit. The third field effect transistor unit and the fourth field effect transistor unit are both connected to the first internal node. The third field effect transistor unit, the fourth field effect transistor unit, the sixth field effect transistor unit, and the seventh field effect transistor unit are all connected to the discrimination and correction circuit. The third field effect transistor unit, the fourth field effect transistor unit, and the plate capacitor unit are all connected to the fifth field effect transistor unit.

5. The high-voltage and high-precision window comparator circuit according to claim 3, characterized in that The discrimination and correction circuit includes a low voltage comparator. The non-inverting input terminal and the inverting input terminal of the low voltage comparator are used to input the differential output voltage. The low voltage comparator is used to output a second logic level according to the differential output voltage.

6. The high-voltage and high-precision window comparator circuit according to claim 5, wherein The discrimination and correction circuit further includes a clock generation and successive approximation controller. The output terminal of the low voltage comparator is connected to the input terminal of the clock generation and successive approximation controller. The input terminal of the offset sampling and holding circuit is connected to the output terminal of the clock generation and successive approximation controller. The clock generation and successive approximation controller is used to generate the correction control voltage signal and the reset signal according to an externally input clock voltage signal, and generate an M-bit binary control voltage signal according to the clock voltage signal and the second logic level.

7. The high-voltage and high-precision window comparator circuit according to claim 6, characterized in that The discrimination and correction circuit further includes an M-bit current digital-to-analog converter. The input terminal of the M-bit current digital-to-analog converter is connected to the output terminal of the clock generation and successive approximation controller. The output terminal of the M-bit current digital-to-analog converter is connected to the first internal node. The M-bit current digital-to-analog converter is used to generate the third differential current signal according to the M-bit binary control voltage signal. The third differential current signal is used to correct the differential current mismatch of the input pair circuit.

8. A high-voltage and high-precision window comparator circuit according to claim 1, wherein, The polarity switching switch includes a first logic gate, a second logic gate, a third logic gate, and an eighth field effect transistor unit. The first input terminal of the first logic gate and the input terminal of the second logic gate are both used to input the polarity flip control voltage signal. The second input terminal of the first logic gate and the second input terminal of the third logic gate are both used to input the reset signal output by the offset correction circuit. The output terminal of the second logic gate is connected to the first input terminal of the third logic gate. The output terminals of the first logic gate and the third logic gate are both connected to the eighth field effect transistor unit. The first internal node and the second internal node are both connected to the eighth field effect transistor unit.

9. The high-voltage and high-precision window comparator circuit according to claim 1, wherein The current digital-to-analog converter includes a driving voltage generation module and a plurality of current steering units. Each current steering unit is connected to the driving voltage generation module. Each current steering unit is also connected to the second internal node. The driving voltage generation module and each current steering unit are used to set the window voltage according to the third differential current signal and the fourth differential current signal.

10. The high-voltage and high-precision window comparator circuit according to claim 1, characterized in that, The active load includes a cascode load, a third current source, a fourth current source, a bias voltage providing unit, and a logic gate unit. The cascode load, the third current source, and the fourth current source are all connected to the second internal node. The third current source, the fourth current source, the logic gate unit, and the bias voltage providing unit are all connected to the cascode load. The third current source and the fourth current source are used to provide a tail current for the cascode load. The cascode load is used to convert the difference between the third differential current signal and the fourth differential current signal into a voltage change. The bias voltage providing unit is used to provide a bias voltage for the cascode load. The logic gate unit is used to perform a level conversion on the voltage change to obtain the first logic level.

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