Logic operation circuit and cryptographic processor

Abstract

The present application discloses a logic operation circuit and a cryptographic processor, which relate to the field of logic operation technology. The logic operation circuit includes a resistive memory unit, wherein the resistive memory unit has a first resistance state and a second resistance state, wherein a first output current in the first resistance state corresponds to a first logic level, and a second output current in the second resistance state corresponds to a second logic level; and a signal processing module, wherein the input end of the signal processing module is used to receive multiple logic signals, the output end of the signal processing module is connected to the input end of the resistive memory unit, and the signal processing module is configured to apply a bias voltage to the resistive memory unit according to the logic signal, so that the resistive memory unit is in the first resistance state or the second resistance state. In terms of hardware, only the resistive memory unit needs to cooperate with the signal processing module, and the voltage-controlled resistance characteristic of the resistive memory unit is utilized to modulate the resistance state of the resistive memory unit to achieve logic operation, thereby reducing the number of transistors, improving the integration density, and reducing dynamic power consumption.

Description

Technical Field

[0001] The present application relates to the field of logic operation technology, and in particular to logic operation circuits and cryptographic processors. Background Art

[0002] Traditional digital logic gate circuits, as core components of integrated circuits, perform fundamental computing functions in various electronic systems. These circuits are typically based on complementary metal-oxide-semiconductor (CMOS) technology. Conventional CMOS logic gates are typically implemented using transmission gate structures or compound logic gates, both of which rely on a large number of stacked transistors. The number of transistors directly correlates to chip area and power consumption. These traditional logic gate circuits struggle to meet the low-power, high-density design requirements of modern systems requiring high levels of integration. Summary of the Invention

[0003] The present application provides a logic operation circuit and a cryptographic processor to at least solve the problem in the related art that conventional CMOS logic gates rely on a large number of transistor stacks and are difficult to meet the low power consumption and high density design requirements.

[0004] The present application provides a logic operation circuit, comprising:

[0005] A resistive memory cell having a first resistance state and a second resistance state, wherein a first output current in the first resistance state corresponds to a first logic level, and a second output current in the second resistance state corresponds to a second logic level;

[0006] A signal processing module, wherein the input end of the signal processing module is used to receive multiple logic signals, the output end of the signal processing module is connected to the input end of the resistive memory unit, and the signal processing module is configured to apply a bias voltage to the resistive memory unit according to the logic signal, so that the resistive memory unit is in a first resistance state or a second resistance state.

[0007] According to one embodiment of the present application, the plurality of logic signals include a first signal and a second signal, and the signal processing module is configured to apply a first voltage and a second voltage having different polarities or amplitudes to the resistive memory cell according to a preset timing sequence when the first signal and the second signal have different logic levels, so as to adjust the resistance state of the resistive memory cell to a first resistance state;

[0008] When the first signal and the second signal have the same logic level, a third voltage and a fourth voltage with the same polarity and amplitude are applied to the resistive memory unit in a preset timing sequence to adjust the resistance state of the resistive memory unit to the second resistance state.

[0009] According to one embodiment of the present application, the first resistance state is a high resistance state, and the second resistance state is a low resistance state. The signal processing module is further configured to apply a first forward bias voltage and a second forward bias voltage to the resistive memory unit in sequence according to a preset timing when the first signal is a low-level signal and the second signal is a high-level signal, wherein the first forward bias voltage is less than a first forward threshold voltage, and the second forward bias voltage is greater than the first forward threshold voltage and less than the second forward threshold voltage.

[0010] The first forward threshold voltage is the forward threshold voltage at which the resistive memory cell transitions from a high resistance state to a low resistance state, and the second forward threshold voltage is the forward threshold voltage at which the resistive memory cell transitions from a low resistance state to a high resistance state. The second forward threshold voltage is greater than the first forward threshold voltage.

[0011] According to one embodiment of the present application, the signal processing module is further configured to apply a third forward bias voltage and a fourth forward bias voltage to the resistive memory unit in sequence according to a preset timing when the first signal is a high-level signal and the second signal is a low-level signal, the third forward bias voltage being greater than the first forward threshold voltage and less than the second forward threshold voltage, and the fourth forward bias voltage being less than the first forward threshold voltage.

[0012] According to one embodiment of the present application, the first resistance state is a high resistance state, and the second resistance state is a low resistance state. The signal processing module is also configured to apply a fifth forward bias voltage and a sixth forward bias voltage to the resistive memory unit in sequence according to a preset timing when the first signal and the second signal are both low-level signals. The fifth forward bias voltage and the sixth forward bias voltage are both less than the first forward threshold voltage at which the resistive memory unit jumps from a high resistance state to a low resistance state.

[0013] According to one embodiment of the present application, the signal processing module is also configured to apply a seventh forward bias voltage and an eighth forward bias voltage to the resistive memory unit in sequence according to a preset timing when the first signal and the second signal are both low-level signals, the seventh forward bias voltage and the eighth forward bias voltage are greater than the first forward threshold voltage and less than the second forward threshold voltage, and the second forward threshold voltage is greater than the first forward threshold voltage.

[0014] According to one embodiment of the present application, the first resistance state is a high resistance state, the second resistance state is a low resistance state, the multiple logic signals also include a third signal, and the signal processing module is further configured to apply a ninth forward bias voltage to the resistive memory unit when the third signal is a low-level signal. The ninth forward bias voltage is less than the first forward threshold voltage at which the resistive memory unit jumps from a high resistance state to a low resistance state.

[0015] According to one embodiment of the present application, the first resistance state is a high resistance state, the second resistance state is a low resistance state, the multiple logic signals further include a third signal, and the signal processing module is further configured to apply a first negative bias voltage to the resistive memory unit when the third signal is a high-level signal, wherein the absolute value of the first negative bias voltage is greater than the absolute value of the first negative phase voltage threshold and less than the absolute value of the second negative phase voltage threshold;

[0016] The first negative phase voltage threshold is the negative threshold voltage at which the resistive memory cell jumps from a high resistance state to a low resistance state, and the second negative phase voltage threshold is the negative threshold voltage at which the resistive memory cell jumps from a low resistance state to a high resistance state. The absolute value of the first negative phase voltage threshold is less than the absolute value of the second negative phase voltage threshold.

[0017] According to one embodiment of the present application, the first resistance state is a high resistance state, and the signal processing module is further configured to apply a second negative bias voltage to the resistive memory unit when the logic operation is completed, so that the resistive memory unit jumps to the first resistance state.

[0018] The present application also provides a cryptographic processor, comprising a word line, a bit line, a non-volatile resistive memory and the aforementioned logic operation circuit, wherein a first end of the logic operation circuit is connected to the bit line, a second end of the logic operation circuit is connected to a first end of the non-volatile resistive memory, and a second end of the non-volatile resistive memory is connected to the bit line.

[0019] According to an embodiment of the present application, the resistive memory unit includes a complementary resistance switch type resistive memory.

[0020] Through this application, since only one resistive memory unit is required in hardware to cooperate with a signal processing module, the voltage-controlled resistance characteristics of the resistive memory unit are utilized to modulate the resistance state of the resistive memory unit to realize logical operations. Therefore, it is possible to solve the technical problem that conventional CMOS logic gates rely on a large number of transistor stacks and are difficult to meet low-power and high-density design requirements, thereby achieving the technical effect of significantly reducing the number of transistors, improving integration density, and reducing dynamic power consumption. BRIEF DESCRIPTION OF THE DRAWINGS

[0021] In order to more clearly illustrate the embodiments of the present application, the following is a brief introduction to the drawings required for use in the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0022] Figure 1 It is a topological diagram of an XOR gate circuit in the related art;

[0023] Figure 2 A block diagram of the logic operation circuit provided in an embodiment of the present application;

[0024] Figure 3 A schematic diagram of the electrical characteristics of a resistive memory cell provided in an embodiment of the present application;

[0025] Figure 4 This is a circuit topology diagram of the cryptographic processor provided in an embodiment of the present application.

[0026] Reference numerals:

[0027] Resistive memory unit 10, signal processing module 20, non-volatile resistive memory 30, bit line BL, word line WL. DETAILED DESCRIPTION

[0028] The following will be combined with the accompanying drawings in the embodiments of this application to clearly and completely describe the technical solutions in the embodiments of this application. Obviously, the embodiments described are only part of the embodiments of this application, not all of them. Based on the embodiments in this application, all other embodiments obtained by ordinary technicians in this field without making creative efforts are within the scope of protection of this application.

[0029] It should be noted that, in the description of this application, the terms "comprises," "includes," or any other variations thereof are intended to cover non-exclusive inclusion, such that a process, method, article, or device comprising a series of elements includes not only those elements, but also other elements not explicitly listed, or elements inherent to such process, method, article, or device. The terms "first," "second," etc., in this application are used to distinguish similar objects, and are not used to describe a particular order or sequence.

[0030] In order to enable those skilled in the art to better understand the present application, the present application is further described in detail below with reference to the accompanying drawings and specific implementation methods.

[0031] Traditional digital logic gate circuits, as core components of integrated circuits, perform fundamental computing functions in various electronic systems. These circuits are typically based on complementary metal-oxide-semiconductor (CMOS) technology. Conventional CMOS logic gates are typically implemented using transmission gate structures or compound logic gates, both of which rely on a large number of stacked transistors. The number of transistors directly correlates to chip area and power consumption. These traditional logic gate circuits struggle to meet the low-power, high-density design requirements of modern systems requiring high levels of integration.

[0032] Figure 1 FIG1 shows a topology diagram of an XOR gate circuit in the related art. Figure 1The exclusive-OR gate (XOR) is a fundamental unit in digital logic. Its function is to output a high level when two logic signals differ and a low level when they match. The XOR operation is also crucial in fields like cryptography, offering higher execution efficiency than encryption operations like addition, subtraction, multiplication, and division. However, the traditional XOR gate circuit topology consists of at least six to ten stacked transistors, and the calculation process relies heavily on turning the transistors on and off, resulting in high power consumption.

[0033] Figure 2 FIG1 shows a block diagram of a logic operation circuit provided by an embodiment of the present application. Figure 2 An embodiment of the present application provides a logic operation circuit, which includes a resistive memory cell 10 and a signal processing module 20. The resistive memory cell 10 has a first resistance state and a second resistance state, wherein a first output current in the first resistance state corresponds to a first logic level, and a second output current in the second resistance state corresponds to a second logic level; the signal processing module 20 has an input terminal for receiving a plurality of logic signals, and an output terminal of the signal processing module 20 is connected to an input terminal of the resistive memory cell 10. The signal processing module 20 is configured to apply a bias voltage to the resistive memory cell 10 according to the logic signal, so that the resistive memory cell 10 is in the first resistance state or the second resistance state.

[0034] The resistive memory cell 10 is a two-terminal device whose core characteristic is voltage-controlled resistance. By applying a voltage pulse of specific polarity, amplitude, and duration across its terminals, the state of the conductive filaments within it can be reversibly altered, causing its resistance to jump between a high-resistance state and a low-resistance state. For ease of explanation, the following describes the operating principle of the logic operation circuit proposed in this application using the example of a high-resistance first resistance state and a low-resistance second resistance state.

[0035] In digital circuits, logic levels represent logic '1' and logic '0' in binary by high and low levels respectively.

[0036] According to Ohm's law, the magnitude of the output current flowing through the resistive memory cell 10 is determined by its current resistance state. A low resistance state produces a large output current, while a high resistance state produces a small output current. That is, when the resistive memory cell 10 is in the high resistance state, the first output current is small, and when the resistive memory cell 10 is in the low resistance state, the second output current is large. The following explanation uses the example where the first output current corresponds to a low logic level and the second output current corresponds to a high logic level.

[0037] A logic signal refers to the original digital signal to be subjected to a logic operation. A logic signal is a high-level signal (representing logic '1') or a low-level signal (representing logic '0').

[0038] The signal processing module 20 can generate and apply a corresponding, preset bias voltage to both ends of the resistive memory cell 10 based on the acquired logic signal combination. The applied bias voltage is mainly used to write the resistive memory cell 10 to a resistance state corresponding to the expected logical output result under the current input combination.

[0039] It should be noted that the specific operation logic implemented by the logic operation circuit can be determined according to the actual application scenario and is not limited here. For example, the logic operation circuit can implement AND logic, OR logic, NAND logic, NOR logic, or XOR logic, etc.

[0040] As an example, the logic signal includes a first signal X1 and a second signal X2. When it is desired to implement AND gate logic, if X1=1 and X2=1, the bias voltage applied to both ends of the resistive memory unit 10 needs to adjust the resistive memory unit 10 to a low resistance state, so that the resistive memory unit 10 generates a larger output current, and then outputs a logic operation result as a high-level signal (representing logic '1').

[0041] In some embodiments, the logic operation circuit further includes a current detection circuit that can detect the magnitude of the output current of the resistive memory cell 10 and convert it back to a standard digital voltage level (high or low), i.e., the final output logic '1' or '0'. For example, if the output current is greater than a preset threshold, it is converted to a logic '1', and if the output current is less than the preset threshold, it is converted to a logic '0'.

[0042] The specific value of the preset threshold value can be determined according to the actual application scenario and is not limited here. For example, the preset threshold value can be 0.5mA or 0.8mA.

[0043] The specific operation logic of the current detection circuit can be determined according to the actual application scenario and is not limited here. For example, the current detection circuit may include a current sensor and a comparator.

[0044] According to the logic operation circuit of the present application, in terms of hardware, only one resistive memory unit 10 is required to cooperate with a signal processing module. The voltage-controlled resistance characteristics of the resistive memory unit 10 are utilized to modulate the resistance state of the resistive memory unit 10 to perform logic operations, thereby reducing the number of transistors, improving the integration density, and reducing dynamic power consumption.

[0045] In some embodiments, the multiple logic signals include a first signal X1 and a second signal X2, and the signal processing module 20 is configured to apply a first voltage and a second voltage with different polarities or amplitudes to the resistive memory unit 10 according to a preset timing when the logic levels of the first signal X1 and the second signal X2 are different, so as to adjust the resistance state of the resistive memory unit 10 to a low resistance state; and to apply a third voltage and a fourth voltage with the same polarity and amplitude to the resistive memory unit 10 according to a preset timing when the logic levels of the first signal X1 and the second signal X2 are the same, so as to adjust the resistance state of the resistive memory unit 10 to a high resistance state.

[0046] The first signal X1 and the second signal X2 have different logic levels, meaning one signal is a logic '1' and the other is a logic '0'. The signal processing module 20 applies two voltage pulses of different polarities or amplitudes to the resistive memory cell 10 according to a preset timing sequence. The first and second voltages have opposite polarities and may have the same or different amplitudes, or the same polarity but different amplitudes. This effectively causes the resistive memory cell 10 to transition from a high-resistance state to a low-resistance state, or ensures that it remains stably in the low-resistance state, corresponding to a corresponding output of a logic '1'.

[0047] The first signal X1 and the second signal X2 have the same logic level, that is, both the first signal X1 and the second signal X2 are logic '1' or both the first signal X1 and the second signal X2 are logic '0'. The signal processing module 20 applies two third and fourth voltages of the same polarity (for example, both positive polarity) and the same amplitude to the resistive memory cell 10 according to a preset timing sequence, adjusting the resistance state of the resistive memory cell 10 to a high-resistance state, corresponding to the output logic '0'.

[0048] The preset timing refers to the pre-set order and time interval for applying voltage pulses. By precisely controlling the timing characteristics of the voltage signal, reliable switching of the resistance state of the resistive memory cell 10 is achieved. The specific setting method of the preset timing can be determined according to the actual application scenario and is not limited here. For example, if the first signal X1 and the second signal X2 have different logic levels, the first voltage can be applied to the resistive memory cell 10 first, and the second voltage can be applied after the first time interval.

[0049] In this embodiment, when the logic levels of the first signal X1 and the second signal X2 are different, the resistance state of the resistive memory unit 10 is a low resistance state, corresponding to the output logic '1'; when the logic levels of the first signal X1 and the second signal X2 are the same, the resistance state of the resistive memory unit 10 is a high resistance state, corresponding to the output logic '0', which conforms to the operation logic of the XOR gate. Compared with the traditional XOR gate logic circuit formed by stacking transistors, the number of transistors is reduced, the integration density is improved, and the dynamic power consumption is reduced.

[0050] In some embodiments, the signal processing module 20 is further configured to apply a first forward bias voltage and a second forward bias voltage to the resistive memory unit 10 in sequence according to a preset timing when the first signal X1 is a low-level signal and the second signal X2 is a high-level signal, the first forward bias voltage is less than the first forward threshold voltage Vth1, and the second forward bias voltage is greater than the first forward threshold voltage Vth1 and less than the second forward threshold voltage Vth2; the first forward threshold voltage Vth1 is the forward threshold voltage at which the resistive memory unit 10 jumps from a high-resistance state to a low-resistance state, the second forward threshold voltage Vth2 is the forward threshold voltage at which the resistive memory unit 10 jumps from a low-resistance state to a high-resistance state, and the second forward threshold voltage Vth2 is greater than the first forward threshold voltage Vth1.

[0051] Figure 3 The electrical characteristics of the resistive memory cell 10 provided in the embodiment of the present application are shown. Figure 3 In some embodiments, the resistive memory unit 10 is a complementary resistance switching type resistive memory, which is composed of two anti-parallel memristors connected in series.

[0052] When the forward bias voltage applied to the resistive memory cell 10 is greater than the first positive threshold voltage Vth1, the resistive memory cell 10 changes from an initial high-resistance state to a low-resistance state and maintains the low-resistance state within a range where the forward bias voltage is greater than the first positive threshold voltage Vth1 and less than the second positive threshold voltage Vth2. When the forward bias voltage increases to exceed the second positive threshold voltage Vth2, the resistive memory cell 10 returns from the low-resistance state to the high-resistance state. Similarly, when the absolute value of the negative bias voltage applied to the resistive memory cell 10 is greater than the absolute value of the first negative threshold voltage Vth3, the resistive memory cell 10 changes from a high-resistance state to a low-resistance state and maintains the low-resistance state within a range where the absolute value of the negative bias voltage is greater than the absolute value of the first negative threshold voltage Vth3 and less than the absolute value of the second negative threshold voltage Vth4. When the absolute value of the negative bias voltage is greater than the absolute value of the second negative threshold voltage Vth4, the resistive memory cell 10 returns from the low-resistance state to the high-resistance state.

[0053] When the first signal X1=0 and the second signal X2=1, a first forward bias voltage is first applied to the resistive memory cell 10. The first forward bias voltage is less than the first forward threshold voltage Vth1, so the resistive memory cell 10 is maintained in a high-resistance state. Then, a second forward bias voltage is applied to the resistive memory cell 10. The second forward bias voltage is greater than the first forward threshold voltage Vth1 and less than the second forward threshold voltage Vth2, so that the resistive memory cell 10 jumps from the high-resistance state to the low-resistance state, so that the resistive memory cell 10 generates a large output current, and then outputs a logic operation result as a high-level signal (logic '1').

[0054] By sequentially applying a first forward bias voltage and a second forward bias voltage to the resistive memory cell 10, a logic '1' can be output when the first signal X1 = 0 and the second signal X2 = 1. The voltage-controlled resistance characteristic of the resistive memory cell 10 can be used to implement an exclusive-OR logic operation, thereby reducing dynamic power consumption.

[0055] In some embodiments, the signal processing module 20 is further configured to apply a third forward bias voltage and a fourth forward bias voltage to the resistive memory unit 10 in sequence according to a preset timing when the first signal X1 is a high-level signal and the second signal X2 is a low-level signal, wherein the third forward bias voltage is greater than the first forward threshold voltage Vth1 and less than the second forward threshold voltage Vth2, and the fourth forward bias voltage is less than the first forward threshold voltage Vth1.

[0056] When the first signal X1=1 and the second signal X2=0, a third forward bias voltage is first applied to the resistive memory cell 10. The third forward bias voltage is greater than the first forward threshold voltage Vth1 and less than the second forward threshold voltage Vth2, so that the resistive memory cell 10 jumps from the initial high resistance state to the low resistance state. Then, a fourth forward bias voltage is applied to the resistive memory cell 10. The fourth forward bias voltage is less than the first forward threshold voltage Vth1. The resistance value of the resistive memory cell 10 does not change, that is, the resistive memory cell 10 maintains the low resistance state, so that the resistive memory cell 10 generates a large output current, and then outputs a logic operation result as a high-level signal (logic '1').

[0057] By sequentially applying a third forward bias voltage and a fourth forward bias voltage to the resistive memory cell 10, a logic '1' can be output when the first signal X1 = 1 and the second signal X2 = 0. The voltage-controlled resistance characteristic of the resistive memory cell 10 can be utilized to implement an exclusive-OR logic operation, thereby reducing dynamic power consumption.

[0058] In some embodiments, the signal processing module 20 is further configured to apply a fifth forward bias voltage and a sixth forward bias voltage to the resistive memory unit 10 in sequence according to a preset timing when the first signal X1 and the second signal X2 are both low-level signals, and the fifth forward bias voltage and the sixth forward bias voltage are both less than the first forward threshold voltage Vth1 at which the resistive memory unit 10 jumps from a high-resistance state to a low-resistance state.

[0059] When the first signal X1=0 and the second signal X2=0, a fifth forward bias voltage and a sixth forward bias voltage are sequentially applied to the resistive memory cell 10. The fifth forward bias voltage and the sixth forward bias voltage are both lower than the first forward threshold voltage Vth1 at which the resistive memory cell 10 switches from a high resistance state to a low resistance state. Therefore, the resistive memory cell 10 always maintains a high resistance state, so that the resistive memory cell 10 generates a small output current, and thus outputs a logic operation result as a low-level signal (logic '0').

[0060] By sequentially applying the fifth forward bias voltage and the sixth forward bias voltage to the resistive memory cell 10, a logic '0' can be output when the first signal X1 = 0 and the second signal X2 = 0. The voltage-controlled resistance characteristic of the resistive memory cell 10 can be used to implement an exclusive-OR logic operation, thereby reducing dynamic power consumption.

[0061] In some embodiments, the signal processing module 20 is further configured to apply a seventh forward bias voltage and an eighth forward bias voltage to the resistive memory unit 10 in sequence according to a preset timing when the first signal X1 and the second signal X2 are both low-level signals, and the seventh forward bias voltage and the eighth forward bias voltage are greater than the first forward threshold voltage Vth1 and less than the second forward threshold voltage Vth2, and the second forward threshold voltage Vth2 is greater than the first forward threshold voltage Vth1.

[0062] When the first signal X1 = 1 and the second signal X2 = 1, a seventh forward bias voltage and an eighth forward bias voltage are sequentially applied to the resistive memory cell 10. Both the seventh forward bias voltage and the eighth forward bias voltage are greater than the first forward threshold voltage Vth1 and less than the second forward threshold voltage Vth2. After the seventh forward bias voltage is applied to the resistive memory cell 10, the resistive memory cell 10 transitions from a high-resistance state to a low-resistance state. While the resistive memory cell 10 is in the low-resistance state, the eighth forward bias voltage having the same magnitude as the seventh forward bias voltage is continuously applied. This resets the low-resistance state of the resistive memory cell 10 to a high-resistance state, causing the resistive memory cell 10 to generate a smaller output current and thereby output a low-level signal (logical '0') as a logical operation result.

[0063] By sequentially applying the seventh forward bias voltage and the eighth forward bias voltage to the resistive memory cell 10, a logic '0' can be output when the first signal X1 = 1 and the second signal X2 = 1. The voltage-controlled resistance characteristic of the resistive memory cell 10 can be used to implement an exclusive-OR logic operation, thereby reducing dynamic power consumption.

[0064] In some embodiments, the multiple logic signals also include a third signal X3, and the signal processing module 20 is further configured to apply a ninth forward bias voltage to the resistive memory unit 10 when the third signal X3 is a low-level signal, and the ninth forward bias voltage is less than the first forward threshold voltage at which the resistive memory unit 10 jumps from a high-resistance state to a low-resistance state.

[0065] In the above embodiment, the resistive memory cell 10 has stored the intermediate result of the XOR operation of the first signal X1 and the second signal X2. When the third signal X3 = 0, it is equivalent to keeping the result of the XOR operation of the first signal X1 and the second signal X2.

[0066] Specifically, when the first signal X1=0 and the second signal X2=1 or the first signal X1=1 and the second signal X2=0, after applying the bias voltage according to the aforementioned embodiment, the resistive memory cell 10 is in a low-resistance state. Under this premise, the third signal X3=0, and a ninth forward bias voltage less than the first forward threshold voltage Vth1 is applied to the resistive memory cell 10. The ninth forward bias voltage does not reach the voltage threshold for triggering a resistance state jump in the resistive memory cell 10. Therefore, the resistive memory cell 10 maintains a low-resistance state, generates a large output current, and outputs a logic operation result as a high-level signal (logic '1').

[0067] It can be understood that when the first signal X1 and the second signal X2 have the same logic level, that is, when the first signal X1=1 and the second signal X2=1 or the first signal X1=0 and the second signal X2=0, after applying the bias voltage according to the above embodiment, the resistive memory unit 10 is in a high-resistance state. Under this premise, the third signal X3=0, and a ninth forward bias voltage less than the first forward threshold voltage Vth1 is applied to the resistive memory unit 10. The ninth forward bias voltage does not reach the voltage threshold for triggering a resistance state jump of the resistive memory unit 10. Therefore, the resistive memory unit 10 maintains a high-resistance state, generates a small output current, and outputs a logic operation result as a low-level signal (logic '0').

[0068] This embodiment only requires a single resistive memory unit 10 to implement continuous XOR operations, which significantly reduces the number of transistors, facilitates improving integration density, and can reduce dynamic power consumption.

[0069] In some embodiments, the multiple logic signals also include a third signal X3, and the signal processing module 20 is further configured to apply a first negative bias voltage to the resistive memory unit 10 when the third signal X3 is a high-level signal, and the absolute value of the first negative bias voltage is greater than the absolute value of the first negative phase voltage threshold Vth3 and less than the absolute value of the second negative phase voltage threshold Vth4; the first negative phase voltage threshold Vth3 is the negative threshold voltage at which the resistive memory unit 10 jumps from a high resistance state to a low resistance state, and the second negative phase voltage threshold Vth4 is the negative threshold voltage at which the resistive memory unit 10 jumps from a low resistance state to a high resistance state, and the absolute value of the first negative phase voltage threshold Vth3 is less than the absolute value of the second negative phase voltage threshold Vth4.

[0070] In the above embodiment, the resistive memory unit 10 has stored the intermediate result of the XOR operation of the first signal X1 and the second signal X2. When the third signal X3 = 1, it is equivalent to flipping the result of the XOR operation of the first signal X1 and the second signal X2.

[0071] For example, a complementary resistance switch type resistive random access memory includes a first memristor and a second memristor, a positive bias voltage adjusts the resistance state of the first memristor, and a negative bias voltage adjusts the resistance state of the second memristor.

[0072] Specifically, when the first signal X1 = 1 and the second signal X2 = 0, or when the first signal X1 = 0 and the second signal X2 = 1, after applying the bias voltage according to the aforementioned embodiment, the first memristor is in a low-resistance state, and a large current flows in the resistive memory cell 10. Under this premise, when the third signal X3 = 1, a first negative bias voltage having an absolute value greater than the absolute value of the first negative phase voltage threshold Vth3 and less than the absolute value of the second negative phase voltage threshold Vth4 is applied to the resistive memory cell 10. The low-resistance state of the resistive memory cell 10 is reset to a high-resistance state, and the resistive memory cell 10 generates a small output current, thereby outputting a low-level signal (logical '0') as the logical operation result.

[0073] It can be understood that when the first signal X1 and the second signal X2 have the same logic level, that is, when the first signal X1=1 and the second signal X2=1 or the first signal X1=0 and the second signal X2=0, after applying the bias voltage according to the above embodiment, the resistive memory unit 10 is in a high-resistance state. Under this premise, the third signal X3=1, the first negative bias voltage is applied to the resistive memory unit 10, the second memristor jumps to a low-resistance state, the current in the resistive memory unit 10 increases, the resistive memory unit 10 generates a larger output current, and then outputs a logic operation result as a high-level signal (logic '1').

[0074] This embodiment only requires a single resistive memory unit 10 to implement continuous XOR operations, which significantly reduces the number of transistors, facilitates improving integration density, and can reduce dynamic power consumption.

[0075] In some embodiments, the signal processing module 20 is further configured to apply a second negative bias voltage to the resistive memory unit 10 when the logic operation is completed, so as to make the resistive memory unit 10 switch to a high-resistance state.

[0076] After completing the logic operation, a second negative bias voltage is applied to switch the resistive memory cell 10 to a high-resistance state. In the high-resistance state, the leakage current of the resistive memory cell 10 is much smaller than that in the low-resistance state, which can significantly reduce static power consumption and wait for the next logic operation.

[0077] Figure 4 The circuit topology diagram of the cryptographic processor provided in the embodiment of the present application is shown. Figure 4 An embodiment of the present application further provides a cryptographic processor, including a word line WL, a bit line BL, a non-volatile resistive memory 30 and the aforementioned logic operation circuit, wherein a first end of the logic operation circuit is connected to the bit line BL, a second end of the logic operation circuit is connected to a first end of the non-volatile resistive memory 30, and a second end of the non-volatile resistive memory 30 is connected to the word line WL.

[0078] Word lines (WL) and bit lines (BL) form the core interconnect structure of the memory array, enabling precise addressing, read / write control, and signal transmission for the nonvolatile resistive random access memory (NRRAM) 30. The NRRAM 30 is used to store pixel information, and the logic operation circuit is used to encrypt and decrypt the pixel information stored in the NRRAM 30.

[0079] In some embodiments, the cryptographic processor includes a plurality of bit lines BL and a plurality of word lines WL, the bit lines BL and the word lines WL forming a crossbar array structure, and a plurality of nonvolatile resistive memory cells 30 and a plurality of resistive memory cells 10 are connected in series in a one-to-one correspondence.

[0080] The cryptographic processor can be used to encrypt and decrypt multi-bit grayscale pixels. Each pixel corresponds to a cross-point unit. During encryption, each pixel is XORed with the key according to the aforementioned logic operation circuit, and the result is then written to the corresponding cross-point unit through array operations. During decryption, the same key is XORed with the encrypted data again, and the original pixel value is restored by reading the resistance state of the cross-point unit.

[0081] As an example, consider a 5×3 resistive memory array storing 15 gray pixels. The pixel in the second row and third column is white (representing a logic '0'), corresponding to a logic '1' in the key bit. Setting the resistive memory cell 10 in this intersection unit to a low-resistance state results in a logic '1' after encryption. During decryption, the resistive memory cell 10 is in a low-resistance state, corresponding to a logic '1'. This logic '1' is XORed with the key bit's logic '1', resulting in a logic '0' after decryption, restoring the original white pixel.

[0082] The specific principles of the logic operation circuit can be referred to the relevant description of the above embodiments, which will not be described in detail here.

[0083] By utilizing the voltage-controlled resistance characteristic of the resistive memory unit 10, the resistance state of the resistive memory unit 10 is modulated to perform an XOR logic operation, thereby realizing encryption and decryption of pixels, reducing the number of transistors, improving integration density, and reducing dynamic power consumption.

[0084] In some embodiments, the resistive memory cell 10 comprises a complementary resistance switch type resistive memory.

[0085] The complementary resistance switch type resistive random access memory consists of two anti-series memristors. By applying voltage pulses of different polarities or amplitudes at a preset timing, one unit can be driven to jump from a high-resistance state to a low-resistance state, and the other unit can jump from a low-resistance state to a high-resistance state. No external comparison circuit or intermediate state storage is required, and the XOR operation is completed in a single step, reducing operation delay and circuit complexity.

[0086] The above describes in detail a logic operation circuit and cryptographic processor provided by the present application. Specific examples are used herein to illustrate the principles and implementation methods of the present application. The description of the above embodiments is intended only to facilitate understanding of the method and core concept of the present application. It should be noted that, without departing from the principles of the present application, a number of improvements and modifications may be made to the present application by a person of ordinary skill in the art, and such improvements and modifications fall within the scope of protection of the claims of the present application.

Claims

1. A logic operation circuit, characterized in that: include: A resistive memory cell, wherein the resistive memory cell is a complementary resistance switch type resistive memory, the resistive memory cell having a first resistance state and a second resistance state, wherein a first output current in the first resistance state corresponds to a first logic level, and a second output current in the second resistance state corresponds to a second logic level; a signal processing module, wherein an input end of the signal processing module is used to receive a plurality of logic signals, an output end of the signal processing module is connected to an input end of the resistive memory unit, and the signal processing module is configured to apply a bias voltage to the resistive memory unit according to the logic signals to place the resistive memory unit in the first resistance state or the second resistance state; The plurality of logic signals include a first signal and a second signal, and the signal processing module is configured to apply a first voltage and a second voltage having different polarities or amplitudes to the resistive memory unit according to a preset timing sequence when the first signal and the second signal have different logic levels, so as to adjust the resistance state of the resistive memory unit to a first resistance state; When the first signal and the second signal have the same logic level, a third voltage and a fourth voltage with the same polarity and amplitude are applied to the resistive memory unit in a preset timing sequence to adjust the resistance state of the resistive memory unit to a second resistance state.

2. The logic operation circuit according to claim 1, wherein: The first resistance state is a high resistance state, and the second resistance state is a low resistance state. The signal processing module is further configured to apply a first forward bias voltage and a second forward bias voltage to the resistive memory unit in sequence according to a preset timing when the first signal is a low-level signal and the second signal is a high-level signal, wherein the first forward bias voltage is less than a first forward threshold voltage, and the second forward bias voltage is greater than the first forward threshold voltage and less than the second forward threshold voltage; The first forward threshold voltage is the forward threshold voltage at which the resistive memory cell transitions from a high resistance state to a low resistance state, and the second forward threshold voltage is the forward threshold voltage at which the resistive memory cell transitions from a low resistance state to a high resistance state, and the second forward threshold voltage is greater than the first forward threshold voltage.

3. The logic operation circuit according to claim 2, wherein: The signal processing module is further configured to apply a third forward bias voltage and a fourth forward bias voltage to the resistive memory unit in sequence according to a preset timing when the first signal is a high-level signal and the second signal is a low-level signal, wherein the third forward bias voltage is greater than the first forward threshold voltage and less than the second forward threshold voltage, and the fourth forward bias voltage is less than the first forward threshold voltage.

4. The logic operation circuit according to claim 1, wherein: The first resistance state is a high resistance state, and the second resistance state is a low resistance state. The signal processing module is further configured to apply a fifth forward bias voltage and a sixth forward bias voltage to the resistive memory unit in sequence according to a preset timing when both the first signal and the second signal are low-level signals. The fifth forward bias voltage and the sixth forward bias voltage are both less than the first forward threshold voltage at which the resistive memory unit jumps from a high resistance state to a low resistance state.

5. The logic operation circuit according to claim 4, wherein: The signal processing module is further configured to apply a seventh forward bias voltage and an eighth forward bias voltage to the resistive memory unit in sequence according to a preset timing when both the first signal and the second signal are low-level signals, wherein the seventh forward bias voltage and the eighth forward bias voltage are greater than the first forward threshold voltage and less than the second forward threshold voltage, and the second forward threshold voltage is greater than the first forward threshold voltage.

6. The logic operation circuit according to claim 1, wherein: The first resistance state is a high resistance state, the second resistance state is a low resistance state, the multiple logic signals also include a third signal, and the signal processing module is further configured to apply a ninth forward bias voltage to the resistive memory unit when the third signal is a low-level signal, and the ninth forward bias voltage is less than the first forward threshold voltage of the resistive memory unit at which the resistive memory unit jumps from a high resistance state to a low resistance state.

7. The logic operation circuit according to claim 1, wherein: The first resistance state is a high resistance state, the second resistance state is a low resistance state, the multiple logic signals further include a third signal, and the signal processing module is further configured to apply a first negative bias voltage to the resistive memory unit when the third signal is a high-level signal, wherein the absolute value of the first negative bias voltage is greater than the absolute value of the first negative phase voltage threshold and less than the absolute value of the second negative phase voltage threshold; The first negative phase voltage threshold is a negative threshold voltage at which the resistive memory unit jumps from a high resistance state to a low resistance state, and the second negative phase voltage threshold is a negative threshold voltage at which the resistive memory unit jumps from a low resistance state to a high resistance state. The absolute value of the first negative phase voltage threshold is less than the absolute value of the second negative phase voltage threshold.

8. The logic operation circuit according to any one of claims 1 to 7, characterized in that: The first resistance state is a high resistance state, and the signal processing module is further configured to apply a second negative bias voltage to the resistive memory unit when a logic operation is completed, so that the resistive memory unit jumps to the first resistance state.

9. A cryptographic processor, characterized in that: The invention comprises a word line, a bit line, a non-volatile resistive random access memory, and a logic operation circuit according to any one of claims 1 to 8, wherein a first end of the logic operation circuit is connected to the bit line, a second end of the logic operation circuit is connected to a first end of the non-volatile resistive random access memory, and a second end of the non-volatile resistive random access memory is connected to the word line.

10. The cryptographic processor according to claim 9, wherein: The resistive memory unit includes a complementary resistance switch type resistive memory.

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