Non-polarity wide voltage range sampling circuit

Abstract

The present invention relates to a non-polarity, wide-range voltage sampling circuit. The circuit comprises a polarity switching circuit (NMOS transistors Q1 and Q2, connected to detection voltages T1 and T2, respectively, with their sources sharing a common ground); an inverting drive circuit (the base of a PNP transistor Q3 is connected to the output of a voltage comparator U1, the collector is connected to the gate of Q1 via R8, and the output of U1 is connected to the gate of Q2 via R10); a voltage comparator circuit (U1 and a voltage divider R1-R4, with the voltages of T1 and T2 divided and connected to the non-inverting and inverting terminals of U1); and an output switching circuit. Q2 conducts when T1 is positive and T2 is negative, and Q1 conducts when T1 is positive and T2 is negative. U1 outputs a high or low voltage level to control the states of Q3, Q1, and Q2. U2 in the output switching circuit switches between CH1 and CH0 and connects to COM according to SEL. The resistance values ​​of R1 and R3, and R2 and R4, are equal, and the voltage divider resistors can be adjusted to accommodate different voltages. This invention implements non-polarity, wide-range voltage sampling, ensuring accurate sampling and circuit stability.

Description

Technical Field

[0001] The present invention relates to the technical field of analog circuit design, and in particular to a wide-range voltage sampling circuit for a single-chip microcomputer analog-to-digital converter (ADC) port, which is particularly suitable for positive and negative voltage non-polarity detection and wide voltage signal conditioning. Background Art

[0002] In modern electronic systems, the analog-to-digital converter (ADC) port of a microcontroller can only sample positive voltage signals. Sampling negative voltages typically requires additional circuit processing. However, existing technologies have numerous drawbacks. For one thing, conventional circuits cannot simultaneously sample positive and negative voltages, making accurate and reliable sampling particularly difficult for higher voltage ranges. Furthermore, unipolar sampling circuits can damage the entire system if the voltage polarity is reversed, posing a safety hazard. For example, in power supply monitoring systems and electrical equipment fault detection, the inability to accurately and safely sample and monitor positive and negative voltages across a wide voltage range limits the system's functionality and application scope.

[0003] Therefore, a non-polarity wide voltage range sampling circuit is urgently needed to solve the problems in the prior art that positive and negative voltages cannot be sampled simultaneously and the system may be damaged when the voltage polarity is reversed. Summary of the Invention

[0004] The purpose of the present invention is to address the above-mentioned problems existing in the prior art and provide a non-polarity wide voltage range sampling circuit, which utilizes the coordinated work of circuits such as MOSFET polarity switching, PNP transistor inverting drive, voltage comparison and analog switch output switching to achieve non-polarity sampling in a wide voltage range.

[0005] In order to achieve the above application objectives, the present invention adopts the following technical solutions: a non-polarity wide voltage range sampling circuit includes:

[0006] Polarity switching circuit: includes NMOS transistor Q1 and NMOS transistor Q2, the drain of NMOS transistor Q1 is connected to detection voltage T1, the drain of NMOS transistor Q2 is connected to detection voltage T2, and the sources of NMOS transistor Q1 and NMOS transistor Q2 are grounded in common;

[0007] Inverting drive circuit: includes a PNP transistor Q3, the base of the PNP transistor Q3 is connected to the output end of the voltage comparator U1, the collector of the PNP transistor Q3 is connected to the gate of the NMOS transistor Q1 via a resistor R8, and the output end of the voltage comparator U1 is also connected to the gate of the NMOS transistor Q2 via a resistor R10;

[0008] Voltage comparison circuit: includes a voltage comparator U1 and a voltage divider composed of resistors R1-R4. Resistors R1 and R2 divide the voltage at the detection voltage T1 and then connect it to the non-inverting terminal of the voltage comparator U1. Resistors R3 and R4 divide the voltage at the detection voltage T2 and then connect it to the inverting terminal of the voltage comparator U1.

[0009] Output switching circuit: includes a single-pole double-throw analog switch U2, the input terminal CH1 of the single-pole double-throw low-resistance analog switch U2 is connected to the voltage dividing point A of the resistor R1 and the resistor R2, the input terminal CH0 is connected to the voltage dividing point B of the resistor R3 and the resistor R4, the common port COM is output to the MCU for sampling, and the output terminal of the voltage comparator U1 is connected to the control terminal SEL of the single-pole double-throw low-resistance analog switch U2.

[0010] Furthermore, when the detection voltage T1 is positive and the detection voltage T2 is negative, the gate of the NMOS transistor Q2 is at a high level, the NMOS transistor Q2 is turned on, and the detection voltage T2 terminal is connected to the ground; when the detection voltage T1 is negative and the detection voltage T2 is positive, the gate of the NMOS transistor Q1 is at a high level, the NMOS transistor Q1 is turned on, and the detection voltage T1 terminal is connected to the ground.

[0011] Furthermore, when the voltage comparator U1 outputs a high level, the PNP transistor Q3 is turned off, the NMOS transistor Q1 is turned off, and the NMOS transistor Q2 is turned on; when the voltage comparator U1 outputs a low level, the PNP transistor Q3 is turned on, the NMOS transistor Q1 is turned on, and the NMOS transistor Q2 is turned off.

[0012] Furthermore, when the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 is at a high level, the input terminal CH1 is connected to the common port COM; when the control terminal SEL is at a low level, the input terminal CH0 is connected to the common port COM.

[0013] Furthermore, the resistance values ​​of the resistor R1 and the resistor R3 are equal, and the resistance values ​​of the resistor R2 and the resistor R4 are equal.

[0014] Furthermore, by adjusting the resistance ratio of the resistors in the voltage divider, different input voltage ranges can be adapted.

[0015] Furthermore, a resistor R9 and a resistor R8 are provided between the NMOS transistor Q1 and the NMOS transistor Q2.

[0016] Furthermore, the base of the PNP transistor Q3 is also connected to a resistor R7 , and the other end of the resistor R7 is grounded.

[0017] Furthermore, the power supply terminals of the voltage comparator U1 are connected to +5V and ground respectively.

[0018] Furthermore, the output terminal of the voltage comparator U1 is connected to the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 via the resistor R5.

[0019] Compared with the prior art, the present invention has the following beneficial effects:

[0020] 1. It realizes non-polarity sampling in a wide voltage range (-80V to +80V), solves the problem of positive and negative voltage polarity conversion of the microcontroller ADC sampling port, breaks through the limitations of existing technology, and greatly expands the sampling voltage range.

[0021] 2. The circuit structure is simple, consisting only of conventional devices such as MOSFET, triode, voltage comparator, analog switch, etc. The small number of devices reduces the complexity and failure points of the circuit and improves reliability.

[0022] 3. It is low-cost and easy to implement, making it easy to promote and apply in various electronic systems that require voltage sampling, thereby improving the overall performance and safety of the system. BRIEF DESCRIPTION OF THE DRAWINGS

[0023] Figure 1 is a circuit diagram of the present invention;

[0024] Figure 2 yes Figure 1 Schematic diagram of the polarity switching circuit Q2 being turned on;

[0025] Figure 3 yes Figure 1 Schematic diagram of the polarity switching circuit Q1 being turned on;

[0026] Figure 4 yes Figure 1 A magnified view of the inverting drive circuit;

[0027] Figure 5 yes Figure 1 A magnified view of the medium voltage comparison circuit;

[0028] Figure 6 yes Figure 1 A magnified view of the output switching circuit. DETAILED DESCRIPTION

[0029] The following will clearly and completely describe the technical solutions in the embodiments of the present invention in conjunction with the accompanying drawings. Obviously, the described embodiments are only part of the embodiments of the present invention, not all of the embodiments. All other embodiments obtained by ordinary technicians in this field based on the embodiments of the present invention are within the scope of protection of the present invention.

[0030] Those skilled in the art should understand that, in the disclosure of the present invention, the terms "longitudinal", "transverse", "up", "down", "front", "back", "left", "right", "vertical", "horizontal", "top", "bottom", "inside", "outside", etc., indicating the orientation or position relationship, are based on the orientation or position relationship shown in the accompanying drawings, which are only for the convenience of describing the present invention and simplifying the description, rather than indicating or implying that the device or element referred to must have a specific orientation, be constructed and operated in a specific orientation. Therefore, the above terms cannot be understood as limiting the present invention.

[0031] like Figure 1 As shown, the non-polarity wide voltage range sampling circuit includes a MOSFET polarity switching circuit 1, a PNP transistor inverting drive circuit 2, a voltage comparison circuit 3 and an output switching circuit 4.

[0032] like Figure 2 and Figure 3 As shown, MOSFET polarity switching circuit 1: the drain of NMOS transistor Q1 is connected to detection voltage T1, the drain of NMOS transistor Q2 is connected to detection voltage T2, the sources of NMOS transistors Q1 and Q2 are grounded, and resistors R9 and R8 are provided between NMOS transistors Q1 and Q2. Here, NMOS transistors Q1 and Q2 are both N-channel MOSFETs.

[0033] When the detection voltage T1 is positive and the detection voltage T2 is negative, the gate of the NMOS tube Q2 is at a high level, the NMOS tube Q2 is turned on, and the detection voltage T2 terminal is connected to the ground; when the detection voltage T1 is negative and the detection voltage T2 is positive, the gate of the NMOS tube Q1 is at a high level, the NMOS tube Q1 is turned on, and the detection voltage T1 terminal is connected to the ground.

[0034] like Figure 4 As shown, PNP transistor inverting drive circuit 2 includes a PNP transistor Q3. The base of PNP transistor Q3 is connected to the output of voltage comparator U1. The collector of PNP transistor Q3 is connected to the gate of NMOS transistor Q1 via resistor R8. The output of voltage comparator U1 is also connected to the gate of NMOS transistor Q2 via resistor R10. The base of PNP transistor Q3 is also connected to resistor R7, the other end of which is grounded. Voltage comparator U1 (model TL331) is paired with resistors R1 (150.0KΩ), R2 (10.0KΩ), R3 (150.0KΩ), and R4 (10.0KΩ) to form a voltage divider network.

[0035] When the voltage comparator U1 outputs a high level, the PNP transistor Q3 is cut off, the NMOS transistor Q1 is cut off, and the NMOS transistor Q2 is turned on; when the voltage comparator U1 outputs a low level, the PNP transistor Q3 is turned on, the NMOS transistor Q1 is turned on, and the NMOS transistor Q2 is cut off. In this way, the inverted drive of Q1 and Q2 can be achieved through the PNP transistor Q3.

[0036] As Figure 5 shown, the voltage comparison circuit 3 includes a voltage comparator U1 and a voltage divider composed of resistors R1 - R4. After the voltages at the T1 terminal of the detected voltage are divided by the resistor R1 and the resistor R2, they are connected to the non-inverting input terminal of the voltage comparator U1. After the voltages at the T2 terminal of the detected voltage are divided by the resistor R3 and the resistor R4, they are connected to the inverting input terminal of the voltage comparator U1. The power supply terminals of the voltage comparator U1 are respectively connected to +5V and ground.

[0037] The resistance value of the resistor R1 is equal to that of the resistor R3, and the resistance value of the resistor R2 is equal to that of the resistor R4. The voltage division ratio is selected according to the measured voltage range ( Figure 5 in the resistor voltage division ratio, it is possible to sample from -80V to +80V). The voltage at point A or point B after voltage division is the sampled voltage. When voltage A > B, the comparator outputs a high level; when A < B, the comparator outputs a low level. The output terminal of the voltage comparator U1 is connected to the gate of the NMOS transistor Q2 through the resistor R10 to drive the NMOS transistor Q2, connected to the base of the PNP transistor Q3 through the resistor R6, and after being inverted and driven by the PNP transistor Q3, the NMOS transistor Q1 is connected to the control terminal SEL of the single-pole double-throw analog switch U2 through the resistor R5.

[0038] As Figure 6 shown, the output switching circuit 4 includes a single-pole double-throw analog switch U2 (model CH443K). The input terminal CH1 of the single-pole double-throw low-resistance analog switch U2 is connected to the voltage division point A of the resistors R1 and R2, the input terminal CH0 is connected to the voltage division point B of the resistors R3 and R4, and the common port COM outputs to the MCU for sampling. The output terminal of the voltage comparator U1 is connected to the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 through the resistor R5.

[0039] The output signal of the voltage comparator U1 controls the control terminal SEL pin of the double-throw analog switch U2. When the voltage comparator U1 outputs a high level, SEL is driven, and the single-pole double-throw analog switch U2 selects to connect CH1 and COM, and the voltage at point A is output to the ADC; when the voltage comparator U1 outputs a low level, the single-pole double-throw analog switch U2 selects to connect CH0 and COM, and the voltage at point B is output to the ADC. In this way, regardless of the polarity of the input voltage, the voltage signal output to the ADC port of the MCU is always a positive voltage signal, achieving non-polar sampling and ensuring that the single-chip microcomputer can accurately collect voltage signals in a wide range.

[0040] The parts not described in detail in the present invention are prior art, so the present invention does not describe them in detail.

[0041] It is to be understood that the term "one" should be understood as "at least one" or "one or more", that is, in one embodiment, the number of an element may be one, while in another embodiment, the number of the elements may be multiple, and the term "one" should not be understood as a limitation on the quantity.

[0042] Although this document uses a lot of professional terms, it does not exclude the possibility of using other terms. These terms are used only to more conveniently describe and explain the essence of the present invention; interpreting them as any additional limitations is contrary to the spirit of the present invention.

[0043] The present invention is not limited to the above-mentioned optimal implementation mode. Anyone can derive other forms of products under the inspiration of the present invention. However, no matter what changes are made in the shape or structure, any technical solution that is the same or similar to the present invention falls within the scope of protection of the present invention.

Claims

1. Non-polarity wide voltage range sampling circuit, characterized in that: include: Polarity switching circuit: comprising an NMOS transistor Q1 and an NMOS transistor Q2, wherein the drain of the NMOS transistor Q1 is connected to the detection voltage T1, the drain of the NMOS transistor Q2 is connected to the detection voltage T2, and the sources of the NMOS transistors Q1 and Q2 are grounded in common; Inverting drive circuit: comprising a PNP transistor Q3, the base of the PNP transistor Q3 being connected to the output end of the voltage comparator U1, the collector of the PNP transistor Q3 being connected to the gate of the NMOS transistor Q1 via a resistor R8, and the output end of the voltage comparator U1 being further connected to the gate of the NMOS transistor Q2 via a resistor R10; Voltage comparison circuit: includes a voltage comparator U1 and a voltage divider formed by resistors R1-R4. Resistors R1 and R2 divide the voltage at the detection voltage T1 and then connect the voltage to the non-inverting terminal of the voltage comparator U1. Resistors R3 and R4 divide the voltage at the detection voltage T2 and then connect the voltage to the inverting terminal of the voltage comparator U1. The connection point between resistors R1 and R2 is voltage divider point A, and the connection point between resistors R3 and R4 is voltage divider point B. Output switching circuit: includes a single-pole double-throw analog switch U2, the input end CH1 of the single-pole double-throw low-resistance analog switch U2 is connected to the voltage dividing point A, the input end CH0 is connected to the voltage dividing point B, the common port COM is output to the MCU for sampling, and the output end of the voltage comparator U1 is connected to the control end SEL of the single-pole double-throw low-resistance analog switch U2.

2. The non-polarity wide voltage range sampling circuit according to claim 1, characterized in that: When the detection voltage T1 is positive and the detection voltage T2 is negative, the gate of the NMOS tube Q2 is at a high level, the NMOS tube Q2 is turned on, and the detection voltage T2 terminal is connected to the ground; when the detection voltage T1 is negative and the detection voltage T2 is positive, the gate of the NMOS tube Q1 is at a high level, the NMOS tube Q1 is turned on, and the detection voltage T1 terminal is connected to the ground.

3. The non-polarity wide voltage range sampling circuit according to claim 1, characterized in that: When the voltage comparator U1 outputs a high level, the PNP transistor Q3 is turned off, the NMOS transistor Q1 is turned off, and the NMOS transistor Q2 is turned on; when the voltage comparator U1 outputs a low level, the PNP transistor Q3 is turned on, the NMOS transistor Q1 is turned on, and the NMOS transistor Q2 is turned off.

4. The non-polarity wide voltage range sampling circuit according to claim 1, characterized in that: When the control terminal SEL of the single-pole double-throw low-resistance analog switch U2 is at a high level, the input terminal CH1 is connected to the common port COM; when the control terminal SEL is at a low level, the input terminal CH0 is connected to the common port COM.

5. The non-polarity wide voltage range sampling circuit according to claim 1, characterized in that: The resistance values ​​of the resistor R1 and the resistor R3 are equal, and the resistance values ​​of the resistor R2 and the resistor R4 are equal.

6. The non-polarity wide voltage range sampling circuit according to claim 1, characterized in that: By adjusting the resistance ratio of the resistors in the voltage divider, different input voltage ranges can be adapted.

7. The non-polarity wide voltage range sampling circuit according to claim 1, characterized in that: Resistors R9 and R8 are provided between the NMOS transistor Q1 and the NMOS transistor Q2.

8. The non-polarity wide voltage range sampling circuit according to any one of claims 1 to 7, characterized in that: The base of the PNP transistor Q3 is further connected to a resistor R7 , and the other end of the resistor R7 is grounded.

9. The non-polarity wide voltage range sampling circuit according to any one of claims 1 to 7, characterized in that: The power supply terminals of the voltage comparator U1 are connected to +5V and ground respectively.

10. The non-polarity wide voltage range sampling circuit according to any one of claims 1 to 7, characterized in that: The output end of the voltage comparator U1 is connected to the control end SEL of the single-pole double-throw low-resistance analog switch U2 via the resistor R5.

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