Method for producing integrated circuit and corresponding integrated circuit

Abstract

The invention relates to a method for manufacturing an integrated circuit and a corresponding integrated circuit. An integrated circuit includes a lateral isolation region defining an active region in a semiconductor substrate. A trench is etched extending vertically in depth into the semiconductor substrate, intended to pass through the lateral isolation regions and the active regions. The formation of the lateral isolation regions includes forming sacrificial lateral isolation regions at locations of trenches etched through the active regions.

Description

[0001] Priority Claim

[0002] This application claims the benefit of priority of French Patent Application No. 2400559, filed on January 19, 2024, the entire content of which is incorporated herein by reference to the maximum extent permitted by law. Technical Field

[0003] The embodiments and examples relate to integrated circuits and, more particularly, to integrated circuits including trenches extending vertically in depth in a substrate, such as integrated circuits incorporating vertical gate buried transistors (e.g., transistors for accessing non-volatile memory cells). Background Art

[0004] Figure 1A 、 Figure 1B and Figure 1C show an example of a memory plane incorporating memory cells CEL1, CEL2 in non-volatile memory technology, the non-volatile memory technology including providing a floating gate state transistor TE in series with a vertical gate buried access transistor TA for each memory cell CEL1, CEL2.

[0005] Figure 1A Illustrate the arrangement of memory cells in a top view of the memory plane (in the semiconductor portion, which is typically designated or referred to as the front-end-of-line (FEOL) in this technology).

[0006] Figure 1B shows Figure 1A a cross-sectional view in plane BB of, the plane BB passing through the gate region and the vertical gate region of the state transistor in width.

[0007] Figure 1C shows Figure 1A a cross-sectional view in plane CC of, passing through the vertical gate region in length.

[0008] Briefly, the state transistor TE enables the storage of charges representing binary data items in its floating gate FG, and the access transistor TA enables selective access to the memory cells CEL1, CEL2, for example, in write and read modes.

[0009] In addition, in order to access the memory cells CEL1, CEL2, the drain region D of the state transistor TE is typically connected to bit lines BL1, BL2, while the source region of the access transistor TA is accessed by a region NISO implanted in depth into the substrate, which region NISO may be referred to as the source plane.

[0010] Typically, the bottom of the vertical gate TRG of the access transistor TA does not contact the source plane NISO in depth, and the source region Simp (also referred to as the source implant) is implanted into the substrate from the bottom of the trench in which the vertical gate TRG has been etched, between the bottom of the vertical gate TRG and the source plane NISO. Thus, the source implant Simp is provided to ensure the electrical continuity between the source region of the vertical gate transistor TRG and the source plane NISO.

[0011] The inventors have noted that performance limitations and yield losses in such non-volatile memory technologies may be related to a low access current in the memory cells, which is caused by a high resistance between the source-drain conductive regions of the access transistor TA in the on state.

[0012] This is because, if the trench including the vertical gate TRG has an effective depth p11 less than the nominal depth p10, the electrical continuity between the source implant Simp and the source plane NISO may be poorly established, which results in the aforementioned increase in the resistance of the access transistor TA.

[0013] The inventors have also established a correlation between the increase in the resistance of the access transistor TA and the depth of the lateral isolation region STI (typically a shallow isolation trench).

[0014] In fact, the trench containing the vertical gate TRG is etched, particularly through the lateral insulation region STI at the surface of the substrate (usually silicon oxide), and then into the substrate (usually single-crystalline silicon). However, etching the trench in silicon oxide is faster than in a single-crystalline substrate.

[0015] Therefore, for an equal etching time, if the depth p21 of the lateral isolation region STI is smaller, then the depth p11 of the trench TRG will be smaller, and if the depth p20 of the lateral isolation region STI is larger (or at the nominal value), then the depth p10 of the trench TRG will be larger (or at the nominal value).

[0016] Finally, a decrease in the depth p21 of the lateral insulation region STI in practice compared to the nominal depth p20 provided in the design may be caused by the phenomenon of stopping the etching of the shallow insulation trench STI (commonly referred to as "STI etch stop").

[0017] This undesirable phenomenon is essentially caused by the saturation of the etching material (reagent) in a too-narrow etching space or the products of the etching reaction. Thus, the "STI etch stop" phenomenon is related to the narrow width of the lateral isolation region STI. On the other hand, for a constant width in the design of the lateral isolation region STI, this phenomenon may occur randomly (especially with respect to the position on the semiconductor wafer) in the manufacturing process and is difficult to control.

[0018] Therefore, there is a need in the art to solve the above problems. Summary of the Invention

[0019] Embodiments and implementations of the aspects set forth below propose to form a sacrificial lateral isolation region over the entire location facing the trench etching, on the one hand in order to prevent the "STI etch stop" phenomenon, and on the other hand in order to obtain a vertical gate structure whose bottom is located at a deeper depth and moreover does not show variations substantially along the entire length of the trench. Specifically, the bottom of the trench is at the same depth as the position in the trench passing through the lateral isolation region and the position passing through the active region.

[0020] It should be noted in particular that the solutions provided in the embodiments and implementations defined below advantageously do not involve modifying the chemical reactions involved in the etching of shallow isolation STI trenches, which would be costly and difficult to practice in existing methods; nor modifying the overall nominal width of the lateral isolation region, which would affect the overall performance of the active region and / or the total surface area of the circuit; nor increasing the trench etching time, which would also have an impact on the formation of other devices using the same steps for etching vertical gate buried transistors.

[0021] Thus, according to one aspect, there is provided a method for manufacturing an integrated circuit, comprising: forming a lateral isolation region in a semiconductor substrate that defines an active region, and etching a trench that extends vertically in depth into the substrate and is intended to pass through the lateral isolation region and the active region, wherein forming the lateral isolation region includes forming a sacrificial lateral isolation region at the position of the active region passing through the etched trench.

[0022] The "position passing through the active region" refers to the positions where the active region is located on both sides of the trench.

[0023] Furthermore, although they have the same nature and are formed in the same steps, there is a difference between the lateral insulation region whose function is to define the active region of the circuit obtained after manufacturing and the sacrificial lateral insulation region whose function is to be etched (sacrificed) to improve the implementation of the etching step.

[0024] In fact, on the one hand, with respect to the etching position, the extent of the lateral isolation region does not have a narrow width that causes the "STI etch stop" phenomenon. Thus, this prevents a reduction in the depth of the vertical gate trench associated with a reduction in the depth of the shallow isolation region, and thus in particular prevents performance losses caused by a high resistance between the source-drain conductive regions of the access transistor in the on state.

[0025] On the other hand, the trench etched through the sacrificial lateral isolation region is deeper than a trench conventionally etched into the semiconductor substrate, which in turn helps to increase the depth of the bottom of the trench, especially in order to prevent performance losses caused by a high resistance between the source-drain conductive regions of the access transistor in the on state.

[0026] According to an embodiment, the structure of the sacrificial lateral isolation region is positioned to be completely removed during the etching of the trench, such that the sidewalls of the etched trench include the uncovered walls of the active region.

[0027] Therefore, the presence of the sacrificial lateral isolation region has no effect on the interface (uncovered walls) between the active region and the trench after etching.

[0028] According to one embodiment, forming the lateral isolation region defines the active region as a strip longitudinally extending in a first direction, while the trench longitudinally extends in a second direction perpendicular to the first direction, and the sacrificial lateral isolation region is positioned along the length of the trench in the second direction.

[0029] Therefore, the sacrificial side isolation region is positioned to "cross" the active region in the second direction, and the trench etching is performed at positions that only face the sacrificial side region and not the alternating strips of the active region and the lateral isolation region.

[0030] According to one implementation, the lateral isolation region is formed by a volume of dielectric material in the substrate, while the active region is formed by the semiconductor material of the substrate; the kinetics of trench etching is faster in the dielectric material than in the semiconductor material of the substrate.

[0031] According to one embodiment, the gate of the vertical gate buried access transistor is formed in a trench that is etched in depth in the substrate, and a stack of a floating gate and a control gate is formed, with the stack at least partially covering the state transistor of the active region near the trench.

[0032] According to another aspect, an integrated circuit is also provided, which includes: a lateral isolation region that defines an active region in a semiconductor substrate; and a device disposed in a trench that vertically extends deep into the substrate and passes through the lateral isolation region and the active region, wherein the bottom of the trench is at a constant and equal depth at the position of the trench passing through the lateral isolation region and at the position passing through the active region.

[0033] According to one embodiment, the component disposed in the trench includes side surfaces that are in direct contact with the active region at the position of the trench passing through the active region.

[0034] According to one embodiment, the lateral isolation region defines the active region as a strip longitudinally extending in a first direction, while the trench longitudinally extends in a second direction perpendicular to the first direction, and the bottom of the trench is at a constant and equal depth along the second direction.

[0035] According to one embodiment, the integrated circuit includes: a vertical-gate buried access transistor, where the vertical gate is a component disposed in the trench; and a state transistor that includes a stack of a floating gate and a control gate, the stack at least partially covering the active region near the trench.

[0036] According to another aspect, there is also provided a semiconductor device that includes a lateral isolation region defining an active region in a semiconductor substrate, where a sacrificial lateral isolation region is further positioned through the active region; by the method defined above, the semiconductor device can be formed by etching a trench at the position of the sacrificial lateral isolation region.

[0037] This aspect of the semiconductor device particularly corresponds to the "intermediate device" of the integrated circuit obtained during the manufacturing method defined above, especially before the step of etching the trench, where the trench extends vertically deep into the substrate and is intended to pass through the lateral isolation region and the active region. BRIEF DESCRIPTION OF THE DRAWINGS

[0038] Other advantages and features of the present invention will become apparent by examining the detailed description of the embodiments and implementations, which are in no way restrictive, and will become apparent from the drawings, in which:

[0039] Figure 1A , Figure 1B and Figure 1C show examples of memory planes incorporating memory cells in non-volatile memory technology;

[0040] Figure 2A , Figure 2B and Figure 2C show the results of the steps of a method for manufacturing an integrated circuit, where a lateral isolation region and a sacrificial lateral isolation region are formed in a semiconductor substrate;

[0041] Figure 3A , Figure 3B and Figure 3C show the memory plane at the end of the step of etching a trench extending deep into the substrate;

[0042] Figure 4A , Figure 4B and Figure 4C show the memory plane at the end of forming a gate structure in the trench; and

[0043] Figure 5A , Figure 5B and Figure 5C show the memory plane at the end of completing the formation of the memory cell and specifically forming the state transistor. DETAILED DESCRIPTION

[0044] Figure 2A , Figure 2B and Figure 2C shows the result of steps for forming a shallow trench isolation (STI) region and a sacrificial shallow trench isolation (STI_SAC) region in a semiconductor substrate SUB in a method for manufacturing an integrated circuit, more specifically, the steps for forming a shallow trench isolation (STI) region and a sacrificial shallow trench isolation (STI_SAC) region in a memory plane of the integrated circuit that is intended to include memory cells.

[0045] Hereinafter, for convenience, the term "shallow trench isolation regions STI, STI_SAC" will refer to a component including a shallow trench isolation (STI) region and a sacrificial shallow trench isolation (STI_SAC) region.

[0046] defines Figure 2A - Figure 2B - Figure 2C and those described hereinafter Figure 3A - Figure 3B - Figure 3C , Figure 4A - Figure 4B - Figure 4C , Figure 5A - Figure 5B - Figure 5C the common orthogonal reference frame XYZ.

[0047] The first direction X and the second direction Y lie in the plane of the front face FA (see above), and the third direction Z is vertical, i.e., perpendicular to the plane of the front face FA.

[0048] Figure 2A shows a top view of the front face FA of the substrate SUB (see below).

[0049] Figure 2B shows Figure 2A a cross-sectional view in a plane BB. The plane BB pointed to by the first direction X and the vertical direction Z lies along the length of the active region ACT (see below).

[0050] Figure 2C shows Figure 2A a cross-sectional view in a plane CC. The plane CC is oriented by the second direction Y and the perpendicular direction Z and passes through the sacrificial shallow trench isolation region STI_SAC.

[0051] The front face FA of the substrate SUB is the face of the device for manufacturing semiconductor components, and is generally represented by "FEOL" for "front-end-of-line".

[0052] Before or after forming the lateral isolation regions STI, STI_SAC, a region NISO has been formed that is implanted into the semiconductor substrate SUB at a depth. The deep implantation region NISO having a dopant type opposite to that of the substrate SUB can provide the function of the source plane of the memory cell. Conventionally, no other steps are actually performed before forming the lateral isolation regions STI, STI_SAC.

[0053] The lateral isolation regions STI, STI_SAC are formed from the front side FA in the surface region of the semiconductor substrate SUB, i.e., the shallow region, for example, substantially 300 nm or between 200 nm and 400 nm.

[0054] The lateral isolation regions STI, STI_SAC are obtained by shallow isolation trench technology, i.e., they are obtained by etching shallow trenches (e.g., 300 nm to 400 nm) that are open in the surface region of the substrate SUB and filling the trenches with a dielectric material (usually silicon oxide).

[0055] The lateral isolation region STI defines the active region ACT of the substrate, and the active region ACT extends in the form of a strip whose length is pointed in the first direction X.

[0056] In the lateral isolation regions formed in this step, the sacrificial lateral isolation region STI_SAC is located at the future etching position of the trench TR ( Figure 3A - Figure 3B - Figure 3C ), in particular, at the position that vertically crosses the active region ACT in the second direction Y.

[0057] Thus, in an absolute sense, the active regions ACT are in the form of strips extending in the first direction X and are interrupted by the sacrificial lateral insulation regions STI_SAC that laterally cross them in the second direction Y.

[0058] Figure 3A , Figure 3B and Figure 3C Shows the memory plane at the end of the step of etching GRTR, and the trench extends deeply into the substrate SUB.

[0059] Figure 3A Shows a top view of the front side FA of the substrate SUB.

[0060] Figure 3B Shows Figure 3A a cross-sectional view in the plane BB (identical to the plane BB of Figure 2A ).

[0061] Figure 3C Shows Figure 3A a cross-sectional view in the plane CC (identical to the plane CC of Figure 2A ).

[0062] Etch GRTR replaces the sacrificial lateral isolation region STI_SAC positioning and can provide a wider width especially in the second direction Y to meet the error tolerance in the alignment of the corresponding etch mask. Note that the mask for trench etch GRTR can be directly aligned with the masks for lateral isolation trench etch STI, STI_ACT. Therefore, the error tolerance to be met is advantageously minimized (since the accumulation of error tolerances from the successive alignment between the two etch steps does not have to be considered).

[0063] The trenches TR etched in this way extend longitudinally in the second direction Y and laterally across a series of strips of lateral isolation regions STI and active regions ACT that extend longitudinally in the first direction X.

[0064] The technique for etching the GRTR trenches TR is typically a dry etch of the reactive ion type, typically reactive ion etching (RIE). This type of etch typically exhibits faster kinetics in the dielectric material (usually silicon oxide) of the lateral isolation region STI than in the semiconductor material (usually single-crystalline silicon) of the active region ACT.

[0065] Therefore, when the etch GRTR reaches the bottom of the shallow isolation trench STI, the portion facing the position of the shallow isolation region STI is etched deeper than the portion facing the position of the active region ACT.

[0066] However, since the sacrificial lateral isolation region STI_SAC is located at the position of this etch GRTR, only the portion facing the position of the shallow isolation region STI is etched (to the maximum depth), with uniform etch kinetics along the entire length (second direction Y) of the trench TR.

[0067] Therefore, the bottom of the trench TR has a shape with substantially no variation in depth along the second direction Y. In other words, the bottom of the trench TR is thus located at a constant depth p10, especially with respect to the position of the trench passing through the lateral isolation region STI and the position of the trench passing through the active region ACT. In other words, in Figure 3A the top view, the bottom of the trench is located at an equal depth with respect to the position of the trench TR passing through the lateral isolation region STI and with respect to the position of the trench TR passing through the active region ACT.

[0068] In fact, "constant depth" or "equal depth" means that the depth varies substantially not at all, i.e., the variation is less than or equal to the variation threshold of the etch method.

[0069] Furthermore, a source region Simp, also referred to as source implant Simp, is implanted in the substrate SUB from the bottom of the trench TR between the bottom of the trench TR and the source plane NISO. The source implant Simp is designed to ensure electrical continuity with the source plane NISO.

[0070] Figure 4A , Figure 4B and Figure 4C show a memory plane at an end of a gate structure TRG formed in a trench TR extending deeply into a substrate SUB.

[0071] Figure 4A Show a top view of a front face FA of a substrate SUB.

[0072] Figure 4B Show Figure 4A in a plane BB (identical to the plane BB of Figure 2A and Figure 3A ) a cross-sectional view.

[0073] Figure 4C Show Figure 4A in a plane CC (identical to the plane CC of Figure 2A , Figure 3A ) a cross-sectional view.

[0074] First, a dielectric gate layer is formed on the bottom and sidewalls of the trench TR, thus typically opening into the semiconductor substrate SUB by oxidation.

[0075] Second, a conductive gate region is formed in the volume of the trench, typically by depositing excess polysilicon on the front face FA and performing a chemical mechanical polishing step until the front face FA.

[0076] The gate structure TRG arranged in the trench TR includes a dielectric gate envelope on the sidewalls and bottom of the trench, and a conductive gate region in the volume defined by the envelope and the front face FA.

[0077] Thus, a source region Simp, NISO of a buried access transistor TA for a memory cell of the memory plane and a vertical gate structure TRG are formed in the trench TR.

[0078] Figure 5A , Figure 5B and Figure 5C Show a memory plane at the end of the step of completing the formation of memory cells CEL1, CEL2, in particular the formation of a state transistor TE.

[0079] Figure 5A Show a top view of a front face FA of a substrate SUB.

[0080] Figure 5B Show Figure 5A in a plane BB a cross-sectional view. The plane BB is identical to Figure 2A, the planes BB of 3A and 4A are the same, and it passes through the gate regions CG and FG of the state transistor TE in the length direction and passes through the vertical gate region TRG in the width direction.

[0081] Figure 5C shows a Figure 5A cross-sectional view in plane CC. Plane CC is the same as the Figure 2A plane CC in 3A and 4A, and it passes through the vertical gate region in the length direction.

[0082] The steps of completing the formation of the memory cells CEL1 and CEL2 include forming a state transistor TE, which includes a floating gate FG having a control gate CG.

[0083] The conductive regions of the state transistor TE are implanted in the active region ACT. The drain region D is connected to the corresponding bit lines BL1 and BL2, and the source region (not shown) of the state transistor TE is also the drain region of the access transistor TA, and a series connection is formed between the state transistor TE and the access transistor TA.

[0084] The bit lines BL1 and BL2 are formed, for example, in a metal layer extending above the memory plane along the first direction X.

[0085] The control gate CG can be fabricated to extend in the second direction Y, so that a control gate line can be formed for selectively accessing the memory cells belonging to the same group called a row.

[0086] The access transistor TA is also fabricated to extend in the second direction Y, and a word line can be formed for selectively accessing the memory cells belonging to the same group called a memory word.

[0087] The floating gate FG is formed to cover the active region ACT unique to each memory cell CEL1 and CEL2 on either side in the first direction X of the vertical gate TRG.

[0088] Specifically, the interface between each floating gate FG and the underlying active region ACT is designed to achieve charge injection through "tunneling effect" (usually through Fowler-Nordheim effect) through the tunneling oxide layer and / or by injecting hot carriers generated by impact ionization.

[0089] The reliability and cycling performance of the memory cells CEL1 and CEL2 are particularly determined by the width of the tunneling effect injection interface (i.e., the width of the active region ACT, i.e., the width of the active region ACT in the second direction Y). The larger the width of the active region ACT, the higher the reliability of the memory cell.

[0090] Thus, by means of the sacrificial lateral isolation region, it will be possible to prevent the phenomenon of the etch stop of the lateral isolation region (in the second direction Y) caused by the narrow width of the lateral isolation region, i.e., the "STI etch stop" towards the trench TRG, without widening the lateral isolation region STI (in the second direction Y) and thus without reducing the width of the active region ACT or the relative reliability y of the memory cells CEL1, CEL2.

[0091] Avoiding the problem of the etch stop of the lateral isolation region, i.e., the "STI etch stop", thus avoids the risk of read and write performance loss by avoiding a reduction in the depth of the vertical gate trench, which reduction in depth of the vertical gate trench can create a high resistance between the source-drain conductive regions of the access transistor TA in the on-state.

[0092] On the other hand, the design of the sacrificial lateral isolation region STI_SAC also enables the trench TR accommodating the vertical gate TRG to be formed with a depth p10 that is greater than the depth p11 of the trenches etched in the semiconductor substrate SUB in the same step ( Figure 1A , 1B, 1C). This additional effect also helps to prevent the risk of read and write performance loss of the memory cells.

[0093] Furthermore, from the perspective of the final device obtained by the method described previously in conjunction with Figure 2A -C to 5A-C, the bottom of the trench TR containing the vertical gate TRG has a very uniform and flat appearance and is located at a constant and equal depth p10 especially with respect to the positions of the trenches passing through the lateral isolation region STI and through the active region ACT.

[0094] These advantages are in particular the result of the structure of the "intermediate" semiconductor device obtained during the process of the method at the end of the step of forming the lateral isolation regions STI, STI_SAC, as Figure 2A , 2B, 2C shows; namely, a semiconductor device including a lateral isolation region STI defining an active region ACT in a semiconductor substrate SUB, wherein the sacrificial lateral isolation region STI_SAC is further positioned through the active region ACT, and this semiconductor device can, or even is intended to, be shaped by etching a trench GRTR at the position of the sacrificial lateral isolation region STI_SAC, as described previously in conjunction with Figure 3A -3B-3C, 4A-4B-4C and 5A-5B-5C.

Claims

1. A method for manufacturing an integrated circuit, comprising: forming a lateral isolation region in a semiconductor substrate that defines an active region; and etching a trench that extends vertically in depth into the semiconductor substrate to pass through the lateral isolation region and the active region; wherein forming the lateral isolation region includes forming a sacrificial lateral isolation region that is positioned at a location of the trench that etches through the active region.

2. The method according to claim 1, wherein forming the sacrificial lateral isolation region includes positioning the sacrificial lateral isolation region that will be completely removed during etching of the trench such that sidewalls of the etched trench include uncovered walls of the active region.

3. The method according to claim 1, wherein forming the lateral isolation region defines the active region as a strip longitudinally extending in a first direction, and wherein etching the trench forms the trench as longitudinally extending in a second direction perpendicular to the first direction, and wherein the sacrificial lateral isolation region is positioned along the length of the trench in the second direction.

4. The method according to claim 1, wherein the lateral isolation region includes a volume of dielectric material in the semiconductor substrate, wherein the active region includes semiconductor material of the semiconductor substrate, and wherein etching the trench includes etching faster in the dielectric material than in the semiconductor material of the semiconductor substrate.

5. The method according to claim 1, further comprising forming a gate of a buried access transistor having a vertical gate etched in depth into the trench in the semiconductor substrate, and forming a stack of a floating gate and a control gate of a state transistor that at least partially covers the active region in the vicinity of forming the trench.

6. A semiconductor device, comprising: a lateral isolation region that defines an active region in a semiconductor substrate; and a sacrificial lateral isolation region positioned through the active region; wherein a trench at the location of the sacrificial lateral isolation region shapes the semiconductor device, the trench extending vertically in depth into the semiconductor substrate to pass through the lateral isolation region and the active region.

7. The semiconductor device according to claim 6, wherein the lateral isolation region defines the active region as a strip longitudinally extending in a first direction, and wherein the trench longitudinally extends in a second direction perpendicular to the first direction, and wherein the sacrificial lateral isolation region is positioned along the length of the trench in the second direction.

8. The semiconductor device according to claim 6, wherein the lateral isolation region includes a volume of dielectric material in the semiconductor substrate, wherein the active region includes semiconductor material of the semiconductor substrate.

9. The semiconductor device according to claim 6 further includes a stack of a gate of a buried access transistor and a floating gate and a control gate of a state transistor, the gate of the buried access transistor having a vertical gate etched in depth into the trench in the semiconductor substrate, and the stack at least partially covering the active region near the trench.

10. An integrated circuit, comprising: a lateral isolation region defining an active region in a semiconductor substrate; and components disposed in a trench that extends vertically in depth into the semiconductor substrate and passes through the lateral isolation region and the active region; wherein a bottom of the trench is located at a constant and equal depth at a position facing the trench passing through the lateral isolation region and a position of the trench passing through the active region.

11. The integrated circuit according to claim 10, wherein the components disposed in the trench include sides that are in direct contact with the active region at a position in the trench passing through the active region.

12. The integrated circuit according to claim 10, wherein the lateral isolation region defines the active region as a strip longitudinally extending in a first direction, wherein the trench longitudinally extends in a second direction perpendicular to the first direction, and wherein the bottom of the trench is located at a constant and equal depth along the second direction.

13. The integrated circuit according to claim 10, further comprising: a buried access transistor having a vertical gate, the vertical gate being the component disposed in the trench; and a state transistor including a stack of a floating gate and a control gate covering at least a portion of the active region near the trench.

Images