Semiconductor device

Abstract

A semiconductor device includes: a reference layer having a fixed spin direction; the metal layer is arranged below the reference layer; a first free layer disposed under the metal layer; a first spin orbit coupling (SOC) layer disposed below the first free layer, and configured to control a spin direction recorded in the first free layer by using a current flowing through the first SOC layer; a second free layer disposed under the first SOC layer; and a second SOC layer disposed below the second free layer and configured to control a spin direction recorded in the second free layer by using a current flowing through the second SOC layer.

Description

[0001] Cross - reference to related applications

[0002] This application claims the priority and benefit of Korean Patent Application No. 10 - 2024 - 0009467, filed with the Korean Intellectual Property Office on January 22, 2024, the entire content of which is incorporated herein by reference. Technical field

[0003] The present disclosure relates to a semiconductor device. Background art

[0004] A magnetic random - access memory (MRAM) implemented by non - volatile memory technology for storing data by using magnetic properties can retain data even when power is off, and provides faster read and write performance and improved durability compared to a conventional dynamic random - access memory (DRAM). An MRAM cell may include a magnetic tunnel junction (MTJ), the MTJ including a reference layer (or fixed layer), a free layer, a tunneling layer formed between the reference layer and the free layer, and a spin - orbit coupling (SOC) layer having a spin direction recorded in the free layer. The spin direction can be recorded in the free layer by a current flowing through the SOC layer, and the resistance value between the free layer and the reference layer can be changed based on whether the spin direction recorded in the free layer is the same as the spin direction recorded in the reference layer. One type of MRAM may include a spin - transfer torque magnetic random - access memory (STT - MRAM), and another type of MRAM may include a spin - orbit torque magnetic random - access memory (SOT - MRAM). Compared with STT - MRAM, SOT - MRAM can provide greater stability and faster driving speed by separating the current paths for reading and writing from each other. Summary of the invention

[0005] The present disclosure attempts to provide a semiconductor device having a minimum occupied area and fewer transistors required for its operation.

[0006] According to an embodiment, a semiconductor device is provided, including: a reference layer having a fixed spin direction; a metal layer disposed below the reference layer; a first free layer disposed below the metal layer; a first spin-orbit coupling (SOC) layer disposed below the first free layer and configured to control a spin direction recorded in the first free layer by using a current flowing through the first SOC layer; a second free layer disposed below the first SOC layer; and a second SOC layer disposed below the second free layer and configured to control a spin direction recorded in the second free layer by using a current flowing through the second SOC layer.

[0007] A blocking layer may be disposed between the reference layer and the metal layer, between the metal layer and the first free layer, or between the first SOC layer and the second free layer.

[0008] The device may further include: a first transistor controlled by a first word line signal to selectively connect the metal layer and the source line to each other; a second transistor controlled by a second word line signal to selectively connect the first SOC layer and the source line to each other; and a third transistor controlled by a third word line signal to selectively connect the second SOC layer and the source line to each other.

[0009] The first SOC layer may be connected to a write bit line, the first SOC layer may be connected to the source line through the second transistor, and the spin direction of the first free layer may be determined based on a current flowing through the first SOC layer between the write bit line and the source line.

[0010] The second SOC layer may be connected to the write bit line, the second SOC layer may be connected to the source line through the third transistor, and the spin direction of the second free layer may be determined based on a current flowing through the second SOC layer between the write bit line and the source line.

[0011] The device may further include a read transistor configured to selectively connect the reference layer and the read bit line to each other, wherein the reference layer is connected to the read bit line through the read transistor, the first SOC layer is connected to the source line through the second transistor, and the spin direction of the first free layer is determined by measuring a resistance value of a first stacked structure including the reference layer, the metal layer, the first free layer, and the first SOC layer.

[0012] When the measured resistance value of the first stacked structure is equal to or greater than a first critical value, the spin directions of the reference layer and the first free layer may be determined to be opposite to each other, and when the measured resistance value of the first stacked structure is less than the first critical value, the spin directions of the reference layer and the first free layer may be determined to be the same as each other.

[0013] The metal layer can be connected to the source line through the first transistor, the second SOC layer can be connected to the source line through the third transistor, and the spin direction of the second free layer can be determined by measuring the resistance value of a second stacked structure including a reference layer, a metal layer, a first free layer, a first SOC layer, a second free layer, and a second SOC layer.

[0014] When the measured resistance value of the second stacked structure is equal to or greater than a second critical value, the spin directions of the first free layer and the second free layer can be determined to be opposite to each other, and when the measured resistance value of the second stacked structure is less than the second critical value, the spin directions of the first free layer and the second free layer can be determined to be the same as each other.

[0015] According to an embodiment, a semiconductor device is provided, including: a reference layer having a fixed spin direction; a first free layer disposed below the reference layer; a first spin orbit coupling (SOC) layer disposed below the first free layer and configured to control the spin direction recorded in the first free layer by using a current flowing through the first SOC layer; a second free layer disposed below the first SOC layer; and a second SOC layer disposed below the second free layer and configured to control the spin direction recorded in the second free layer by using a current flowing through the second SOC layer.

[0016] A blocking layer can be disposed between the reference layer and the first free layer, or between the first SOC layer and the second free layer.

[0017] The device may further include: a first transistor controlled by a first word line signal to selectively connect the first SOC layer and the source line to each other; and a second transistor controlled by a second word line signal to selectively connect the second SOC layer and the source line to each other.

[0018] The first SOC layer can be connected to a write bit line, the first SOC layer can be connected to the source line through the first transistor, and the spin direction of the first free layer can be determined based on the current flowing through the first SOC layer between the write bit line and the source line.

[0019] The second SOC layer can be connected to a write bit line, the second SOC layer can be connected to the source line through the second transistor, and the spin direction of the second free layer can be determined based on the current flowing through the second SOC layer between the write bit line and the source line.

[0020] The device may further include a read transistor configured to selectively connect the reference layer and the read bit line to each other, wherein the reference layer is connected to the read bit line through the read transistor, the first SOC layer is connected to the source line through the first transistor, and the spin direction of the first free layer is determined by measuring a first resistance value of a first stack structure including the reference layer, the first free layer, and the first SOC layer.

[0021] The reference layer may be connected to the read bit line through the read transistor, the second SOC layer may be connected to the source line through the second transistor, and the spin direction of the second free layer may be determined by measuring a second resistance value of a second stack structure including the reference layer, the first free layer, the first SOC layer, the second free layer, and the second SOC layer.

[0022] When the difference between the first resistance value and the second resistance value is measured to be equal to or greater than a third critical value, the spin directions of the first free layer and the second free layer may be determined to be opposite to each other, and when the difference between the first resistance value and the second resistance value is measured to be less than the third critical value, the spin directions of the first free layer and the second free layer may be determined to be the same as each other.

[0023] According to an embodiment, a semiconductor device is provided, including: a reference layer having a fixed spin direction; a first free layer disposed below the reference layer and having a physical property in which a resistance value of the first free layer is determined to correspond to a first digit of a ternary number based on the spin direction of the first free layer; a first spin orbit coupling (SOC) layer disposed below the first free layer and configured to control the spin direction of the first free layer by using a current flowing through the first SOC layer; a second free layer disposed below the first SOC layer and having a physical property in which a resistance value of the second free layer is determined to correspond to a second digit of the ternary number based on the spin direction of the second free layer; and a second SOC layer disposed below the second free layer and configured to control the spin direction of the second free layer by using a current flowing through the second SOC layer.

[0024] A blocking layer may be disposed between the reference layer and the first free layer, or between the first SOC layer and the second free layer.

[0025] The spin directions of the first free layer and the second free layer may be determined by converting a resistance value measured between the reference layer and the second SOC layer into a ternary number. BRIEF DESCRIPTION OF THE DRAWINGS

[0026] Figure 1 is a diagram illustrating a semiconductor device according to an embodiment.

[0027] Figure 2 And Figure 3 is a diagram showing a write operation of a semiconductor device according to an embodiment.

[0028] Figures 4 to 7 is a diagram showing a read operation of a semiconductor device according to an embodiment.

[0029] Figure 8 is a diagram showing a semiconductor device according to another embodiment.

[0030] Figures 9 to 11 is a diagram showing a read operation of a semiconductor device according to an embodiment.

[0031] Figure 12 is a diagram showing a semiconductor device according to still another embodiment.

[0032] Figure 13 And Figure 14 is a diagram showing a read operation of a semiconductor device according to an embodiment.

[0033] Figure 15 is a block diagram showing a system including a semiconductor device according to an embodiment. DETAILED DESCRIPTION

[0034] Hereinafter, embodiments of the present disclosure will be described in detail with reference to the accompanying drawings so that those skilled in the art to which the present disclosure pertains can easily practice the present disclosure. However, the present disclosure can be implemented in various different forms and is not limited to the embodiments described herein. In addition, in the drawings, parts irrelevant to the description are omitted to clearly describe the present disclosure, and similar parts are denoted by similar reference numerals throughout the specification.

[0035] Throughout the specification and claims, unless otherwise expressly described, "including" any component will be understood to imply including another component rather than excluding another component. Terms including ordinal numbers such as "first", "second", etc. may be used to describe various components. However, these components are not limited by these terms. The term is only used to distinguish one component from another.

[0036] The terms used herein are for the purpose of describing particular embodiments only and are not restrictive. As used herein, unless the context clearly dictates otherwise, "a", "an", "the", and "at least one" do not denote a limitation of quantity and are intended to include both the singular and the plural. For example, "element" has the same meaning as "at least one element" unless the context clearly dictates otherwise. "At least one" should not be construed as limiting "a" or "an". "Or" means "and / or". As used herein, the term "and / or" includes any and all combinations of one or more of the associated listed items.

[0037] Figure 1 It is a diagram showing a semiconductor device according to an embodiment.

[0038] Reference Figure 1 , the semiconductor device 10 according to an embodiment may include a reference layer 11, a plurality of barrier layers 121 to 125, a plurality of free layers 132 to 135, a plurality of spin-orbit coupling (SOC) layers 142 to 145, and a metal layer 15. As shown, the semiconductor device 10 may have a vertically stacked structure in which the barrier layers, free layers, and SOC layers are repeatedly stacked.

[0039] The reference layer 11 may have a fixed spin direction. The reference layer 11 may include at least one of iron (Fe), cobalt (Co), and nickel (Ni), or may include at least one of boron (B), silicon (Si), zirconium (Zr), platinum (Pt), palladium (Pd), copper (Cu), and tungsten (W).

[0040] The barrier layers 121 to 125 may each be made of an insulating material that is thin enough to allow electrons to move by tunneling, for example, a few nanometers (nm) thick. The barrier layers 121 to 125 may each be made of a material such as magnesium oxide (MgO) or aluminum oxide (Al2O3). Generally, MgO can be widely used because MgO has a relatively high tunnelmagnetoresistance (TMR) ratio and is thus good in terms of performance and stability. However, Al2O3 can still be used in some applications.

[0041] The free layers 132 to 135 may respectively have spin directions that can be switched by the current flowing through the SOC layers 142 to 145. The free layers 132 to 135 may each include at least one of iron (Fe), cobalt (Co), and nickel (Ni), or may include at least one of boron (B), silicon (Si), zirconium (Zr), platinum (Pt), palladium (Pd), copper (Cu), and tungsten (W).

[0042] The SOC layers 142 to 145 may be layers for recording specific spin directions in the free layers 132 to 135 respectively by using current. The SOC layers 142 to 145 may each include ruthenium (Ru), aluminum (Al), tantalum (Ta), platinum (Pt), tungsten (W), palladium (Pd), zirconium (Zr), copper (Cu), or an alloy thereof.

[0043] In a vertical stacking structure, the metal layer 15 may be disposed below the reference layer 11. Here, the metal layer 15 may include a metal material including copper (Cu). The free layer 132 may be disposed below the metal layer 15, and the SOC layer 142 may be disposed below the free layer 132. The SOC layer 142 may have a specific spin direction recorded in the free layer 132 by using an electric current. In addition, the free layer 133 may be disposed below the SOC layer 142, and the SOC layer 143 may be disposed below the free layer 133. The SOC layer 143 may have a specific spin direction recorded in the free layer 133 by using an electric current. In a similar pattern, the following layers may be disposed below the SOC layer 143: the free layer 134, the SOC layer 144 for recording a specific spin direction in the free layer 134, the free layer 135, and the SOC layer 145 for recording a specific spin direction in the free layer 135.

[0044] Meanwhile, the blocking layer 121 may be disposed between the reference layer 11 and the metal layer 15. In addition, the blocking layer 122 may be disposed between the metal layer 15 and the free layer 132. In addition, the blocking layers 123, 124, and 125 may be respectively disposed between the SOC layer 142 and the free layer 133, between the SOC layer 143 and the free layer 134, and between the SOC layer 144 and the free layer 135.

[0045] The semiconductor device 10 may also include a plurality of transistors T1 to T5. The transistor T1 may be controlled by the word line signal WL1 to selectively connect the metal layer 15 and the source line to each other, the transistor T2 may be controlled by the word line signal WL2 to selectively connect the SOC layer 142 and the source line to each other, and the transistor T3 may be controlled by the word line signal WL3 to selectively connect the SOC layer 143 and the source line to each other. In a similar pattern, the transistor T4 or T5 may be controlled by the word line signal WL4 or WL5 to selectively connect the SOC layer 144 or 145 and the source line to each other. Each of the metal layer 15 and the SOC layers 142, 143, 144, or 145 may have one side connected to the transistor T1, T2, T3, T4, or T5, and the other side connected to the write bit line WBL.

[0046] Meanwhile, the semiconductor device 10 may further include a read transistor TA. The read transistor TA may selectively connect the reference layer 11 and the read bit line RBL to each other by a certain control signal.

[0047] The scope of the present disclosure is not limited to Figure 1The range shown in [description], and the number of layers included in the vertical stacking structure can be variably changed based on the specific implementation purpose and implementation environment of the stacking structure. For example, if necessary, the number of repetitions of the stacking structure including the free layer, the SOC layer, and the barrier layer provided below the reference layer 11, the barrier layer 121, and the metal layer 15 can be changed, and there is no limit to the number of layers to be stacked as long as the process permits.

[0048] Hereinafter, the description describes a write operation for performing spin recording in the free layer provided on the desired SOC layer by controlling the transistors T2, T3, T4, or T5 to cause current to flow to the desired SOC layer among the SOC layers 142 to 145.

[0049] Figure 2 and Figure 3 is a diagram showing a write operation of a semiconductor device according to an embodiment.

[0050] Referring to Figure 2 , the SOC layer 142 can have one side connected to the source line through the transistor T2 and the other side connected to the write bit line WBL. The transistor T2 can be turned on by the word line signal WL2, and the spin direction of the free layer 132 can be determined based on the current flowing through the SOC layer 142 between the write bit line WBL and the source line.

[0051] Next, referring to Figure 3 , the SOC layer 143 can have one side connected to the source line through the transistor T3 and the other side connected to the write bit line WBL. As Figure 2 shown, the transistor T3 can be turned on by the word line signal WL3 after determining the spin direction of the free layer 132, and the spin direction of the free layer 133 can be determined based on the current flowing through the SOC layer 143 between the write bit line WBL and the source line.

[0052] In a similar manner, the transistor T4 can be turned on by the word line signal WL4 after determining the spin direction of the free layer 133, and the spin direction of the free layer 134 can be determined based on the current flowing through the SOC layer 144. Next, the transistor T5 can be turned on by the word line signal WL5, and the spin direction of the free layer 135 can be determined based on the current flowing through the SOC layer 145.

[0053] Hereinafter, the description describes a read operation for identifying the data recorded in the free layers 132, 133, 134, or 135 by controlling the transistors T1, T2, T3, T4, or T5 and the transistor TA. That is, the spin directions of the free layers 132, 133, 134, and 135 can all be [reference] Figure 2 and 3determined in the described manner, and the spin directions of the free layers 132, 133, 134, and 135 can then be determined in the manner described below.

[0054] Figures 4 to 7 is a diagram showing a read operation of a semiconductor device according to an embodiment.

[0055] Refer to Figure 4 , the reference layer 11 can be connected to the read bit line RBL through the read transistor TA, and the SOC layer 142 can be connected to the source line through the transistor T2. When the read transistor TA and the transistor T2 are turned on, the resistance value of the stacked structure including the reference layer 11, the metal layer 15, the free layer 132, and the SOC layer 142, and the barrier layers 121 and 122 provided between these layers can be measured. The spin direction of the free layer 132 can be determined by measuring this resistance value.

[0056] Specifically, when the resistance value is measured to be a predetermined first critical value or greater, the spin directions of the reference layer 11 and the free layer 132 can be determined to be opposite to each other, and when the resistance value is measured to be less than the first critical value, the spin directions of the reference layer 11 and the free layer 132 can be determined to be the same as each other. Figure 4 represents the case where the resistance value is a predetermined first critical value or greater. Here, it can be seen that the spin directions of the reference layer 11 and the free layer 132 are opposite to each other.

[0057] Next, referring to Figure 5 , the metal layer 15 can be connected to the source line through the transistor T1, and the SOC layer 143 can be connected to the source line through the transistor T3. When the transistor T1 and the transistor T3 are turned on, the resistance value of the stacked structure including the metal layer 15, the free layer 132, the SOC layer 142, the free layer 133, the SOC layer 143, and the barrier layers 122 and 123 provided between these layers can be measured. The spin direction of the free layer 133 can be determined by measuring this resistance value.

[0058] Specifically, when the resistance value is measured to be a predetermined second critical value or greater, the spin directions of the free layer 132 and the free layer 133 can be determined to be opposite to each other, and when the resistance value is less than the second critical value, the spin directions of the free layer 132 and the free layer 133 can be determined to be the same as each other. Figure 5 shows the case where the resistance value is less than the predetermined second critical value. Here, it can be seen that the spin directions of the free layer 132 and the free layer 133 are the same as each other.

[0059] Next, refer to Figure 6, the SOC layer 142 can be connected to the source line through the transistor T2, and the SOC layer 144 can be connected to the source line through the transistor T4. When the transistors T2 and T4 are turned on, the resistance value of the stacked structure including the SOC layer 142, the free layer 133, the SOC layer 143, the free layer 134, the SOC layer 144, and the barrier layers 123 and 124 provided between these layers can be measured. The spin direction of the free layer 134 can be determined by measuring this resistance value.

[0060] Specifically, when the resistance value is measured to be equal to or greater than a predetermined third critical value, the spin directions of the free layer 133 and the free layer 134 can be determined to be opposite to each other, and when the resistance value is measured to be less than the third critical value, the spin directions of the free layer 133 and the free layer 134 can be determined to be the same as each other. Figure 6 The case where the resistance value is equal to or greater than a predetermined third critical value is shown. Here, it can be seen that the spin directions of the free layer 133 and the free layer 134 are opposite to each other.

[0061] Next, referring to Figure 7 , the SOC layer 143 can be connected to the source line through the transistor T3, and the SOC layer 145 can be connected to the source line through the transistor T5. When the transistors T3 and T5 are turned on, the resistance value of the stacked structure including the SOC layer 143, the free layer 134, the SOC layer 144, the free layer 135, the SOC layer 145, and the barrier layers 124 and 125 provided between these layers can be measured. The spin direction of the free layer 135 can be determined by measuring the resistance value.

[0062] Specifically, when the resistance value is measured to be equal to or greater than a predetermined fourth critical value, the spin directions of the free layer 134 and the free layer 135 can be determined to be opposite to each other, and when the resistance value is measured to be less than the fourth critical value, the spin directions of the free layer 134 and the free layer 135 can be determined to be the same as each other. Figure 7 The case where the resistance value is equal to or greater than a predetermined fourth critical value is shown. Here, it can be seen that the spin directions of the free layer 134 and the free layer 135 are opposite to each other. In this way, the spin directions of all the free layers included in the vertical stacked structure can be identified.

[0063] The above-mentioned first critical value, second critical value, third critical value, and fourth critical value can all be set to the same value, or at least one of these values can be set to a different value.

[0064] Referring to Figures 1 to 7The described semiconductor device 10 with a vertical stacked structure can achieve a higher bit density while miniaturizing the magnetic tunnel junction (MTJ) and reducing its footprint. In addition, the semiconductor device can have fewer transistors required for its operation, thus enabling more effective scaling compared to magnetic random access memory (MRAM) devices in a conventional array form.

[0065] Specifically, for comparison, assume that the vertical stacked structure of the semiconductor device 10 uses the same N free layers, i.e., the same data capacity (e.g., N bits). Here, the vertical stacked structure including N free layers can have a footprint reduced to approximately 1 / N of the footprint of an MRAM device in a conventional array form. In addition, a conventional spin-orbit torque magnetic random access memory (SOT-MRAM) may require two transistors for each MTJ for its operation. However, the vertical stacked structure according to an embodiment may require fewer transistors for read operations. That is, the vertical stacked structure including N free layers may only require N + 2 transistors, and thus has a significant improvement compared to a conventional SOT-MRAM that requires 2N transistors. Further, a conventional SOT-MRAM sharing some SOT layers may require additional devices to prevent the same data from being recorded in a series of bidirectional bits on the write path. On the other hand, the vertical stacked structure according to an embodiment may not require additional devices for data writing.

[0066] Figure 8 is a diagram showing a semiconductor device according to another embodiment.

[0067] Reference Figure 8 , the semiconductor device 20 according to an embodiment can include a reference layer 21, a plurality of barrier layers 221 to 224, a plurality of free layers 231 to 234, and a plurality of spin-orbit coupling (SOC) layers 241 to 244. As shown in the drawings, the semiconductor device 20 can have a vertical stacked structure in which the barrier layers, free layers, and SOC layers are stacked repeatedly.

[0068] In a vertical stacking structure, the free layer 231 can be disposed below the reference layer 21, and the SOC layer 241 can be disposed below the free layer 231. The SOC layer 241 can be used to record a specific spin direction in the free layer 231 by using a current. In addition, the free layer 232 can be disposed below the SOC layer 241, and the SOC layer 242 can be disposed below the free layer 232. The SOC layer 242 can be used to record a specific spin direction in the free layer 232 by using a current. In a similar pattern, the following layers can be disposed below the SOC layer 242: the free layer 233, the SOC layer 243 for recording a specific spin direction in the free layer 233, the free layer 234, and the SOC layer 244 for recording a specific spin direction in the free layer 234.

[0069] Meanwhile, the blocking layer 221 can be disposed between the reference layer 21 and the free layer 231. In addition, the blocking layer 222 can be disposed between the SOC layer 241 and the free layer 232. In addition, the blocking layers 223 and 224 can be disposed between the SOC layer 242 and the free layer 233, and between the SOC layer 243 and the free layer 234, respectively.

[0070] The semiconductor device 20 can further include a plurality of transistors T1 to T4. The transistor T1 can be controlled by the word line signal WL1 to selectively connect the SOC layer 241 and the source line to each other, and the transistor T2 can be controlled by the word line signal WL2 to selectively connect the SOC layer 242 and the source line to each other. In a similar pattern, the transistor T3 or T4 can be controlled by the word line signal WL3 or WL4 to selectively connect the SOC layer 243 or 244 and the source line to each other. The SOC layers 241, 242, 243, or 244 can have one side connected to the transistor T1, T2, T3, or T4 and the other side connected to the write bit line WBL.

[0071] Meanwhile, the semiconductor device 20 can further include a read transistor TA. The read transistor TA can selectively connect the reference layer 21 and the read bit line RBL to each other through a certain control signal.

[0072] The scope of the present disclosure is not limited to Figure 8 the scope shown in, and the number of layers included in the vertical stacking structure can be differently changed based on the specific implementation purpose and implementation environment of the stacking structure. For example, if necessary, the number of repetitions of the stacking structure including the free layer, the SOC layer, and the blocking layer disposed below the reference layer 21 and the blocking layer 221 can be changed, and there is no limit to the number of layers to be stacked as long as the process permits.

[0073] The write operation can be similar to that described above with reference to Figure 2 and Figure 3performed in the described manner. Specifically, the transistor T1 can be turned on by the word line signal WL1, and the spin direction of the free layer 231 can be determined based on the current flowing through the SOC layer 241 between the write bit line WBL and the source line. The transistor T2 can be turned on by the word line signal WL2 after the spin direction of the free layer 231 is determined, and the spin direction of the free layer 232 can be determined based on the current flowing through the SOC layer 242 between the write bit line WBL and the source line.

[0074] In a similar manner, the transistor T3 can be turned on by the word line signal WL3 after the spin direction of the free layer 232 is determined, and the spin direction of the free layer 233 can be determined based on the current flowing through the SOC layer 243. Next, the transistor T4 can be turned on by the word line signal WL4, and the spin direction of the free layer 234 can be determined based on the current flowing through the SOC layer 244.

[0075] Hereinafter, the description describes a read operation of identifying data recorded in the free layers 231, 232, 233, or 234 by the control of the transistors T1, T2, T3, or T4 and the transistor TA. That is, the spin directions of the free layers 231, 232, 233, and 234 can be all determined, and then the spin directions of the free layers 231, 232, 233, and 234 can be determined in the manner described below.

[0076] Figures 9 to 11 is a diagram showing a read operation of a semiconductor device according to an embodiment.

[0077] Refer to Figure 9 , the reference layer 21 can be connected to the read bit line RBL through the read transistor TA, and the SOC layer 241 can be connected to the source line through the transistor T1. The spin direction of the free layer 231 can be determined by measuring the resistance value of the stacked structure including the reference layer 21, the free layer 231, and the SOC layer 241 and the barrier layer 221 provided between these layers. As shown in the figure, the measured resistance value can be identified as "1".

[0078] When the resistance value identified as "1" is measured to be equal to or greater than a predetermined fifth critical value, the spin directions of the reference layer 21 and the free layer 231 can be determined to be opposite to each other, and when the resistance value identified as "1" is measured to be less than the fifth critical value, the spin directions of the reference layer 21 and the free layer 231 can be determined to be the same as each other. Figure 9 shows a case where the resistance value identified as '1' is less than the fifth critical value. Here, it can be seen that the spin directions of the reference layer 21 and the free layer 231 are the same as each other.

[0079] Next, the reference layer 21 can be connected to the read bit line RBL through the read transistor TA, and the SOC layer 242 can be connected to the source line through the transistor T2. The spin direction of the free layer 232 can be determined by measuring the resistance value of a stacked structure including the reference layer 21, the free layers 231 and 232, and the SOC layers 241 and 242, and the barrier layers 221 and 222 respectively disposed between these layers. As shown in the figure, the measured resistance value can be identified as "2".

[0080] When the difference between the resistance value identified as "1" and the resistance value identified as "2" is measured to be a predetermined sixth critical value or greater, the spin directions of the free layer 231 and the free layer 232 can be determined to be opposite to each other, and when the difference between the resistance value identified as "1" and the resistance value identified as "2" is measured to be less than the sixth critical value, the spin directions of the free layer 231 and the free layer 232 can be determined to be the same as each other. Figure 9 The case where the difference is less than the sixth critical value is shown. Here, it can be seen that the spin directions of the free layer 231 and the free layer 232 are the same as each other.

[0081] Next, the reference layer 21 can be connected to the read bit line RBL through the read transistor TA, and the SOC layer 243 can be connected to the source line through the transistor T3. The spin direction of the free layer 233 can be determined by measuring the resistance value of a stacked structure including the reference layer 21, the free layers 231, 232 and 233, the SOC layers 241, 242 and 243, and the barrier layers 221, 222 and 223 respectively disposed between these layers. As shown in the figure, the measured resistance value can be identified as "3".

[0082] When the difference between the resistance value identified as "2" and the resistance value identified as "3" is measured to be a predetermined seventh critical value or greater, the spin directions of the free layer 232 and the free layer 233 can be determined to be opposite to each other, and when the difference between the resistance value identified as "2" and the resistance value identified as "3" is measured to be less than the seventh critical value, the spin directions of the free layer 232 and the free layer 233 can be determined to be the same as each other. Figure 9 The case where the difference is less than the seventh critical value is shown. Here, it can be seen that the spin directions of the free layer 232 and the free layer 233 are the same as each other.

[0083] Next, the reference layer 21 can be connected to the read bit line RBL through the read transistor TA, and the SOC layer 244 can be connected to the source line through the transistor T4. The spin direction of the free layer 234 can be determined by measuring the resistance value of the stacked structure including the reference layer 21, the free layers 231, 232, 233, and 234, the SOC layers 241, 242, 243, and 244, and the barrier layers 221, 222, 223, and 224 respectively provided between these layers. As shown in the figure, the measured resistance value can be identified as "4".

[0084] When the difference between the resistance value identified as "3" and the resistance value identified as "4" is measured to be a predetermined eighth critical value or greater, the spin directions of the free layer 233 and the free layer 234 can be determined to be opposite to each other, and when the difference between the resistance value identified as "3" and the resistance value identified as "4" is measured to be less than the eighth critical value, the spin directions of the free layer 233 and the free layer 234 can be determined to be the same as each other. Figure 9 The case where the difference is less than the eighth critical value is shown. Here, it can be seen that the spin directions of the free layer 233 and the free layer 234 are the same as each other. In this way, the spin directions of all the free layers included in the vertical stacked structure can be identified.

[0085] The above-mentioned fifth critical value, sixth critical value, seventh critical value, and eighth critical value can all be set to the same value, or at least one of these values can be set to a different value.

[0086] Reference Figure 10 can perform the read operation in the manner described above with respect to Figure 9 In this case, it can be seen that the spin directions of the reference layer 21 and the free layer 231 are the same as each other because the resistance value identified as '1' is less than the fifth critical value, and it can be seen that the spin directions of the free layer 231 and the free layer 232 are opposite to each other because the difference between the resistance value identified as '1' and the resistance value identified as '2' is the sixth critical value or greater. Next, it can be seen that the spin directions of the free layer 232 and the free layer 233 are opposite to each other because the difference between the resistance value identified as "2" and the resistance value identified as "3" is the seventh critical value or greater, and it can be seen that the spin directions of the free layer 233 and the free layer 234 are the same as each other because the difference between the resistance value identified as "3" and the resistance value identified as "4" is less than the eighth critical value.

[0087] Reference Figure 11 can perform the read operation in the manner described above with respect to Figure 9The read operation is performed in the described manner. In this case, it can be seen that since the resistance value labeled "1" is the fifth critical value or greater, the spin directions of the reference layer 21 and the free layer 231 are opposite to each other. It can be seen that since the difference between the resistance value labeled "1" and the resistance value labeled "2" is less than the sixth critical value, the spin directions of the free layer 231 and the free layer 232 are the same as each other. It can be seen that since the difference between the resistance value labeled "2" and the resistance value labeled "3" is less than the seventh critical value, the spin directions of the free layer 232 and the free layer 233 are the same as each other. And it can be seen that since the difference between the resistance value labeled "3" and the resistance value labeled "4" is the eighth critical value or greater, the spin directions of the free layer 233 and the free layer 234 are opposite to each other.

[0088] According to the reference Figures 8 to 11 For the semiconductor device 20 with the vertically stacked structure described, for comparison, it is assumed that the semiconductor device 20 uses the same N free layers, that is, the same data capacity (e.g., N bits). Here, the vertically stacked structure including N free layers can have an occupied area reduced to about 1 / N of the occupied area of a magnetic random access memory (MRAM) device having a conventional array form. In addition, a conventional spin-orbit torque magnetic random access memory (SOT-MRAM) may require two transistors for each magnetic tunnel junction (MTJ) for its operation. However, the vertically stacked structure according to the embodiment may require fewer transistors for the read operation. That is, the vertically stacked structure including N free layers may only require N + 1 transistors, and thus has a significant improvement compared to the conventional SOT-MRAM that requires 2N transistors.

[0089] Figure 12 is a diagram showing a semiconductor device according to another embodiment.

[0090] Reference Figure 12 , the semiconductor device 30 according to the embodiment may include a reference layer 31, a plurality of barrier layers 321 to 324, a plurality of free layers 331 to 334, and a plurality of spin-orbit coupling (SOC) layers 341 to 344. As shown, the semiconductor device 30 may have a vertically stacked structure in which the barrier layer, the free layer, and the SOC layer are repeatedly stacked.

[0091] In the vertically stacked structure, the free layer 331 may be disposed below the reference layer 31, and the free layer 331 has a physical property that the resistance value of the free layer 331 is determined to correspond to the value of the first digit of a ternary number based on its spin direction. For example, the free layer 331 may be fabricated to have a resistance value based on the spin direction of 1 or 2 (i.e., 1 (3) or 2 (3)) The resistance value determined therebetween. Here, the resistance value may have a unit of, for example, Ω. The SOC layer 341 may be disposed below the free layer 331, and the SOC layer 341 may have a specific spin direction recorded in the free layer 331 by using a current. Additionally, the free layer 332 may be disposed below the SOC layer 341, and the free layer 332 has a physical property in which the resistance value of the free layer 332 is determined to correspond to a value corresponding to the second digit of a ternary number based on its spin direction. For example, the free layer 332 may be fabricated to have a resistance value determined between 3 or 6 (i.e., 10 (3) or 20 (3) ) based on the spin direction. The SOC layer 342 may be disposed below the free layer 332, and the SOC layer 342 may have a specific spin direction recorded in the free layer 332 by using a current.

[0092] Next, the free layer 333 may be disposed below the SOC layer 342, and the free layer 333 has a physical property in which the resistance value of the free layer 333 is determined to correspond to a value corresponding to the third digit of a ternary number based on its spin direction. For example, the free layer 333 may be fabricated to have a resistance value determined between 9 or 18 (i.e., 100 (3) or 200 (3) ) based on the spin direction. The SOC layer 343 may be disposed below the free layer 333, and the SOC layer 343 may have a specific spin direction recorded in the free layer 333 by using a current. Additionally, the free layer 334 may be disposed below the SOC layer 343, and the free layer 334 has a physical property in which the resistance value of the free layer 334 is determined to correspond to a value corresponding to the fourth digit of a ternary number based on its spin direction. For example, the free layer 334 may be fabricated to have a resistance value determined between 27 or 54 (i.e., 1000 (3) or 2000 (3) ) based on the spin direction. The SOC layer 344 may be disposed below the free layer 334, and the SOC layer 344 may have a specific spin direction recorded in the free layer 332 by using a current.

[0093] Meanwhile, the barrier layer 321 may be disposed between the reference layer 31 and the free layer 331. Additionally, the barrier layer 322 may be disposed between the SOC layer 341 and the free layer 332. Furthermore, the barrier layers 323 and 324 may be respectively disposed between the SOC layer 342 and the free layer 333, and between the SOC layer 343 and the free layer 334.

[0094] The semiconductor device 30 may further include a plurality of transistors T1 to T4. The transistor T1 may be controlled by a word line signal WL1 to selectively connect the SOC layer 341 and the source line to each other, and the transistor T2 may be controlled by a word line signal WL2 to selectively connect the SOC layer 342 and the source line to each other. In a similar manner, the transistor T3 or T4 may be controlled by a word line signal WL3 or WL4 to selectively connect the SOC layer 343 or 344 and the source line to each other. The SOC layers 341, 342, 343, or 344 may have one side connected to the transistors T1, T2, T3, or T4 and the other side connected to the write bit line WBL.

[0095] Meanwhile, the semiconductor device 30 may further include a sense transistor TA. The sense transistor TA may selectively connect the reference layer 31 and the sense bit line RBL to each other through a certain control signal.

[0096] The scope of the present disclosure is not limited to Figure 12 the scope shown in, and the number of layers included in the vertical stack structure may be differently changed based on the specific implementation purpose and implementation environment of the vertical stack structure. For example, the number of repetitions of the stack structure including the free layer, the SOC layer, and the barrier layer provided below the reference layer 31 and the barrier layer 321 may be changed as needed, and there is no limit to the number of layers to be stacked as long as the process allows.

[0097] The write operation may be performed in a manner similar to that described above with reference to Figure 2 and Figure 3 . Specifically, the transistor T1 may be turned on by the word line signal WL1, and the spin direction of the free layer 331 may be determined based on the current flowing through the SOC layer 341 between the write bit line WBL and the source line. The transistor T2 may be turned on by the word line signal WL2 after the spin direction of the free layer 331 is determined, and the spin direction of the free layer 332 may be determined based on the current flowing through the SOC layer 342 between the write bit line WBL and the source line.

[0098] In a similar manner, the transistor T3 may be turned on by the word line signal WL3 after the spin direction of the free layer 332 is determined, and the spin direction of the free layer 333 may be determined based on the current flowing through the SOC layer 343. Next, the transistor T4 may be turned on by the word line signal WL4, and the spin direction of the free layer 334 may be determined based on the current flowing through the SOC layer 344.

[0099] In the following, a read operation for identifying data recorded in free layers 331, 332, 333, or 334 by controlling transistors T1, T2, T3, or T4 and transistor TA is described. That is, the spin directions of all of the free layers 331, 332, 333, and 334 can be determined, and then the spin directions of the free layers 331, 332, 333, and 334 can be determined in the manner described below.

[0100] Figure 13 and Figure 14 is a diagram showing a read operation of a semiconductor device according to an embodiment.

[0101] Referring Figure 13 , the spin direction of the free layer 331, 332, 333, or 334 can be determined by measuring the resistance value between the reference layer 31 and the SOC layer 344 and converting the measured resistance value into a ternary number.

[0102] In an embodiment, the resistance value measured between the reference layer 31 and the SOC layer 344 may be 40. In this case, 40 can be represented as 1111 in the ternary number system (3) . 1111 (3) can be 1×3 3 +1×3 2 +1×3 1 +1×3 0 , and the coefficient of the highest order (i.e., the third order) term can be determined based on the spin direction of the free layer 334, and the coefficient of the next higher order (i.e., the second order) term can be determined based on the spin direction of the free layer 333. Additionally, the coefficient of the next higher order (i.e., the first order) term can be determined based on the spin direction of the free layer 332, and the coefficient of the lowest order (i.e., the zero order) term can be determined based on the spin direction of the free layer 331. Based on this correspondence, the spin direction of the free layer 334 can be determined as the spin direction in the case where the resistance value is 1×3 3 =27, and the spin direction of the free layer 333 can be determined as the spin direction in the case where the resistance value is 1×3 2 =9. Furthermore, the spin direction of the free layer 332 can be determined as the spin direction in the case where the resistance value is 1×3 1 =3, and the spin direction of the free layer 331 can be determined as the spin direction in the case where the resistance value is 1×3 0 =1. In this way, even if the resistance value is measured only once, the spin directions of all of the free layers included in the vertically stacked structure can be identified.

[0103] In another embodiment, the resistance value measured between the reference layer 31 and the SOC layer 344 may be 44. In this case, 44 can be represented as 1122 in the ternary number system(3) Here, the spin direction of the free layer 334 can be determined as the spin direction when the resistance value is 1×3 3 = 27, and the spin direction of the free layer 333 can be determined as the spin direction when the resistance value is 1×3 2 = 9. In addition, the spin direction of the free layer 332 can be determined as the spin direction when the resistance value is 2×3 1 = 6, and the spin direction of the free layer 331 can be determined as the spin direction when the resistance value is 2×3 0 = 2.

[0104] In another embodiment, the resistance value measured between the reference layer 31 and the SOC layer 344 can be 52. In this case, 52 can be represented as 1221 in the ternary number system (3) Here, the spin direction of the free layer 334 can be determined as the spin direction when the resistance value is 1×3 3 = 27, and the spin direction of the free layer 333 can be determined as the spin direction when the resistance value is 2×3 2 = 18. In addition, the spin direction of the free layer 332 can be determined as the spin direction when the resistance value is 2×3 1 = 6, and the spin direction of the free layer 331 can be determined as the spin direction when the resistance value is 1×3 0 = 1.

[0105] Next, referring to Figure 14 , in an embodiment, the resistance value measured between the reference layer 31 and the SOC layer 344 can be 68. In this case, 68 can be represented as 2112 in the ternary number system (3) Here, the spin direction of the free layer 334 can be determined as the spin direction when the resistance value is 2×3 3 = 54, and the spin direction of the free layer 333 can be determined as the spin direction when the resistance value is 1×3 2 = 9. In addition, the spin direction of the free layer 332 can be determined as the spin direction when the resistance value is 1×3 1 = 3, and the spin direction of the free layer 331 can be determined as the spin direction when the resistance value is 2×3 0 = 2.

[0106] In another embodiment, the resistance value measured between the reference layer 31 and the SOC layer 344 can be 76. In this case, 76 can be represented as 2211 in the ternary number system (3) Here, the spin direction of the free layer 334 can be determined as the spin direction when the resistance value is 2×3 3The spin direction in the case of = 54, and the spin direction of the free layer 333 can be determined to be the spin direction in the case where the resistance value is 2 × 3 2 = 18. In addition, the spin direction of the free layer 332 can be determined to be the spin direction in the case where the resistance value is 1 × 3 1 = 3, and the spin direction of the free layer 331 can be determined to be the spin direction in the case where the resistance value is 1 × 3 0 = 1.

[0107] In another embodiment, the resistance value measured between the reference layer 31 and the SOC layer 344 can be 80. In this case, 80 can be represented as 2222 in the ternary number system (3) . Here, the spin direction of the free layer 334 can be determined to be the spin direction in the case where the resistance value is 2 × 3 3 = 54, and the spin direction of the free layer 333 can be determined to be the spin direction in the case where the resistance value is 2 × 3 2 = 18. In addition, the spin direction of the free layer 332 can be determined to be the spin direction in the case where the resistance value is 2 × 3 1 = 6, and the spin direction of the free layer 331 can be determined to be the spin direction in the case where the resistance value is 2 × 3 0 = 2.

[0108] According to the semiconductor device 30 of the vertical stacking structure described with reference to Figures 12 to 14 For comparison, assume that the semiconductor device 30 uses the same N free layers, that is, the same data capacity (e.g., N bits). Here, the vertical stacking structure including N free layers can have an occupied area reduced to about 1 / N of the occupied area of a magnetic random access memory (MRAM) device having a conventional array form. In addition, a conventional spin-orbit torque magnetic random access memory (SOT-MRAM) may require two transistors for each magnetic tunnel junction (MTJ) for its operation. However, the vertical stacking structure according to the embodiment may require fewer transistors for the read operation. That is, the vertical stacking structure including N free layers may only require N + 1 transistors, and thus has a significant improvement over the conventional SOT-MRAM that requires 2N transistors. Additionally, even if the resistance value is measured only once, the spin directions of all the free layers included in the vertical stacking structure can be identified.

[0109] Figure 15 is a block diagram showing a system including a semiconductor device according to an embodiment.

[0110] Refer to Figure 15, According to an embodiment, a system 40 including a semiconductor device may include a magnetic random access memory (MRAM) 450. The system 40 may include a computing device 410. In some embodiments, the computing device 410 may refer to any electronic device capable of computing by performing arithmetic or logical operations on data. The computing device 410 may be, for example, a server, a workstation, a desktop computer, a laptop computer, a tablet PC, a smart phone, a control system for another electronic device, or a storage device connected to a network. In some embodiments, the computing device 410 may include a non-transitory computer-readable storage medium storing computer-readable instructions, and the computer is configured to execute one or more steps of the methods disclosed in the specification.

[0111] The computing device 410 may include a processor 415, a memory 430, and a storage device 440. The processor 415 may refer to any electronic component that performs arithmetic or logical operations executed by the computing device. For example, in some embodiments, the processor 415 may be a general-purpose processor that executes stored program code. In some other embodiments, the processor 415 may be a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc., which may be operated by data stored in the memory 430 or the storage device 440. In some other embodiments, the processor 415 may be a controller for a storage device, a networking device, etc.

[0112] The processor 415 may include a cache 420. In some embodiments, the cache 420 may store data for use by the processor 415. In some embodiments, the cache 420 may be smaller and faster than the memory 430 and copy the data to a location frequently used in the memory 430. In some embodiments, the processor 415 may include multiple caches 420. In some embodiments, the cache 420 may include at least one type of memory medium for storing data, such as static random access memory (SRAM) 422 or MRAM 450. For example, in some embodiments, the cache 420 may include SRAM 422. In some other embodiments, the cache 420 may include MRAM 450. In some other embodiments, the cache 420 may include a combination of SRAM 422, MRAM 450, and another type of storage medium.

[0113] The memory 430 may be connected to the processor 415 via a memory bus 435. In some embodiments, the memory 430 may store data directly addressable by the processor 415. In some embodiments, the memory 430 may include at least one type of memory medium for storing data, such as dynamic random access memory (DRAM) 432 or MRAM 450. For example, in some embodiments, the memory 430 may include DRAM 432. In some other embodiments, the memory 430 may include MRAM 450. In some other embodiments, the memory 430 may include a combination of DRAM 432, MRAM 450, and another type of memory medium.

[0114] The storage device 440 may be connected to the processor 115 via a storage device bus 445. In some embodiments, the storage device bus 445 may be a peripheral bus of the computing device 410, such as a Peripheral Component Interconnect Express (PCIe) bus, Serial Advanced Technology Attachment (SATA) bus, Parallel Advanced Technology Attachment (PATA) bus, Small Computer System Interface (SCSI) bus, FireWire bus, Universal Serial Bus (USB), or PCIe Advanced Switching bus (PCIe-AS). In some embodiments, the storage device 440 may store data that can be accessed via at least one storage controller rather than directly addressable by the processor 415. In some embodiments, the storage device 440 may be larger than the memory 430. In some embodiments, the storage device 440 may include at least one type of memory medium for storing data, such as a hard disk drive, NAND flash memory 442, or MRAM 450. For example, in some embodiments, the storage device 440 may include NAND flash memory 442. In some other embodiments, the storage device 440 may include MRAM 450. In some other embodiments, the storage device 440 may include a combination of NAND flash memory 442, MRAM 450, and another type of memory medium.

[0115] In some embodiments, MRAM 450 can be used to store data in cache 420, memory 430, storage device 440, or another component that stores data. For example, computing device 410 can include MRAM 450 in cache 420, memory 430, or storage device 440. In some other embodiments, computing device 410 can use MRAM 450 for memory 430 and use another type of memory or another type of storage medium for cache 420 or storage device 440. Conversely, in some other embodiments, computing device 410 can use MRAM 450 for storage device 440 and use another type of memory medium for cache 420 or memory 430. Additionally, if memory 430 is non-volatile memory, a certain type of computing device 410 can include memory 430 (e.g., in a microcontroller) without including storage device 440, or can include memory 430 without including cache 420 for dedicated processor 415. Given the disclosure in the specification, various combinations of cache 420, memory 430, or storage device 440 and the use of cache 420, memory 430, storage device 440, or MRAM 450 for another application will become apparent.

[0116] According to the embodiments described above, a semiconductor device can provide an MRAM having a vertical stacked structure in which a tunnel barrier layer, a free layer, and a SOC layer are repeatedly stacked, thereby achieving a higher bit density while miniaturizing the MTJ and reducing its footprint. In addition, the semiconductor device can have fewer transistors required for its operation, thereby achieving a more effective scaling compared to an MRAM device having a conventional array form.

[0117] Although the embodiments of the present disclosure have been described in detail above, the scope of the present disclosure is not limited thereto. That is, various modifications and changes made by those skilled in the art of the present disclosure by using the basic concepts of the present disclosure defined in the appended claims also fall within the scope of the present disclosure.

Claims

1. A semiconductor device, comprising: a reference layer having a fixed spin direction; a metal layer disposed below the reference layer; a first free layer disposed below the metal layer; a first spin-orbit coupling (SOC) layer disposed below the first free layer and configured to control the spin direction recorded in the first free layer by using a current flowing through the first SOC layer; a second free layer disposed below the first SOC layer; and a second SOC layer disposed below the second free layer and configured to control the spin direction recorded in the second free layer by using a current flowing through the second SOC layer.

2. The device according to claim 1, further comprising: a blocking layer disposed between the reference layer and the metal layer, between the metal layer and the first free layer, or between the first SOC layer and the second free layer.

3. The device according to claim 1, further comprising: a first transistor controlled by a first word line signal to selectively connect the metal layer and a source line to each other; a second transistor controlled by a second word line signal to selectively connect the first SOC layer and the source line to each other; and a third transistor controlled by a third word line signal to selectively connect the second SOC layer and the source line to each other.

4. The device according to claim 3, wherein the first SOC layer is connected to a write bit line, the first SOC layer is connected to the source line through the second transistor, and the spin direction of the first free layer is determined based on the current flowing through the first SOC layer, and the first SOC layer is disposed between the write bit line and the source line.

5. The device according to claim 4, wherein the second SOC layer is connected to the write bit line, the second SOC layer is connected to the source line through the third transistor, and the spin direction of the second free layer is determined based on the current flowing through the second SOC layer, and the second SOC layer is disposed between the write bit line and the source line.

6. The device according to claim 3, further comprising a read transistor configured to selectively connect the reference layer and a read bit line to each other, wherein the reference layer is connected to the read bit line through the read transistor, the first SOC layer is connected to the source line through the second transistor, and the spin direction of the first free layer is determined by measuring a resistance value of a first stack structure including the reference layer, the metal layer, the first free layer, and the first SOC layer.

7. The device according to claim 6, wherein when the measured resistance value of the first stack structure is equal to or greater than a first critical value, the spin direction of the reference layer and the spin direction of the first free layer are determined to be opposite to each other, and when the measured resistance value of the first stack structure is less than the first critical value, the spin direction of the reference layer and the spin direction of the first free layer are determined to be the same as each other.

8. The device according to claim 6, wherein, The metal layer is connected to the source line through the first transistor, the second SOC layer is connected to the source line through the third transistor, and the spin direction of the second free layer is determined by measuring the resistance value of a second stacked structure including the reference layer, the metal layer, the first free layer, the first SOC layer, the second free layer, and the second SOC layer.

9. The device according to claim 8, wherein, when the measured resistance value of the second stacked structure is equal to or greater than a second critical value, the spin directions of the first free layer and the second free layer are determined to be opposite to each other, and when the measured resistance value of the second stacked structure is measured to be less than the second critical value, the spin directions of the first free layer and the second free layer are determined to be the same as each other.

10. A semiconductor device, comprising: a reference layer having a fixed spin direction; a first free layer disposed below the reference layer; a first spin-orbit coupling (SOC) layer disposed below the first free layer and configured to control the spin direction recorded in the first free layer by using a current flowing through the first SOC layer; a second free layer disposed below the first SOC layer; and a second SOC layer disposed below the second free layer and configured to control the spin direction recorded in the second free layer by using a current flowing through the second SOC layer.

11. The device according to claim 10, further comprising: a blocking layer disposed between the reference layer and the first free layer, or between the first SOC layer and the second free layer.

12. The device according to claim 10, further comprising: a first transistor controlled by a first word line signal to selectively connect the first SOC layer and the source line to each other; and a second transistor controlled by a second word line signal to selectively connect the second SOC layer and the source line to each other.

13. The device according to claim 12, wherein, the first SOC layer is connected to a write bit line, the first SOC layer is connected to the source line through the first transistor, and the spin direction of the first free layer is determined based on the current flowing through the first SOC layer, and the first SOC layer is disposed between the write bit line and the source line.

14. The device according to claim 13, wherein, the second SOC layer is connected to the write bit line, the second SOC layer is connected to the source line through the second transistor, and the spin direction of the second free layer is determined based on the current flowing through the second SOC layer, and the second SOC layer is disposed between the write bit line and the source line.

15. The device according to claim 12, further comprising a read transistor configured to selectively connect the reference layer and a read bit line to each other, wherein the reference layer is connected to the read bit line through the read transistor, the first SOC layer is connected to the source line through the first transistor, and The spin direction of the first free layer is determined by measuring a first resistance value of a first stacked structure including the reference layer, the first free layer, and the first SOC layer.

16. The apparatus according to claim 15, wherein the reference layer is connected to the read bit line through the read transistor, the second SOC layer is connected to the source line through the second transistor, and the spin direction of the second free layer is determined by measuring a second resistance value of a second stacked structure including the reference layer, the first free layer, the first SOC layer, the second free layer, and the second SOC layer.

17. The apparatus according to claim 16, wherein when the difference between the first resistance value and the second resistance value is measured to be equal to or greater than a third critical value, the spin directions of the first free layer and the second free layer are determined to be opposite to each other, and when the difference between the first resistance value and the second resistance value is measured to be less than the third critical value, the spin directions of the first free layer and the second free layer are determined to be the same as each other.

18. A semiconductor device, comprising: a reference layer having a fixed spin direction; a first free layer disposed below the reference layer and having a physical property in which a resistance value of the first free layer is determined to be a value corresponding to a first digit of a ternary number based on a spin direction of the first free layer; a first spin orbit coupling (SOC) layer disposed below the first free layer and configured to control a spin direction of the first free layer by using a current flowing through the first SOC layer; a second free layer disposed below the first SOC layer and having a physical property in which a resistance value of the second free layer is determined to be a value corresponding to a second digit of the ternary number based on a spin direction of the second free layer; and a second SOC layer disposed below the second free layer and configured to control a spin direction of the second free layer by using a current flowing through the second SOC layer.

19. The apparatus according to claim 18, further comprising: a blocking layer disposed between the reference layer and the first free layer, or between the first SOC layer and the second free layer.

20. The apparatus according to claim 19, wherein the spin directions of the first free layer and the second free layer are determined by converting a resistance value measured between the reference layer and the second SOC layer into the ternary number.

Images