Apparatus and method for coupling plurality of semiconductor devices

Abstract

Apparatuses and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a coupling point at an intermediate semiconductor device of the group, and propagated on different (e.g., opposite) signal paths away from the coupling point to other semiconductor devices of the group. The load from the coupling point at the intermediate semiconductor device to other semiconductor devices of a group may be more balanced than, for example, a semiconductor device at an end of the group (e.g., a lowest semiconductor device of the stack, a highest semiconductor device of the stack, etc.) having a coupling point and providing a signal from the coupling point. A more balanced topology may reduce timing differences between times at which signals arrive at each of the semiconductor devices.

Description

[0001] Relevant information of divisional application

[0002] This application is a divisional application, and the parent application of this divisional application is an invention patent application with the application number of "202110653272.1" and the title of "Device and Method for Coupling Multiple Semiconductor Devices" filed on June 11, 2021. Technical Field

[0003] The present disclosure relates to memory devices, and more particularly to devices and methods for coupling multiple semiconductor devices. Background Art

[0004] In recent years, three-dimensional (3D) memory devices have been introduced. Some 3D memory devices are formed by vertically stacking die and coupling the die using through-silicon (or through-substrate) vias (TSVs) and / or wire bonding. Thus, 3D memory may also be referred to as "stacked memory". 3D memory can provide a larger memory capacity and / or higher bandwidth than non-3D memory with less area increase. Example 3D memory devices include Hybrid Memory Cube (HMC), High Bandwidth Memory (HBM), and Master-Slave Memory (MSM), each of which may include multiple dynamic random access memory (DRAM) die coupled to each other in a stack.

[0005] The memory device may be coupled to an external circuit that provides command, address, and data signals to the stacked die to access the memory. The stacked die are typically coupled to the external circuit at the lowest height die, where the inter-level bonding connects upward to the remaining die in the stack.

[0006] However, as memory speed increases, the delay between signals reaching the lowest height die and the highest height die in the stack becomes non-negligible. The operation timing of the memory device is typically set based on the worst case (i.e., the signal arrival time at the highest height die in the stack) to accommodate the timing differences of the arriving signals. This method may result in a reduction in the performance of the memory device. Additionally, as memory speed continues to increase, the timing differences in the signal arrival times from the lowest die to the highest die in the stack may no longer be tolerable for the desired system performance. Summary of the Invention

[0007] According to one aspect of the present disclosure, a device is disclosed. The device includes: a plurality of memory devices including a first, a second, and a third memory device, the first memory device including a first bonding pad, the second memory device including a second bonding pad, the third memory device including a third bonding pad, the second memory device being disposed between the first and the third memory devices; a first conductor coupled to the first and the second bonding pads; a second conductor coupled to the second and the third bonding pads; and a third conductor coupled to the second bonding pad and configured to provide a signal to the second bonding pad, wherein the first conductor provides the signal from the second bonding pad to the first bonding pad in a first signal timing and the second conductor provides the signal from the second bonding pad to the third bonding pad in a second signal timing equal to the first signal timing.

[0008] According to another aspect of the present disclosure, a multi-die device is provided. The multi-die device includes: a substrate including conductive signal lines; a semiconductor device stack attached to the substrate; and a conductor coupled to the conductive signal lines of the substrate and to a bonding pad of an intermediate semiconductor device of the semiconductor device stack.

[0009] According to yet another aspect of the present disclosure, a device is provided. The device includes: a semiconductor device stack including a lowest semiconductor device, a highest semiconductor device, and at least one intermediate semiconductor device disposed between the lowest and the highest semiconductor devices; a plurality of conductors coupled to bonding pads of the semiconductor devices of the stack; and a source conductor coupled to a coupling point at a bonding pad of one of the at least one intermediate semiconductor devices, wherein the first and the second of the plurality of conductors are also coupled to the bonding pad of one of the at least one intermediate semiconductor devices.

[0010] According to yet another aspect of the present disclosure, a method is provided. The method includes: providing a signal to an intermediate semiconductor device of a semiconductor device stack, the intermediate semiconductor device being disposed between a first and a second semiconductor device also included in the semiconductor device stack; propagating the signal away from the intermediate semiconductor device to the first semiconductor device through a first signal path coupled to the intermediate semiconductor device and the first semiconductor device; and propagating the signal away from the intermediate semiconductor device to the second semiconductor device through a second signal path coupled to the intermediate semiconductor device and the second semiconductor device. Description of the Drawings

[0011] Figure 1 is a diagram showing a multi-die device.

[0012] Figure 2 is a block diagram of a semiconductor device according to an embodiment of the present disclosure.

[0013] Figure 3 is a layout diagram of a semiconductor device according to an embodiment of the present disclosure.

[0014] Figure 4 is a cross-sectional view of a conductive structure of a semiconductor device according to an embodiment of the present disclosure.

[0015] Figure 5 is a diagram showing a multi-die device according to an embodiment of the present disclosure.

[0016] Figure 6 is a schematic diagram of semiconductor devices coupled together according to an embodiment of the present disclosure.

[0017] Figure 7 is a plan view of bonding pads of semiconductor devices coupled together according to an embodiment of the present disclosure.

[0018] Figure 8 is a flowchart of a semiconductor device for providing a signal to a stack of semiconductor devices according to an embodiment of the present disclosure. Detailed Description

[0019] Devices and methods for coupling semiconductor devices are disclosed. In a group of semiconductor devices (e.g., a stack of semiconductor devices), a signal is provided to a coupling point at an intermediate semiconductor device of the group, and the signal is propagated away from the coupling point along different (e.g., opposite) signal paths to other semiconductor devices of the group. Compared to having a coupling point at a semiconductor device at the end of the group (e.g., the lowest semiconductor device of the stack, the highest semiconductor device of the stack, etc.) and providing the signal from the coupling point, the load from the coupling point at the intermediate semiconductor device to other semiconductor devices of the group may be more balanced. A more balanced topology may reduce the timing difference between the times when the signal reaches each of the semiconductor devices.

[0020] Various embodiments of the present disclosure will be explained in detail below with reference to the accompanying drawings. The following detailed description refers to the drawings which show, in an illustrative manner, specific aspects and embodiments of the present disclosure. The detailed description includes sufficient details for those skilled in the art to practice the embodiments of the present disclosure. Without departing from the scope of the present disclosure, other embodiments may be utilized and structural, logical, and electrical changes may be made. The various embodiments disclosed herein are not necessarily mutually exclusive, as some of the disclosed embodiments may be combined with one or more other disclosed embodiments to form new embodiments.

[0021] Figure 1It is a diagram showing the multi-die device 100. The multi-die device 100 may include a stack 115 of semiconductor devices 120. The stack 115 is shown as including 10 semiconductor devices 120(0) to 120(9). Each of the semiconductor devices 120(0) to 120(9) may be, for example, a memory device, such as a dynamic random access memory (DRAM) device.

[0022] The semiconductor devices 120 of the stack 115 may be attached to each other, and the stack 115 may be attached to a substrate 130. The substrate 130 may include conductive signal lines to route signals to and from the stack 115 of semiconductor devices 120 along the substrate. One or more of the signal lines may be coupled to external terminals 140, such as solder balls, etc. Other circuits may also be attached to the substrate 130 and also coupled to the conductive signal lines. Thus, the circuits attached to the substrate 130 may be coupled to the stack 115 of semiconductor devices 120, for example, through the conductive signal lines. Figure 1 Circuit 135 attached to the substrate 130 and coupled to the stack 115 of semiconductor devices 120 is shown. Circuit 135 may be a register clock driver (RCD). The RCD circuit receives and buffers signals provided to the multi-die device 100 and may provide the signals to the stack 115 of semiconductor devices 120.

[0023] The semiconductor devices 120 may be stacked in a staggered manner, providing an "overlapping stack" configuration for the stack 115. That is, the semiconductor devices 120 are offset from each other to allow the edge regions of the semiconductor devices 120 to be exposed. The exposed edge regions may include bonding pads coupled to conductors 125. The conductors 125 may be bonding wires, and the bonding pads in the edge regions may be coupled together through the bonding wires.

[0024] Except for the lowest-height semiconductor device 120(0), the bonding pads of each semiconductor device 120 are coupled to the bonding pads of the immediately preceding semiconductor device 120 in the stack. For example, as Figure 1 shown, the bonding pads of semiconductor device 120(9) are coupled to the bonding pads of semiconductor device 120(8) through bonding wire 125(9), the bonding pads of semiconductor device 120(8) are coupled to the bonding pads of semiconductor device 120(7) through bonding wire 125(8), and so on down to the bonding pads of semiconductor device 120(0). The semiconductor device 120(0) is coupled to the conductive signal lines of the substrate 130 through bonding wire 125(0). Thus, the circuits attached to the substrate 130 (e.g., circuit 135) may be coupled to the semiconductor devices 120, for example, through the conductive signal lines and bonding wires 125.

[0025] Using Figure 1The arrangement shown provides different arrival times for signals provided to stack 115 (e.g., from circuit 135) to semiconductor device 120 due to the inherent propagation delay through bond wires 125. For example, a signal first arrives at semiconductor device 120(0) through bond wire 125(0), then arrives at semiconductor device 120(1) at a later time after propagating through bond wire 125(1), then arrives at semiconductor device 120(2) at an even later time after propagating through bond wire 125(2), and so on until the signal finally arrives at semiconductor device 120(9) after propagating through bond wire 125(9). Since the stack contains several semiconductor devices 120 and as memory speeds continue to increase, the time delay between the time a signal arrives at the first of the semiconductor devices 120 in stack 115 and the time it arrives at the last of the semiconductor devices 120 may have a greater impact on the performance of the multi-die device 100.

[0026] Figure 2 is a block diagram of a semiconductor device 210 in accordance with an embodiment of the present disclosure. For example, in some embodiments, semiconductor device 210 may be a memory integrated into a single semiconductor chip (e.g., a semiconductor die). Example memories may include volatile memories (e.g., dynamic random access memory (DRAM) and static random access memory (SRAM)), and non-volatile memories (e.g., flash memory, resistive memory, and ferroelectric memory or any combination thereof).

[0027] Semiconductor device 210 includes a memory cell array 211. Memory cell array 211 includes a plurality of banks, each bank including a plurality of word lines WL, a plurality of bit lines BL, and a plurality of memory cells MC disposed at intersections of the plurality of word lines WL and the plurality of bit lines BL. Selection of the word lines WL is performed by row decoder / driver 212 and selection of the bit lines BL is performed by column decoder / driver 213. Sense amplifiers 218 are coupled to corresponding bit lines BL and are connected to local I / O line pairs LIOT / B. The local I / O line pairs LIOT / B are connected to main I / O line pairs MIOT / B via transfer gates TG 219 that act as switches.

[0028] Semiconductor device 210 includes a plurality of terminals. In some embodiments of the present disclosure, the terminals may be die pads. The plurality of terminals includes command and address terminals 221, clock terminals 223 and 223’, data terminals 224, data strobe terminals 224’, power supply terminals 225 and 226. The data terminals 224 may be coupled to an output buffer of input / output circuit 217 for a read operation. Alternatively, the data terminals 224 may be coupled to an input buffer of input / output circuit 217 to perform a write access to the memory in response to a data strobe signal DQS provided at data strobe terminal 224’.

[0029] Command and address signals CA including commands and memory addresses are supplied to command and address terminal 221. The address supplied to command and address terminal 221 is transferred to address decoder 232 via command and address input circuit 231. Address decoder 232 receives the address and supplies the decoded row address to row decoder / driver 212, and supplies the decoded column address to column decoder / driver 213. Address decoder 232 also receives the bank address and supplies the bank address to row decoder / driver 212 and / or column decoder / driver 213. In the self-refresh mode, self-refresh circuit 238 may supply the row address to row decoder / driver 212 for self-refresh operation.

[0030] The command supplied to command and address terminal 221 is supplied to command decoder 234 via command and address input circuit 231. Command decoder 234 decodes the command and supplies the decoded command to internal control signal generator 237. Internal control signal generator 237 may generate various internal command signals in response to the decoded command from command decoder 234. For example, the internal commands may include a row command signal for selecting a word line and a column command signal for selecting a bit line, such as a read command or a write command.

[0031] Therefore, when an activate command is issued and the activate command is timely supplied to the row address, and a read command is timely supplied to the column address, read data is read from the memory cell MC specified by the row address and the column address in memory cell array 211. The read data DQ is output from data terminal 224 via read / write amplifier 215 and input / output circuit 217. Similarly, when an activate command is issued and the activate command is timely supplied to the row address, and a write command is timely supplied to the column address, the write data DQ supplied to data terminal 224 is supplied to memory cell array 211 via input / output circuit 217 and read / write amplifier 215 and written in the memory cell MC specified by the row address and the column address.

[0032] A clock signal CK_t and CK_c are respectively supplied to the clock terminal 223, and a data clock signal WCK_t and WCK_c are supplied to the clock terminal 223'. The clock input circuit 235 receives the clock signals CK_t and CK_c and WCK_t and WCK_c and generates an internal clock signal ICLK. The internal clock signal ICLK may include an internal clock signal based on the clock signals CK_t and CK_c and / or an internal clock signal based on the data clock signals WCK_t and WCK_c. Some or all of the internal clock signals ICLK are supplied to the internal clock and timing generator 236, which in response generates a phase-controlled internal clock signal LCLK. The internal clock and timing generator 236 may include a DLL circuit, but is not limited thereto. The phase-controlled internal clock signal LCLK may be supplied to the input / output circuit 217 and used to time the input and / or output of data. The internal clock and timing generator 236 may further generate various other internal clock signals for various memory operations.

[0033] A power supply potential VDD and VSS are supplied to the power supply terminal 225. These power supply potentials VDD and VSS are supplied to the power supply circuit 239. The power supply circuit 239 may generate various internal potentials, for example, VPP, VOD, VARY, VPERI, etc. The internal potential VPP is mainly used in the row decoder / driver 212, the internal potentials VOD and VARY are mainly used in the sense amplifiers 218 included in the memory cell array 211, and the internal potential VPERI is used in many other circuit blocks. A power supply potential VDDQ and VSSQ are supplied to the power supply terminal 226. These power supply potentials VDDQ and VSSQ are supplied to the input / output circuit 217. The power supply potentials VDDQ and VSSQ may be the same potentials as the power supply potentials VDD and VSS supplied to the power supply terminal 225, respectively. However, the power supply potentials VDDQ and VSSQ may be used in the input / output circuit 217 such that the power supply noise generated by the input / output circuit 217 does not propagate to other circuit blocks.

[0034] Figure 3 is a layout diagram of the semiconductor device 310 according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device 310 includes Figure 2 the semiconductor device 210.

[0035] The semiconductor device 310 may have edges 350a, 350b, 350c, and 350d that define the ends of the semiconductor device 310. Edges 350b and 350d may extend along a first direction 357a and edges 350a and 350c may extend along a second direction 357b that may be perpendicular to the first direction 357a. The semiconductor device 310 may include a pad formation region 351, a peripheral circuit region 352, and a memory cell array region 353 that includes memory cells, circuits, and signal lines (e.g., sense amplifier circuits, address decoder circuits, data input / output lines, etc.). The peripheral circuit region 352 may include various circuits and signal lines for performing various operations of the semiconductor device 310. For example, the peripheral circuit region 352 may include command and address input circuits, address and command decoders, clock circuits, power circuits, and input / output circuits. The peripheral circuit region 352 may also include terminals (e.g., as previously described for Figure 1 the semiconductor device 170) that are coupled to various circuits of the semiconductor device. The terminals may be, for example, die pads of the semiconductor device.

[0036] The pad formation region 351 may include a plurality of bonding pads 354 disposed along the edge 350a. The plurality of bonding pads 354 may be coupled to the terminals (e.g., die pads) of the semiconductor device and represent the external terminals of the semiconductor device 310. For example, the plurality of bonding pads 354 may include data terminals, command and address terminals, clock terminals, and / or power supply terminals.

[0037] The circuits included in the memory cell array region 353 and / or the circuits of the peripheral circuit region 352 may be coupled to one or more of the bonding pads 354 included in the pad formation region 351. As previously described, the various circuits of the semiconductor device 300 may be coupled to the terminals (e.g., die pads). Conductive structures may be used to couple the terminals to one or more of the bonding pads 354. Thus, the circuits coupled to the terminals are also coupled to the bonding pads 354. The conductive structures may extend from the locations of the terminals included in the memory cell array region 353 and / or the peripheral circuit region 352 to the pad formation region 351. In some embodiments of the present disclosure, the conductive structures may include conductive redistribution layers (RDLs).

[0038] Figure 4 is a cross-sectional view of a conductive structure of a semiconductor device according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the conductive structure may be included in Figure 2 the semiconductor device 210, Figure 1 the semiconductor device 120 of the multi-die device 100, Figure 3 the semiconductor device 310, and / or any semiconductor device according to embodiments of the present disclosure. For example, in some embodiments of the present disclosure, the conductive structure may be included inFigures 1 to 3 in a conductive redistribution layer (RDL) in one or more of the semiconductor devices.

[0039] The conductive structure 430 can couple the terminal 440 of the semiconductor device to the bonding pad 420. In some embodiments of the present disclosure, the terminal 440 can be a die pad. The terminal 440 can be coupled to one or more circuits 445 of the semiconductor device. Thus, the bonding pad 420 can be coupled to the circuit 445 through the conductive structure 430 and the terminal 440. In some embodiments of the present disclosure, the circuit 445 can be, for example, a circuit included in a memory cell array region (e.g., Figure 3 the memory cell array region 352). In some embodiments of the present disclosure, the circuit 445 can be, for example, a circuit included in a peripheral circuit region (e.g., Figure 3 the peripheral circuit region 354). The circuit 445 can be used to perform various operations of the semiconductor device. In some embodiments of the present disclosure, the circuit 445 can include command and address input circuits, address and command decoders, clock circuits, power circuits, input / output circuits, and other circuits.

[0040] The bonding pad 420, conductive structure 430, terminal 440, and circuit 445 of the semiconductor device can be formed from a semiconductor structure. The semiconductor structure can include conductive layers, conductive vias, insulating interlayers, etc. The terminal 440 can be coupled to the circuit 445 through, for example, a metal layer and / or a conductive via. The conductive structure 430 can be disposed on one or more insulating interlayers. As previously described, the conductive structure 430 can be further coupled to the bonding pad 420. The conductive structure 430 extends from the terminal 440 to the bonding pad 420 such that the bonding pad 420 and the circuit terminal 440 can be coupled together. Thus, the circuit 445 coupled to the terminal 440 can be accessed externally through the bonding pad 420. The bonding pad 420 can be exposed through an opening 425 in the passivation layer 435. In some embodiments of the present disclosure, the passivation layer 435 can be a polyimide material.

[0041] In some embodiments of the present disclosure, the conductive structure 430 can be coupled to the terminal 440 (e.g., the die pad of the semiconductor device) of the semiconductor device to provide a bonding pad 420 for coupling to the terminal 440 at different locations. For example, the terminal 440 can represent a die pad typically located in a peripheral circuit region along the central region of the semiconductor device, and the conductive structure 430 can couple the die pad in the central region to the bonding pad 420 located along the edge of the semiconductor device. The bonding pads 420 along the edge can be more conveniently located and provide coupling to the circuit 445 of the semiconductor device, i.e., through the conductive structure 430 and the terminal 440.

[0042] Figure 5FIG. 0 is a diagram showing a multi-die device 500 in accordance with an embodiment of the present disclosure. The multi-die device 500 may include a stack 515 of semiconductor devices 520. Embodiments of the present disclosure are not limited to Figure 5 the specific number of semiconductor devices 520 included in the stack 515 shown in Figure 2 FIG. Figure 2 . Each of the semiconductor devices 520 may include a semiconductor device 210 of

[0043] FIG. . Each of the semiconductor devices 520 may be, for example, a memory device such as a dynamic random access memory (DRAM) device. The semiconductor devices 520 of the stack 515 may be attached to each other, and the stack 515 may be attached to a substrate 530. In some embodiments of the present disclosure, the semiconductor devices 520 are attached to each other and / or attached to the substrate 530 via a sticky epoxy resin. The substrate 530 may include conductive signal lines to route signals to and from the stack 515 of semiconductor devices 520 along the substrate. One or more of the signal lines may be coupled to external terminals 540. In some embodiments of the present disclosure, the external terminals 540 may include solder balls or the like. Other circuits may also be attached to the substrate 530 and also coupled to the conductive signal lines. Thus, the circuits attached to the substrate 530 may be coupled to the stack 515 of semiconductor devices 520, for example, via the conductive signal lines. Figure 5 FIG. Figure 5 shows a circuit 535 attached to the substrate 530 and coupled to the stack 515 of semiconductor devices 520. In some embodiments of the present disclosure, the circuit 535 may be a register clock driver (RCD). In such embodiments of the present disclosure, the RCD circuit receives and buffers signals provided to the multi-die device 500 and may provide the signals to the stack 515 of semiconductor devices 520. Without departing from the scope of the present disclosure, additional or alternative circuits may be included in the multi-die device 500, and / or the circuit 535 may also be other circuits.

[0044] The semiconductor devices 520 may be stacked in a staggered manner, thereby providing a “shingled stack” configuration for the stack 515. That is, the semiconductor devices 520 are offset from each other to allow the edge regions of the semiconductor devices 520 to be exposed. The exposed edge regions may include bonding pads coupled to conductors 525. In some embodiments of the present disclosure, the conductors 525 may be bonding wires, and the bonding pads in the edge regions may be coupled together via the bonding wires.

[0045] Except for the lowest-height semiconductor device 520(0), the bonding pads of each semiconductor device 520 are coupled to the bonding pads of at least one other semiconductor device 520 in the stack. For example, as shown in Figure 5As shown, the bonding pads of semiconductor device 520(8) are coupled to the bonding pads of semiconductor device 520(9) via conductor 525(9), and the bonding pads are further coupled to the bonding pads of semiconductor device 520(7) via conductor 525(8). Similarly, the bonding pads of semiconductor device 520(1) are coupled to the bonding pads of semiconductor device 520(2) via conductor 525(2), and the bonding pads are further coupled to the bonding pads of semiconductor device 520(0) via conductor 525(1).

[0046] Semiconductor device 520(4) is coupled to a conductive signal line of substrate 530 via source conductor 510. Source conductor 510 may be coupled to, for example, a bonding pad of semiconductor device 520(4). Semiconductor device 520(4) is coupled to semiconductor device 520(3), which is coupled to semiconductor device 520(2), which is coupled to semiconductor device 520(1), which is coupled to semiconductor device 520(0). Semiconductor device 520(4) is also coupled to semiconductor device 520(5), which is coupled to semiconductor device 520(6), which is coupled to semiconductor device 520(7), which is coupled to semiconductor device 520(8), which is coupled to semiconductor device 520(9). Thus, a circuit (e.g., circuit 535) attached to substrate 530 may be coupled to stack 515 of semiconductor devices 520 via, for example, the conductive signal line and source conductor 510 and conductor 525.

[0047] In an embodiment of the present disclosure, coupling to stack 515 at an intermediate semiconductor device of semiconductor device 520 may reduce the timing difference between the times at which signals reach each of the semiconductor devices. The intermediate semiconductor device may be any semiconductor device between the lowest semiconductor device and the highest semiconductor device (e.g., semiconductor device 520(0) (lowest) and semiconductor device 520(9) (highest)). From a coupling perspective, coupling to the intermediate semiconductor device of stack 515 may provide a more balanced topology.

[0048] Although Figure 5Describe the semiconductor devices 520 in stack 515. However, in other embodiments of the present disclosure, the semiconductor devices 520 may be arranged in groups in different ways. For example, the semiconductor devices may be arranged horizontally in a row relative to each other. The coupling point may be to the middle semiconductor device of a horizontally arranged group of semiconductor devices. In such embodiments, the signal provided to the coupling point may propagate horizontally in opposite directions from the coupling point to the semiconductor devices at the opposite ends of the horizontal arrangement of the semiconductor devices. In some embodiments of the present disclosure, the semiconductor devices 520 are physically positioned relative to each other in other arrangements. More generally, the scope of the present disclosure is not intended to be limited to a stacked arrangement of semiconductor devices.

[0049] For example, in Figure 5 In the embodiment of the present disclosure shown in, the conductive signal lines of the substrate 530 are coupled to the stack 515 at the middle semiconductor device 520(4) through the source conductor 510. Compared with having the coupling point, for example, at the lowest semiconductor device, the load from the coupling point at the semiconductor device 520(4) to the lowest semiconductor device 520(0) and to the highest semiconductor device 520(9) is more balanced. Therefore, the timing difference of the signals from the coupling point at the semiconductor device 520(4) to the lowest semiconductor device 520(0) and to the highest semiconductor device 520(9) of the stack can be reduced.

[0050] It may be advantageous to have the coupling point at a middle semiconductor device near the center of a group of semiconductor devices (e.g., a stack). The "center" semiconductor device is the middle semiconductor device of the group, which may be positioned in the group such that there is an equal number of semiconductor devices in either direction from the center semiconductor device to the opposite end semiconductor devices. For example, in a stack of nine semiconductor devices, the center semiconductor device is the fifth semiconductor device, which is positioned in the stack such that there are four semiconductor devices in a first direction to the first end semiconductor device (e.g., the lowest semiconductor device) and four semiconductor devices in a second direction to the second end semiconductor device (e.g., the highest semiconductor device). In the case where the group contains an even number of semiconductor devices, the center semiconductor device may be either of the two semiconductor devices positioned in the group such that there is an almost equal number of semiconductor devices in either direction from the center semiconductor device to the opposite end semiconductor devices (e.g., + / - 1 semiconductor device). For example, in a stack of eight semiconductor devices, the center semiconductor device is the fourth or fifth semiconductor device, which is positioned in the stack such that there are four semiconductor devices in a first direction to the first end semiconductor device and three semiconductor devices in a second direction to the second end semiconductor device.

[0051] Figure 6 is a schematic diagram of semiconductor devices coupled together according to an embodiment of the present disclosure. In some embodiments of the present disclosure,Figure 6 The semiconductor device can represent Figure 5 the stack 515 of the semiconductor device 520. In some embodiments of the present disclosure, Figure 6 the semiconductor device can represent a group of semiconductor devices arranged laterally with respect to each other. In some embodiments of the present disclosure, Figure 6 the semiconductor device can represent semiconductor devices in other physical arrangements. For purposes of ease of description, reference will be made to Figure 5 the semiconductor device 520 to describe Figure 6 the semiconductor device. However, Figure 6 the semiconductor device is not necessarily limited thereto.

[0052] The bonding pads of the semiconductor devices 520(0) to 520(9) are coupled by conductors 525(1) to 525(9). For example, the bonding pad of the semiconductor device 520(0) is coupled to the bonding pad of the semiconductor device 520(1) by the conductor 525(1); the bonding pad of the semiconductor device 520(1) is coupled to the bonding pad of the semiconductor device 520(2) by the conductor 525(2); the bonding pad of the semiconductor device 520(2) is coupled to the bonding pad of the semiconductor device 520(3) by the conductor 525(3); the bonding pad of the semiconductor device 520(3) is coupled to the bonding pad of the semiconductor device 520(4) by the conductor 525(4); the bonding pad of the semiconductor device 520(4) is coupled to the bonding pad of the semiconductor device 520(5) by the conductor 525(5); the bonding pad of the semiconductor device 520(5) is coupled to the bonding pad of the semiconductor device 520(6) by the conductor 525(6); the bonding pad of the semiconductor device 520(6) is coupled to the bonding pad of the semiconductor device 520(7) by the conductor 525(7); the bonding pad of the semiconductor device 520(7) is coupled to the bonding pad of the semiconductor device 520(8) by the conductor 525(8); and the bonding pad of the semiconductor device 520(8) is coupled to the bonding pad of the semiconductor device 520(9) by the conductor 525(9).

[0053] The source conductor 510 is coupled to the bonding pad of the semiconductor device 520(4). The source conductor 510 can be coupled to another circuit and / or a conductive signal line such as, for example, a substrate. Thus, the circuit and / or the conductive signal line can be coupled to other semiconductor devices.

[0054] In Figure 6In the example, only one bonding pad is shown for each of the semiconductor devices 520. However, without departing from the scope of the present disclosure, each of the semiconductor devices 520 may include additional bonding pads that can be coupled to other semiconductor devices 520. The bonding pads of the semiconductor devices 520 may also represent one or more physical bonding pads that can be coupled together, and thus are not limited to only one physical bonding pad to which a plurality of conductors are coupled. For example, in some embodiments of the present disclosure, the bonding pad of a semiconductor device may represent two bonding pads coupled together, one bonding pad coupled to the bonding pad of a first adjacent semiconductor device and another bonding pad coupled to the bonding pad of a second adjacent semiconductor device. In some embodiments of the present disclosure, the bonding pad of a semiconductor device may represent three bonding pads coupled together, a first bonding pad coupled to the bonding pad of a first adjacent semiconductor device, a second bonding pad coupled to the bonding pad of a second adjacent semiconductor device, and a third bonding pad to which the source conductor 510 can be coupled.

[0055] The conductor 525 includes an inherent propagation delay that can affect the timing of the signal reaching the corresponding semiconductor device. However, in the case where the source conductor 510 is coupled to an intermediate one of the semiconductor devices 520(0) to 520(9), a more balanced topology can be provided. The intermediate semiconductor device can be, for example, a semiconductor device between a first-end semiconductor device and a second-end semiconductor device (e.g., between the semiconductor device 520(0) (first end) and the semiconductor device 520(9) (second end)). The more balanced topology can reduce the timing difference between the times at which the signal reaches each of the semiconductor devices 520. For example, as Figure 6 shown in the example, using the coupling point at the bonding pad of the semiconductor device 520(4), the signal provided on the source conductor 510 propagates through four conductors 525(4) to 525(1) to reach the semiconductor device 520(0) (e.g., the first-end semiconductor device) and propagates through five conductors 525(5) to 525(9) to reach the semiconductor device 520(9) (e.g., the second-end semiconductor device).

[0056] In embodiments of the present disclosure where each of the conductors 525 provides a similar propagation delay, the difference in the arrival times of the signal provided on the source conductor 510 at the semiconductor device 520(0) and at the semiconductor device 520(9) is approximately equal to the propagation delay of one conductor 525 (e.g., the conductor 525(9), the fifth conductor), which in some embodiments of the present disclosure can be considered approximately equal to the same propagation delay to the semiconductor device 520(0) and to the semiconductor device 520(9).

[0057] In contrast, compared to an arrangement in which a signal is first provided to a semiconductor device 520(0) (e.g., a first-end semiconductor device) and the signal propagates through conductors 525(1) to 525(9) to semiconductor device 520(9), the difference in signal timing can be significantly greater. For example, the signal reaches semiconductor device 520(9) after the propagation delay of nine conductors 525. Thus, the difference in signal timing between semiconductor device 520(0) and semiconductor device 520(9) is the total propagation delay of nine conductors 525, which can be a significantly longer delay than the timing difference of the propagation delay of one conductor 525, e.g., for Figure 6 the instance of.

[0058] An arrangement that couples a source conductor to an intermediate semiconductor device of a group of semiconductor devices (e.g., a semiconductor device stack) can be advantageous in reducing the difference in signal timing for signals reaching the two-end semiconductor devices. This arrangement can provide improved signal integrity for unidirectional signals with high loads (e.g., command and address signals, chip select signals, clocks, and other signals). The disclosed arrangement may also require lighter driving and lighter terminal termination (e.g., at the die termination) to provide an effective data eye at the receiver circuit.

[0059] Figure 7 is a plan view of bonding pads of semiconductor devices coupled together according to an embodiment of the present disclosure. Although Figure 7 five semiconductor devices 720(2) to 720(6) are shown, additional semiconductor devices can be coupled to semiconductor devices 720(2) to 720(6) without departing from the scope of the present disclosure. For example, in some embodiments of the present disclosure, the semiconductor devices can be included in a multi-die device (e.g., Figure 2 the multi-die device 200).

[0060] Bonding pads 715 to 717 can be included in the pad formation regions of the respective semiconductor devices 720(2) to 720(6). The corresponding bonding pads of each semiconductor device are coupled together by conductors 725. For example, the bonding pads 715(2) to 715(6) of semiconductor devices 720(2) to 720(6) are coupled together by conductors 725(3)A to 725(6)A; the bonding pads 716(2) to 716(6) of semiconductor devices 720(2) to 720(6) are coupled together by conductors 725(3)B to 725(6)B; and the bonding pads 717(2) to 717(6) of semiconductor devices 720(2) to 720(6) are coupled together by conductors 725(3)C to 725(6)C. Although only three bonding pads 715 to 717 are shown for each semiconductor device 720, additional bonding pads can be included without departing from the scope of the present disclosure.

[0061] The corresponding conductors 710A to 710C are coupled to the bonding pads 715(4) to 717(4) of the intermediate semiconductor device 720(4). Each of the conductors 710A to 710C can be coupled to a circuit such as a substrate and / or a conductive signal line. The signals provided on the corresponding conductors 710 can be provided to each of the semiconductor devices through the conductors 725 coupled to the corresponding bonding pads 715 to 717. By having a coupling point at the intermediate semiconductor device and propagating the signals away from the coupling point to the semiconductor devices through the conductors in two different (e.g., opposite) signal paths, the signal timing of the signals can be made more balanced. For example, the signal timing of the signal arriving at the semiconductor device 720(2) and the signal arriving at the semiconductor device 720(6) can be approximately equal because the propagation delay through the conductor 725 should be approximately equal to the propagation delay from the coupling point at the bonding pads 715(4) to 717(4) of the semiconductor device 720(4) to the corresponding bonding pads 715(2) to 717(2) of the semiconductor device 720(2), and approximately equal to the propagation delay from the coupling point at the bonding pads 715(4) to 717(4) to the corresponding bonding pads 715(6) to 717(6) of the semiconductor device 720(6).

[0062] Figure 8 is a flowchart of a semiconductor device that provides signals to a stack of semiconductor devices according to an embodiment of the present disclosure. In some embodiments of the present disclosure, the semiconductor device can be included in a Figure 5 stack of semiconductor devices and / or Figure 6 coupled semiconductor devices. In some embodiments of the present disclosure, the stack of semiconductor devices for a Figure 8 method can include bonding pads coupled together as described with reference to Figure 7 . The semiconductor device is a memory device, such as a DRAM device in some embodiments of the present disclosure. For ease of description, the method 800 of the flowchart will be described with reference to the stack 515 of the semiconductor device 520 of Figure 5 . However, Figure 8 the method 800 is not necessarily limited thereto. Figure 8

[0063] Figure 5 At step 801, a signal is provided to an intermediate semiconductor device of a stack of semiconductor devices. The intermediate semiconductor device can be between a first semiconductor device and a second semiconductor device. For example, referring to Figure 5Stack 515 of semiconductor device 520, semiconductor device 520(4) can be the middle semiconductor device between semiconductor devices 520(3) and 520(5). The signal can be, for example, a signal provided by a circuit (such as circuit 535) external to the stack. As previously described, circuit 535 and stack 515 can be attached to a substrate including conductive signal lines. The signal can be provided to semiconductor device 520(4) through the conductive signal lines and through source conductor 510 that is coupled to the conductive signal lines and to the bonding pads of semiconductor device 520(4).

[0064] At step 803, a signal is provided away from the middle semiconductor device to a first semiconductor device on a first signal path. For example, referring again to Figure 5 Stack 515 of semiconductor device 520, semiconductor device 520(3) can be the first semiconductor device and the first signal path can be conductor 525(3). Conductor 525(3) can be coupled to the bonding pads of semiconductor device 520(4) and to the bonding pads of semiconductor device 520(3). The signal provided to semiconductor device 520(4) (e.g., to the bonding pads of semiconductor device 520(4)) can be provided away from semiconductor device 520(4) on conductor 525(3) to semiconductor device 520(3).

[0065] At step 805, a signal is also provided away from the middle semiconductor device to a second semiconductor device on a second signal path. For example, referring again to Figure 5 Stack 515 of semiconductor device 520, semiconductor device 520(5) can be the second semiconductor device and the second signal path can be conductor 525(5). Conductor 525(5) can be coupled to the bonding pads of semiconductor device 520(4) and to the bonding pads of semiconductor device 520(5). The signal provided to semiconductor device 520(4) can be provided away from semiconductor device 520(4) on conductor 525(5) to semiconductor device 520(5). In some embodiments of the present disclosure, the second signal path (e.g., conductor 525(5)) and the first signal path (e.g., conductor 525(3)) can be opposite signal paths to provide signals away from the middle semiconductor device (e.g., semiconductor device 520(4)).

[0066] The signal paths (e.g., conductors 525(3) and 525(5)) include an inherent propagation delay in timing that can affect the time it takes for a signal to reach the corresponding semiconductor device. As previously described, providing a signal to an intermediate one of the semiconductor devices (e.g., intermediate semiconductor device 520(4)) and providing the signal away from the intermediate semiconductor device to the first and second semiconductor devices on the corresponding signal paths (e.g., semiconductor device 520(3) on conductor 525(3) and semiconductor device 520(5) on conductor 525(5)) can provide a more balanced topology. Thus, the timing difference in the time it takes for a signal to reach the first and second semiconductor devices can be reduced. For example, in some embodiments of the present disclosure, due to the coupling through the intermediate semiconductor device, the propagation delay of a signal through the first signal path to the first semiconductor device can be equal to the propagation delay of the signal through the second signal path to the second semiconductor device.

[0067] Certain details have been described to provide a sufficient understanding of the examples of the present disclosure. However, it will be apparent to those skilled in the art that the examples of the present disclosure may be practiced without these specific details. In addition, the specific examples of the present disclosure described herein should not be construed as limiting the scope of the present disclosure to these specific examples. In other instances, well-known circuits, control signals, timing protocols, and software operations have not been shown in detail to avoid unnecessarily obscuring the present disclosure. Additionally, terms such as "couples" and "coupled" mean that two components may be directly or indirectly electrically coupled. Indirect coupling may imply that two components are coupled through one or more intermediate components.

[0068] From the foregoing, it will be appreciated that although specific embodiments of the present disclosure have been described herein for purposes of illustration, various modifications may be made without departing from the spirit and scope of the present disclosure. Accordingly, the scope of the present disclosure should not be limited to any specific embodiment described herein.

Claims

1. A method, comprising: Providing a signal to an intermediate semiconductor device of a semiconductor device stack, the intermediate semiconductor device being disposed between a first semiconductor device and a second semiconductor device also included in the semiconductor device stack; Propagating the signal away from the intermediate semiconductor device to the first semiconductor device through a first signal path coupled to the intermediate semiconductor device and the first semiconductor device; And Propagating the signal away from the intermediate semiconductor device to the second semiconductor device through a second signal path coupled to the intermediate semiconductor device and the second semiconductor device.

2. The method according to claim 1, wherein providing the signal to the intermediate semiconductor device includes providing the signal to a bonding pad of the intermediate semiconductor device, and wherein the first signal path and the second signal path are coupled to the bonding pad of the intermediate semiconductor device.

3. The method according to claim 1, wherein propagating the signal away from the intermediate semiconductor device on the first and second signal paths includes propagating the signal away from the intermediate semiconductor device on opposite signal paths.

4. The method according to claim 1, wherein providing the signal to the intermediate semiconductor device includes providing the signal from a circuit coupled to the intermediate semiconductor device through a conductive signal line of a substrate and a source conductor coupled to the conductive signal line and the intermediate semiconductor device.

5. The method according to claim 1, wherein the first semiconductor device is limited to receiving the signal via the first signal path coupled to the intermediate semiconductor device and the first semiconductor device, and wherein the second semiconductor device is limited to receiving the signal via the second signal path coupled to the intermediate semiconductor device and the second semiconductor device.

6. The method according to claim 1, wherein the intermediate semiconductor device includes a central semiconductor device of the semiconductor device stack.

7. The method according to claim 1, wherein the signal propagates to the first semiconductor device in a first signal timing, and wherein the signal propagates to the second semiconductor device in a second signal timing equal to the first signal timing.

8. The method according to claim 1, wherein the semiconductor device stack includes an even number of semiconductor devices.

9. The method according to claim 1, wherein the semiconductor device stack includes an odd number of semiconductor devices.

10. The method according to claim 1, wherein a first propagation delay of the signal to the first semiconductor device is equal to a second propagation delay of the signal to the second semiconductor device.

11. A method, comprising: Providing a signal to a second memory device of a plurality of memory devices, wherein the second memory device is disposed between a first memory device and a third memory device of the plurality of memory devices; Propagating the signal from the second memory device to the first memory device through a first signal path, wherein the first memory device is limited to receiving the signal via the first signal path; And Propagate the signal from the second memory device to the third memory device via a second signal path, wherein the third memory device is limited to receiving the signal via the second signal path.

12. The method of claim 11, wherein the plurality of memory devices includes a memory device stack.

13. The method of claim 11, wherein the plurality of memory devices includes a lowest memory device and a highest memory device.

14. The method of claim 11, wherein the first signal path and the second signal path are opposite signal paths.

15. The method of claim 11, wherein the first signal path and the second signal path have the same propagation delay.

16. The method of claim 1, wherein providing the signal to the second memory device includes providing the signal to a bonding pad of the second memory device, and wherein the first signal path and the second signal path are coupled to the bonding pad of the second memory device.

17. The method of claim 11, wherein providing the signal to the second memory device includes providing the signal from a circuit that is coupled to the second memory device from a conductive signal line that passes through a substrate and a source conductor that is coupled to the conductive signal line and the second memory device.

18. The method of claim 12, wherein the second memory device includes an intermediate memory device of the memory device stack.

19. The method of claim 11, wherein the plurality of memory devices includes an even number of memory devices.

20. An apparatus comprising: A first memory device, a second memory device, and a third memory device, wherein the second memory device is disposed between the first memory device and the third memory device; A first conductor coupled to a first bonding pad of the first memory device and a second bonding pad of the second memory device; A second conductor coupled to the second bonding pad of the second memory device and a third bonding pad of the third memory device; And A source conductor coupled to the second bonding pad of the second memory device, wherein the source conductor is configured to provide a signal to the second bonding pad, wherein the signal propagates to the first semiconductor device through the first conductor, wherein the signal propagates to the third semiconductor device through the second conductor, wherein the first memory device is limited to receiving the signal at the first bonding pad through the second bonding pad, and the third memory device is limited to receiving the signal at the third bonding pad through the second bonding pad.

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