Semiconductor structure and forming method thereof

Abstract

The invention provides a semiconductor structure and a forming method thereof, and the semiconductor structure comprises a semiconductor substrate, and a first insulating layer, a conductive layer, a second insulating layer and a hard mask layer are sequentially formed on the surface of the semiconductor substrate. A first opening for exposing the semiconductor substrate is formed in the first insulating layer, the conductive layer, the second insulating layer and the hard mask layer; the first side wall is located on a part of the side wall of the first opening and covers the hard mask layer, the second insulating layer and a part of the conductive layer on the side wall of the first opening; the collector electrode is located at the bottom of the first opening, and the top surface is not higher than the top surface of the first insulating layer; the base electrode is located on the surface of the collector electrode, and the top surface is not lower than the bottom surface of the first side wall; and the emitting electrode is located on the surface of the base electrode and fills the first opening. The invention provides a semiconductor structure and a forming method thereof, which can ensure enough contact area between a base and an outer base region, prevent short circuit between an emitter and the outer base region and improve the reliability of a device.

Description

Technical Field

[0001] This application relates to the field of semiconductor technology, and in particular, to a semiconductor structure and a method for forming the same. Background Art

[0002] An HBT (heterojunction bipolar transistor) is a heterogenous triode, which is often applied to the radio frequency field. The continuous improvement of its operating speed is mainly achieved by innovating the device structure to reduce parasitic resistance and capacitance. Currently, most of the most advanced technical solutions of germanium-silicon HBTs in the world are based on the selective epitaxy dual-poly self-aligned DPSA-SEG solution. In this solution, the connection between the device base region and the outer base region initially adopts a vertical contact solution. Subsequently, a side contact structure was proposed, which relies on the epitaxial growth on the side of the outer base region to form the connection between the inner and outer base regions. Compared with the earlier vertical contact solution, the side contact solution can reduce the parasitic capacitance between the base region and the collector and improve the device performance.

[0003] However, the current side contact solution is prone to problems such as short circuit between the emitter and the outer base region or too small contact area between the base and the outer base region. Therefore, it is necessary to provide a more effective and reliable technical solution to improve device reliability. Summary of the Invention

[0004] This application provides a semiconductor structure and a method for forming the same, which can improve device reliability.

[0005] One aspect of this application provides a method for forming a semiconductor structure, including: providing a semiconductor substrate, on which a first insulating layer, a conductive layer, a second insulating layer, and a hard mask layer are sequentially formed; forming a first opening that penetrates the hard mask layer, the second insulating layer, and extends into the conductive layer; forming a first sidewall on the sidewall of the first opening; etching the conductive layer at the bottom of the first opening until the first insulating layer is exposed; forming a second sidewall on the sidewall of the first opening, and etching the first insulating layer at the bottom of the first opening until the semiconductor substrate is exposed; forming a collector in the first opening with a top surface not higher than the top surface of the first insulating layer; removing the second sidewall; forming a base on the surface of the collector with a top surface not lower than the bottom surface of the first sidewall; and forming an emitter on the surface of the base to fill the first opening.

[0006] In some embodiments of the present application, a method for forming a second sidewall on the sidewall of the first opening and etching the first insulating layer at the bottom of the first opening to expose the semiconductor substrate includes: forming a second sidewall material layer on the bottom and sidewalls of the first opening and on the surface of the hard mask layer; performing a first etching process to remove the second sidewall material layer on the bottom of the first opening and on the surface of the hard mask layer and etching the first insulating layer at the bottom of the first opening into the first insulating layer, leaving the second sidewall material layer on the sidewall of the first opening as the second sidewall; performing a second etching process to continue etching the first insulating layer at the bottom of the first opening to expose the semiconductor substrate and etching and thinning the second sidewall.

[0007] In some embodiments of the present application, the material of the first sidewall includes silicon nitride, the material of the second sidewall includes silicon oxide, and the material of the first insulating layer includes silicon oxide.

[0008] In some embodiments of the present application, the first etching process is a dry etching process, and the second etching process is a wet etching process.

[0009] In some embodiments of the present application, after thinning the second sidewall, the thickness of the first sidewall is the same as the thickness of the second sidewall.

[0010] In some embodiments of the present application, the top surface of the collector is flush with the top surface of the first insulating layer.

[0011] In some embodiments of the present application, the top surface of the base is flush with the bottom surface of the first sidewall.

[0012] Another aspect of the present application further provides a semiconductor structure formed by a method for forming a semiconductor structure as described above, including: a semiconductor substrate, on which a first insulating layer, a conductive layer, a second insulating layer, and a hard mask layer are sequentially formed, and a first opening exposing the semiconductor substrate is formed in the first insulating layer, the conductive layer, the second insulating layer, and the hard mask layer; a first sidewall located on a part of the sidewall of the first opening covering the hard mask layer, the second insulating layer, and a part of the conductive layer on the sidewall of the first opening; a collector located at the bottom of the first opening and having a top surface not higher than the top surface of the first insulating layer; a base located on the surface of the collector and having a top surface not lower than the bottom surface of the first sidewall; and an emitter located on the surface of the base and filling the first opening.

[0013] In some embodiments of the present application, the top surface of the collector is flush with the top surface of the first insulating layer.

[0014] In some embodiments of the present application, the top surface of the base is flush with the bottom surface of the first sidewall.

[0015] The present application provides a semiconductor structure and a method for forming the same, which can ensure sufficient contact area between the base and the outer base region and prevent short - circuit between the emitter and the outer base region, and can improve the device reliability. BRIEF DESCRIPTION OF THE DRAWINGS

[0016] The following drawings detail exemplary embodiments disclosed in the present application. Wherein the same reference numerals represent similar structures in several views of the drawings. Those of ordinary skill in the art will understand that these embodiments are non - restrictive, exemplary embodiments, and the drawings are only for the purpose of illustration and description, and are not intended to limit the scope of the present application. Embodiments in other ways may also achieve the inventive concept in the present application. It should be understood that the drawings are not drawn to scale.

[0017] Wherein:

[0018] Figures 1 to 10 are schematic structural diagrams of each step in the method for forming the semiconductor structure according to the embodiment of the present application. DETAILED DESCRIPTION OF THE EMBODIMENTS

[0019] The following description provides specific application scenarios and requirements of the present application, aiming to enable those skilled in the art to manufacture and use the content of the present application. For those skilled in the art, various local modifications to the disclosed embodiments are obvious, and without departing from the spirit and scope of the present application, the general principles defined here can be applied to other embodiments and applications. Therefore, the present application is not limited to the disclosed embodiments, but to the broadest scope consistent with the claims.

[0020] The technical solution of the present invention will be described in detail below with reference to the embodiments and the drawings.

[0021] Figures 1 to 10 are schematic structural diagrams of each step in the method for forming the semiconductor structure according to the embodiment of the present application. The method for forming the semiconductor structure according to the embodiment of the present application will be described in detail below with reference to the drawings.

[0022] Referring to Figure 1 as shown, a semiconductor substrate 100 is provided, and a first insulating layer 110, a conductive layer 120, a second insulating layer 130, and a hard mask layer 140 are sequentially formed on the surface of the semiconductor substrate 100.

[0023] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide, etc.; or (iv) a combination of the above.

[0024] In some embodiments of the present application, a well region 101 and isolation structures 102 located on both sides of the well region 101 are further formed in the semiconductor substrate 100. The well region 101 is formed by an ion implantation process. The material of the isolation structures 102 includes insulating materials such as silicon oxide.

[0025] In some embodiments of the present application, the material of the first insulating layer 110 includes insulating materials such as silicon oxide. The thickness of the first insulating layer 110 is 100 to 200 nanometers, such as 110 nanometers, 120 nanometers, 140 nanometers, 160 nanometers, or 180 nanometers, etc. The first insulating layer 110 is used for insulating and isolating the semiconductor substrate 100 and the conductive layer 120.

[0026] In some embodiments of the present application, the material of the conductive layer 120 is a conductive material such as polysilicon. The thickness of the conductive layer 120 is 50 to 100 nanometers, such as 60 nanometers, 70 nanometers, 80 nanometers, or 90 nanometers, etc.

[0027] In some embodiments of the present application, the material of the second insulating layer 130 includes insulating materials such as silicon oxide. The thickness of the second insulating layer 130 is 10 to 30 nanometers, such as 15 nanometers, 20 nanometers, or 25 nanometers, etc. The second insulating layer 130 is used for insulating and isolating the conductive layer 120.

[0028] In some embodiments of the present application, the material of the hard mask layer 140 includes silicon nitride. The thickness of the hard mask layer 140 is 50 to 100 nanometers, such as 60 nanometers, 70 nanometers, 80 nanometers, or 90 nanometers, etc. On the one hand, the hard mask layer 140 and the second insulating layer 130 together play a role in insulating and isolating the conductive layer 120. On the other hand, the hard mask layer 140 plays a role as a mask in subsequent etching processes.

[0029] Reference Figure 2 As shown, a first opening 150 is formed through the hard mask layer 140, the second insulating layer 130 and extending into the conductive layer 120, and a first sidewall 151 is formed on the sidewall of the first opening 150. The first opening 150 does not penetrate through the conductive layer 120, and the bottom of the first opening 150 stops in the conductive layer 150. The first opening 150 is located above the well region 101.

[0030] In some embodiments of the present application, the method for forming the first opening 150 is dry etching, and the etching depth can be controlled by controlling the etching time.

[0031] In some embodiments of the present application, the thickness of the remaining conductive layer 120 at the bottom of the first opening 150 is about half of that of the conductive layer 120 at other positions, for example, 40 to 60 nanometers, such as 45 nanometers, 50 nanometers, or 55 nanometers, etc.

[0032] In some embodiments of the present application, the thickness of the first sidewall 151 is 10 to 30 nanometers, such as 15 nanometers, 20 nanometers, or 25 nanometers, etc. The material of the first sidewall 151 is, for example, silicon nitride.

[0033] Reference Figure 3 As shown, etch the conductive layer 120 at the bottom of the first opening 150 until the first insulating layer 110 is exposed.

[0034] Reference Figures 4 to 6 As shown, form a second sidewall 152 on the sidewall of the first opening 150, and etch the first insulating layer 110 at the bottom of the first opening 150 until the semiconductor substrate 100 is exposed.

[0035] Reference Figure 4 As shown, form a second sidewall material layer 152a on the bottom and sidewall of the first opening 150 and on the surface of the hard mask layer 140. The thickness of the second sidewall material layer 152a is 30 to 50 nanometers, such as 35 nanometers, 40 nanometers, or 45 nanometers, etc.

[0036] Reference Figure 5 As shown, perform a first etching process to remove the second sidewall material layer 152a on the bottom of the first opening 150 and on the surface of the hard mask layer 140, and etch the first insulating layer 110 at the bottom of the first opening 150 into the first insulating layer 110. The remaining second sidewall material layer 152a on the sidewall of the first opening 150 becomes the second sidewall 152. The thickness of the remaining first insulating layer 110 at the bottom of the first opening 150 is 10% to 50% of the thickness of the second sidewall 152, about 10 to 30 nanometers, such as 15 nanometers, 20 nanometers, or 25 nanometers, etc.

[0037] Reference Figure 6 As shown, perform a second etching process to continue etching the first insulating layer 110 at the bottom of the first opening 150 until the semiconductor substrate 100 is exposed, and etch and thin the second sidewall 152.

[0038] In some embodiments of the present application, the first etching process is a dry etching process, and the second etching process is a wet etching process.

[0039] In some embodiments of the present application, the material of the first sidewall 151 includes silicon nitride, the material of the second sidewall 152 includes silicon oxide, and the material of the first insulating layer 110 includes silicon oxide. Using such materials can ensure that other film layers will not be damaged by excessive etching during each etching process.

[0040] In some embodiments of the present application, after thinning the second sidewall 152, the thickness of the first sidewall 151 is the same as the thickness of the second sidewall 152.

[0041] Reference Figure 7 As shown, a collector 160 is formed in the first opening 150 with a top surface not higher than the top surface of the first insulating layer 110. Specifically, the collector 160 is formed in the first opening 150 by an epitaxial growth process using the semiconductor substrate 100 as a matrix.

[0042] In some embodiments of the present application, the top surface of the collector 160 is flush with the top surface of the first insulating layer 110. The material of the collector 160 is, for example, silicon.

[0043] Reference Figure 8 As shown, the second sidewall 152 is removed. The method for removing the second sidewall 152 is, for example, wet etching.

[0044] Reference Figure 9 As shown, a base 170 is formed on the surface of the collector 160 with a top surface not lower than the bottom surface of the first sidewall 151. The base 170 is electrically connected to the conductive layer 120. The base 170 is also referred to as the inner base region and corresponds to the outer base region represented by the conductive layer 120.

[0045] In some embodiments of the present application, the top surface of the base 170 is flush with the bottom surface of the first sidewall 151.

[0046] In some embodiments of the present application, the method for forming the base 170 is, for example: growth is carried out using the collector 160 as a matrix by a selective epitaxial growth process. The material of the base 170 is, for example, silicon germanium.

[0047] Reference Figure 10 As shown, an emitter 180 is formed on the surface of the base 170 to fill the first opening 150 and extend to the surface of the hard mask layer 140.

[0048] In some embodiments of the present application, the material of the emitter 180 is, for example, polysilicon. The method for forming the emitter 180 includes chemical vapor deposition process, physical vapor deposition process, etc.

[0049] In the technical solution of the present application, the first sidewall 151 is raised to expose the conductive layer 120 with a set size, which can avoid the short circuit between the conductive layer 120 and the emitter 180 or the collector 160 while ensuring that the contact area between the conductive layer 120 and the base 170 is sufficient.

[0050] In the technical solution of the present application, the height by which the first sidewall 151 is raised is consistent with the remaining thickness of the conductive layer 120 after being etched initially. Dry etching is more precise in controlling the etching amount compared to wet etching, so that the product yield can be improved and the device performance can be ensured to be stable.

[0051] The present application provides a method for forming a semiconductor structure. The semiconductor structure is specifically, for example, an HBT (heterojunction bipolar transistor), in which the base and the external base region are in a side contact structure. The technical solution of the present application can ensure a sufficient contact area between the base and the external base region and prevent short circuit between the emitter and the external base region, and can improve the device reliability.

[0052] The present application also provides a semiconductor structure formed by the method for forming a semiconductor structure as described above. Referring to Figure 10 as shown, it includes: a semiconductor substrate 100, on the surface of the semiconductor substrate 100, a first insulating layer 110, a conductive layer 120, a second insulating layer 130, and a hard mask layer 140 are sequentially formed. A first opening 150 exposing the semiconductor substrate 100 is formed in the first insulating layer 110, the conductive layer 120, the second insulating layer 130, and the hard mask layer 140; a first sidewall 151, covering the hard mask layer 140, the second insulating layer 130, and a part of the conductive layer 120 on the sidewalls of the part of the first opening 150; a collector 160, located at the bottom of the first opening 150 and the top surface not being higher than the top surface of the first insulating layer 110; a base 170, located on the surface of the collector 160 and the top surface not being lower than the bottom surface of the first sidewall 151; an emitter 180, located on the surface of the base 170 and filling the first opening 150.

[0053] In some embodiments of the present application, the material of the semiconductor substrate 100 includes (i) elemental semiconductors, such as silicon or germanium, etc.; (ii) compound semiconductors, such as silicon carbide, gallium arsenide, gallium phosphide, or indium phosphide, etc.; (iii) alloy semiconductors, such as silicon germanium carbide, silicon germanium, gallium phosphide arsenide, or gallium indium phosphide, etc.; or (iv) a combination of the above.

[0054] In some embodiments of the present application, a well region 101 and isolation structures 102 located on both sides of the well region 101 are further formed in the semiconductor substrate 100. The well region 101 is formed by an ion implantation process. The material of the isolation structures 102 includes insulating materials such as silicon oxide.

[0055] In some embodiments of the present application, the material of the first insulating layer 110 includes insulating materials such as silicon oxide. The thickness of the first insulating layer 110 is 100 to 200 nanometers, such as 110 nanometers, 120 nanometers, 140 nanometers, 160 nanometers, or 180 nanometers, etc. The first insulating layer 110 is used to insulate and isolate the semiconductor substrate 100 and the conductive layer 120.

[0056] In some embodiments of the present application, the material of the conductive layer 120 is a conductive material such as polysilicon. The thickness of the conductive layer 120 is 50 to 100 nanometers, such as 60 nanometers, 70 nanometers, 80 nanometers, or 90 nanometers, etc.

[0057] In some embodiments of the present application, the material of the second insulating layer 130 includes insulating materials such as silicon oxide. The thickness of the second insulating layer 130 is 10 to 30 nanometers, such as 15 nanometers, 20 nanometers, or 25 nanometers, etc. The second insulating layer 130 is used to insulate and isolate the conductive layer 120.

[0058] In some embodiments of the present application, the material of the hard mask layer 140 includes silicon nitride. The thickness of the hard mask layer 140 is 50 to 100 nanometers, such as 60 nanometers, 70 nanometers, 80 nanometers, or 90 nanometers, etc. On the one hand, the hard mask layer 140 and the second insulating layer 130 together play a role in insulating and isolating the conductive layer 120. On the other hand, the hard mask layer 140 plays a role as a mask in subsequent etching processes.

[0059] In some embodiments of the present application, the thickness of the first sidewall 151 is 10 to 30 nanometers, such as 15 nanometers, 20 nanometers, or 25 nanometers, etc. The material of the first sidewall 151 is, for example, silicon nitride.

[0060] In some embodiments of the present application, the material of the first sidewall 151 includes silicon nitride, and the material of the first insulating layer 110 includes silicon oxide.

[0061] In some embodiments of the present application, the top surface of the collector 160 is flush with the top surface of the first insulating layer 110. The material of the collector 160 is, for example, silicon.

[0062] The base 170 is electrically connected to the conductive layer 120. The base 170 is also referred to as the inner base region, corresponding to the outer base region represented by the conductive layer 120.

[0063] In some embodiments of the present application, the top surface of the base 170 is flush with the bottom surface of the first sidewall 151.

[0064] In some embodiments of the present application, an emitter 180 is formed on the surface of the base 170, filling the first opening 150 and extending to the surface of the hard mask layer 140.

[0065] In some embodiments of the present application, the material of the emitter 180 is, for example, polysilicon.

[0066] In the technical solution of the present application, the first sidewall 151 is lifted, exposing a conductive layer 120 with a set size, which can avoid short-circuit contact between the conductive layer 120 and the emitter 180 or the collector 160 while ensuring that the contact area between the conductive layer 120 and the base 170 is sufficient.

[0067] In the technical solution of the present application, the height by which the first sidewall 151 is lifted is consistent with the remaining thickness of the conductive layer 120 after being etched initially. Dry etching is more precise in controlling the etching amount compared to wet etching, which can improve the product yield and ensure stable device performance.

[0068] The present application provides a semiconductor structure and a method for forming the same. The semiconductor structure is specifically, for example, an HBT (heterojunction bipolar transistor), in which the base and the external base region have a side contact structure. The technical solution of the present application can ensure a sufficient contact area between the base and the external base region and prevent short-circuit between the emitter and the external base region, and can improve device reliability.

[0069] In summary, after reading the content of the present application, those skilled in the art can understand that the foregoing application content may be presented only by way of example and may not be restrictive. Although not explicitly stated herein, those skilled in the art can understand that the present application is intended to encompass various reasonable changes, improvements, and modifications to the embodiments. These changes, improvements, and modifications are within the spirit and scope of the exemplary embodiments of the present application.

[0070] It should be understood that the term "and / or" used in this embodiment includes any or all combinations of one or more of the associated listed items. It should be understood that when an element is referred to as being "connected" or "coupled" to another element, it can be directly connected or coupled to the other element, or there may also be an intermediate element.

[0071] Similarly, it should be understood that when an element such as a layer, region, or substrate is referred to as being "on" another element, it can be directly on the other element, or there may also be an intermediate element. In contrast, the term "directly" means without an intermediate element. It should also be understood that the terms "comprise", "comprising", "include" or "including", when used in this application document, specify the presence of the recited features, wholes, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, wholes, steps, operations, elements, components, and / or their groups.

[0072] It should also be understood that although the terms first, second, third, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the teachings of the present application, a first element in some embodiments may be referred to as a second element in other embodiments. The same reference numerals or the same reference identifiers represent the same elements throughout the specification.

[0073] In addition, the present application specification describes exemplary embodiments by referring to idealized exemplary cross-sectional views and / or plan views and / or three-dimensional views. Therefore, differences from the illustrated shapes due to, for example, manufacturing techniques and / or tolerances are foreseeable. Thus, the exemplary embodiments should not be construed as limited to the shapes of the regions shown herein, but should include deviations in the shapes caused by, for example, manufacturing. For example, an etched region shown as rectangular will typically have rounded or curved features. Therefore, the regions shown in the figures are substantially schematic, and their shapes are not intended to show the actual shape of the regions of the device nor to limit the scope of the exemplary embodiments.

Claims

1. A method for forming a semiconductor structure, characterized in that, Comprising: Providing a semiconductor substrate, on the surface of which a first insulating layer, a conductive layer, a second insulating layer, and a hard mask layer are sequentially formed; Forming a first opening that penetrates the hard mask layer, the second insulating layer, and extends into the conductive layer; Forming a first sidewall on the sidewall of the first opening; Etching the conductive layer at the bottom of the first opening until the first insulating layer is exposed; Forming a second sidewall on the sidewall of the first opening, and etching the first insulating layer at the bottom of the first opening until the semiconductor substrate is exposed; Forming a collector in the first opening with a top surface not higher than the top surface of the first insulating layer; Removing the second sidewall; Forming a base on the surface of the collector with a top surface not lower than the bottom surface of the first sidewall; Forming an emitter on the surface of the base to fill the first opening.

2. The method for forming a semiconductor structure according to claim 1, wherein, The method of forming a second sidewall on the sidewall of the first opening and etching the first insulating layer at the bottom of the first opening until the semiconductor substrate is exposed includes: Forming a second sidewall material layer on the bottom and sidewall of the first opening and the surface of the hard mask layer; Performing a first etching process to remove the second sidewall material layer on the bottom and surface of the hard mask layer of the first opening and etching the first insulating layer at the bottom of the first opening into the first insulating layer, with the remaining second sidewall material layer on the sidewall of the first opening becoming the second sidewall; Performing a second etching process to continue etching the first insulating layer at the bottom of the first opening until the semiconductor substrate is exposed, and etching and thinning the second sidewall.

3. The method for forming a semiconductor structure according to claim 2, wherein, The material of the first sidewall includes silicon nitride, the material of the second sidewall includes silicon oxide, and the material of the first insulating layer includes silicon oxide.

4. The method for forming a semiconductor structure according to claim 2, wherein, The first etching process is a dry etching process, and the second etching process is a wet etching process.

5. The method for forming a semiconductor structure according to claim 2, wherein, After thinning the second sidewall, the thickness of the first sidewall is the same as the thickness of the second sidewall.

6. The method for forming a semiconductor structure according to claim 1, wherein, The top surface of the collector is flush with the top surface of the first insulating layer.

7. The method for forming a semiconductor structure according to claim 1, wherein The top surface of the base is flush with the bottom surface of the first sidewall.

8. A semiconductor structure formed by a method for forming a semiconductor structure according to any one of claims 1-7, characterized in that, Comprising: A semiconductor substrate, on the surface of which a first insulating layer, a conductive layer, a second insulating layer, and a hard mask layer are sequentially formed, and a first opening exposing the semiconductor substrate is formed in the first insulating layer, the conductive layer, the second insulating layer, and the hard mask layer; A first sidewall, located on a part of the sidewall of the first opening, covering the hard mask layer, the second insulating layer, and a part of the conductive layer on the sidewall of the first opening; A collector, located at the bottom of the first opening with a top surface not higher than the top surface of the first insulating layer; A base, located on the surface of the collector with a top surface not lower than the bottom surface of the first sidewall; An emitter, located on the surface of the base and filling the first opening.

9. The semiconductor structure according to claim 8, wherein, The top surface of the collector is flush with the top surface of the first insulating layer.

10. The semiconductor structure according to claim 8, wherein The top surface of the base is flush with the bottom surface of the first sidewall.

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