Heterogeneous interface regulated synaptic transistor and preparation method and application thereof

Abstract

The invention relates to the technical field of electronic devices, in particular to a synaptic transistor regulated and controlled by a heterogeneous interface and a preparation method and application of the synaptic transistor. The invention provides a synaptic transistor for regulating and controlling a heterogeneous interface. The synaptic transistor structurally comprises a substrate, an active layer, a side gate dielectric layer, a source electrode, a drain electrode and a side gate which are sequentially stacked, wherein the source electrode and the drain electrode are arranged on the two sides of the side gate dielectric layer. Wherein the substrate is composed of a doped n-type Si layer and SiO2 with H < + > adsorbed on the surface, the side gate dielectric layer is [PVDF-HFP] [EMIM-TFSI] ionic glue, and the active layer is an indium tin zinc oxide film. The structures in the synaptic transistor are mutually coordinated, so that the synaptic transistor has the capability of simulating transmission of different neurotransmitters; meanwhile, the transistor can also realize autonomous switching between long-range synaptic plasticity and short-range synaptic plasticity by adjusting side synaptic peak intensity, so that complex and diversified functional characteristics of biological synapses can be simulated more comprehensively.

Description

Technical Field

[0001] The present invention belongs to the technical field of electronic devices. More specifically, it relates to a synaptic transistor with heterogeneous interface regulation, its preparation method and application. Background Art

[0002] In the construction of artificial neural networks and neuromorphic computing systems, artificial synaptic transistor devices play an important role. They simulate the functions of synapses in the biological brain and show significant advantages compared with the traditional von Neumann architecture. Under the von Neumann architecture, the storage and processing units are separated, resulting in low efficiency of information processing and storage and the existence of the "von Neumann bottleneck". While synaptic transistor devices can simulate the signal transmission and information processing methods of the human brain, achieving high-efficiency parallel processing and low-power consumption operations. Synaptic transistor devices achieve precise regulation with the assistance of gate voltage by simulating the plasticity of biological synapses, avoiding unit crosstalk, and at the same time being able to perform parallel learning, making it easier to achieve advanced synaptic functions such as filtering and neuromorphic computing, providing new ideas for solving the bottleneck problems of traditional computer architectures and promoting the development of the field of neuromorphic computing.

[0003] In the real biological nervous system, the postsynaptic membrane of a biological synapse is affected by presynaptic neurotransmitters from multiple parties, and the combined effect of these complex signals is the key to information processing in the nervous system. However, currently, most are single-gate regulated synaptic transistor devices, which have obvious limitations in simulating the complexity of biological synapses: on the one hand, in terms of the complexity of signal transmission, single-gate regulated synaptic transistors only have the ability to transmit a single type (excitatory or inhibitory) of signal, making it difficult for them to simulate the complex process of different neurotransmitter transmissions in biological synapses; on the other hand, the synaptic plasticity performance of single-gate regulated synaptic transistors is limited and they cannot autonomously achieve the switching between long-range and short-range plasticity. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the defects and deficiencies that existing single-gate synaptic transistors are difficult to simulate the complex process of different neurotransmitter transmissions and cannot autonomously achieve the switching between long-range and short-range synaptic plasticity, and to provide a synaptic transistor with heterogeneous interface regulation.

[0005] Another object of the present invention is to provide a preparation method for the above-mentioned synaptic transistor with heterogeneous interface regulation.

[0006] Another object of the present invention is to provide the application of the above-mentioned synaptic transistor with heterogeneous interface regulation in the preparation of bionic sensing devices, neuromorphic memories or brain-like computing chips.

[0007] The above objects of the present invention are achieved by the following technical solutions:

[0008] The present invention protects a synaptic transistor with heterogeneous interface regulation, which includes a substrate, an active layer, a side gate dielectric layer, a source electrode and a drain electrode disposed on both sides of the side gate dielectric layer, and a side gate, which are stacked in sequence.

[0009] Among them, the substrate is composed of a doped n-type Si layer (serving as the main gate) and SiO2 with adsorbed H on its surface (serving as the main gate dielectric layer). +

[0010] The side gate dielectric layer is an ionic gel of [PVDF-HFP][EMIM-TFSI].

[0011] The active layer is an indium tin zinc oxide thin film (ITZO thin film).

[0012] The synaptic transistor with heterogeneous interface regulation proposed by the present invention includes a substrate, an active layer, a side gate dielectric layer, a source electrode and a drain electrode disposed on both sides of the side gate dielectric layer, and a side gate. Among them, the main gate in the substrate can effectively regulate the charge distribution on the surface of the active layer through dielectric coupling, which helps to induce the generation of the electric double layer effect. At the same time, the trace H existing in the main gate dielectric layer in the substrate lays the foundation for the emergence of the electric double layer effect. The side gate regulates the ion distribution and interface effect. The cation EMIM and anion TFSI rich in the ionic gel of [PVDF-HFP][EMIM-TFSI] have both high dielectric constant and ionic conductivity, which can significantly increase the carrier concentration and electron mobility in the channel. The ITZO thin film has high surface flatness, excellent interface characteristics, outstanding optoelectronic properties and high field effect mobility, providing a basis for efficient carrier transport. These structures coordinate with each other, can simulate the transmission of different neurotransmitters, and can realize the dynamic switching of long-range and short-range synaptic plasticity by changing the side synaptic spike intensity, thus realizing the complex functions of biological synapses. + , + and - anion TFSI, have both high dielectric constant and ionic conductivity, can significantly increase the carrier concentration and electron mobility in the channel. The ITZO thin film has high surface flatness, excellent interface characteristics, outstanding optoelectronic properties and high field effect mobility, providing a basis for efficient carrier transport. These structures coordinate with each other, can simulate the transmission of different neurotransmitters, and can realize the dynamic switching of long-range and short-range synaptic plasticity by changing the side synaptic spike intensity, thus realizing the complex functions of biological synapses.

[0013] This device realizes the simulation of synaptic complex functions through the coordinated regulation of the upper and lower double-layer interfaces: the regulation of the upper interface (ITZO layer / ionic gel interface) is through the strong electric double layer effect and ion doping effect formed by cations and anions in the ionic gel. When a side gate voltage is applied, the ions redistribute under the drive of the electric field, and directly regulate the transport characteristics of the charge carriers on the surface of the active layer by enhancing or reconstructing the electric double layer structure. The regulation of the lower interface (ITZO layer / SiO2 interface with adsorbed H on its surface) is through the synergistic action of dielectric coupling and the weak electric double layer effect induced by trace H. The dielectric coupling effect results from the transmission of the electric field through the SiO2 main gate dielectric layer, while the weak electric double layer effect is caused by H on the surface of SiO2. + on its surface + and + ​The electrostatic interaction between the adsorption layer and the active layer generates, and the two together achieve fine regulation of the interfacial potential. The postsynaptic current generated by the upper and lower interface regulation is output through the source and drain electrodes, and its amplitude, polarity, and time dynamic characteristics are determined by the superposition and competition of the two-channel current. By dynamically adjusting the two-channel current ratio through the side gate voltage, the complex postsynaptic response under the cooperative action of excitatory and inhibitory neurotransmitters in biological synapses is accurately simulated.

[0014] Preferably, the thickness of the substrate is 480 - 520 μm.

[0015] More preferably, the thickness of the substrate is 500 μm.

[0016] Preferably, the thickness of the main gate is 479.71 - 519.69 μm.

[0017] More preferably, the thickness of the main gate is 499.7 μm.

[0018] Preferably, the thickness of the main gate dielectric layer is 290 - 310 nm.

[0019] More preferably, the thickness of the main gate dielectric layer is 300 nm.

[0020] Preferably, the thickness of the active layer is 28 - 32 nm.

[0021] More preferably, the thickness of the active layer is 30 nm.

[0022] Furthermore, the indium tin zinc oxide thin film is prepared by magnetron sputtering deposition using indium tin oxide and zinc oxide targets as raw materials.

[0023] Even further, the magnetron sputtering method is a technique that uses energetic particles to bombard the target surface in a vacuum, causing the bombarded particles to deposit on the substrate.

[0024] Even further, the preparation method of the active layer includes the following steps:

[0025] Under Ar and O2, indium tin oxide (ITO) and zinc oxide (ZnO) targets are used to prepare an ITZO thin film by magnetron sputtering deposition, and the obtained ITZO thin film is annealed to obtain the active layer.

[0026] Preferably, the range of the Ar:O2 gas flow rate is (8 - 12):(5 - 8) sccm.

[0027] More preferably, the Ar:O2 gas flow rate is 10:6 sccm.

[0028] Furthermore, the power of the ITO target is 95 - 100 W.

[0029] Furthermore, the power of the ZnO target is 120 - 130 W.

[0030] Furthermore, the annealing temperature is 300 - 350 °C.

[0031] Preferably, the annealing time is 2 - 3 h.

[0032] Furthermore, the source electrode and the drain electrode are made of the same material; the source electrode and the drain electrode are made of gold, silver or copper.

[0033] Preferably, the source electrode and the drain electrode are made of gold.

[0034] Preferably, the thickness of the source electrode and the drain electrode is 30 - 60 nm. The source electrode and the drain electrode within this thickness range can adhere more firmly to the substrate, thereby further reducing the risk of detachment.

[0035] More preferably, the thickness of the source electrode and the drain electrode is 35 - 45 nm.

[0036] Furthermore, the preparation method of the [PVDF - HFP][EMIM - TFSI] ionic gel includes the following steps:

[0037] Mix the polyvinylidene fluoride - hexafluoropropylene copolymer (PVDF - HFP) solution and 1 - ethyl - 3 - methylimidazolium bis(trifluoromethylsulfonyl)imide (EMIM - TFSI) evenly, and after curing, obtain the [PVDF - HFP][EMIM - TFSI] ionic gel.

[0038] Preferably, the mass concentration of the polyvinylidene fluoride - hexafluoropropylene copolymer solution is 0.2 - 0.33 g / mL.

[0039] More preferably, the mass concentration of the polyvinylidene fluoride - hexafluoropropylene copolymer solution is 0.25 - 0.3 g / mL.

[0040] Furthermore, the specific preparation method of the polyvinylidene fluoride - hexafluoropropylene copolymer solution includes the following steps:

[0041] Fully dissolve the polyvinylidene fluoride - hexafluoropropylene copolymer in an organic solvent to obtain a viscous PVDF - HFP solution.

[0042] Furthermore, the organic solvent includes one or more of acetone, N - methylpyrrolidone, and dimethylformamide.

[0043] Preferably, the dissolution temperature is 40 - 80 °C.

[0044] Preferably, the dissolution time is 1 - 3 h.

[0045] Furthermore, the mass-volume ratio of the polyvinylidene fluoride-hexafluoropropylene copolymer (PVDF-HFP) to 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide (EMIM-TFSI) is 1:(0.5 - 4) g / mL.

[0046] Still further, the mass-volume ratio of the PVDF-HFP to the EMIM-TFSI is 1:(1 - 3) g / mL.

[0047] Preferably, the mass-volume ratio of the PVDF-HFP to the EMIM-TFSI is 1:2 g / mL. Under this ratio condition, the synergistic effect of the PVDF-HFP and the EMIM-TFSI is better, further improving the performance of the material.

[0048] Preferably, the temperature of the mixing is 40 - 80 °C.

[0049] Preferably, the time of the mixing is 6 - 24 h.

[0050] Furthermore, as a preferred method, the curing is carried out using a mold.

[0051] Specifically, the curing is to uniformly pour the obtained uniformly mixed solution into a mold and dry and cure it at 80 - 85 °C.

[0052] Preferably, the time of the drying is 1 - 5 h.

[0053] Furthermore, the thickness of the side gate dielectric layer is 5 - 20 μm. The side gate dielectric layer within this thickness range exhibits better ionic conductivity, can effectively reduce the leakage current, and thus further improve the reliability and overall performance of the device.

[0054] Preferably, the thickness of the side gate dielectric layer is 8 - 15 μm.

[0055] More preferably, the thickness of the side gate dielectric layer is 10 μm.

[0056] Preferably, the side gate electrode is gold or silver.

[0057] More preferably, the side gate electrode is silver. Compared with gold (Au), the raw material cost of silver is lower, which can significantly reduce the manufacturing cost of the device and thus improve the technical economy.

[0058] Furthermore, the thickness of the side gate electrode is 50 - 70 nm.

[0059] Preferably, the thickness of the side gate electrode is 55 - 65 nm.

[0060] More preferably, the thickness of the side gate electrode is 60 nm.

[0061] The present invention protects a method for preparing the above-mentioned synaptic transistor with heterogeneous interface regulation, comprising the following steps:

[0062] S1. Prepare an indium tin zinc oxide thin film on a substrate as an active layer;

[0063] S2. Align a mask on the surface of the active layer obtained in step S1, and evaporate source and drain electrodes on both sides of the surface of the active layer;

[0064] S3. Prepare [PVDF-HFP][EMIM-TFSI] ionic gel as a side gate dielectric layer, align a mask on the surface of the [PVDF-HFP][EMIM-TFSI] ionic gel, and evaporate a side gate on the surface of the [PVDF-HFP][EMIM-TFSI] ionic gel;

[0065] S4. Remove the mask in step S2, and attach the [PVDF-HFP][EMIM-TFSI] ionic gel covered with the side gate in step S3 to the channel region formed between the source electrode and the drain electrode. The resulting device is a synaptic transistor with heterogeneous interface regulation.

[0066] Preferably, in steps S2 and S3, the evaporation rate of the evaporation

[0067] The present invention protects the application of the above-mentioned synaptic transistor with heterogeneous interface regulation in preparing bionic sensing devices, neuromorphic memories or brain-like computing chips.

[0068] Compared with the prior art, the present invention has the following beneficial effects:

[0069] The present invention provides a synaptic transistor with heterogeneous interface regulation, the structure of which includes a substrate, an active layer, a side gate dielectric layer, a source electrode and a drain electrode arranged on both sides of the side gate dielectric layer, and a side gate, which are stacked in sequence. Among them, the substrate is composed of a doped n-type Si layer and SiO2 with H adsorbed on the surface + on the surface, the side gate dielectric layer is [PVDF-HFP][EMIM-TFSI] ionic gel, and the active layer is an indium tin zinc oxide thin film. The various structures in this synaptic transistor coordinate with each other, enabling it to have the ability to simulate the transmission of different neurotransmitters; at the same time, this transistor can also autonomously switch between long-term and short-term synaptic plasticity by adjusting the side synaptic spike intensity, thereby more comprehensively simulating the complex and diverse functional characteristics of biological synapses. Description of the Drawings

[0070] Figure 1 It is a schematic structural diagram of the synaptic transistor with heterogeneous interface regulation in Example 1; the schematic diagram mainly focuses on expressing the structural position relationship, rather than accurately reflecting the actual thickness of each layer.

[0071] Figure 2 The graphs (a-d) show the changes in postsynaptic current of the heterointerface-regulated synaptic transistor in Example 1 under synaptic spikes on different sides.

[0072] Figure 3 This is a graph showing changes in postsynaptic current of the heterointerface-regulated synaptic transistor in Example 1 under a pair of consecutive main synaptic spikes at different time intervals and under different side synaptic spikes.

[0073] Figure 4 The double pulse facilitation index diagrams (a-d) of the heterointerface-regulated synaptic transistor in Example 1 under different side synaptic spike intensities.

[0074] Figure 5 Graphs (a-d) of the postsynaptic current variation of the heterointerface-regulated synaptic transistor in Example 1 when a series of different numbers of pulses are simultaneously applied to the main and side synaptic spikes under different side synaptic spikes.

[0075] Figure 6 This is a spike number plasticity index diagram of the synaptic transistor regulated by the heterojunction interface in Example 1 under different side synaptic spike intensities.

[0076] Figure 7 This is a normalized weight retention curve of the heterointerface-regulated synaptic transistor in Example 1 after the spike is removed. DETAILED DESCRIPTION

[0077] The present invention is further described below in conjunction with the accompanying drawings and specific examples, but the examples do not limit the present invention in any form. Unless otherwise specified, the reagents, methods and equipment used in the present invention are conventional reagents, methods and equipment in the art.

[0078] Unless otherwise specified, the reagents and materials used in the following examples are commercially available.

[0079] Figure 2 (a) Figure 2 In Figure (a), Figure 2 (b) Figure 2 The order of the other figures is similar.

[0080] Example 1 A heterogeneous interface-regulated synaptic transistor and a method for preparing the same

[0081] 1. A synaptic transistor regulated by a heterogeneous interface, the schematic diagram of which is shown in FIG. Figure 1 As shown, the stacked substrate-doped n-type Si layer (as the main gate) and the surface adsorbed H +SiO2 thin film (as the main gate dielectric layer), active layer - ITZO thin film, side gate dielectric layer - [PVDF - HFP][EMIM - TFSI] ionic gel, source electrode - Au and source electrode - Au disposed on both sides of the side gate dielectric layer, side gate - Ag.

[0082] 2. The preparation method of the above - mentioned synaptic transistor with heterogeneous interface regulation includes the following steps:

[0083] S1. Pretreatment of the substrate

[0084] The substrate is successively placed in deionized water, acetone solution, and isopropanol, ultrasonically cleaned for 30 min respectively, and dried with nitrogen to obtain the pretreated substrate. Among them, the thickness of the main gate is 499.7 μm, the thickness of the main gate dielectric layer is 300 nm, and the total thickness of the substrate is 500 μm.

[0085] S2. Preparation of the active layer

[0086] On the pretreated substrate obtained in step S1, an ITZO active layer is deposited by magnetron co - sputtering method using ITO target and ZnO target at room temperature. During the sputtering process, the powers of the ITO target and ZnO target are 100 W and 130 W respectively, the air pressure in the cavity is 0.5 Pa, and the Ar:O2 gas flow rate is fixed at 10:6 sccm. Under an air environment, it is annealed at 350 °C for 3 h to obtain an ITZO thin film with a thickness of 30 nm.

[0087] S3. Evaporation of electrodes

[0088] The customized mask is attached to the surface of the active layer prepared in step S2, and then placed in a coating machine. First, it is coated at a deposition rate of for 5 nm, and then the deposition rate is increased to and coated for 30 nm. Finally, Au layers with a thickness of 35 nm are obtained on both sides of the surface of the active layer as the source electrode - Au and the drain electrode - Au.

[0089] S4. Preparation of the side gate dielectric layer

[0090] S4 - 1. Mix polyvinylidene fluoride - hexafluoropropylene copolymer (PVDF - HFP) with acetone, stir at 60 °C for 1 h until completely dissolved to obtain a PVDF - HFP solution with a mass concentration of 0.25 g / mL;

[0091] S4-2. According to the mass of PVDF-HFP input in step S4-1, measure the corresponding volume of 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide (EMIM-TFSI) according to the mass-volume ratio of 2 mL of EMIM-TFSI per 1 g of PVDF-HFP, and add it to the PVDF-HFP solution obtained in step S4-1. Stir at 60 °C for 12 h until the solution is clear, transparent and bubble-free to obtain the [PVDF-HFP][EMIM-TFSI] ionic gel solution;

[0092] S4-3. Pour the [PVDF-HFP][EMIM-TFSI] ionic gel solution obtained in step S4-2 evenly into a mold, transfer it to an 80 °C drying oven and dry for 2 h to obtain a peelable [PVDF-HFP][EMIM-TFSI] ionic gel, that is, the side gate dielectric layer (10 μm);

[0093] S5. Fabricate the side gate

[0094] Attach the customized mask plate to the surface of the [PVDF-HFP][EMIM-TFSI] ionic gel conductor film obtained in step S4, and then transfer it to a coating machine to evaporate the Ag square electrode as the side gate (60 nm); Remove the mask plate in step S3, and then attach the [PVDF-HFP][EMIM-TFSI] ionic gel conductor film covered with the Ag square electrode to the channel region formed between the source electrode and the drain electrode. The resulting device is a synaptic transistor with heterogeneous interface regulation.

[0095] Example 2 A synaptic transistor with heterogeneous interface regulation and its preparation method

[0096] The difference from Example 1 is that in step S4-2 of the preparation method of the synaptic transistor with heterogeneous interface regulation, the mass-volume ratio of 2 mL of 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide (EMIM-TFSI) per 1 g of PVDF-HFP is replaced with a mass-volume ratio of 3 mL of EMIM-TFSI per 1 g of PVDF-HFP.

[0097] Other steps and conditions are the same as those in Example 1.

[0098] Example 3 A synaptic transistor with heterogeneous interface regulation and its preparation method

[0099] The difference from Example 1 is that in step S4-1 of the preparation method of the synaptic transistor with heterogeneous interface regulation, the PVDF-HFP solution with a mass concentration of 0.25 g / mL is replaced with a PVDF-HFP solution with a mass concentration of 0.3 g / mL.

[0100] Other steps and conditions are the same as those in Example 1.

[0101] Experimental Example 1: Performance Test of Postsynaptic Current of Synaptic Transistor under Different Lateral Synaptic Spike Stimulations

[0102] 1. Experimental Method

[0103] Take the synaptic transistor with heterointerface regulation prepared in Example 1 as the test sample. Connect the probes of electrodes SUM1 and SUM2 to the source electrode - Au and drain electrode - Au of the transistor respectively, connect the probe of electrode SUM3 to Si serving as the main gate, and connect the probe of electrode SUM4 to the Ag square electrode serving as the lateral gate. Use a Keithley 4200 - SCS semiconductor characterization analyzer to continuously apply a reading voltage of 0.01V to electrode SUM2, and apply 4 groups of different pulses to electrodes SUM3 and SUM4 as presynaptic spikes. Among them, ① apply a single main synaptic spike with a duration of 0.05s and an amplitude of 1V to electrode SUM3, and do not apply a pulse to electrode SUM4; ② apply a single main synaptic spike with a duration of 0.05s and an amplitude of 1V to electrode SUM3, and at the same time apply a single lateral synaptic spike with a duration of 0.05s and an amplitude of - 0.5V to electrode SUM4; ③ apply a single main synaptic spike with a duration of 0.05s and an amplitude of 1V to electrode SUM3, and at the same time apply a single lateral synaptic spike with a duration of 0.05s and an amplitude of 0.5V to electrode SUM4; ④ apply a single main synaptic spike with a duration of 0.05s and an amplitude of 1V to electrode SUM3, and at the same time apply a single lateral synaptic spike with a duration of 0.05s and an amplitude of 1V to electrode SUM4. Test the postsynaptic current diagrams after pulse stimulations under four different lateral synaptic spike intensities.

[0104] 2. Experimental Results

[0105] As Figure 2 shown, when there is no lateral modulation (i.e., no lateral synaptic spike is applied) ( Figure 2 (a)), when a 1V main synaptic spike is applied to the main gate, a slight activation phenomenon of H + will occur at the bottom interface, forming a weak electric double layer with the bottom interface of ITZO. This effect acts synergistically with the dielectric coupling effect to induce carrier transport at the bottom interface, simulating the excitatory postsynaptic current of excitatory neurotransmitters such as γ - aminobutyric acid (GABA) medium. At this time, the change in postsynaptic current is 8.58 μA; when a - 0.5V lateral synaptic spike is applied to the lateral gate, the negative electric field generated by ion gel coupling will inhibit the activation of H + , hinder the vertical transport of carriers, and simulate the synaptic inhibition state under the synergistic action of inhibitory neurotransmitters such as glutamate. At this time, the postsynaptic current is 4.45 μA ( Figure 2(b)); When a 0.5 V side synaptic spike is applied to the side gate, EMIM + will accumulate in large quantities at the top interface of ITZO, forming a strong electric double layer effect, activating the top interface as an electron carrier auxiliary channel, simulating the enhancement of short-term plasticity induced by glutamate, and the postsynaptic current increases to 21.25 μA ( Figure 2 (c)); When the side synaptic spike intensity increases to 1 V, the migration of EMIM⁺ intensifies, and some cations penetrate into the interior of ITZO through interface defects (still remaining near the top interface), significantly enhancing the electric double layer effect, simulating the long-term plasticity induced by glutamate, and the postsynaptic current reaches 99.38 μA ( Figure 2 (d)).

[0106] In summary, by adjusting the amplitude of the side gate voltage, this device can not only simulate the transmission of excitatory (side synaptic spikes with positive voltage applied) or inhibitory (side synaptic spikes with negative voltage applied) neurotransmitters, but also achieve a dynamic transition of the postsynaptic current from short-term plasticity to long-term plasticity: Long-term plasticity (1 V side synaptic spike): The postsynaptic current still remains 17.29 μA (accounting for 17.4% of the initial current) at 20 s, and the decline curve is gentle; Short-term plasticity (0.5 V, 0 V, -0.5 V side synaptic spikes): The current rapidly drops to the baseline level within 10 s. This result indicates that the lateral gate voltage modulation can precisely control the channel charge distribution and achieve the regulation of synaptic plasticity at multiple hierarchical scales.

[0107] Experimental Example 2: Tests on Postsynaptic Current and Double-Pulse Facilitation Performance of Synaptic Transistors under Stimulation with Different Side Synaptic Spike Intensities

[0108] 1. Experimental Method

[0109] Using a Keithley 4200-SCS semiconductor characterization analyzer, a reading voltage of 0.01 V was continuously applied to the electrode SUM2. At the same time, a pair of consecutive 1 V pulses was applied to the electrode SUM3 as the main synaptic spike, and the time intervals of the pulse pairs were set to 0.05 s, 0.1 s, 0.2 s, 0.4 s, 0.8 s, 1.6 s, 3.2 s, and 6.4 s in sequence. At the same time as the main synaptic spike was triggered, voltages with different amplitudes were applied to the electrode SUM4 as side synaptic spikes, and their pulse amplitudes were -0.5 V, 0 V, 0.5 V, and 1 V respectively. Through testing, the data of the change in postsynaptic current under stimulation with different side synaptic spike intensities under the condition of the same main synaptic spike intensity were obtained ( Figure 3 ). Further, by performing double-exponential fitting on the tested data, the data of the change in the double-pulse facilitation index were obtained ( Figure 4 ).

[0110] 2. Experimental Results

[0111] The results are as Figure 3As shown, a pair of consecutive 1V main synaptic spikes were applied to the main gate, and the pulse pairs had different time intervals. At the same time, tunable side synaptic spikes were triggered to study the double-pulse facilitation of the device. With the increase in the intensity of the side synaptic spikes, ion accumulation promoted the transport of carriers at the channel interface, thereby inducing a larger postsynaptic current. Specifically, when the applied side synaptic spike was -0.5V, the maximum change in the postsynaptic current of the device was 13.29 μA; when the intensity of the applied side synaptic spike increased to 1V, the maximum change in the postsynaptic current of the device increased to 138.41 μA. It can be seen that within the regulation range of the side synaptic spike voltage from -0.5V to 1V, the current regulation range of the device was 125.12 μA. As Figure 4 shown, the double-pulse facilitation index of the device at different side synaptic spike intensities was obtained by double-exponential fitting (y = C1*exp(-x / τ1)+C2*exp(-x / τ2)+y0, where C1 and C2 are the initial facilitation values in the fast-decay and slow-decay stages). It can be seen that the double-pulse facilitation index declined with the increase in the time interval, which demonstrated the characteristics of biological synapses. As the intensity of the side synaptic spike increased from -0.5V ( Figure 4 (a)) to 1V ( Figure 4 (d)), its facilitation ability showed obvious flexible adjustment. Specifically, the fast relaxation time τ1 increased from 173 ms to 677 ms, and the slow relaxation time τ2 increased from 1.53 s to 5.05 s. Experimental Example 3 Spike number-dependent plasticity test of synaptic transistors under different numbers of main and side synaptic spikes and side synaptic spike amplitudes

[0112] 1. Experimental method

[0113] Using a Keithley 4200-SCS semiconductor parameter analyzer, a reading voltage of 0.01V was continuously applied to the electrode SUM2, and 6 groups of pulse sequences were applied to the electrode SUM3. Each group of pulse sequences contained 5, 10, 20, 30, 50, and 100 pulses with an amplitude of -4V, and the duration of a single pulse was 0.05 s. These pulse signals served as the main presynaptic spikes. At the same time as the main synaptic spikes were triggered, voltages with different amplitudes were applied to the electrode SUM4 as side synaptic spikes, and their pulse amplitudes were -0.5V, 0V, 0.5V, and 1V respectively. Through testing, the postsynaptic currents ( Figure 5 ) under 4 groups of different side synaptic spike number stimulations were obtained. The 4 groups of data obtained from the test were processed to obtain the data of the change in the spike number-dependent plasticity index ( Figure 6 ). In addition, after removing the postsynaptic current spikes from these 4 groups of data, the normalized weight retention curve data ( Figure 7 ) were further processed.

[0114] 2. Experimental Results

[0115] In this experiment, to simulate the spike - number - dependent plasticity of synaptic transistors, a method of applying a series of main synaptic spikes with an amplitude of - 1V to the main gate of the synaptic transistor was adopted, and different side - synaptic - spike amplitude conditions were set. The experimental results show that as the number of main synaptic spikes increases, the electric double - layer effect gradually enhances, thereby promoting the increase of the postsynaptic current. Specifically, when there is no effect of side - synaptic spikes, when the number of main synaptic spikes increases from 5 to 30, the change in the maximum postsynaptic current increases from 33.8 μA to 52.7 μA( Figure 5 (a)); when the amplitudes of side - synaptic spikes are - 0.5V, 0.5V, and 1V respectively, and - 1V main synaptic spikes are also applied, as the number of spikes increases from 5 to 30, the change in the maximum postsynaptic current increases from 22.18 μA to 41.54 μA( Figure 5 (b)), from 44.68 μA to 77.30 μA( Figure 5 (c)), and from 83.97 μA to 112.23 μA( Figure 5 (d)). It can be seen from Figure 6 that when the side - synaptic spike is - 0.5V, the spike - number - dependent plasticity index shows the highest linearity. This phenomenon indicates that under this condition, the ion activation efficiency at the interface is relatively low, and it is difficult for ions to reach the saturation state. On the contrary, as the intensity of the side - synaptic spike increases, cations rapidly accumulate at the interface and quickly reach the saturation state, thereby weakening the linear relationship between the spike - number - dependent plasticity index and the number of spikes. It can be seen from Figure 7 that adjusting the side - synaptic spike from a negative voltage to a positive voltage can effectively regulate the postsynaptic current, changing it from short - term plasticity to long - term plasticity. This means that the switching between long - term / short - term synaptic plasticity of the device can be achieved by regulating the side - synaptic spike.

[0116] The above - mentioned embodiments are the preferred embodiments of the present invention, but the embodiments of the present invention are not limited by the above - mentioned embodiments. Any other changes, modifications, substitutions, combinations, and simplifications made without departing from the spirit and principle of the present invention shall be equivalent replacement methods and are all included in the protection scope of the present invention.

Claims

1. A synaptic transistor with heterogeneous interface regulation, characterized in that, It includes a substrate, an active layer, a side gate dielectric layer, a source electrode and a drain electrode disposed on both sides of the side gate dielectric layer, and a side gate electrode, which are stacked in sequence. Wherein, the substrate is composed of a doped n-type Si layer and SiO2 adsorbed with H on the surface + on its surface; The side gate dielectric layer is an ionic gel of [PVDF-HFP][EMIM-TFSI]. The active layer is an indium tin zinc oxide thin film.

2. The synaptic crystal with heterogeneous interface regulation according to claim 1, characterized in that The side gate electrode is made of gold or silver.

3. The synaptic transistor with heterogeneous interface regulation according to claim 1, characterized in that The preparation method of the [PVDF-HFP][EMIM-TFSI] ionic gel includes the following steps: Mix a polyvinylidene fluoride-hexafluoropropylene copolymer solution and 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide salt evenly, and after curing, obtain the [PVDF-HFP][EMIM-TFSI] ionic gel.

4. The synaptic transistor with heterogeneous interface regulation according to claim 3, wherein The mass-volume ratio of the polyvinylidene fluoride-hexafluoropropylene copolymer to the 1-ethyl-3-methylimidazolium bis(trifluoromethylsulfonyl)imide salt is 1:(0.5-4) g / mL.

5. The synaptic transistor with heterogeneous interface regulation according to claim 1, wherein, The materials of the source electrode and the drain electrode are the same; the source electrode and the drain electrode are made of gold, silver or copper.

6. The synaptic transistor with heterogeneous interface regulation according to claim 1, wherein The indium tin zinc oxide thin film is prepared by magnetron sputtering deposition using indium tin oxide and zinc oxide targets as raw materials.

7. The synaptic transistor with heterogeneous interface regulation according to claim 1, wherein The thickness of the gate dielectric layer is 5-20 μm.

8. The synaptic transistor with heterogeneous interface regulation according to claim 1, wherein, The thickness of the active layer is 28-32 nm.

9. The preparation method of the synaptic transistor with heterogeneous interface regulation according to any one of claims 1 to 8, characterized in that, It includes the following steps: S1. Prepare an indium tin zinc oxide thin film on the substrate as the active layer. S2. Attach a mask plate to the surface of the active layer obtained in step S1, and evaporate the source electrode and the drain electrode on both sides of the surface of the active layer. S3. Prepare the [PVDF-HFP][EMIM-TFSI] ionic gel as the side gate dielectric layer, attach the mask plate to the surface of the [PVDF-HFP][EMIM-TFSI] ionic gel, and evaporate the side gate electrode on the surface of the [PVDF-HFP][EMIM-TFSI] ionic gel. S4. Remove the mask plate in step S2, and attach the [PVDF-HFP][EMIM-TFSI] ionic gel covered with the side gate electrode obtained in step S3 to the channel region formed between the source electrode and the drain electrode. The obtained device is a synaptic transistor with heterogeneous interface regulation.

10. Use of the synaptic transistor with heterogeneous interface regulation according to any one of claims 1 to 8 in the preparation of a bionic sensing device, a neuromorphic memory or a brain-like computing chip.

Images