Method of processing a semiconductor structure and semiconductor processing apparatus

Abstract

The application discloses a processing method of a semiconductor structure and a semiconductor processing device, and belongs to the technical field of semiconductor processing. The processing method comprises the following steps: providing a to-be-etched piece, the to-be-etched piece comprising a target etching layer, a patterned mask layer and a medium structure, the target etching layer having a plurality of isolation grooves, the patterned mask layer being located above the target etching layer, the medium structure being filled in the patterned mask layer and each isolation groove, and the top surface of the medium structure being flush with the top surface of the patterned mask layer, the patterned mask layer being used as a mask structure in the process of forming the plurality of isolation grooves on the target etching layer; removing part of the medium structure filled in the patterned mask layer; removing the patterned mask layer; and removing part of the remaining medium structure to a preset depth. The processing method can solve the problem that, in the process of a shallow trench isolation technology, the layer structure above a fin-shaped structure is removed, the fin-shaped structure is easily broken, the performance of a device is reduced, and the yield is reduced.

Description

TECHNICAL FIELD

[0001] The present application belongs to the technical field of semiconductor processing, and particularly relates to a processing method of a semiconductor structure and a semiconductor processing device. BACKGROUND

[0002] In the process of semiconductor processing, the feature size reduction is the current technical development trend. However, after the feature size is reduced to the processing limit of the photolithography machine, if the feature size needs to be further reduced, the auxiliary technology needs to be used to increase the pattern density. In the common auxiliary technology, since the double pattern process needs to perform two times of photolithography process, a high alignment accuracy is required, and the double pattern process does not have the ability to continuously multiply the pattern density. Therefore, the self-aligned multiple pattern technology is usually used to form a FinFET structure (Fin Field-Effect Transistor). However, in the process of STI (Shallow Trench Isolation) process, when the chemical mechanical polishing process is used to remove the dielectric structure, since the width of the fin-shaped structure on the substrate is relatively small, the fin-shaped structure is easily damaged in the grinding process, and even the fin-shaped structure is broken, which leads to the performance degradation of the device and the yield reduction. SUMMARY

[0003] The purpose of the embodiments of the present application is to provide a processing method of a semiconductor structure and a semiconductor processing device, so as to solve the problem that in the process of the shallow trench isolation process, when the layer structure above the fin-shaped structure is removed, the fin-shaped structure is easily broken, which leads to the performance degradation of the device and the yield reduction.

[0004] In a first aspect, the present application discloses a processing method of a semiconductor structure, which comprises the following steps:

[0005] providing a to-be-etched piece, wherein the to-be-etched piece comprises a target etching layer, a patterned mask layer and a dielectric structure, the target etching layer has a plurality of isolation grooves, the patterned mask layer is located above the target etching layer, the dielectric structure is filled in the patterned mask layer and each of the isolation grooves, and the top surface of the dielectric structure is flush with the top surface of the patterned mask layer, and the patterned mask layer is used as a mask structure in the process of forming a plurality of the isolation grooves on the target etching layer;

[0006] removing part of the dielectric structure filled in the patterned mask layer;

[0007] removing the patterned mask layer;

[0008] removing the remaining part of the dielectric structure to a preset depth.

[0009] In a second aspect, the present application discloses a semiconductor processing device, which comprises a processor, a memory, and a program or instruction stored in the memory and executable on the processor, and the program or instruction is executed by the processor to implement the steps of the processing method as described above.

[0010] The embodiment of the present application discloses a processing method of a semiconductor structure, which first needs to provide an etching object, in which a target etching layer has a plurality of isolation grooves, and a patterned mask layer is arranged above the target etching layer, at the same time, a medium structure of the etching object is filled in the patterned mask layer and each isolation groove, the top surface of the medium structure is flush with the top surface of the patterned mask layer, and a plurality of isolation grooves are processed on a substrate to form a mask structure of the target etching layer. In order to remove the patterned mask layer, in the embodiment of the present application, first, part of the medium structure filled in the patterned mask layer is removed, so that the patterned mask layer is integrally exposed outside the target etching layer, and then the patterned mask layer is removed, and then part of the remaining medium structure is removed to a preset depth, so that the fin structure is exposed again. Since the patterned mask layer and the target etching layer are independently formed, the connection reliability between the two is relatively low, and then in the process of removing the patterned mask layer, the force acting on the patterned mask layer is difficult to transmit to the fin structure below, which can reduce the probability of damage to the fin structure and improve the yield of the product. BRIEF DESCRIPTION OF DRAWINGS

[0011] The accompanying drawings, which are included to provide a further understanding of the present application and are incorporated in and constitute a part of this application, illustrate embodiments of the present application and serve to explain the present application. In the drawings:

[0012] Figure 1 A schematic diagram of a process flow for removing a layer structure above a target etching layer in the prior art;

[0013] Figure 2 A schematic diagram of a process flow for removing a layer structure above a target etching layer by using the processing method disclosed in the embodiment of the present application;

[0014] Figure 3 A flowchart of the processing method disclosed in the embodiment of the present application;

[0015] Figure 4 A schematic diagram of a film structure required for forming an etching object in the processing method disclosed in the embodiment of the present application;

[0016] Figures 5a-5m A schematic diagram of an intermediate structure at different nodes in the forming process of the patterned mask layer in the processing method disclosed in the embodiment of the present application;

[0017] Figures 6a-6c The schematic diagram of the intermediate structure at different nodes in the forming process of the to-be-etched member in the processing method disclosed by the embodiments of the present application.

[0018] Reference signs:

[0019] 10-target etching layer, 11-finger structure, 12-isolation groove, 20-patterned mask layer, 30-dielectric structure, 30'-dielectric cover layer, 40-patterned transition layer, 50-patterned pattern transfer layer,

[0020] 101-substrate, 102-transition layer, 103-second mask layer, 104-pattern transfer layer, 105-second core layer, 106-first mask layer, 107-etching stop layer, 108-first core layer, 109-SOC layer, 110-BARC layer, 111-photolithography resist layer, 112-deposition layer, 113-side wall, 114-second deposition layer, 115-second side wall. DETAILED DESCRIPTION

[0021] The technical solutions in the embodiments of the present application will be described clearly and completely below in conjunction with the drawings in the embodiments of the present application. Obviously, the described embodiments are only some of the embodiments of the present application, rather than all the embodiments of the present application. Based on the embodiments in the present application, all the other embodiments obtained by those skilled in the art without any creative work under the premise that the embodiments in the present application are within the protection scope of the present application.

[0022] The terms “first”, “second”, and the like in the specification and claims of the present application are used to distinguish similar objects, and are not used to describe a specific order or sequence. It should be understood that the data used in this way can be exchanged under appropriate circumstances, so that the embodiments of the present application can be implemented in an order other than those illustrated or described herein, and the objects distinguished by “first”, “second”, etc. are generally a category, and are not limited to the number of objects, for example, the first object can be one or more. In addition, “and / or” in the specification and claims indicates at least one of the connected objects, and the character “ / ” generally indicates that the front and rear associated objects are in an “or” relationship.

[0023] As Figure 3As shown, the embodiment of the present application discloses a processing method of semiconductor structure, which is applied to shallow trench isolation process, especially to shallow trench isolation process of Fin FET. Before the shallow trench isolation process, a fin structure 11 (i.e. Fin structure) is usually formed, and in order to ensure the electrical isolation between adjacent Fin FETs, a shallow trench isolation structure is needed to be formed between two adjacent fin structures. In detail, by etching the substrate, an isolation groove 12 can be formed between any two adjacent fin structures 11 to provide electrical isolation for the two adjacent fin structures 11, wherein the substrate after the above process is the target etching layer 10 which has multiple isolation grooves and multiple fin structures 11.

[0024] In addition, in order to ensure the quality of the subsequent pattern, after the isolation groove with the required depth is formed on the target etching layer 10 (i.e. substrate), the mask layer of the target etching layer 10 still has a part remaining. Therefore, in the embodiment of the present application, the etching object includes the target etching layer 10 and the patterned mask layer 20. In the process of etching the substrate to form the target etching layer 10, the patterned mask layer 20 is used as a mask structure.

[0025] In addition, in order to ensure the isolation effect, the multiple isolation grooves formed on the target etching layer 10 need to be filled with a medium in the process, and therefore, in the embodiment of the present application, the etching object further includes a medium structure 30, and the medium structure 30 is filled in each isolation groove. In addition, in order to improve the electrical isolation effect of the isolation groove, in the process of forming the medium structure 30, each isolation groove needs to be filled with the medium structure as much as possible, and therefore, the medium structure can be in an overfilling state in the isolation groove, i.e. the upper surface of the medium structure exceeds the upper surface of the target etching layer. At the same time, in order to ensure the normal transfer of the pattern, the mask layer directly serving as the substrate has been patterned, and the pattern of the patterned mask layer corresponds to the isolation groove of the target etching layer. In the case that the upper surface of the medium structure exceeds the upper surface of the target etching layer, the medium structure is naturally filled in the pattern of the patterned mask layer, i.e. in the embodiment of the present application, the medium structure is filled in each isolation groove of the target etching layer and each patterned mask layer.

[0026] Furthermore, in order to ensure relatively high uniformity in the removal of dielectric material at different positions in the pattern of the patterned mask layer when removing the portion of the dielectric structure that fills the patterned mask layer, in this embodiment, the top surface of the dielectric structure 30 can be flush with the top surface of the patterned mask layer 20. This ensures that when removing the dielectric structure 30, the thickness of the dielectric material at different positions in the pattern of the patterned mask layer 20 is the same, so as to make the removal thickness (or depth) of the dielectric material at different positions in the pattern of the patterned mask layer 20 equal in the same amount of time, thereby facilitating the removal of the patterned mask layer.

[0027] Based on the above situation, such as Figure 2 As shown in the embodiments of this application, the processing method includes:

[0028] A workpiece to be etched is provided, comprising a target etch layer 10, a patterned mask layer 20, and a dielectric structure 30. The target etch layer 10 has multiple isolation trenches and includes multiple fin structures. In the target etch layer 10, any isolation trench is used to electrically isolate two adjacent fin structures. The patterned mask layer 20 is located above the target etch layer 10. The dielectric structure 30 fills the patterned mask layer 20 and each isolation trench, and the top surface of the dielectric structure 30 is flush with the top surface of the patterned mask layer 20. In addition, as described above, multiple isolation trenches are formed on the substrate to form the target etch layer 10, and the patterned mask layer 20 serves as a mask structure for the substrate.

[0029] Next, the portion of the dielectric structure 30 located above the target etched layer 10 and the patterned mask layer 20 need to be removed. In related technologies, such as Figure 1 As shown, the patterned mask layer 20 is typically removed first by etching, followed by chemical mechanical polishing (CMP) to remove the portion of the dielectric structure 30 above the target etched layer 10, thus exposing the target etched layer 10. However, because the width of the fin structure is relatively small, and the dielectric material in the isolation trench of the target etched layer 10 and the dielectric material above the target etched layer 10 are formed in the same process stage, the dielectric material in the dielectric structure 30 located in the pattern of the patterned mask layer 20 and in the isolation trench has relatively strong integrity. This makes it easy for the shear force on the dielectric structure 30 to be transmitted to the fin structure when the dielectric material above the target etched layer 10 is removed by CMP, making the fin structure prone to damage or even breakage.

[0030] Therefore, in the processing method disclosed in the embodiments of this application, such as Figure 2As shown, the technical solution is given that the part filled in the patterned mask layer 20 in the dielectric structure 30 is removed first, and then the patterned mask layer 20 is removed. In the case of adopting the technical solution, after the part filled in the patterned mask layer 20 in the dielectric structure 30 is removed, the patterned mask layer 20 is exposed as a whole, and compared with the connection reliability between the dielectric structure 30 and the patterned mask layer, the connection reliability between the patterned mask layer 20 and the target etching layer 10 is relatively low due to the fact that the patterned mask layer 20 and the target etching layer 10 are independently formed, and then in the process of removing the patterned mask layer 20, the force acting on the patterned mask layer 20 is difficult to be transmitted to the fin structure below, so compared with the related art, the technical solution disclosed in the present application can reduce the probability of damage to the fin structure when removing the layer structure above the fin structure in the shallow trench isolation process, and improve the yield of the product.

[0031] In detail, after the step S1, as shown in FIG. 2, the processing method further includes: Figure 3 As shown in FIG. 2, in combination with Figure 2 The processing method disclosed in the embodiments of the present application further includes:

[0032] S2, removing the part filled in the patterned mask layer 20 in the dielectric structure 30;

[0033] S3, removing the patterned mask layer 20.

[0034] Of course, after the step S3, a part of the dielectric material filled in each isolation groove can be further removed by etching or the like to expose the fin structure.

[0035] That is, in the embodiments of the present application, the processing method further includes:

[0036] S4, removing the part of the remaining dielectric structure to a preset depth. Of course, in this process, the removal depth of the remaining dielectric structure can be selected flexibly according to actual needs, for example, the aforementioned depth can correspond to the height of the fin structure, which is not limited herein.

[0037] The embodiment of the present application discloses a processing method of a semiconductor structure, which first needs to provide a to-be-etched piece. In the to-be-etched piece, a target etching layer 10 has a plurality of isolation grooves, and a patterned mask layer 20 is arranged above the target etching layer 10. Meanwhile, a medium structure 30 of the to-be-etched piece is filled in the patterned mask layer 20 and each isolation groove, the top surface of the medium structure 30 is flush with the top surface of the patterned mask layer 20, and a plurality of isolation grooves are processed on a substrate to form the target etching layer 10. In the process of forming the mask structure of the substrate into the patterned mask layer 20. In order to remove the patterned mask layer 20, in the embodiment of the present application, the part of the medium structure 30 filled in the patterned mask layer 20 is removed first, so that the patterned mask layer 20 is exposed to the target etching layer 10 as a whole, and then the patterned mask layer 20 is removed. Then, remove part of the remaining medium structure 30 to a preset depth, so that the fin structure is exposed again. Since the patterned mask layer 20 and the target etching layer 10 are independently formed, the connection reliability between the two is relatively low, and then in the process of removing the patterned mask layer 20, the force acting on the patterned mask layer 20 is difficult to transmit to the fin structure below, which can reduce the probability of damage to the fin structure and improve the yield of the product.

[0038] Further, in one specific embodiment of the present application, the etching method can be used to remove the part of the medium structure 30 filled in the patterned mask layer 20. Of course, in this process, the etching gas needs to be selected according to the specific material of the target etching layer 10, the mask layer and the medium structure, so as to ensure that the medium structure 30 has a high selectivity to the mask layer during etching. That is, in the embodiment of the present application, the processing method comprises: removing the part of the medium structure filled in the patterned mask layer by a first etching step, that is, stopping the etching of the medium structure at a position flush with the bottom of the patterned mask layer. More specifically, by controlling the etching time of the first etching step, the medium structure 30 is etched to a position flush with the bottom of the patterned mask layer 20, so as to completely expose the patterned mask layer 20 for removal in the subsequent step.

[0039] In one specific embodiment of the present application, the medium structure can be formed by deposition. For this purpose, as shown in Figures 6a-6c the step of providing the to-be-etched piece comprises:

[0040] forming the patterned mask layer on the substrate 101, as shown in Figure 6a ;

[0041] etching the substrate by using the patterned mask layer, and forming a plurality of fin structures and isolation grooves on the substrate to form a target etching layer, as shown in Figure 6b , wherein the isolation grooves are used to electrically isolate two adjacent fin structures.

[0042] The deposition step forms a dielectric structure between the target etching layer 10 and the patterned mask layer 20.

[0043] Specifically, in the process of forming the dielectric structure by deposition, the dielectric material gradually fills the isolation grooves 12 of the target etching layer 10, and as the deposition process continues, the height of the dielectric material filled in the isolation grooves gradually increases until it is flush with the top surface of the target etching layer 10, so that the dielectric material fills the isolation grooves. In order to make the flatness of the dielectric material on the top of the isolation groove relatively better, it is necessary to make the dielectric material in an overfill state relative to the isolation groove, and for this purpose, in the embodiments of the present application, the dielectric material can be further deposited and filled in the pattern of the patterned mask layer.

[0044] Optionally, in the process of filling the dielectric material in the pattern of the patterned mask layer, when the filling height of the dielectric material is flush with the upper surface of the patterned mask layer, the deposition process can be stopped, that is, the upper surface of the dielectric material is flush with the upper surface of the patterned mask layer, which can form the above-mentioned to-be-etched piece.

[0045] In order to further improve the flatness of the top of the dielectric material in the isolation groove to improve the performance of the semiconductor device, in another embodiment of the present application, when the dielectric material is deposited on the target etching layer and the patterned mask layer by the deposition step, the dielectric material can be gradually deposited to a position where the upper surface exceeds the upper surface of the patterned mask layer, so that the upper part of the patterned mask layer also forms a dielectric material.

[0046] That is, in the embodiments of the present application, the above-mentioned forming a dielectric structure between the target etching layer and the patterned mask layer by the deposition step comprises:

[0047] forming a dielectric cover layer 30' on the target etching layer and the patterned mask layer by the deposition step, wherein the upper surface of the dielectric cover layer 30' is higher than the upper surface of the patterned mask layer 20, as shown in Figure 6c ;

[0048] Then, it further comprises: chemical mechanical polishing of the dielectric cover layer 30', until the patterned mask layer is exposed, forming a dielectric structure 30, in which case, the to-be-etched piece required by the embodiments of the present application can also be obtained, that is, Figure 2 the structure in the upper left corner of the first figure of Figure 2 .

[0049] That is, in the embodiment of the present application, when the dielectric structure 30 is formed, after the dielectric material has filled the patterned mask layer 20 by over-deposition, the deposition process is still continued to make the dielectric material cover the entire patterned mask layer and form a dielectric cover layer 30', and then the chemical mechanical polishing method is used to gradually remove the part of the dielectric cover layer 30' above the patterned mask layer. In the foregoing process, the flatness of the upper surface of the dielectric material is gradually improved, and then when polished to the position flush with the patterned mask layer and the dielectric structure to be etched is formed, the flatness of the upper surface of the dielectric structure is relatively high, thereby improving the performance of the subsequent semiconductor device. It should be noted that the upper surface of the dielectric cover layer is not a fixed surface during the chemical mechanical polishing process, but continuously changes.

[0050] Further, between the step of forming the dielectric cover layer and the step of chemical mechanical polishing the dielectric cover layer, the processing method disclosed in the embodiment of the present application can further include:

[0051] Annealing the dielectric cover layer.

[0052] In the case of using the technical solution of the present application, the annealing method can be used to improve the density of the dielectric material in the dielectric cover layer, which makes the electrical isolation provided by the dielectric material stronger, and further improves the electrical isolation effect of the isolation groove on the two adjacent fin structures.

[0053] As described above, the processing method disclosed in the embodiment of the present application includes removing part of the remaining dielectric structure to a preset depth, which is different from the removal method of the part of the dielectric structure above the patterned mask layer. In the embodiment of the present application, the etching method can be used to further remove the part of the dielectric structure between the two adjacent fin structures to prevent damage to the fin structure in the foregoing removal process.

[0054] That is, the above step S4 includes:

[0055] By the second etching step, part of the remaining dielectric structure is removed to a preset depth to expose the fin structure.

[0056] In addition, in order to further prevent the fin-shaped structure from being damaged in the process of removing the patterned mask layer 20, in an embodiment of the present application, the patterned mask layer 20 can also be removed by etching. Compared with removing the patterned mask layer by chemical mechanical polishing, the method disclosed in the embodiment of the present application can hardly cause the patterned mask layer 20 to be subjected to shearing force in the process of removing the patterned mask layer 20, thereby greatly reducing the probability of the fin-shaped structure being damaged by external force. Of course, in the process of removing the patterned mask layer 20 by etching, the etching gas needs to be selected according to the materials of the mask layer and the target etching layer 10, so as to ensure that the mask layer has a high selectivity ratio with respect to the target etching layer 10.

[0057] Based on the above embodiment, in order to reduce the etching control difficulty of the mask layer and prevent over-etching from occurring in the process of etching to remove the patterned mask layer and damaging the target etching layer, in the embodiment of the present application, the etching object can also include a patterned transition layer 40, and the patterned transition layer 40 is located between the fin-shaped structure 11 and the patterned mask layer 20. Of course, similar to the patterned mask layer 20, the patterned transition layer 40 is formed by etching a transition layer and pattern transfer. The pattern structure formed on the transition layer is the same as the pattern structure formed on the mask layer, that is, in the process of etching the substrate to form the target etching layer 10 having a plurality of isolation grooves, the pattern structure is first transferred to the mask layer to form the patterned mask layer 20, then transferred to the transition layer to form the patterned transition layer 40, and finally transferred to the substrate to form the target etching layer 10. In the etching process, the transition layer is used to provide a balanced internal stress. When the target etching layer is a silicon substrate, the transition layer can be formed by using silicon oxide and the like. In addition, when the etching object includes the patterned transition layer, a part of the dielectric structure is filled in the pattern of the patterned transition layer in the process of forming the dielectric structure.

[0058] In an embodiment of the present application, the patterned transition layer 40 can also have a selectivity ratio with respect to the patterned mask layer 20, that is, the selectivity ratio of the transition layer and the mask layer is greater than 1. In this case, when the patterned mask layer 20 is removed by etching, the transition layer 40 can also provide a certain etching stop effect, so that when the lower edge of the patterned mask layer 20 is basically completely etched and removed, the part that continues to be etched is the patterned transition layer, thereby the etching rate and other parameters can be used to more accurately and quickly determine the stopping point of the foregoing etching process, thereby reducing the process difficulty and preventing the target etching layer 10 from being etched.

[0059] Of course, when using the above technical solution, after the patterned mask layer is etched away, in order to achieve the etching purpose of the portion of the dielectric structure located between any two adjacent fin structures, it is necessary to remove the patterned transition layer. Therefore, in the processing method disclosed in the embodiments of this application, after removing the patterned mask layer, it further includes: removing the patterned transition layer and the portion of the dielectric structure filled in the patterned transition layer. More specifically, the etching selectivity of the transition layer and the dielectric material can be made comparable, or the dielectric material can have a high selectivity relative to the transition layer, so that during the etching of the dielectric structure, even when the patterned transition layer is removed or substantially removed, the portion of the dielectric structure located between any two adjacent fin structures (i.e., the portion in the remaining dielectric structure) can be etched to a preset depth.

[0060] Furthermore, in the embodiments of this application, a self-aligned multi-patterning technique can be used to form a patterned mask layer.

[0061] In detail, during the process of etching multiple isolation trenches on a substrate to form the part to be etched, a film structure can be formed first, such as... Figure 4 As shown, the film structure, from bottom to top, can sequentially include: a substrate 101, a transition layer 102, a second mask layer 103, a pattern transfer layer 104, a second axial layer 105, a first mask layer 106, an etch stop layer 107, a first axial layer 108, a SOC (Spin-On Carbon) layer 109, a BARC (Bottom Anti-Reflective Coating) layer 110, and a photoresist layer 111. The second mask layer 103 is used to form a patterned mask layer in the part to be etched. Based on the aforementioned film structure, after etching and deposition processes, the desired patterned mask layer 20 can be formed on the substrate 101, and this patterned mask layer 20 has a relatively high pattern density. It should be noted that this embodiment only uses self-aligned quadruple patterning (SAQP) as an example; however, the present invention is not limited to this, and other methods of forming patterned mask layers are also feasible.

[0062] like Figure 5a As shown, based on the aforementioned film structure, the photoresist layer 111 can be patterned into a photoresist layer through exposure and development processes, such as... Figure 5b and Figure 5c As shown, by using etching, the pattern of the photoresist layer 111 can be sequentially transferred to the BARC layer 110, the SOC layer 109, and the first axial layer 108, and is stopped by the etching stop layer 107. Then, as... Figure 5dAs shown, by means of deposition, a deposition layer 112 can be formed on the outer wall of the patterned first core layer, and as shown Figure 5e As shown, by means of etching, the portion of the deposition layer 112 on the top of the patterned first core layer is removed, so as to form a sidewall 113 on both sides of each structure in the patterned first core layer. Then, as shown Figure 5f As shown, the patterned first core layer is removed, so as to achieve the purpose of micro-etching and increasing the pattern density. Then, as shown Figure 5g As shown, by means of etching, the pattern (i.e. the sidewall 113) with doubled pattern density is transferred to the first mask layer 106, and as shown Figures 5h-5j As shown, by means of further etching, the pattern of the patterned first mask layer is transferred to the second core layer 105, so as to form a patterned second core layer, and as shown Figure 5k and Figure 5l As shown, by means of deposition, a second deposition layer 114 is formed on the outer side of each structure in the patterned core layer, and by means of etching, the portion of the second deposition layer 114 on the top of the patterned second core layer is removed, so as to form a second sidewall 115 on both sides of the patterned second core layer, and as shown Figure 5m As shown, after the patterned second core layer is removed, the pattern density can be further doubled, so as to be four times of the initial pattern density. Then, by taking the second sidewall 115 as a mask structure, the pattern can be transferred to the pattern transfer layer 104 and the second mask layer 103 in sequence, and in the case that the transition layer 102 is provided, the pattern can be further transferred to the transition layer 102. In the above process, as shown Figure 5m As shown, by transferring the pattern formed above the pattern transfer layer 104 to the second mask layer 103, a patterned mask layer 20 can be formed. Based on this, by taking the patterned mask layer as a mask structure, the substrate 101 is etched, so as to form a plurality of isolation grooves 12 on the substrate 101, thereby forming a target etching layer 10.

[0063] In the process of forming the patterned mask layer by means of the self-aligned multiple pattern technology, in order to further improve the pattern quality, when the plurality of isolation grooves 12 with a preset depth have been formed on the substrate 101, the pattern transfer layer 104 can still have a portion remaining, i.e. when the target etching layer 10 is formed, the thickness of the patterned pattern transfer layer 50 is still greater than 0. In other words, in the embodiment of the present application, as shown Figure 6b As shown, when the pattern is transferred to the mask layer 103 and the etching work of the isolation groove 13 on the substrate 101 is completed, the patterned pattern transfer layer 50 still has at least a portion remaining, which can further improve the pattern quality formed on the target etching layer 10.

[0064] Based on any of the above processing methods, the embodiment of the present application further discloses a semiconductor structure formed by any of the above processing methods.

[0065] The embodiment of the present application further provides a semiconductor process equipment, which comprises a processor, a memory, a program or instructions stored in the memory and executable on the processor, the program or instructions being executed by the processor to realize each process of the above-mentioned processing method embodiment and achieve the same technical effects. To avoid repetition, details are not described herein.

[0066] The embodiment of the present application further provides a storage medium, which stores a program or instructions, the program or instructions being executed by the processor to realize each process of the processing method embodiment provided by any one of the above-mentioned embodiments and achieve the same technical effects. To avoid repetition, details are not described herein.

[0067] The processor is the processor in the semiconductor process equipment in the above-mentioned embodiments. The storage medium comprises a computer storage medium, such as a computer read-only memory (ROM), a random access memory (RAM), a magnetic disk or an optical disk.

[0068] It should be noted that, in this document, the term “comprising” or “including” or any other variant thereof is intended to cover non-exclusive inclusion, so that a process, method, article or apparatus including a series of elements not only includes those elements, but also includes other elements not explicitly listed or inherent to such a process, method, article or apparatus. Without more limitations, the element defined by the statement “comprising a” does not exclude the presence of additional identical elements in the process, method, article or apparatus including the element. In addition, it should be pointed out that the scope of the method and apparatus in the embodiments of the present application is not limited to the order of performing functions shown or discussed, but can also include performing functions in a substantially simultaneous manner or in a reverse order, for example, the described method can be performed in an order different from that described, and various steps can also be added, omitted or combined. In addition, the features described with reference to some examples can be combined in other examples.

[0069] The embodiments of the present application are described above in combination with the drawings, but the present application is not limited to the above-mentioned specific embodiments, the above-mentioned specific embodiments are only illustrative and not restrictive, and a person of ordinary skill in the art can make many forms under the inspiration of the present application without departing from the scope of the present application and the scope protected by the claims.

Claims

1. A method of processing a semiconductor structure, characterized by, The method comprises the following steps: providing a to-be-etched piece, wherein the to-be-etched piece comprises a target etching layer (10), a patterned mask layer (20) and a dielectric structure (30), the target etching layer has a plurality of isolation grooves (12), the patterned mask layer (20) is arranged above the target etching layer (10), the dielectric structure (30) is filled in the patterned mask layer (20) and each of the isolation grooves (12), and a top surface of the dielectric structure (30) is flush with a top surface of the patterned mask layer (20), the patterned mask layer (20) is used as a mask structure in the process of forming a plurality of the isolation grooves (12) on the target etching layer (10); removing part of the dielectric structure filled in the patterned mask layer, so that the patterned mask layer is exposed as a whole; removing the patterned mask layer; removing part of the remaining dielectric structure to a preset depth.

2. The method of claim 1, wherein, The step of removing part of the dielectric structure filled in the patterned mask layer comprises: stopping etching of the dielectric structure at a position flush with a bottom of the patterned mask layer by controlling an etching time of a first etching step.

3. The method of claim 1 wherein, The step of providing the to-be-etched piece comprises: forming the patterned mask layer on a substrate; etching the substrate by using the patterned mask layer, and forming a plurality of fin structures and isolation grooves on the substrate to form a target etching layer, the isolation grooves are used to electrically isolate two adjacent fin structures; forming a dielectric structure between the target etching layer and the patterned mask layer by a deposition step.

4. The method of claim 3, wherein The step of forming the dielectric structure between the target etching layer and the patterned mask layer by the deposition step comprises: forming a dielectric cover layer on the target etching layer and the patterned mask layer by the deposition step, an upper surface of the dielectric cover layer is higher than an upper surface of the patterned mask layer; chemically mechanically polishing the dielectric cover layer until the patterned mask layer is exposed to form the dielectric structure.

5. The method of claim 4, wherein, The method further comprises the following steps between the step of forming the dielectric cover layer and the step of chemically mechanically polishing the dielectric cover layer: performing an annealing treatment on the dielectric cover layer.

6. The method of claim 3, wherein The step of removing part of the remaining dielectric structure to a preset depth comprises: removing part of the remaining dielectric structure to a preset depth by a second etching step to expose the fin structure.

7. The method of claim 3, wherein The to-be-etched piece further comprises a patterned transition layer arranged between the fin structure and the patterned mask layer.

8. The processing method according to claim 3, wherein: the patterned mask layer is formed by using a self-aligned multiple pattern technology.

9. The method of claim 8, wherein, The patterned mask layer is provided with a pattern transfer layer on a side away from the target etching layer, and a thickness of the pattern transfer layer is greater than 0 when the substrate is formed with a plurality of isolation grooves of preset depths.

10. A semiconductor process apparatus, characterized by, The apparatus comprises a processor, a memory and a program or instructions stored in the memory and executable on the processor, and the program or instructions are executed by the processor to implement the steps of the processing method according to any one of claims 1 to 9.

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