Semiconductor device structure and forming method thereof

Abstract

The invention relates to a semiconductor device structure and a forming method thereof. The embodiment of the invention relates to a semiconductor device structure. The structure includes a substrate, an insulating material disposed on the substrate, a first fin structure extending upwardly from the substrate through the insulating material, and a second fin structure extending upwardly from the substrate through the insulating material, where the first fin structure and the second fin structure extend in a first direction. The structure further includes an isolation trench structure disposed between the first fin structure and the second fin structure, the isolation trench structure extending in a second direction perpendicular to the first direction, where the isolation trench structure has a bottom portion in contact with the top surface of the substrate, and the bottom of the isolation trench structure and the top surface of the substrate define a substantially flat interface.

Description

Technical Field

[0001] The present disclosure relates to semiconductor device structures and methods of forming the same. Background Art

[0002] As the semiconductor industry advances to nanotechnology process nodes in pursuit of higher device density, higher performance, and lower cost, challenges from both manufacturing and design issues have led to the development of multi-gate devices such as fin field-effect transistors (FinFETs) and gate-all-around (GAA) transistors. To continue to provide the required scaling and increased density for multi-gate devices in advanced technology nodes, it is necessary to continue to reduce the gate pitch. Various schemes (e.g., poly on diffusion edge (PODE) and continuous poly on diffusion edge (CPODE)) have been used to reduce the gate pitch while preventing leakage current between transistors. However, it has been observed that parasitic fin bipolar transistors can be formed during the etching process, which results in the formation of an EPI-substrate-EPI leakage path.

[0003] Therefore, there is a need to improve the processing and manufacturing of ICs. Summary of the Invention

[0004] According to one aspect of the present disclosure, a semiconductor device structure is provided, including: a substrate; an insulating material disposed on the substrate; a first fin structure extending upward from the substrate through the insulating material; a second fin structure extending upward from the substrate through the insulating material, the first fin structure and the second fin structure extending in a first direction; and an isolation trench structure disposed between the first fin structure and the second fin structure, the isolation trench structure extending in a second direction perpendicular to the first direction; wherein the isolation trench structure has a bottom surface in contact with the top surface of the substrate, and the bottom surface of the isolation trench structure and the top surface of the substrate define a substantially flat interface.

[0005] According to one aspect of the present disclosure, a semiconductor device structure is provided, including: a substrate; an insulating material disposed on the substrate, the insulating material and a first portion of the substrate defining a first interface; a first fin structure extending upward from the substrate through the first portion of the insulating material; a second fin structure extending upward from the substrate through a second portion of the insulating material; and an isolation trench structure disposed between the first fin structure and the second fin structure, wherein at least some portions of the isolation trench structure are separated from each other by a third portion of the insulating material.

[0006] According to one aspect of the present disclosure, a method for forming a semiconductor device structure is provided, including: forming a first fin structure and a second fin structure from a substrate, the first fin structure and the second fin structure each including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately; forming an insulating material on the substrate; forming a metal gate structure on the insulating material and on a portion of each of the first fin structure and the second fin structure; removing a portion of the metal gate structure above the first fin structure and the second fin structure; removing some portions of the first fin structure and the second fin structure, the insulating material, and the substrate through one or more etching processes to form isolation trenches having a substantially flat bottom surface extending between opposite sidewalls of the isolation trenches; and filling the isolation trenches with a dielectric material. BRIEF DESCRIPTION OF THE DRAWINGS

[0007] Aspects of the present disclosure are best understood from the following detailed description when read with the accompanying drawings. It should be noted that, in accordance with standard practice in the industry, various features are not drawn to scale. In fact, for the sake of clarity of discussion, the dimensions of various features may be arbitrarily increased or decreased.

[0008] Figures 1 to 6 is a perspective view of various stages of manufacturing a semiconductor device structure according to some embodiments.

[0009] Figures 7A to 10A is along Figure 6 a cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line A-A according to some embodiments.

[0010] Figures 7B to 10B is along Figure 6 a cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line B-B according to some embodiments.

[0011] Figures 7C to 10C is along Figure 6 a cross-sectional side view of various stages of manufacturing a semiconductor device structure taken along line C-C according to some embodiments.

[0012] Figures 11A - 11B to Figures 18A - 18B and Figures 21A - 21B to Figures 25A - 25B are cross-sectional side views of one of the various stages of manufacturing Figure 10A and Figure 10B a semiconductor device structure according to some embodiments, Figure 10A and Figure 10B respectively showing a plurality of fin structures arranged in the X direction and the Y direction.

[0013] Figure 18B - 1Shows a part of a substrate as shown in accordance with some embodiments Figure 18B An enlarged view of a part of the substrate shown in

[0014] Figure 19 And Figure 20 Shows an embodiment in which an isolation trench is etched to have a bottom that extends to a certain depth into the well region of the substrate, in accordance with some embodiments.

[0015] Figure 19 - 1 Shows a part of a substrate as shown in accordance with some embodiments Figure 19 An enlarged view of a part of the substrate shown in

[0016] Figure 26 And Figure 27 Show cross-sectional views of semiconductor device structures in accordance with the embodiments shown in Figure 19 And Figure 20 respectively.

[0017] Figure 28 Is a top view of a semiconductor device structure as shown in Figure 25A And Figure 25B in accordance with some embodiments.

[0018] Figure 29A 、 Figure 29B 、 Figure 29C Are cross-sectional views of a semiconductor device structure taken along lines D-D, E-E, and F-F of Figure 28 respectively.

[0019] Figures 30 to 36 Shows an alternative embodiment in accordance with some embodiments, in which a portion of the insulating material remains within the isolation trench structure and on the top surface of the exposed substrate.

[0020] Figures 37 to 43 Shows an alternative embodiment in accordance with some embodiments, in which a portion of the insulating material remains within the isolation trench structure and is disposed away from the top surface of the exposed substrate.

[0021] Figure 44A And Figures 44B to 49A And Figure 49B Are cross-sectional views of one of the various stages of manufacturing a semiconductor device structure in accordance with some alternative embodiments.

[0022] Figure 50 Is an enlarged view of a part of a substrate as shown in Figure 49B in accordance with some embodiments.

[0023] Figure 51 Shows an embodiment in which the isolation trench structure has a bottom that is at substantially the same height as the top surface of the substrate, in accordance with some embodiments.

[0024] Figure 51 - 1 shows a magnified view of a portion of the substrate shown in Figure 51 in accordance with some embodiments.

[0025] Figure 52 shows a cross-sectional view of a semiconductor device structure in accordance with an alternative embodiment.

[0026] Figure 53 shows a cross-sectional view of a semiconductor device structure in accordance with an alternative embodiment.

[0027] Figure 54 shows in accordance with some embodiments Figure 52 and Figure 53 a magnified view of a portion of the substrate shown in DETAILED DESCRIPTION

[0028] The following disclosure provides many different embodiments or examples for implementing different features of the provided subject matter. To simplify the present disclosure, specific examples of components and arrangements are described below. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first feature over or on a second feature may include embodiments in which the first and second features are formed in direct contact, and may also include embodiments in which additional features may be formed between the first and second features such that the first and second features may not be in direct contact. Additionally, the present disclosure may repeat reference numerals and / or letters in the various examples. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0029] Furthermore, spatially relative terms (such as, "beneath", "below", "lower", "above", "on", "upper", etc.) may be used herein to facilitate describing one element or feature's relationship to another (one or more) element(s) or (one or more) feature(s) shown in the figures. In addition to the orientation depicted in the figures, spatially relative terms are also intended to encompass different orientations of the device in use or operation. The device may be oriented in other directions (rotated 90 degrees or at other orientations), and the spatially relative descriptors used herein may be interpreted accordingly.

[0030] As integrated circuits are scaled down, the epitaxial critical dimension (EPI CD, which refers to the spacing between epitaxial regions) becomes smaller and smaller. A small EPI CD makes it challenging to etch trenches in an insulating structure without damaging adjacent structures (such as epitaxial source / drain features). Exemplary insulating structures can include a Continuous-Poly-On-Diffusion-Edge (CPODE) structure that removes a portion or all of a selected fin structure and replaces the selected fin structure with an insulating material to form isolation trenches. The CPODE structure avoids leakage current from passing through epitaxial source / drain features, transistors, and the silicon substrate. Embodiments of the present disclosure can be applied to other devices that can include CPODE or CMODE structures, such as planar FETs, Fin-FETs, horizontal gate-all-around (HGAA) FETs, vertical gate-all-around (VGAA) FETs, and other suitable devices.

[0031] Figures 1 to 54 An exemplary process for manufacturing a semiconductor device structure 100 in accordance with embodiments of the present disclosure is shown. It should be understood that additional operations can be provided before, during, and after the Figures 1 to 54 process shown, and for additional embodiments of the method, some of the operations described below can be replaced or eliminated. The order of the operations / processes is not restrictive and is interchangeable.

[0032] Figures 1 to 6 is a perspective view of various stages of manufacturing a semiconductor device structure 100 in accordance with some embodiments. As Figure 1 shown, the semiconductor device structure 100 includes a semiconductor layer stack 104 formed over a front surface of a substrate 101. The substrate 101 can be a semiconductor substrate. The substrate 101 can include a crystalline semiconductor material such as, but not limited to, silicon (Si), germanium (Ge), silicon-germanium (SiGe), gallium arsenide (GaAs), indium antimonide (InSb), gallium phosphide (GaP), gallium antimonide (GaSb), indium aluminum arsenide (InAlAs), indium gallium arsenide (InGaAs), gallium antimonide phosphide (GaSbP), gallium arsenide antimonide (GaAsSb), and indium phosphide (InP). In some embodiments, the substrate 101 is a silicon-on-insulator (SOI) substrate having an insulating layer (not shown) disposed between two silicon layers for enhanced insulation. In one aspect, the insulating layer is an oxygen-containing layer.

[0033] The substrate 101 can include various regions that have been doped with impurities (e.g., dopants having p-type or n-type conductivity). Depending on the circuit design, the dopants can be, for example, phosphorus for an n-well region and boron for a p-well region.

[0034] The semiconductor layer stack 104 includes alternating semiconductor layers made of different materials to facilitate the formation of a nanostructured channel in a multi-gate device, such as a nanostructured channel FET. In some embodiments, the semiconductor layer stack 104 includes a first semiconductor layer 106 and a second semiconductor layer 108. In some embodiments, the semiconductor layer stack 104 includes alternating first semiconductor layers 106 and second semiconductor layers 108. The first semiconductor layer 106 and the second semiconductor layer 108 are made of semiconductor materials having different etch selectivities and / or oxidation rates. For example, the first semiconductor layer 106 may be made of Si, while the second semiconductor layer 108 may be made of SiGe. In some examples, the first semiconductor layer 106 may be made of SiGe, while the second semiconductor layer 108 may be made of Si. Alternatively, in some embodiments, either of the semiconductor layers 106, 108 may be or include other materials, such as Ge, SiC, GeAs, GaP, InP, InAs, InSb, GaAsP, AlInAs, AlGaAs, InGaAs, GaInP, GaInAsP, or any combination thereof. In some embodiments, the second semiconductor layer 108 may be etched during the process and replaced with other materials, such as SiO or SiN.

[0035] The first semiconductor layer 106 and the second semiconductor layer 108 are formed by any suitable deposition process, such as epitaxy. By way of example, epitaxial growth of the layers of the semiconductor layer stack 104 may be performed by a molecular beam epitaxy (MBE) process, a metalorganic chemical vapor deposition (MOCVD) process, and / or other suitable epitaxial growth processes.

[0036] The first semiconductor layer 106 or a portion thereof may form the (one or more) nanostructured channels of the semiconductor device structure 100 in a subsequent manufacturing stage. The term nanostructure is used herein to denote any material portion having nanoscale or even micron-scale dimensions and having an elongated shape, regardless of the cross-sectional shape of the portion. Thus, the term refers to elongated material portions having circular and substantially circular cross-sections, as well as beam-shaped or bar-shaped material portions including, for example, cylindrical or substantially rectangular cross-sections. The (one or more) nanostructured channels of the semiconductor device structure 100 may be surrounded by gate electrodes. The semiconductor device structure 100 may include nanostructured transistors. The nanostructured transistors may be referred to as nanosheet transistors, nanowire transistors, gate-all-around (GAA) transistors, multi-bridge channel (MBC) transistors, or any transistor having a gate electrode surrounding the channel. The use of the first semiconductor layer 106 to define one or more channels of the semiconductor device structure 100 is further discussed below.

[0037] Each first semiconductor layer 106 may have a thickness in the range between about 5 nm and about 30 nm. The thickness of each second semiconductor layer 108 may be equal to, less than, or greater than the thickness of the first semiconductor layer 106. In some embodiments, each second semiconductor layer 108 has a thickness in the range between about 2 nm and about 50 nm. As Figure 1 shown, three first semiconductor layers 106 and three second semiconductor layers 108 are alternately arranged, which is for illustrative purposes only and is not intended to limit the scope specifically recited in the claims. It can be understood that any number of first semiconductor layers 106 and second semiconductor layers 108 can be formed in the semiconductor layer stack 104, and the number of layers depends on the predetermined number of channels of the semiconductor device structure 100.

[0038] In Figure 2 this, fin structures 112 are formed from the semiconductor layer stack 104. Each fin structure 112 has an upper portion including semiconductor layers 106, 108 and a substrate portion 116 formed from the substrate 101. The fin structures 112 can be formed by patterning a hard mask layer (not shown) formed on the semiconductor layer stack 104 using multi-patterning operations including a lithography process and an etching process. The etching process may include dry etching, wet etching, reactive ion etching (RIE), and / or other suitable processes. The lithography process may include forming a photoresist layer (not shown) over the hard mask layer, exposing the photoresist layer to a pattern, performing a post-exposure bake process, and developing the photoresist layer to form a mask element including the photoresist layer. In some embodiments, patterning the photoresist layer to form the mask element may be performed using an electron beam (e-beam) lithography process. The etching process forms trenches 114 through the hard mask layer, through the semiconductor layer stack 104, and into the substrate 101 in unprotected areas, leaving multiple extended fin structures 112. The trenches 114 extend in the X direction. Dry etching (e.g., RIE), wet etching, and / or a combination thereof can be used to etch the trenches 114. In some embodiments, each fin structure 112 has a longitudinal axis in the X direction.

[0039] In Figure 3In [the process], after forming the fin structure 112, an insulating material 118 is formed on the substrate 101. The insulating material 118 fills the trenches 114 between adjacent fin structures 112 until the fin structures 112 are embedded in the insulating material 118. Then, a planarization operation (such as a chemical mechanical polishing (CMP) method and / or an etch-back method) is performed such that the top of the fin structures 112 is exposed. The insulating material 118 can be made of silicon oxide, silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN, fluorinated silicate glass (FSG), a low-K dielectric material, or any suitable dielectric material. The insulating material 118 can be a multi-layer dielectric structure. The insulating material 118 can be formed by any suitable method, such as low-pressure chemical vapor deposition (LPCVD), plasma-enhanced CVD (PECVD), or flowable CVD (FCVD).

[0040] In Figure 4 [the process], the insulating material 118 is recessed to form the isolation region 120. The recessing of the insulating material 118 exposes some portions of the fin structures 112, such as the semiconductor layer stack 104. The recessing of the insulating material 118 exposes the trenches 114 between adjacent fin structures 112. The isolation region 120 can be formed using a suitable process (such as a dry etching process, a wet etching process, or a combination thereof). The top surface of the insulating material 118 can be flush with or lower than the surface of the second semiconductor layer 108 that contacts the substrate portion 116 formed from the substrate 101.

[0041] In Figure 5 [the process], one or more sacrificial gate structures 130 (only one is shown) are formed on the semiconductor device structure 100. The sacrificial gate structure 130 is formed on a portion of the fin structure 112. Each sacrificial gate structure 130 can include a sacrificial gate dielectric layer 132, a sacrificial gate electrode layer 134, and a mask layer 136. The sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136 can be formed by: sequentially depositing the covering layers of the sacrificial gate dielectric layer 132, the sacrificial gate electrode layer 134, and the mask layer 136, and then patterning these layers into the sacrificial gate structure 130. Then, gate spacers 138 are formed on the sidewalls of the sacrificial gate structure 130. For example, the gate spacers 138 can be formed by conformally depositing one or more layers of the gate spacers 138 and anisotropically etching the one or more layers. In some embodiments, the gate spacers 138 are also formed on the sidewalls of the exposed portions of the fin structures 112. Although only one sacrificial gate structure 130 is shown, in some embodiments, two or more sacrificial gate structures 130 can be arranged along the X direction.

[0042] The sacrificial gate dielectric layer 132 may include one or more dielectric materials, such as silicon oxide-based materials. The sacrificial gate electrode layer 134 may include silicon, such as polysilicon or amorphous silicon. The mask layer 136 may include more than one layer, such as an oxide layer and a nitride layer. The gate spacers 138 may be made of a dielectric material (such as silicon oxide, silicon nitride, silicon carbide, silicon oxynitride, SiCN, silicon oxycarbide, SiOCN, and / or a combination thereof).

[0043] The portion of the fin structure 112 covered by the sacrificial gate electrode layer 134 of the sacrificial gate structure 130 serves as the channel region of the semiconductor device structure 100.

[0044] In Figure 6 , the portions of the fin structure 112 not covered by the sacrificial gate structure 130 and the gate spacers 138 are recessed to a level above, at, or below the top surface of the isolation region 120. The recessing of these portions of the fin structure 112 can be accomplished by an etching process (isotropic or anisotropic etching process), and the etching process can be selective to one or more crystal planes of the substrate 101. The etching process can be a dry etching (such as RIE, NBE, etc.) or a wet etching (such as using tetramethylammonium hydroxide (TMAH), ammonium hydroxide (NH4OH), or any suitable etchant).

[0045] Figure 7A , Figure 7B and Figure 7C are cross-sectional side views of the semiconductor device structure 100 taken along lines A-A, B-B, and C-C of Figure 6 respectively.

[0046] Figure 8A , Figure 8B and Figure 8C are cross-sectional side views of one of the respective stages of manufacturing the semiconductor device structure 100 taken along lines A-A, B-B, and C-C of Figure 6 according to some embodiments. As Figure 8A shown, the edge portions of each second semiconductor layer 108 of the semiconductor layer stack 104 are horizontally removed in the X direction. The removal of the edge portions of the second semiconductor layer 108 forms cavities. In some embodiments, these portions of the second semiconductor layer 108 are removed by a selective wet etching process. In the case where the second semiconductor layer 108 is made of SiGe and the first semiconductor layer 106 is made of silicon, a wet etchant (such as, but not limited to, ammonium hydroxide (NH4OH), tetramethylammonium hydroxide (TMAH), ethylenediamine pyrocatechol (EDP), or potassium hydroxide (KOH) solution) can be used to selectively etch the second semiconductor layer 108.

[0047] After removing the edge portion of each second semiconductor layer 108, a dielectric layer is deposited in the cavity to form a dielectric spacer 144. The dielectric spacer 144 can be made of a low-K dielectric material (e.g., SiON, SiCN, SiOC, SiOCN, or SiN). The dielectric spacer 144 can be formed by first forming a conformal dielectric layer using a conformal deposition process (e.g., ALD), and then removing the portion of the conformal dielectric layer other than the dielectric spacer 144 by anisotropic etching. During the anisotropic etching process, the dielectric spacer 144 is protected by the first semiconductor layer 106. The remaining second semiconductor layer 108 is capped between the dielectric spacers 144 along the X direction.

[0048] Figure 9A , Figure 9B and Figure 9C According to some embodiments, Figure 6 AA, BB and CC of FIG. 1 are cross-sectional side views of one of the various stages of manufacturing the semiconductor device structure 100. Figure 9A and Figure 9C As shown, a source / drain (S / D) region 146 is formed from the substrate portion 116. In some embodiments, the S / D region 146 can be grown vertically and horizontally to form small planes that can correspond to the crystal planes of the material used for the substrate portion 116. In the present disclosure, the source region and the drain region can be used interchangeably, and their structures are basically the same. In addition, (one or more) source / drain regions can refer to the source or drain individually or collectively, depending on the context. The S / D region 146 can be made of one or more layers of Si, SiP, SiC and SiCP for n-channel FETs or one or more layers of Si, SiGe, Ge for p-channel FETs. For p-channel FETs, p-type dopants (e.g., boron (B)) can also be included in the S / D region 146. The S / D region 146 can be formed by an epitaxial growth method using CVD, ALD or MBE.

[0049] Figure 10A , Figure 10B and Figure 10C According to some embodiments, Figure 6 A cross-sectional side view of one of the various stages of manufacturing the semiconductor device structure 100 taken along lines AA, BB, and CC. Figure 10A , Figure 10B and Figure 10CIn [the structure], a contact etch stop layer (CESL) 162 is conformally formed on the exposed surface of the semiconductor device structure 100. The CESL 162 covers the sidewalls of the sacrificial gate structure 130, the insulating material 118, and the S / D regions 146. The CESL 162 may include an oxygen-containing material or a nitrogen-containing material, such as silicon nitride, silicon carbonitride, silicon oxynitride, carbon nitride, silicon oxide, silicon carbon oxide, etc., or a combination thereof, and may be formed by CVD, PECVD, ALD, or any suitable deposition technique. Next, an interlayer dielectric (ILD) layer 164 is formed on the CESL 162 over the semiconductor device structure 100. The material of the ILD layer 164 may include a compound containing Si, O, C, and / or H, such as silicon oxide, SiCOH, or SiOC. An organic material (such as a polymer) may also be used for the ILD layer 164. The ILD layer 164 may be deposited by a PECVD process or other suitable deposition technique. In some embodiments, after the ILD layer 164 is formed, the semiconductor device structure 100 may be heat-treated to cure the ILD layer 164.

[0050] After the ILD layer 164 is formed, a planarization operation (such as CMP) is performed on the semiconductor device structure 100 until the sacrificial gate electrode layer 134 is exposed. In some embodiments, after the planarization process, the ILD layer 164 is recessed, and a capping layer 139 is formed on the recessed ILD layer 164. The capping layer 139 may include a nitride (such as silicon nitride) to protect the ILD layer 164 during subsequent processes. A second planarization process may be performed to remove the portion of the capping layer 139 that is formed on the sacrificial gate electrode layer 134. After the planarization process, the top surfaces of the capping layer 139, the CESL 162, the gate spacers 138, and the sacrificial gate electrode layer 134 are substantially coplanar.

[0051] Figures 11A - 11B to Figures 18A - 18B and Figures 21A - 21B to Figures 25A - 25B are cross-sectional side views of one of the respective stages of manufacturing Figure 10A and Figure 10B the semiconductor device structure 100 according to some embodiments, Figure 10A and Figure 10B respectively showing a plurality of fin structures disposed along the X direction and the Y direction. In Figure 12A and Figure 12BIn, a mask structure 1302 is formed on the top surfaces of the sacrificial gate electrode layer 134, the gate spacer 138, the CESL 162, and the capping layer 139 (or the first ILD layer 164 if the capping layer 139 is not formed). The mask structure 1302 may include a hard mask 1304 and a resist layer 1306. The hard mask 1304 may be any suitable masking material. In some embodiments, the hard mask 1304 is formed of a nitrogen-containing material (such as SiN or SiCN). The resist layer 1306 may be a single-layer photoresist or a three-layer photoresist. An exemplary three-layer photoresist may include a bottom layer 1308, an intermediate layer 1310 disposed on the bottom layer 1308, and a photoresist top layer 1312 disposed on the intermediate layer 1310. The resist layer 1306 may be formed by any suitable process (such as spin coating). The bottom layer 1308 may be a bottom anti-reflective coating (BARC) layer. The intermediate layer 1310 may be a silicon-containing inorganic polymer that provides anti-reflective properties and / or hard mask properties for a lithography process. The photoresist top layer 1312 may be a DUV resist (KrF) resist, an argon fluoride (ArF) resist, an EUV resist, an electron beam (e-beam) resist, or an ion beam resist.

[0052] In Figure 13A and Figure 13B In, the photoresist top layer 1312 is patterned to form a plurality of photoresist mandrels separated from each other by openings. For ease of illustration, only two openings 1402a, 1402b are shown. The patterned photoresist top layer 1312 is used as a mask to transfer the pattern in the photoresist top layer 1312 (i.e., the openings 1402a, 1402b) to the intermediate layer 1310, the bottom layer 1308, and the mask layer 1304. The openings 1402a, 1402b define isolation trenches to be formed in the substrate portions of the fin structures 102b, 102c. The isolation trenches may be provided between adjacent active regions. The term "active region" refers to a region where a transistor is formed. As will be discussed in more detail below, the isolation trenches may be formed by performing a fin cut (or slice cut) process. The isolation trenches will be filled with a dielectric to form a continuous polysilicon (CPODE) trench at the diffusion edge. The fin cut (or slice cut) process may be referred to as a CPODE process. The term "diffusion edge" is equivalently referred to as an active edge, which is an edge adjacent to an adjacent active region. The CPODE process can be used to reduce the gate pitch, thereby increasing the density of multi-gate devices, and thus increasing the device performance required for highly scaled circuits and devices.

[0053] In Figure 14A and Figure 14B In, the photoresist top layer 1312 ( Figure 13A and Figure 13B) The patterns therein (i.e., openings 1402a, 1402b) are transferred to the mask layer 1304 to form the patterned mask layer 1304'. Then, the bottom layer 1308, the intermediate layer 1310, and the photoresist top layer 1312 are removed. The formation of the patterned mask layer 1304' can be achieved by one or more lithography processes. As a result of the one or more lithography processes, some portions of the hard mask 1304 are removed, and trench patterns 1402a', 1402b' (collectively referred to as trench pattern 1402') are formed in the patterned mask layer 1304', and a portion of the sacrificial gate electrode layer 134 is exposed. The trench patterns 1402a', 1402b' are elongated openings aligned with the sacrificial gate structure 130. Etching chemicals (e.g., CF4, CHF3, CH2F2, CHF3, C4F6, etc.) can be used to perform the removal of some portions of the hard mask 1304 (and the native oxide formed thereon). Then, the patterned mask layer 1304' can be used to protect the active regions during subsequent removal of the exposed sacrificial gate structure and fin cutting (or die cutting) processes.

[0054] In Figure 15A and 15B , the exposed sacrificial gate structure (e.g., the sacrificial gate electrode layer 134) is selectively removed to form openings 1602a, 1602b (collectively referred to as openings 1602). The openings 1602 expose the gate spacers 138 and the sacrificial gate dielectric layer 132. The removal of the exposed sacrificial gate structure can be performed by a selective etching process that removes the sacrificial gate electrode layer 134 but substantially does not affect the gate spacers 138 and the sacrificial gate dielectric layer 132. The sacrificial gate dielectric layer 132 protects the first semiconductor layer 106 and the second semiconductor layer 108 during the etch-back process. In some embodiments, the sacrificial gate dielectric layer 132 can also be removed during the selective etching process. In some embodiments, the etching chemical is selective to the sacrificial gate structure to be etched while minimizing the etching of the surrounding dielectric layers (e.g., the insulating material 118, the gate spacers 138, the CESL 162, and the first ILD layer 164). In some embodiments, chlorine-containing gases (e.g., SiCl4, BCl3, Cl2, CHCl3, CCl4, and / or BCl3), bromine-containing gases (e.g., HBr and / or CHBr3), iodine-containing gases, other suitable gases, and / or plasmas and / or combinations thereof can be used to remove the sacrificial gate structure 130. In some embodiments, the sacrificial gate electrode layer 134 has a top surface flush with the top of the sacrificial gate dielectric layer 132. The following fin cutting or die cutting process will remove the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132 in the CPODE trenches.

[0055] In Figure 16A andFigure 16B In this case, an etching process is performed to remove the sacrificial gate dielectric layer 132. The etching process can be a dry etching process, a wet etching process, or a combination thereof. The etching process selectively removes the sacrificial gate dielectric layer 132 without affecting the first semiconductor layer 106, the second semiconductor layer 108, and the sacrificial gate electrode layer 134.

[0056] Figure 17A and Figures 17B to 24A and Figure 24B illustrates the process of extending the opening 1602 into the substrate portion of the fin structures 102b, 102c for forming isolation trenches. In particular, the isolation trenches (and subsequent CPODE structures) are formed such that the exposed substrate 101 has a substantially flat top surface, which prevents the top of the exposed substrate from forming fin-like structures and becoming parasitic bipolar junction transistors (BJTs). In Figure 17A and Figure 17B a first semiconductor etching process 141 is performed to remove the first semiconductor layer 106 and the second semiconductor layer 108 (and in some cases, a small portion of the insulating material 118 exposed due to ion bombardment), thereby forming a first section of the isolation trench 1802. The first semiconductor etching process 141 is a fin cutting (or slice cutting) process. The first semiconductor etching process 141 is performed using the patterned mask layer 1304' as an etching mask. The first semiconductor etching process 141 can be a dry etching process, a reactive ion etching (RIE) process, and / or other suitable processes. In some embodiments, the first semiconductor etching process 141 is an anisotropic etching (directional etching) process. The first semiconductor etching process 141 is performed such that the exposed first semiconductor layer 106, the second semiconductor layer 108, and some portions of the substrate 101 forming the fin structures 102b, 102c are selectively removed. A portion of the insulating material 118 surrounding the fin structures 102b, 102c can also be removed. In some embodiments, a self-aligned CPODE etching process is used to achieve the removal of the exposed first semiconductor layer 106, the second semiconductor layer 108, and some portions of the substrate 101. The self-aligned CPODE etching process is configured to have a high etching selectivity such that the etching rate of the first semiconductor layer 106 and the second semiconductor layer 108 is greater than the etching rate of the inner spacer 144. As a result, after the fin cutting process, the inner spacer 144 remains substantially intact.

[0057] As a result of the first semiconductor etching process 141, the isolation trenches 1802a, 1802b (collectively referred to as the isolation trench 1802) are formed and extended into some portions of the substrate 101 forming the fin structures 102b, 102c ( Figure 17A)。In various embodiments, a first semiconductor etch process 141 is performed such that first segments of the isolation trenches 1802a, 1802b are formed to have straight and symmetric sidewall profiles (with respect to an imaginary line passing through the centers of the respective isolation trenches 1802a, 1802b in the depth direction of the isolation trenches 1802a, 1802b). In some embodiments, the isolation trenches 1802a, 1802b may have a first depth D1, which is defined by the distance between the topmost first semiconductor layer 106 and the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b. The first depth D1 may be selected according to a desired level of the narrowest critical dimension (CD). In some embodiments, the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b is at substantially the same height as the bottom of the epitaxial S / D feature 146. In some embodiments, the bottom surface 1802bs1 of the isolation trenches 1802a, 1802b is lower than the top surface of the well portion of the substrate 101. In some embodiments, the first depth D1 is substantially equal to the height of the epitaxial S / D feature.

[0058] The self-aligned CPODE etch process can be achieved by plasma etching using bromine-based etch chemicals (and / or chlorine-based etch chemicals) and oxygen-based chemicals. Exemplary bromine-based etch chemicals can include, but are not limited to, HBr, Br2, BBr3, etc. or combinations thereof. Exemplary chlorine-based etch chemicals can include, but are not limited to, Cl2, CHCl3, CCl4, BCl3, etc. or combinations thereof. Exemplary oxygen-based etch chemicals can include, but are not limited to, O2, CO2, O3, water vapor, etc. or combinations thereof. In some embodiments, the plasma etching is performed in a high-density plasma processing chamber using an inductively coupled plasma (ICP) or a dipole antenna plasma source. In some embodiments, a resonant antenna plasma source or an electron cyclotron resonance (ECR) plasma source can also be used to achieve low-pressure operation (e.g., about 0.2 ± 0.05 mTorr). The plasma can be driven by an RF power generator using AC current operating at multiple 13.56 MHz frequencies. The processing chamber can be operated at a pressure in the range of about 0.2 mTorr to about 150 mTorr and a temperature in the range of about 20 degrees Celsius to about 120 degrees Celsius. The RF power generator is operated to provide a source power between about 100 W and about 2500 W. Higher directionality can be achieved by adding bias power to the substrate pedestal in the processing chamber. In this case, a DC bias power operating in the range of about 0 V to about 1000 V (e.g., about 50 V to 150 V) can be used. In some cases, pulsed plasma etching can be used. In this case, the output of the power generator can be controlled by a pulsed signal with a duty cycle in the range of about 5% to 95%. Alternatively, the self-aligned CPODE etch process can use only bias power (with zero source power) to enhance etch directionality.

[0059] Although bromine-based or chlorine-based etch chemicals have been discussed, other etch chemicals can also be used, such as fluorine-based etch chemicals. Exemplary fluorine-containing gases can include, but are not limited to, CF4, SF6, CH2F2, C2H4F2, CHF3, C2F6, NF3, etc. or combinations thereof. Alternatively, the etchant used in the first semiconductor etch process 141 can be a fluorine / chlorine-based etch chemical, a fluorine / bromine-based etch chemical, or any combination thereof.

[0060] In some embodiments, the plasma etching can be performed in a plasma etch chamber having in-situ ALD capabilities for forming silicon oxide or silicon nitride.

[0061] In Figure 18A and Figure 18BIn this case, a second semiconductor etching process 147 is performed to further remove the exposed insulating material 118 and the substrate portions forming the fin structures 102b, 102c. Similarly, the second semiconductor etching process 147 is performed such that the second sections of the isolation trenches 1802a, 1802b are formed to have straight and symmetric sidewall profiles (with respect to an imaginary line passing through the centers of the respective isolation trenches 1802a, 1802b in the depth direction of the isolation trenches 1802a, 1802b). The isolation trenches 1802 are formed with a uniform CD in the depth direction. In particular, the second semiconductor etching process 147 is performed such that the bottom of the isolation trenches 1802 (or in other words, the top surface 101ts of the exposed substrate 101) is flat or substantially flat. The term "flat" or "substantially flat" as described in the present disclosure means that the surface is substantially planar, and the standard deviation from the flat surface above this surface is less than about 5 nm to about 20 nm. The substrate 101 with a flat top surface 101ts does not form a parasitic bipolar junction transistor, which would otherwise be generated in a conventional semiconductor etching process where the substrate 101 is etched to form high aspect ratio fin structures in the well region, resulting in the formation of an EPI - substrate - EPI leakage path.

[0062] The second semiconductor etching process 147 is performed using an etching chemical similar to that of the first semiconductor etching process 141. The substrate portions of the fin structures 102b, 102c can be removed by the second semiconductor etching process 147, which can be a plasma etching process including HBr and / or Cl2. In some embodiments, O2 and / or CO2 can be added to the HBr - and / or Cl2 - based plasma to facilitate the dissociation of plasma by - products. In some embodiments, the plasma etching process can be a high - density plasma process using process conditions similar to those of the first semiconductor etching process 141. The second semiconductor etching process 147 is performed to extend the isolation trenches 1802a, 1802b to a height substantially equal to the height of the interface 137 defined by the substrate 101 and the insulating material 118. The isolation trenches 1802a, 1802b have a second depth D2 measured from the topmost first semiconductor layer 106 to the bottom surface 1802bs2 of the isolation trenches 1802a, 1802b. In other words, the depth of each isolation trench 1802a, 1802b extends from the first depth D1 to the second depth D2. The isolation trenches 1802 with a uniform CD in the depth direction can be obtained through a cyclic process. For example, the Figure 17A and Figures 17B to 18A and Figure 18B processes in can be repeated until the isolation trenches 1802a, 1802b reach a predetermined height.

[0063] One or more etch conditions can be controlled to achieve a low selectivity etch between silicon (e.g., substrate 101) and silicon oxide (e.g., insulating material 118). For example, during the second semiconductor etch process 147, a low pressure process (e.g., a chamber pressure below about 50 mTorr) and / or a high bias power to the substrate pedestal (e.g., greater than 300 V) can be utilized to compensate for the etch selectivity required to remove the insulating material 118 and the substrate portions of the fin structures 102b, 102c. In some embodiments, the bias power used during the second semiconductor etch process 147 is greater than the bias power used during the first semiconductor etch process 141.

[0064] In some embodiments, boron trichloride (BCl3) etc. can be used to enhance the etch selectivity of silicon oxide, thereby achieving a low selectivity etch between silicon and silicon oxide. In some embodiments, the bottom surfaces 1802bs2 of the isolation trenches 1802a, 1802b can be at a height within the well region or the accumulation region of the substrate 101. The term "accumulation region" refers to a non-conductive region in the substrate 101 that is lower than the depletion region (a conductive region located at / near the well region of the substrate 101). In any case, the second depth D2 is sufficient to block the path of leakage current through the epitaxial source / drain features and the silicon substrate. In some embodiments, the second depth D2 can be in the range between about 60 nm and about 200 nm.

[0065] In some embodiments, after the second semiconductor etch process 147, the top surface 101ts of the exposed substrate 101 can have a wavy profile. Figure 18B - 1 A magnified view of a portion of the substrate 101 shown in Figure 18B is shown. It should be understood that Figure 18B - 1 the embodiments of Figure 18B can be applied to

[0066] the embodiments of Figure 19 any one or more of the embodiments shown in the present disclosure, wherein the bottom of the isolation trench 1802 is at the height of the interface 137 defined by the substrate 101 and the insulating material 118. Accordingly, the subsequent CPODE structure has a bottom with a wavy profile.

[0066] In some embodiments, the second semiconductor etch process 147 is performed such that the bottom surface of the isolation trench 1802 is at a height lower than the interface 137 defined by the substrate 101 and the insulating material 118. In some cases, the bottom surface is at a height within the well region of the substrate 101. Figure 19An embodiment is shown in which the isolation trench 1802 is etched to have a bottom 1802bs3 that extends to a certain depth into the well region of the substrate 101. Such a recess in the substrate 101 can be obtained by controlling one or more etching conditions to achieve a low selectivity etching between silicon (e.g., the substrate 101) and silicon oxide (e.g., the insulating material 118). For example, during the second semiconductor etching process 147, a low-pressure process (e.g., a chamber pressure below about 50 mTorr) and / or a high bias power to the substrate pedestal (e.g., greater than 300 V) can be utilized to compensate for the etching selectivity required to remove the insulating material 118 and the substrate portions of the fin structures 102b, 102c. In some embodiments, the bias power used during the second semiconductor etching process 147 is greater than the bias power used during the first semiconductor etching process 141.

[0067] In some embodiments, the second semiconductor etching process 147 is performed such that a portion of the insulating material 118 is retained and protrudes inwardly above the sidewall 134s of the sacrificial gate electrode layer 134, as Figure 20 shown. Such a protrusion 118p of the insulating material 118 can be formed by the protection of the patterned mask layer 1304' during the second semiconductor etching process 147. Similarly, the isolation trench 1802 is etched to have a bottom that extends to a certain depth into the well region of the substrate 101. Thus, the bottom surface 1802bs4 is at a height below the interface 137 defined by the substrate 101 and the insulating material 118.

[0068] In Figure 19 or Figure 20 any of the embodiments, the top surface 101ts of the substrate 101 can have a wavy profile. Figure 19 - 1 An enlarged view of a portion of the substrate 101 shown in Figure 19 is shown in accordance with some embodiments. In some embodiments, the exposed substrate 101 is etched to have peaks 101p and valleys 101v. The peak 101p can have a distance D3 measured from the highest point at the top surface 101ts of the exposed substrate 101 to the interface 137 (defined by the substrate 101 and the insulating material 118), while the valley 101v can have a distance D4 measured from the lowest point at the top surface 101ts of the exposed substrate 101 to the interface 137. In some embodiments, the ratio of the distance D3 to the distance D4 can be from about 1.1 to about 1.5, such as about 1.3. It should be understood that Figure 19 - 1 the embodiments of Figure 20 can be applied to

[0069] the embodiments ofFigure 21A and Figure 21B , the isolation trenches 1802 ( Figure 18A and Figure 18B ) are filled with a dielectric material 2130. In some embodiments, a dielectric liner 2132 may be disposed between the dielectric material 2130 and the exposed surfaces of the isolation trenches 1802. The dielectric material 2130 filled within the isolation trenches 1802 and the dielectric liner 2132 form an isolation trench structure (so-called CPODE trench) 2134. The isolation trench structure 2134 has a substantially flat bottom surface 1802bs2. The bottom surface 1802bs2 of the isolation trench structure 2134 and the top surface 101ts of the substrate 101 define a substantially flat interface. The dielectric material 2130 and the dielectric liner 2132 may be made of an oxygen-containing material such as silicon oxide (SiO2); a nitrogen-containing material such as silicon nitride, silicon oxynitride (SiON), SiOCN, SiCN; a low-k dielectric material; or any suitable dielectric material. The dielectric material 2130 may include a different chemical material from the dielectric liner 2132 and may be formed by any suitable process such as CVD, PECVD, FCVD, or ALD process.

[0070] In Figure 22A and Figure 22B , once the isolation trenches 1802 are filled, a planarization process (e.g., CMP process) may be performed to remove the portion of the dielectric material formed above the patterned mask layer 1304'. The planarization process may be performed until a portion of the capping layer 139 or the ILD layer 164 is exposed.

[0071] In Figure 23A and Figure 23B , the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108 are removed. The exposed dielectric liner 2132 on the sidewalls of the dielectric material 2130 may also be removed. The removal of the sacrificial gate structure 130 and the semiconductor layer 108 forms an opening 166 between the first semiconductor layers 106. The capping layer 139, the CESL 162, and the first ILD layer 164 protect the epitaxial source / drain features 146 during the removal process. The sacrificial gate structure 130 may be removed using plasma dry etching and / or wet etching. In some embodiments, a wet etchant (e.g., tetramethylammonium hydroxide (TMAH) solution) may be used to selectively remove the sacrificial gate electrode layer 134 and the sacrificial gate dielectric layer 132, but not the gate spacers 138, the isolation trench structure 2134, the first ILD layer 164, and the CESL 162. After removing the sacrificial gate structure 130, the first semiconductor layer 106 and the inner spacers 144 are exposed to the opening 166.

[0072] InFigure 24A and Figure 24B In Figure 24B , an alternative gate structure 190 is formed. Each of the alternative gate structures 190 may include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interface layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The IL 178 may also be formed on the exposed surfaces of the substrate 101, the insulating material 118, and the dielectric layer 2132. The IL 178 may include or be made of the following: an oxide (e.g., silicon oxide) formed by thermal oxidation or chemical oxidation of the first semiconductor layer 106, a nitride (e.g., silicon nitride, silicon oxynitride, oxynitride, etc.), and / or a dielectric layer (e.g., hafnium silicate). Next, the gate dielectric layer 180 is formed on the exposed surfaces of the semiconductor device structure 100 (e.g., on the IL (if any), the sidewalls of the gate spacers 138, the top surfaces of the first ILD layer 164, the CESL 162, and the capping layer 139). The gate dielectric layer 180 may be formed of a different chemical material from the sacrificial gate dielectric layer 132. The gate dielectric layer 180 may include or be made of a high-k dielectric material. The gate dielectric layer 180 may be a conformal layer formed by a conformal process (e.g., an ALD process, a PECVD process, a molecular beam deposition (MBD) process, etc. or a combination thereof).

[0073] After forming the IL (if any) and the gate dielectric layer 180, the gate electrode layer 182 is formed on the gate dielectric layer 180. The gate electrode layer 182 fills the opening 166( Figure 23A) and surrounds a portion of each of the first semiconductor layers 106. The gate electrode layer 182 includes one or more layers of conductive material, such as polysilicon, aluminum, copper, titanium, tantalum, tungsten, cobalt, molybdenum, tantalum nitride, nickel silicide, cobalt silicide, TiN, WN, WCN, TiAl, TiTaN, TiAlN, TaN, TaCN, TaC, TaSiN, metal alloys, other suitable materials, and / or combinations thereof. The gate electrode layer 182 can be formed by PVD, CVD, ALD, electroplating, or other suitable methods. In some embodiments, one or more optional conformal layers (not shown) can be deposited conformally (and sequentially if more than one) between the gate dielectric layer 180 and the gate electrode layer 182. The one or more optional conformal layers can include one or more barrier layers and / or capping layers and one or more work function tuning layers. The one or more barrier layers and / or capping layers can include or can be: nitrides of tantalum and / or titanium, silicon nitride, carbon nitride, and / or aluminum nitride; nitrides, carbon nitrides, and / or carbides of tungsten; and so on; or combinations thereof. The one or more work function tuning layers can include or can be: nitrides of titanium and / or tantalum, silicon nitride, carbon nitride, aluminum nitride, aluminum oxide, and / or aluminum carbide; nitrides, carbon nitrides, and / or carbides of tungsten; cobalt; platinum; and so on; or combinations thereof.

[0074] The portions of the gate electrode layer 182, one or more optional conformal layers (if any), and the gate dielectric layer 180 that are above the top surfaces of the first ILD layer 164, the CESL 162, the capping layer 139 (if any), and the gate spacers 138 can be removed by a planarization process (e.g., by a CMP process). After the CMP process, the top surfaces of the isolation trench structure 2134, the first ILD layer 164, the CESL 162, the gate spacers 138, and the gate electrode layer 182 are substantially coplanar.

[0075] At Figure 25A and Figure 25BIn [the structure], one or more metal gate etch-back (MGEB) processes may optionally be performed on the gate electrode layer 182. The MGEB process is performed to recess the top surfaces of the gate electrode layer 182 and the gate dielectric layer 180 to a level lower than the top surface of the gate spacer 138. In some embodiments, the gate spacer 138 is also recessed to a level lower than the top surface of the ILD layer 164. A self-aligned contact layer 192 is formed over the gate electrode layer 182. The self-aligned contact layer 192 may be a dielectric material (e.g., SiN) having an etch selectivity with respect to the ILD layer 164. The self-aligned contact layer 192 protects the gate electrode layer 182 during the formation of the contact openings. Then, a silicide layer 184 is formed over the epitaxial source / drain feature 146, and an S / D contact 186 is formed in the contact openings over the silicide layer 184. The contact 186 may include a conductive material such as Ru, Mo, Co, Ni, W, Ti, Ta, Cu, Al, TiN, or TaN. Although not shown, a barrier layer (e.g., TiN, TaN, etc.) may be formed on the sidewalls of the contact openings before forming the S / D contact 186. Then, a planarization process (e.g., CMP) is performed to remove the over-deposited contact material and expose the top surface of the gate electrode layer 182.

[0076] It can be seen that the isolation trench structure 2134 has a substantially flat bottom surface 1802bs2, which is at the same height as the interface 137 defined by the substrate 101 and the insulating material 118. The bottom surface 1802bs2 extends across the diameter of the isolation trench structure 2134 and contacts the substantially flat top surface of the substrate 101. It has been observed that the lattice mismatch and different thermal expansion characteristics between the substrate 101 and the dielectric material 2130 (of the isolation trench structure 2134) may cause charge trapping at the interface of the silicon and the refill dielectric heterostructure. Negative trapped charges at the interface of the silicon and the refill dielectric heterostructure may cause P-type EPI to P-type EPI leakage through the parasitic PNP bipolar junction transistor (BJT), while positive trapped charges at the interface of the silicon and the refill dielectric heterostructure may cause N-type EPI to N-type EPI leakage through the parasitic NPN BJT. Although reducing the depth of the CPODE / CMODE structure can prevent the formation of parasitic fin BJTs under the STI (i.e., the insulating material 118), insufficient etch amount may still cause silicon residues on the sidewalls of the STI, resulting in current leakage. By forming the isolation trench structure 2134 with a flat bottom surface 1802bs2, no fin structure is formed on the top of the substrate 101, which would otherwise become a parasitic BJT. As a result, leakage current through the epitaxial source / drain feature and the silicon substrate is avoided.

[0077] Figure 26 and Figure 27Cross-sectional views of semiconductor device structure 100 according to the embodiments shown in Figure 19 and Figure 20 are shown. It can be seen that isolation trench structure 2134 is formed such that the bottom of isolation trench structure 2134 extends to a certain depth into the well region of substrate 101. In particular, bottom surface 1802bs3 and bottom surface 1802bs4 of isolation trench structure 2134 are at a height lower than interface 137 defined by substrate 101 and insulating material 118. In any case, isolation trench structure 2134 has sidewalls composed of insulating material 118 and substrate 101. In Figure 27 's embodiment, the portion of insulating material 118 protruding into isolation trench structure 2134 has a top surface 118t in contact with dielectric material 2130, and sidewall 118s of insulating material 118 is in contact with dielectric liner 2132.

[0078] Figure 28 is a top view of semiconductor device structure 100 according to some embodiments in Figure 25A and Figure 25B . For clarity, some components of semiconductor device structure 100, such as self-aligned contact layer 192 and CESL 162, etc., are omitted in Figure 28 . Figure 29A 、 Figure 29B 、 Figure 29C are cross-sectional views of semiconductor device structure 100 taken along lines D-D, E-E, and F-F of Figure 28 respectively. As visible in Figure 29B , isolation trench structure 2134 extends through insulating material 118 (e.g., STI) and into the well region of substrate 101 to block leakage current between transistors. Additionally, isolation trench structure 2134 with a flat silicon interface also eliminates parasitic fin BJTs in and / or below the well region of substrate 101. Thus, leakage path 2801 through EPI - transistor - substrate - EPI ( Figure 28 ) is avoided.

[0079] It should be understood that further complementary metal - oxide - semiconductor (CMOS) and / or backend - of - line (BEOL) processes can be performed on semiconductor device structure 100 to form various features, such as transistors, contacts / via, interconnect metal layers, dielectric layers, passivation layers, etc. Semiconductor device structure 100 may also include a backside contact (not shown) on the backside of substrate 101 such that the source or drain of epitaxial S / D feature 146 is connected to a backside power rail (e.g., positive voltage VDD or negative voltage VSS) through the backside contact.

[0080] Figures 30 to 36An alternative embodiment is shown in which a portion of the insulating material 118 remains within the isolation trench structure and on the top surface 101ts of the exposed substrate 101. In Figure 30 , after the first semiconductor etch process 141 removes the first semiconductor layer 106 and the second semiconductor layer 108 (and in some cases a small portion of the insulating material 118), a modified second semiconductor etch process 149 is performed to further remove some portions of the exposed insulating material 118 and the substrate portions forming the fin structures 102b, 102c. The modified second semiconductor etch process 149 is a selective etch process that selectively or preferentially removes silicon (e.g., the substrate portions forming the fin structures 102b, 102c) over silicon oxide (e.g., the insulating material 118). As a result, insulating material 118 in the form of multiple fin-like structures 118f remains at the bottom of the isolation trenches 1802a, 1802b (collectively referred to as isolation trenches 1802). The top of the fin-like structures 118f of the insulating material 118 is at a height lower than the top surface of the insulating material 118 or the interface 142 defined by the insulating material 118 and the sacrificial gate electrode layer 134. In some embodiments, after the modified second semiconductor etch process 149, the top surface 101ts of the exposed substrate 101 may have a flat as well as a curved profile ( Figure 36 ).

[0081] Directional silicon etching can be achieved by using a plasma etch process with HBr / Cl2-based chemicals with added O2 and / or CO2 (similar to those used in the second semiconductor etch process 147). Higher directionality can be achieved by applying a bias power to the substrate pedestal in the processing chamber. Due to ion bombardment, the top of the insulating material 118 may have a curved recess. In some embodiments, the modified second semiconductor etch process 149 is a two-step process that includes an anisotropic etch process and an isotropic etch process. The anisotropic etch process can be a plasma etch using bromine (e.g., HBr)- or chlorine (e.g., Cl2)-based etch chemicals as previously discussed with respect to the first semiconductor etch process 141 (in Figure 17A and Figure 17B ). The isotropic etch process can be a plasma etch using fluorine (e.g., NF3)- and / or hydrogen (e.g., H2)-based etch chemicals. In some embodiments, a bias power is applied during both the anisotropic etch process and the isotropic etch process. In some embodiments, a bias power is applied during the anisotropic etch process, and the isotropic etch process is performed without bias power. Alternatively, the anisotropic etch process can be a dry etch process, and the isotropic etch process can be a wet etch process to achieve a high selectivity etch between the substrate 101 and the insulating material 118.

[0082] In some embodiments, the modified second semiconductor etch process 149 is a plasma-based atomic layer etch (ALE) process, which is a cyclic etch process of gas incorporation and ion bombardment for removing material layer by layer, with less damage to the structure. The ALE process facilitates the formation of the flat top surface 101ts of the substrate 101. An exemplary ALE process may include (1) incorporating a halogen-based etch gas (e.g., fluorine-based, chlorine-based, and / or bromine-based chemicals as described above) into the semiconductor device structure 100 disposed in the processing chamber, and the etch gas adsorbs on and chemically reacts with the insulating material 118 and the substrate portions forming the fin structures 102b, 102c; (2) purging the residual dose gas from the processing chamber; (3) bombarding the insulating material 118 and the substrate portions forming the fin structures 102b, 102c with low-energy inert ions (e.g., argon) to remove the reacted surface layer; and (4) purging the etch by-products from the processing chamber. In some embodiments, a radical-based ALE process may be used.

[0083] In some embodiments, the ALE process may use oxygen molecules or radicals to chemically react with the insulating material 118 and the substrate portions forming the fin structures 102b, 102c, and the reacted layer (e.g., SiO2) is removed by an HF-based chemical.

[0084] In Figure 31 , the isolation trench 1802 ( Figure 30 ) is filled with a dielectric material 2130a (e.g., the dielectric material 2130). Similarly, a dielectric liner 2132a (e.g., the dielectric liner 2132) may be first disposed on the exposed surface of the isolation trench 1802. That is, the dielectric liner 2132a is deposited on the exposed surfaces of each fin structure 118f of the insulating material 118, the insulating material 118, the substrate 101, the sacrificial gate electrode layer 134, and the sidewalls of the patterned mask layer 1304'. The dielectric material 2130a filled in the isolation trench 1802 and the dielectric liner 2132a form an isolation trench structure 2134a. The isolation trench structure 2134a has a plurality of fin-shaped insulating materials 118f on the substantially flat top surface 101ts of the substrate 101.

[0085] In Figure 32 , once the isolation trench 1802 is filled, a planarization process may be performed to remove the portion of the dielectric material formed above the patterned mask layer 1304', such as those discussed above with respect to Figure 22A and Figure 22B . The planarization process may be performed until a portion of the capping layer 139 or the sacrificial gate electrode layer 134 is exposed.

[0086] In Figure 33Remove the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108, e.g., as discussed above with respect to Figure 23A and Figure 23B as discussed above.

[0087] In Figure 34 form an alternative gate structure. Each of the alternative gate structures 190 may include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interface layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The IL 178, the gate dielectric layer 180, and the gate electrode layer 182 may be formed in a manner similar to that discussed above with respect to Figure 24A and Figures 24B to 25A and Figure 25B as discussed above.

[0088] Portions of the gate electrode layer 182 and the gate dielectric layer 180 above the top surfaces of the first ILD layer 164 (not shown), the CESL 162 (not shown), the capping layer 139 (not shown), and the gate spacer 138 (not shown) may be removed by a planarization process. After the CMP process, the top surfaces of the isolation trench structure 2134a, the first ILD layer 164, the CESL 162, the gate spacer 138, and the gate electrode layer 182 are substantially coplanar.

[0089] In some embodiments, the modified second semiconductor etch process 149 is configured as a highly selective etch process such that most of the insulating material 118 remains within the isolation trench 1802. Figure 35 A cross-sectional view of a semiconductor device structure 100 according to an alternative embodiment is shown, in which the fin structure 118f-1 of the insulating material 118 in the isolation trench structure 2134 has a top at substantially the same height as the insulating material 118 under the gate electrode layer 182.

[0090] Figure 36 A view showing a portion of the substrate 101 shown in Figure 34 and Figure 35 according to some embodiments is shown. It can be seen that the top surface 101ts of the substrate 101 may include a substantially flat first portion 101ts-1 and a second portion 101ts-2 having a curved profile due to being pre-exposed to the etch chemicals during the modified second semiconductor etch process 149. The lowest top surface 101ts-2 of the substrate 101 is at a height lower than the interface 137 defined by the substrate 101 and the insulating material 118.

[0091] Figures 37 to 43Shows an alternative embodiment in which a portion of the insulating material 118 remains within the isolation trench structure and is disposed away from the top surface 101ts of the exposed substrate 101. In Figure 37 After the first semiconductor etching process 141 removes the first semiconductor layer 106 and the second semiconductor layer 108 (and in some cases a small portion of the insulating material 118), a modified second semiconductor etching process 151 is performed to further remove some portions of the exposed insulating material 118, the substrate portions forming the fin structures 102b, 102c, and a portion of the exposed substrate 101. The modified second semiconductor etching process 151 is a selective etching process that selectively removes silicon (e.g., the substrate portions forming the fin structures 102b, 102c and the substrate 101) over silicon oxide (e.g., the insulating material 118). The modified second semiconductor etching process 151 is performed such that the bottom surface 1802bs5 of the isolation trench 1802 is at a height lower than the interface 137 defined by the substrate 101 and the insulating material 118. As a result, the insulating material 118 in the form of a plurality of fin structures 118f-2 remains within the isolation trench 1802 and is separated from the recessed substrate 101 by the opening 150. Additionally, the isolation trench structure 2134a is formed to have a substantially flat bottom surface 1802bs5, as described above with respect to Figure 18B , Figure 19 and Figure 20 discussed.

[0092] Referring to Figure 28 and Figure 37 , the fin structures 118f-2 of the insulating material 118 are connected to or supported by the epitaxial source / drain features 146, which may be disposed along the X direction (into the paper). The top of the fin structures 118f-2 of the insulating material 118 is at a height lower than the top surface of the insulating material 118 or the interface 142 defined by the insulating material 118 and the sacrificial gate electrode layer 134. The bottom of each fin structure 118f-2 of the insulating material 118 is at substantially the same height as the interface 137 defined by the substrate 101 and the insulating material 118.

[0093] The modified second semiconductor etch process 151 is similar to the modified second semiconductor etch process 149. In one embodiment, a two-step process including an anisotropic etch process and an isotropic etch process is used. The anisotropic etch process is a plasma etch using an etch chemical based on bromine (e.g., HBr), while the isotropic etch process is a plasma etch using an etch chemical based on fluorine (e.g., NF3) and / or based on hydrogen (e.g., H2). To compensate for the etch selectivity required to remove the substrate 101 and the substrate portions forming the fin structures 102b, 102c, a high-pressure process for the substrate pedestal (e.g., a chamber pressure greater than about 50 mTorr) and / or a high bias power (e.g., greater than 300 V) can be used. In some embodiments, a high bias power is applied during the anisotropic etch process, while a low bias power is used during the isotropic etch process. Alternatively, the anisotropic etch process can be a dry etch process, and the isotropic etch process can be a wet etch process to achieve a high selectivity etch between the substrate 101 and the insulating material 118.

[0094] In Figure 38 , the isolation trench 1802 ( Figure 37 ) is filled with a dielectric material 2130b (e.g., the dielectric material 2130). Similarly, a dielectric liner 2132b (e.g., the dielectric liner 2132) can be first disposed on the exposed surface of the isolation trench 1802. That is, the dielectric liner 2132b is deposited on the exposed surfaces of each fin structure 118f-2 of the insulating material 118, the insulating material 118, the substrate 101, the sacrificial gate electrode layer 134, and the patterned mask layer 1304'. The dielectric material 2130b filled in the isolation trench 1802 and the dielectric liner 2132b form an isolation trench structure 2134b. Each fin structure among the plurality of fin structures 118f-2 of the insulating material 118 in the isolation trench structure 2134b is separated from the flat top surface 101ts of the substrate 101 by the dielectric material 2130 and the dielectric liner 2132.

[0095] In Figure 39 , once the isolation trench 1802 is filled, a planarization process can be performed to remove the portion of the dielectric material formed above the patterned mask layer 1304', such as those discussed above with respect to Figure 22A and Figure 22B . The planarization process can be performed until a portion of the capping layer 139 or the sacrificial gate electrode layer 134 is exposed.

[0096] In Figure 40 , the sacrificial gate structure 130, the sacrificial gate dielectric layer 132, and the second semiconductor layer 108 are removed, such as those discussed above with respect to Figure 23A and Figure 23B .

[0097] In Figure 41 a replacement gate structure is formed. Each of the replacement gate structures 190 may include a gate dielectric layer 180 and a gate electrode layer 182. In some embodiments, an interface layer (IL) 178 may be formed between the gate dielectric layer 180 and the first semiconductor layer 106. The IL 178, the gate dielectric layer 180, and the gate electrode layer 182 may be formed in a manner similar to the manner discussed above with respect to Figure 24A and Figures 24B to 25A and Figure 25B . The portions of the gate electrode layer 182 and the gate dielectric layer 180 that are above the top surfaces of the first ILD layer 164 (not shown), the CESL 162 (not shown), the capping layer 139 (not shown), and the gate spacer 138 (not shown) may be removed by a planarization process. After the CMP process, the top surfaces of the isolation trench structure 2134a, the first ILD layer 164, the CESL 162, the gate spacer 138, and the gate electrode layer 182 are substantially coplanar.

[0098] In some embodiments, the modified second semiconductor etch process 151 is configured as a highly selective etch process such that most of the insulating material 118 remains within the isolation trench 1802. Figure 42 A cross-sectional view of a semiconductor device structure 100 according to an alternative embodiment is shown. In this embodiment, the fin structure 118f-3 of the insulating material 118 in the isolation trench structure 2134c has a top that is at substantially the same height as the insulating material 118 below the gate electrode layer 182 (or the interface 153 defined by the IL 178 and the insulating material 118). The bottom of each fin structure 118f-3 of the insulating material 118 is at substantially the same height as the interface 137 defined by the substrate 101 and the insulating material 118.

[0099] Figure 43 A magnified view of a portion of the substrate 101 shown in Figure 41 and Figure 42 according to some embodiments is shown. It can be seen that the substrate 101 may be etched to have peaks 101p and valleys 101v, thereby creating a CPODE structure having a waveform bottom surface profile.

[0100] Although Figures 10A to 43 the various embodiments in describe a CPODE pre-processing method (i.e., during front-end-of-line (FEOL) processing before metal gate formation), these embodiments are equally applicable to a CPODE post-processing method (or so-called CMODE process), i.e., during middle-end-of-line (MEOL) processing after metal gate formation.Figure 44A and Figures 44B to 49A and Figure 49B is a cross - sectional view of one of the various stages of manufacturing a semiconductor device structure 100 according to some embodiments involving the CMODE process (i.e., after forming a metal gate structure). In Figure 44A and Figure 44B , the sacrificial gate structure 130 ( Figure 10A and Figure 10B ), the sacrificial dielectric layer 132 ( Figure 10A and Figure 10B ), and the second semiconductor layer 108 ( Figure 10A and Figure 10B ) have been replaced by IL (not shown), the gate dielectric layer 180, and the gate electrode layer 182, such as those discussed above with respect to Figure 23A and Figures 23B to 24A and Figure 24B . The gate dielectric layer 180 and the gate electrode layer 182 are planarized by, for example, CMP until the top surface of the ILD 164 is exposed. Then, a mask layer 181 is formed on the gate electrode layer 182, the ILD layer 164, the gate spacer 138, and the CESL 162. The mask layer 181 may include the same material as the hard mask 1304 described above.

[0101] In Figure 45A and Figure 45B , a mask structure 152 is formed on the mask layer 181. In some embodiments, the mask structure 152 is a three - layer photoresist. For example, the mask structure 152 may include a bottom layer 154 and an intermediate layer 156 disposed on the bottom layer 154. The bottom layer 154 and the intermediate layer 156 are made of different materials such that the optical properties and / or etching properties of the bottom layer 154 and the intermediate layer 156 are different from each other. In some embodiments, the bottom layer 154 may be a carbon layer, while the intermediate layer 156 may be a silicon - rich layer that is designed to provide an etching selectivity between the intermediate layer 156 and the bottom layer 154. The mask structure 152 further includes a photoresist layer 158, which may be a chemically amplified photoresist layer and may be a positive photoresist or a negative photoresist. The photoresist layer 158 may include a polymer. The photoresist layer 158 may be formed by spin - coating. The photoresist layer 158 may be patterned to have an opening 159 formed therein.

[0102] In Figure 46A and Figure 46B , the opening 159 is extended into the intermediate layer 156, the bottom layer 154, and the mask layer 181 to expose at least some portions of the gate electrode layer 182. Then, the mask structure 152 is removed after the opening 159 is extended into the mask layer 181.

[0103] InFigure 47A and Figure 47B and, a patterned mask layer 181 is used as a mask to remove some portions of the gate electrode layer 182, the gate dielectric layer 180, the first semiconductor layer 106, the insulating material 118, and the substrate portions forming the fin structures 102e, 102f. Any suitable dry etching, wet etching, or combination thereof (e.g., those discussed above with respect to Figures 14A to 20 ) can be used to effect the removal of the layers. As a result of the (one or more) removal processes, isolation trenches 4702 are formed. The isolation trenches 4702 are etched to have a bottom 4702bs1 that extends to a certain depth into the well region of the substrate 101. Such a recess in the substrate 101 can be obtained by controlling one or more etching conditions to achieve a low selectivity etching between silicon (e.g., the substrate 101) and silicon oxide (e.g., the insulating material 118). For example, during the removal process, a low pressure process (e.g., a chamber pressure below about 50 mTorr) and / or a high bias power to the substrate pedestal (e.g., greater than 300 V) can be utilized to compensate for the etching selectivity required to remove the insulating material 118 and the substrate portions of the fin structures 102e, 102f.

[0104] In some embodiments, the isolation trenches 4702 are etched such that the bottom surface 4702bs1 of the isolation trenches 4702 (or, in other words, the top surface 101ts of the exposed substrate 101) is substantially flat. In one embodiment, the bottom surface 4702bs1 is at a height below the interface 137 defined by the substrate 101 and the insulating material 118. As described above, the substrate 101 having a flat top surface 101ts does not form parasitic bipolar junction transistors in the well region, which may lead to the formation of an EPI - substrate - EPI leakage path.

[0105] In Figure 48A and Figure 48B , the isolation trenches 4702 ( Figure 47A and Figure 47B ) are filled with a dielectric material 4730 (e.g., the dielectric material 2130). Similarly, a dielectric liner 4732 (e.g., the dielectric liner 2132) can be first disposed on the exposed surfaces of the isolation trenches 4702. That is, the dielectric liner 4732 is deposited on the exposed surfaces of the insulating material 118, the substrate 101, the gate electrode layer 182, and the patterned mask layer 181. The dielectric material 4730 filled within the isolation trenches 4702 and the dielectric liner 4732 form an isolation trench structure (so - called CMODE trench) 4734. The isolation trench structure 4734 has a substantially flat bottom surface corresponding to the top surface 101ts of the substrate 101.

[0106] In Figure 49A and Figure 49BOnce the isolation trench 4702 is filled, a planarization process can be performed to remove the portion of the dielectric material that is formed above the patterned mask layer 181’, such as those discussed above with respect to Figure 22A and Figure 22B . The planarization process can be performed until the ILD 164 is exposed. After the planarization process, the top surfaces of the dielectric material 4730, the dielectric liner 4732, the gate electrode layer 182, the ILD layer 164, the gate spacer 138, and the CESL 162 are substantially coplanar.

[0107] Figure 50 is an enlarged view of a portion of the substrate 101 shown in Figure 49B . It can be seen that the substrate 101 can be etched to have peaks 101p and valleys 101v, thereby creating a CMODE structure 4734 with a wavy bottom surface profile.

[0108] Figure 51 shows an embodiment in which the isolation trench structure (CMODE structure) 4734a has a bottom 4702bs2 that is at substantially the same height as the top surface 101ts of the substrate 101. In this embodiment, any suitable dry etching, wet etching, or combination thereof (such as those discussed above with respect to Figures 14A to 18B ) can be used to etch the substrate 101.

[0109] Figure 51 - 1 shows an enlarged view of a portion of the substrate 101 shown in Figure 51 according to some embodiments. It can be seen that the substrate 101 can be etched to have peaks 101p and valleys 101v, thereby creating a CMODE structure with a wavy bottom surface profile.

[0110] Figure 52 shows a cross-sectional view of a semiconductor device structure 100 according to an alternative embodiment. In this embodiment, the isolation trench structure (CMODE structure) 4734b has a substantially flat bottom surface 4702bs3 at a height below the interface 137 defined by the substrate 101 and the insulating material 118. In particular, a plurality of fin structures 118f-4 of the insulating material 118 are retained in the isolation trench structure 4734b. Although not shown, the fin structures 118f-4 of the insulating material 118 are connected to or supported by the epitaxial source / drain features 146, which may be disposed in the X direction (into the paper). Each of the fin structures in the fin structures 118f-4 of the insulating material 118 has a top that is at substantially the same height as the interface 155 defined by the insulating material 118 below the gate dielectric layer 180 and the gate electrode layer 182. It can be formed by any suitable process (such as those discussed above with respect toFigures 37 to 43 Those described) form fin structures 118f-4 of the insulating material 118.

[0111] Figure 53 A cross-sectional view of a semiconductor device structure 100 according to an alternative embodiment is shown. Figure 53 The embodiment of... is substantially the same as Figure 52 the embodiment of..., except that the fin structures 118f-5 of the insulating material 118 in the isolation trench structure 4734b have tops at a height lower than the interface 155 defined by the insulating material 118 under the gate dielectric layer 180 and the gate dielectric layer 182. The bottom of each fin structure 118f-5 of the insulating material 118 is at substantially the same height as the interface 137 defined by the substrate 101 and the insulating material 118.

[0112] Figure 54 A view showing according to some embodiments Figure 52 and Figure 53 an enlarged view of a portion of the substrate 101 shown in.... It can be seen that the substrate 101 can be etched to have peaks 101p and valleys 101v, thereby producing a CMODE structure with a waveform bottom surface profile.

[0113] Embodiments of the present disclosure provide improved isolation trench structures (e.g., CPODE / CMODE structures) having a substantially flat bottom surface in contact with the top surface of the substrate. The isolation trench structure with a flat bottom surface prevents the top surface of the substrate from forming fin structures and becoming a parasitic bipolar junction transistor (BJT). In some cases, the isolation trench structure can extend into the well region of the substrate to block leakage current through EPI - transistor - substrate - EPI.

[0114] A semiconductor device structure is shown. The structure includes a substrate, an insulating material disposed on the substrate, a first fin structure extending upward from the substrate through the insulating material, and a second fin structure extending upward from the substrate through the insulating material, wherein the first fin structure and the second fin structure extend in a first direction. The structure further includes an isolation trench structure disposed between the first fin structure and the second fin structure, the isolation trench structure extending in a second direction perpendicular to the first direction, wherein the isolation trench structure has a bottom in contact with the top surface of the substrate, and the bottom of the isolation trench structure and the top surface of the substrate define a substantially flat interface.

[0115] Another embodiment is a semiconductor device structure. The structure includes a substrate and an insulating material disposed on the substrate, wherein the insulating material and a first portion of the substrate define a first interface. The structure further includes a first fin structure extending upward from the substrate through a first portion of the insulating material, a second fin structure extending upward from the substrate through a second portion of the insulating material, and an isolation trench structure disposed between the first fin structure and the second fin structure, wherein at least some portions of the isolation trench structure are separated from each other by a third portion of the insulating material.

[0116] Yet another embodiment is a method for forming a semiconductor device structure. The method includes: forming a first fin structure and a second fin structure from a substrate, the first fin structure and the second fin structure each including a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately. The method further includes: forming an insulating material on the substrate; forming a metal gate structure on the insulating material and on a portion of each of the first fin structure and the second fin structure; removing a portion of the metal gate structure above the first fin structure and the second fin structure; removing portions of the first fin structure, the second fin structure, the insulating material, and the substrate by one or more etching processes to form an isolation trench having a substantially flat bottom surface extending between opposite sidewalls of the isolation trench; and filling the isolation trench with a dielectric material.

[0117] The features of several embodiments are outlined above so that those skilled in the art can better understand aspects of the present disclosure. Those skilled in the art should appreciate that they can readily use the present disclosure as a basis for designing or modifying other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments described herein. Those skilled in the art should also recognize that these equivalent constructs do not depart from the spirit and scope of the present disclosure, and that they can make various changes, substitutions, and alterations without departing from the spirit and scope of the present disclosure.

[0118] Example 1. A semiconductor device structure, comprising:

[0119] a substrate;

[0120] an insulating material disposed on the substrate;

[0121] a first fin structure extending upward from the substrate through the insulating material;

[0122] a second fin structure extending upward from the substrate through the insulating material, the first fin structure and the second fin structure extending in a first direction; and

[0123] an isolation trench structure disposed between the first fin structure and the second fin structure, the isolation trench structure extending in a second direction perpendicular to the first direction;

[0124] Wherein, the isolation trench structure has a bottom surface in contact with the top surface of the substrate, and the bottom surface of the isolation trench structure and the top surface of the substrate define a substantially flat interface.

[0125] Example 2. The semiconductor device structure according to Example 1, wherein the insulating material and the substrate define a second interface, and the first interface and the second interface are at substantially the same height.

[0126] Example 3. The semiconductor device structure according to Example 1, wherein the insulating material and the substrate define a second interface, and the first interface is at a height lower than the second interface.

[0127] Example 4. The semiconductor device structure according to Example 1, wherein the isolation trench structure further comprises:

[0128] A plurality of fin structures disposed on the substrate, wherein the plurality of fin structures and the insulating material are formed of the same material.

[0129] Example 5. The semiconductor device structure according to Example 4, wherein the top surface of one or more of the plurality of fin structures is at a height lower than the top surface of the insulating material.

[0130] Example 6. The semiconductor device structure according to Example 4, wherein the top surface of one or more of the plurality of fin structures is at substantially the same height as the top surface of the insulating material.

[0131] Example 7. The semiconductor device structure according to Example 4, wherein each of the plurality of fin structures is connected to or supported by an epitaxial source / drain feature.

[0132] Example 8. A semiconductor device structure, comprising:

[0133] A substrate;

[0134] An insulating material disposed on the substrate, a first portion of the insulating material and the substrate defining a first interface;

[0135] A first fin structure extending upward from the substrate through the first portion of the insulating material;

[0136] A second fin structure extending upward from the substrate through the second portion of the insulating material; and

[0137] An isolation trench structure disposed between the first fin structure and the second fin structure, wherein at least some portions of the isolation trench structure are separated from each other by a third portion of the insulating material.

[0138] Example 9. The semiconductor device structure according to Example 8, wherein the third portion of the insulating material includes a plurality of fin structures.

[0139] Example 10. The semiconductor device structure according to Example 8, wherein the bottom of the isolation trench structure and the second portion of the substrate define a second interface lower than the first interface.

[0140] Example 11. The semiconductor device structure according to Example 9, wherein each fin structure in the plurality of fin structures is surrounded by a dielectric liner.

[0141] Example 12. The semiconductor device structure according to Example 10, wherein the third portion of the insulating material is separated from the second portion of the substrate by the isolation trench structure.

[0142] Example 13. The semiconductor device structure according to Example 10, wherein the third portion of the insulating material has a top at a third height, and the third height is substantially at the same height as the first interface.

[0143] Example 14. The semiconductor device structure according to Example 10, wherein the third portion of the insulating material has a top at a third height, and the third height is at a height lower than the first interface.

[0144] Example 15. The semiconductor device structure according to Example 10, wherein the bottom of the isolation trench structure has a wavy profile.

[0145] Example 16. The semiconductor device structure according to Example 10, wherein the bottom of the isolation trench structure has a substantially flat profile.

[0146] Example 17. A method for forming a semiconductor device structure, comprising:

[0147] Forming a first fin structure and a second fin structure from a substrate, the first fin structure and the second fin structure each comprising a plurality of first semiconductor layers and a plurality of second semiconductor layers stacked alternately;

[0148] Forming an insulating material on the substrate;

[0149] Forming a metal gate structure on the insulating material and on a portion of each of the first fin structure and the second fin structure;

[0150] Removing a portion of the metal gate structure above the first fin structure and the second fin structure;

[0151] Removing some portions of the first fin structure, the second fin structure, the insulating material, and the substrate by one or more etching processes to form isolation trenches having a substantially flat bottom surface extending between opposite sidewalls of the isolation trenches; and filling the isolation trenches with a dielectric material.

[0152] Example 18. The method according to Example 17, wherein a bottom surface of the isolation trench is at a height lower than an interface defined by the substrate and the insulating material.

[0153] Example 19. The method according to Example 17, wherein the one or more etching processes are performed such that fin-shaped portions of the insulating material remain within the isolation trenches.

[0154] Example 20. The method according to Example 19, wherein each portion of the insulating material in a fin shape is surrounded by a dielectric lining.

Claims

1. A semiconductor device structure, comprising: A substrate; An insulating material disposed on the substrate; A first fin structure extending upward from the substrate through the insulating material; A second fin structure extending upward from the substrate through the insulating material, the first fin structure and the second fin structure extending in a first direction; And An isolation trench structure disposed between the first fin structure and the second fin structure, the isolation trench structure extending in a second direction perpendicular to the first direction; Wherein the isolation trench structure has a bottom surface in contact with the top surface of the substrate, and the bottom surface of the isolation trench structure and the top surface of the substrate define a substantially flat interface.

2. The semiconductor device structure according to claim 1, wherein, The insulating material and the substrate define a second interface, and the first interface is at substantially the same height as the second interface.

3. The semiconductor device structure according to claim 1, wherein, The insulating material and the substrate define a second interface, and the first interface is at a height lower than the second interface.

4. The semiconductor device structure according to claim 1, wherein, The isolation trench structure further comprises: A plurality of fin structures disposed on the substrate, wherein the plurality of fin structures and the insulating material are formed of the same material.

5. The semiconductor device structure according to claim 4, wherein, The top of one or more of the plurality of fin structures is at a height lower than the top surface of the insulating material.

6. The semiconductor device structure according to claim 4, wherein, The top of one or more of the plurality of fin structures is at substantially the same height as the top surface of the insulating material.

7. The semiconductor device structure according to claim 4, wherein, Each of the plurality of fin structures is connected to or supported by an epitaxial source / drain feature.

8. A semiconductor device structure, comprising: A substrate; An insulating material disposed on the substrate, a first portion of the insulating material and the substrate defining a first interface; A first fin structure extending upward from the substrate through the first portion of the insulating material; A second fin structure extending upward from the substrate through the second portion of the insulating material; And An isolation trench structure disposed between the first fin structure and the second fin structure, wherein at least some portions of the isolation trench structure are separated from each other by a third portion of the insulating material.

9. The semiconductor device structure according to claim 8, wherein, The third portion of the insulating material comprises a plurality of fin structures.

10. A method for forming a semiconductor device structure, comprising: Forming a first fin structure and a second fin structure from a substrate, the first fin structure and the second fin structure each comprising a plurality of alternating stacked first semiconductor layers and a plurality of second semiconductor layers; Forming an insulating material on the substrate; Forming a metal gate structure on the insulating material and on a portion of each of the first fin structure and the second fin structure; Removing the portion of the metal gate structure above the first fin structure and the second fin structure; Removing the first fin structure and the second fin structure, some portions of the insulating material, and the substrate by one or more etching processes to form an isolation trench having a substantially flat bottom surface extending between opposite sidewalls of the isolation trench; And Filling the isolation trench with a dielectric material.

Images