Semiconductor structure and manufacturing method thereof

Abstract

A method of embodiments of the present disclosure includes forming a structure including a plurality of channel members vertically stacked over a substrate; forming a source / drain feature adjoining the channel member; after forming the source / drain features, depositing a dielectric material layer wrapping the channel members wherein voids remain between adjacent channel members after depositing the dielectric material layer; selectively removing a central portion of the dielectric material layer to release the channel member; and forming a metal gate structure wrapping the channel member. A side portion of the dielectric material layer is between the metal gate structure and the source / drain feature. The embodiment of the invention also relates to a semiconductor structure and a manufacturing method thereof.

Description

Technical Field

[0001] Embodiments of the present application relate to semiconductor structures and methods of manufacturing the same. Background Art

[0002] The semiconductor integrated circuit (IC) industry has experienced exponential growth. Technological advances in IC materials and design have produced multiple generations of ICs, with each generation having smaller and more complex circuits than the previous one. During the development of ICs, the functional density (i.e., the number of interconnected devices per chip area) has generally increased, while the geometric size (i.e., the smallest component (or line) that can be created using a manufacturing process) has decreased. Such scaling processes generally provide benefits by increasing production efficiency and reducing related costs. Such scaling also increases the complexity of processing and manufacturing ICs.

[0003] For example, as integrated circuit (IC) technology has advanced towards smaller technology nodes, multi-gate metal oxide semiconductor field effect transistors (multi-gate MOSFETs or multi-gate devices) have been introduced to improve gate control by increasing gate-channel coupling, reducing off-state current, and reducing short-channel effects (SCEs). A multi-gate device generally refers to a device having a gate structure or a portion thereof disposed above more than one side of a channel region. A gate-all-around (GAA) transistor is an example of a multi-gate device, and multi-gate devices have become popular and promising candidates for high-performance and low-leakage applications. A GAA transistor has a gate structure that can extend partially or completely around a channel region to provide access to the channel region on two or more sides. As GAA devices continue to scale, challenges have emerged. For example, in a GAA process flow, the formation of inner spacers may be an important process for reducing capacitance and preventing leakage between the gate stack and the source / drain regions. However, existing structures and manufacturing techniques have various problems, including causing poor epitaxial growth and crystal dislocations in the source / drain regions. Thus, while existing structures and manufacturing techniques are generally sufficient for their intended purposes, they are not entirely satisfactory in all respects. Summary of the Invention

[0004] Some embodiments of the present application provide a method of fabricating a semiconductor structure, including: forming a stack including a plurality of channel layers interleaved with a plurality of sacrificial layers over a substrate; patterning the stack to form fin structures; forming a dummy gate stack over the channel regions of the fin structures; depositing gate spacers on sidewalls of the dummy gate stack; recessing source / drain regions of the fin structures to form source / drain trenches that expose sidewalls of the channel layers and sidewalls of the sacrificial layers; epitaxially growing a first epitaxial layer from the sidewalls of the channel layers and the sidewalls of the sacrificial layers; epitaxially growing a second epitaxial layer on the first epitaxial layer; removing the dummy gate stack; selectively removing the sacrificial layers in the channel regions to release the channel layers as channel members; depositing a dielectric material layer that wraps the channel members; removing the dielectric material layer from the channel regions while a portion of the dielectric material layer directly under the gate spacers remains as an internal spacer; and forming a metal gate structure that wraps the channel members, with the internal spacer being between the metal gate structure and the first epitaxial layer.

[0005] Some other embodiments of the present application provide a method of fabricating a semiconductor structure, including: forming a structure including a plurality of channel members vertically stacked over a substrate; forming source / drain components adjacent to the channel members; after forming the source / drain components, depositing a dielectric material layer that wraps the channel members, wherein voids remain between adjacent ones of the channel members after depositing the dielectric material layer; selectively removing a central portion of the dielectric material layer to release the channel members; and forming a metal gate structure that wraps the channel members, wherein side portions of the dielectric material layer are between the metal gate structure and the source / drain components.

[0006] Some further embodiments of the present application provide a semiconductor structure, including: a plurality of nanostructures suspended over a substrate; a gate structure that wraps each of the plurality of nanostructures; gate spacers disposed on sidewalls of the gate structure; source / drain components adjacent to the nanostructures; and an internal spacer between the gate structure and the source / drain components and extending between two adjacent ones of the nanostructures, wherein the internal spacer includes a first sidewall facing the source / drain components and a second sidewall facing the gate structure, the first sidewall being straight and perpendicular, and the second sidewall being curved toward the source / drain components. Description of the Drawings

[0007] Embodiments of the present disclosure are best understood from the following detailed description when read in conjunction with the accompanying drawings. It should be emphasized that, in accordance with standard practice in the industry, the various components are not drawn to scale and are for illustrative purposes only. In fact, for clarity of discussion, the dimensions of the various components may be arbitrarily increased or decreased.

[0008] Figure 1 A flowchart of a method for forming a semiconductor device in accordance with one or more aspects of embodiments of the present disclosure is shown.

[0009] Figure 2 、 Figure 3 、 Figure 4 、 Figure 5A 、 Figure 5B 、 Figure 6 、 Figure 7A 、 Figure 7B 、 Figure 8A 、 Figure 8B 、 Figure 8C 、 Figure 9A 、 Figure 9B 、 Figure 10A 、 Figure 10B 、 Figure 11A 、 Figure 11B 、 Figure 12A 、 Figure 12B 、 Figure 12C 、 Figure 13A 、 Figure 13B 、 Figure 14A 、 Figure 14B 、 Figure 15A 、 Figure 15B 、 Figure 16A and Figure 16B shows a partial cross-sectional view of a work-in-progress (WIP) structure in accordance with one or more aspects of embodiments of the present disclosure during a manufacturing process according to the method of Figure 1 。 DETAILED DESCRIPTION

[0010] The following disclosure provides many different embodiments or examples for implementing the different features of the provided subject matter. Specific examples of components and arrangements are described below to simplify embodiments of the present disclosure. Of course, these are merely examples and are not intended to be limiting. For example, in the following description, forming a first component above or on a second component may include embodiments where the first and second components are formed in direct contact, and may also include embodiments where additional components may be formed between the first and second components such that the first and second components may not be in direct contact. Additionally, embodiments of the present disclosure may repeat reference numerals and / or characters in various instances. This repetition is for the purpose of simplicity and clarity and does not in itself indicate a relationship between the various embodiments and / or configurations discussed.

[0011] For ease of description, this document may use spatial relative terms such as "under", "below", "lower", "above", "upper", etc. to describe the relationship between one element or component and another (or other) element or component as shown in the figures. In addition to the orientations depicted in the figures, the spatial relative terms are intended to include different orientations of the device during use or operation. The device may be oriented in other ways (rotated 90 degrees or in other orientations), and the spatial relative descriptors used herein may be interpreted accordingly.

[0012] In addition, when describing a numerical value or a range of numerical values with terms such as "about", "approximately", etc., as understood by those of ordinary skill in the art, such terms are intended to cover a reasonable range of values that takes into account the variations that inherently occur during manufacturing. For example, based on known manufacturing tolerances associated with manufacturing a component having a characteristic related to a numerical value, a numerical value or a range of numerical values covers a reasonable range including the described numerical value, such as within + / - 10% of the described numerical value. For example, a material layer having a thickness of "about 5 nm" may include a size range from 4.25 nm to 5.75 nm, where the manufacturing tolerance associated with depositing the material layer, known to those of ordinary skill in the art, is + / - 15%.

[0013] Embodiments of the present disclosure generally relate to multi-gate transistors and manufacturing methods, and more particularly, to the formation of internal spacers during the manufacture of all-around gate (GAA) transistors. The internal spacers provide isolation between the gate structure and adjacent source / drain regions inside the GAA transistor. As used herein, the source / drain region may refer to a region that provides a source and / or a drain for one or more devices. It may also refer to the source or drain of one or more devices individually or jointly, depending on the context.

[0014] Multi-gate transistors include those transistors whose gate structures are formed on at least two sides of a channel region. These multi-gate devices may include p-type field effect transistors (PFETs) or n-type field effect transistors (NFETs). Specific examples presented herein are embodiments of a type of multi-gate transistor called an all-around gate (GAA) transistor. The GAA transistor includes a gate structure or a portion thereof (e.g., wrapping the channel) formed on all four sides of the channel. The devices presented herein also include embodiments having a channel disposed in one or more nanostructures such as nanosheets, nanowires, bar-shaped nanostructures, and / or other suitable configurations. The nanostructures are also referred to as channel members. Presented herein are embodiments of devices that may have one or more channel members (e.g., nanosheets) associated with a single, continuous gate structure. However, those of ordinary skill in the art will recognize that this teaching may apply to a single channel member (e.g., a single nanosheet) or any number of channel members. Those of ordinary skill in the art may recognize other examples of semiconductor devices that may benefit from aspects of the embodiments of the present disclosure.

[0015] The GAA transistor includes an internal spacer and a gate spacer (also referred to as an external spacer), as well as other spacers. The internal spacer is typically formed before the source / drain components. In an exemplary GAA manufacturing process, after manufacturing the source / drain trenches, the spacer for the internal spacer is fabricated by partially removing the sacrificial layer that is alternately arranged with the channel layer. Then, the internal spacer is formed in the spacer by dielectric material deposition and appropriate etching processes. However, the internal spacer introduces a dielectric surface that intersects with the semiconductor surface of the channel layer on the sidewalls of the source / drain trenches. Therefore, the subsequent epitaxial growth of the source / drain components is limited to those discontinuous semiconductor surfaces exposed on the sidewalls of the source / drain trenches. The portions of the source / drain components that grow separately from those discontinuous semiconductor surfaces will be merged later after reaching a certain height. However, such an epitaxial growth process may easily result in poor epitaxial quality (e.g., having voids underneath) and source / drain component dislocations in the source / drain region. The purpose of the embodiments of the present disclosure is to design a method for forming the internal spacer so as to improve the quality of the source / drain components in the source / drain region during epitaxial growth while maintaining the integrity of the precise dimensions and positions of the internal spacer.

[0016] In an exemplary process for forming a GAA transistor according to an embodiment of the present disclosure, a fin structure having a channel layer and a sacrificial layer is formed over a substrate. After forming a dummy gate stack over the channel region of the fin structure, a gate sidewall spacer is formed over the dummy gate stack. The source / drain regions of the fin structure are recessed. Then, source / drain components are formed over the source / drain grooves. After removing the dummy gate stack, the sacrificial layer is selectively removed to release the channel layer as a channel member. Then, a dielectric layer is deposited in the space between adjacent channel members. Then, the dielectric layer is etched back and partially recessed to form an internal spacer between the channel members. Then, a gate structure is formed to wrap each of the channel members.

[0017] Aspects of embodiments of the present disclosure will now be described in more detail with reference to the accompanying drawings. In this regard, Figure 1 is a flowchart of a method 100 for forming a semiconductor structure from a work-in-progress (WIP) structure according to an embodiment of the present disclosure. Method 100 is merely an example and is not intended to limit the embodiments of the present disclosure to what is explicitly shown in method 100. Additional steps may be provided before, during, and after method 100, and for additional embodiments of the method, some of the steps described may be replaced, eliminated, or moved around. For simplicity, not all steps are described in detail herein. The following describes method 100 in conjunction with Figures 2 to 16B describes method 100, Figures 2 to 16B is according to Figure 1Partial cross-sectional views of the WIP structure 200 of an embodiment of method 100 in different manufacturing stages. Since the WIP structure 200 will be manufactured into a semiconductor structure or a semiconductor device, the WIP structure 200 is also referred to herein as the semiconductor structure 200 or the semiconductor device 200. To avoid doubt, Figures 2 to 16B the X, Y, and Z directions in

[0018] are perpendicular to each other. Throughout the embodiments of the present disclosure, unless otherwise explicitly described, the same reference numerals represent the same components or steps. Figure 1 and Figure 2 referring to Figure 2 and

[0019] Figure 2 Figure 2As shown, this is for illustrative purposes only and is not intended to limit beyond what is specifically recited in the claims. It will be understood that any number of epitaxial layers can be formed in stack 204. The number of layers depends on the performance requirements for semiconductor device 200. In some embodiments, the number of channel layers 208 is between 2 and 10.

[0020] The sacrificial layer 206 and the channel layer 208 in stack 204 can be deposited using a molecular beam epitaxy (MBE) process, a vapor phase epitaxy (VPE) process, and / or other suitable epitaxial growth processes. As noted above, in at least some instances, the sacrificial layer 206 includes an epitaxially grown silicon germanium (SiGe) layer, and the channel layer 208 includes an epitaxially grown silicon (Si) layer. In some embodiments, the sacrificial layer 206 and the channel layer 208 are substantially dopant-free (i.e., have an unintentional dopant concentration from about 0 atoms / cm 3 to about 1×10 17 atoms / cm 3 ), where, for example, no intentional doping is performed during the epitaxial growth process for stack 204.

[0021] Referring Figure 1 and Figure 3 , method 100 includes block 104, in which a fin structure 212 is formed from stack 204 and substrate 202. To pattern stack 204, a hard mask layer can be deposited over stack 204 to form an etch mask. The hard mask layer can be a single layer or multiple layers. For example, the hard mask layer can include a pad oxide layer and a pad nitride layer disposed over the pad oxide layer. The fin structure 212 can be patterned from stack 204 and substrate 202 using a lithography process and an etching process. The lithography process can include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. In some embodiments, the etching process can include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. As Figure 3 shown, the etching process in block 104 forms trenches that vertically extend through portions of stack 204 and substrate 202. The trenches define the fin structure 212. In some implementations, a double patterning or multiple patterning process can be used to define the fin structure, which has, for example, a pitch less than that achievable using a single, direct lithography process. For example, in one embodiment, a material layer is formed over the substrate and patterned using a lithography process. A spacer is formed adjacent to the patterned material layer using a self-alignment process. The material layer is then removed, and the remaining spacer or mandrel can then be used to pattern the fin structure 212 by etching portions of stack 204 and substrate 202. As Figure 3As shown, the fin structure 212 extends vertically in the Z direction and longitudinally in the X direction. As Figure 3 As shown, the fin structure 212 includes a fin base 212B patterned from the substrate 202 and a patterned stack 204 disposed directly above the fin base 212B. In some instances, the width of the fin structure 212 measured in the Y direction can be between about 3 nm and about 20 nm.

[0022] Still referring to Figure 1 and Figure 3 , method 100 includes block 106, where an isolation component 214 is formed around the fin base 212B of the fin structure 212. In Figure 3 In some embodiments shown, the isolation component 214 is disposed on the sidewalls of the fin base 212B. In some embodiments, the isolation component 214 can be formed in a trench to isolate the fin structure 212 from adjacent fin structures. The isolation component 214 can also be referred to as a shallow trench isolation (STI) component 214. For example, in some embodiments, a dielectric layer is first deposited over the substrate 202 and the trench is filled with the dielectric layer. In some embodiments, the dielectric layer can include silicon oxide, silicon oxynitride, fluorine-doped silicate glass (FSG), a low-k dielectric, combinations thereof, and / or other suitable materials. In various instances, the dielectric layer can be deposited by a chemical vapor deposition (CVD) process, a sub-atmospheric CVD (SACVD) process, a flowable CVD process, a spin-on process, and / or other suitable processes. Then, the deposited dielectric material is thinned and planarized, for example, by a chemical mechanical polishing (CMP) process. The planarized dielectric layer is further recessed or etched back by a dry etching process, a wet etching process, and / or a combination thereof to form the Figure 3 STI component 214 shown. After the recessing, the fin structure 212 rises above the STI component 214 while the fin base 212B is embedded or buried in the isolation component 214.

[0023] Referring to Figure 1 and Figure 4 , method 100 includes block 108, where a semiconductor liner 210 is deposited over the fin structure 212. After forming the isolation component 214, the semiconductor liner 210 can be deposited over the semiconductor device 200 (including over the isolation component 214, over the top surface of the fin structure 212, and along the sidewalls of the fin structure 212). The semiconductor liner 210 is used to protect the sidewalls of the sacrificial layer 206 as they are subject to undesired damage during the manufacturing process. In some embodiments, the semiconductor liner 210 can include silicon (Si). In some implementations, the semiconductor liner 210 can be deposited using physical vapor deposition (PVD), CVD, or atomic layer deposition (ALD).

[0024] Referring toFigure 1 and Figures 5A to 5B , method 100 includes block 110, where a dummy gate stack 220 is formed over the channel region 212C of the fin structure 212. The dummy gate stack 220 serves as a placeholder to undergo various processes and will be removed and replaced by a functional gate structure. Other processes and configurations are also possible. Figure 5B is a cross-sectional view along the Figure 5A A-A' line in Figure 5B . In some embodiments as shown in Figure 5B , multiple dummy gate stacks 220 are formed over the fin structure 212, and the fin structure 212 can be divided into a channel region 212C located under the dummy gate stacks 220 and a source / drain region 212SD not located under the dummy gate stacks 220. The channel region 212C is adjacent to the source / drain region 212SD. As shown in

[0025] The formation of the dummy gate stack 220 can include depositing layers in the dummy gate stack 220 and patterning these layers. Referring to Figure 5A , a dummy dielectric layer 216, a dummy electrode layer 218, and a gate top hard mask layer 222 can be deposited blanketly over the semiconductor device 200. The dummy dielectric layer 216 can be formed on the fin structure 212 using a chemical vapor deposition (CVD) process, an ALD process, an oxygen plasma oxidation process, or other suitable processes. In the depicted embodiment, the dummy dielectric layer 216 is formed using an oxygen plasma oxidation process that substantially oxidizes the semiconductor liner 210 to form the dummy dielectric layer 216. In some instances, the dummy dielectric layer 216 can include silicon oxide. Thereafter, the dummy electrode layer 218 can be deposited over the dummy dielectric layer 216 using a CVD process, an ALD process, or other suitable processes. In some instances, the dummy electrode layer 218 can include polysilicon. For patterning purposes, the gate top hard mask layer 222 can be deposited on the dummy electrode layer 218 using a CVD process, an ALD process, or other suitable processes. Then, the gate top hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216 can be patterned to form the dummy gate stack 220, as shown in Figure 6As shown. For example, the patterning process may include a lithography process (e.g., photolithography or electron beam lithography) and an etching process. The lithography process may also include photoresist coating (e.g., spin coating), soft baking, mask alignment, exposure, post-exposure baking, photoresist development, rinsing, drying (e.g., spin drying and / or hard baking), other suitable lithography techniques, and / or combinations thereof. The lithography process forms a patterned photoresist layer. Then, in the etching process, the patterned photoresist layer is applied as an etch mask to pattern the top gate hard mask layer 222, the dummy electrode layer 218, and the dummy dielectric layer 216. In some embodiments, the etching process may include dry etching (e.g., RIE etching), wet etching, and / or other etching methods. In some embodiments, the top gate hard mask layer 222 may include a silicon oxide layer 222a and a silicon nitride layer 222b above the silicon oxide layer 222a. As Figure 6 shown, the patterned dummy gate stack 220 is patterned such that it is disposed only above the channel region 212C and not above the source / drain regions 212SD.

[0026] Referring Figure 1 to Figure 6 and, method 100 includes block 112, wherein a gate spacer layer 226 is deposited over the semiconductor device 200, including over the dummy gate stack 220. In some embodiments, the gate spacer layer 226 is conformally deposited over the semiconductor device 200, including over the top surface and sidewalls of the dummy gate stack 220. The term "conformal" is used herein to facilitate the description of a layer having a substantially uniform thickness over various regions. The gate spacer layer 226 may be deposited over the dummy gate stack 220 using a process such as a CVD process, a sub-atmospheric CVD (SACVD) process, an ALD process, or other suitable process. The gate spacer layer 226 may be a single layer or multiple layers. At least one layer of the gate spacer layer 226 may include silicon carbonitride, silicon oxycarbide, silicon carbonitride oxide, or silicon nitride. In some embodiments, the gate spacer layer 226 may include an inner layer 226a of silicon oxide and an outer layer 226b of silicon nitride above the inner layer 226a.

[0027] Referring Figure 1 to Figures 7A to 7B, Method 100 includes block 114, in which the source / drain regions 212SD of the fin structures 212 are anisotropically recessed to form source / drain trenches 228. The anisotropic etching may include dry etching or a suitable etching process for etching portions of the source / drain regions 212SD and the substrate 202. The resulting source / drain trenches 228 extend vertically through the depth of the stack 204 and partially into the substrate 202. Exemplary dry etching processes for block 114 may implement an oxygen-containing gas, a fluorine-containing gas (e.g., CF4, SF6, CH2F2, CHF3, and / or C2F6), a chlorine-containing gas (e.g., Cl2, CHCl3, CCl4, and / or BCl3), a bromine-containing gas (e.g., HBr and / or CHBr3), an iodine-containing gas, other suitable gases, and / or plasmas and / or combinations thereof. As Figure 7B shown, the source / drain regions 212SD of the fin structures 212 are recessed to expose the sidewalls of the sacrificial layer 206 and the channel layer 208. Because the source / drain trenches 228 extend into the substrate 202 below the stack 204, the source / drain trenches 228 include a bottom surface and lower sidewalls defined in the substrate 202. Referring to Figure 7B , Figure 7B includes a partial cross-sectional view across two adjacent source / drain regions 212SD. As Figure 7B shown, above the source / drain regions 212SD, most of the fin structures 212 are etched away, and the top surface of the fin base 212B is exposed in the source / drain regions 212SD. Because the gate spacer layer 226 is etched at a slower rate than the fin structures 212, the gate spacer layer 226 in the source / drain regions 212SD rises above the top surface of the fin base 212B. The portion of the gate spacer layer 226 remaining on the sidewalls of the pseudo-gate stack 220 (as Figure 7A shown) is referred to as a gate spacer, while the other portion of the gate spacer layer 226 remaining on the top surface of the fin base 212B (as Figure 7B shown) is also referred to as a fin spacer.

[0028] Referring to Figure 1 and Figures 8A to 8C , Method 100 includes block 116, in which source / drain components 244 are formed above the source / drain regions 212SD. The source / drain components 244 include a p-type source / drain component 244P formed in the NFET region (as Figure 8A shown) and an n-type source / drain component 244N formed in the PFET region (as Figure 8B shown). Figure 8Cis a partial cross-sectional view spanning two adjacent source / drain regions 212SD, one of which includes a p-type source / drain component 244P and the other of which includes an n-type source / drain component 244N.

[0029] The p-type source / drain component 244P may include silicon germanium (SiGe) and a p-type dopant, such as boron (B), gallium (Ga), or a combination thereof. In the depicted embodiment, as Figure 8A shown, the p-type source / drain component 244P may include multiple layers. For example, the p-type source / drain component 244P may include a lightly doped epitaxial layer 244Pa overlying the sidewalls and bottom surface of the source / drain trench 228 and a heavily doped epitaxial layer 244Pb overlying the lightly doped epitaxial layer 244Pa. The lightly doped epitaxial layer 244Pa includes a smaller dopant concentration (e.g., B%) and a smaller germanium concentration (e.g., Ge%) in atomic percentage compared to the heavily doped epitaxial layer 244Pb to reduce crystal dislocations and other crystal defects. In some embodiments, the G% in the lightly doped epitaxial layer 244Pa is between about 10% and about 20%, and the G% in the heavily doped epitaxial layer 244Pb is between about 30% and about 60%. It should be noted that the G% in the lightly doped epitaxial layer 244Pa is also different from the G% in the sacrificial layer 206, which allows the sacrificial layer 206 to be selectively etched away using the lightly doped epitaxial layer 244Pa as an etch stop layer in a subsequent process. For example, the G% in the sacrificial layer 206 may be in the range between about 20% and 30%, which is higher than the G% of the lightly doped epitaxial layer 244Pa but lower than the G% of the heavily doped epitaxial layer 244Pb.

[0030] Each of the epitaxial layers 244Pa and 244Pb can be formed using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the epitaxial layers 244Pa and 244Pb can be achieved by in-situ doping. Since the sidewalls and bottom surface of the source / drain trench 228 include a continuous semiconductor surface starting from the end portions of the sacrificial layer 206, the end portions of the channel layer 208, and the top surface of the substrate 202, the lightly doped epitaxial layer 244Pa is a continuous layer. In the depicted embodiment, the lightly doped epitaxial layer 244Pa has two vertical portions and a horizontal portion that form a U shape. Each vertical portion of the lightly doped epitaxial layer 244Pa conformally covers the sidewalls of the source / drain trench 228 with a substantially uniform thickness T1. In the depicted embodiment, the outer sidewall of the lightly doped epitaxial layer 244Pa facing the fin structure 212 and the inner sidewall of the lightly doped epitaxial layer 244Pa facing the source / drain trench 228 are both substantially flat and vertical. The horizontal portion of the lightly doped epitaxial layer 244Pa has a thickness T2 greater than T1 (i.e., T2>T1) due to a faster crystal growth rate from the top surface of the substrate 202. The heavily doped epitaxial layer 244Pb includes a lower portion surrounded by the lightly doped epitaxial layer 244Pa and an upper portion covering the lightly doped epitaxial layer 244Pa. The lower portion of the heavily doped epitaxial layer 244Pb has a thickness T3 greater than T1 (i.e., T3>T1) such that the heavily doped epitaxial layer 244Pb can account for a majority of the volume of the p-type source / drain component 244P to reduce the contact resistance. Depending on the epitaxial growth time of the lightly doped epitaxial layer 244Pa, in an alternative embodiment, the thickness T3 can be less than T2 (i.e., T3<T2), as Figure 8A depicted in, or greater than T2 (i.e., T3>T2).

[0031] The n-type source / drain component 244N can include silicon (Si) and an n-type dopant such as phosphorus (P), arsenic (As), antimony (Sb), or a combination thereof. In the depicted embodiment, as Figure 8B shown, the n-type source / drain component 244N can include multiple layers. For example, the n-type source / drain component 244N can include a lightly doped epitaxial layer 244Na located above the sidewalls and bottom surface of the source / drain trench 228 and a heavily doped epitaxial layer 244Nb located above the lightly doped epitaxial layer 244Na. The lightly doped epitaxial layer 244Na includes a smaller dopant concentration (e.g., P%) expressed in atomic percentage compared to the heavily doped epitaxial layer 244Nb to reduce crystal dislocations and other crystal defects. In some embodiments, the P% in the lightly doped epitaxial layer 244Na is between about 10% and about 20%, and the P% in the heavily doped epitaxial layer 244Pb is between about 30% and about 60%.

[0032] Each of the epitaxial layers 244Na and 244Nb can be formed using vapor phase epitaxy (VPE), ultra-high vacuum CVD (UHV-CVD), or molecular beam epitaxy (MBE). Doping of the epitaxial layers 244Na and 244Nb can be achieved by in-situ doping. Since the sidewalls and bottom surface of the source / drain trench 228 include a continuous semiconductor surface starting from the end portions of the sacrificial layer 206, the end portions of the channel layer 208, and the top surface of the substrate 202, the lightly doped epitaxial layer 244Na is a continuous layer. In the depicted embodiment, the lightly doped epitaxial layer 244Na has two vertical portions and a horizontal portion that form a U shape. Each vertical portion of the lightly doped epitaxial layer 244Na conformally covers the sidewalls of the source / drain trench 228 with a substantially uniform thickness T1'. In the depicted embodiment, the outer sidewall of the lightly doped epitaxial layer 244Na facing the fin structure 212 and the inner sidewall of the lightly doped epitaxial layer 244Na facing the source / drain trench 228 are both substantially flat and vertical. The horizontal portion of the lightly doped epitaxial layer 244Na has a thickness T2' greater than T1' (i.e., T2' > T1') due to a faster crystal growth rate from the top surface of the substrate 202. The heavily doped epitaxial layer 244Nb includes a lower portion surrounded by the lightly doped epitaxial layer 244Na and an upper portion covering the lightly doped epitaxial layer 244Na. In the depicted embodiment, the lower portion of the heavily doped epitaxial layer 244Nb has a thickness T3' less than T1' and T2 (i.e., T3' < T1' < T2), such that the lightly doped epitaxial layer 244Na can occupy most of the volume of the n-type source / drain component 244N. Optionally, depending on the epitaxial growth time of the lightly doped epitaxial layer 244Na, the thickness T3' can be greater than T1' but less than T2' (i.e., T1' < T3' < T2'), or greater than T1' and T2' (i.e., T1' < T2' < T3').

[0033] In the depicted embodiment, since the heavily doped epitaxial layer 244Nb has a lower portion smaller than the heavily doped epitaxial layer 244Pb, during epitaxial growth, the upper portion of the heavily doped epitaxial layer 244Nb can protrude beyond the top surface of the lightly doped epitaxial layer 244Na more than the heavily doped epitaxial layer 244Pb. In other words, the topmost portion of the n-type source / drain component 244N can be higher than the topmost portion of the p-type source / drain component 244P. Additionally, compared to the generally flat top surface of the upper portion of the heavily doped epitaxial layer 244Pb, the upper portion of the heavily doped epitaxial layer 244Nb can have a wavy top surface. In other words, the top surface of the n-type source / drain component 244N can have a larger surface roughness than the top surface of the p-type source / drain component 244P.

[0034] In Figure 8CIn some embodiments shown, the n-type source / drain component 244N may be adjacent to the p-type source / drain component 244P. The n-type source / drain component 244N may include silicon (Si) and an n-type dopant such as phosphorus (P), arsenic (As), or antimony (Sb). The p-type source / drain component 244P may include silicon germanium (SiGe) and a p-type dopant such as boron (B). The fin spacers 226 may be disposed on the lower sidewalls of each of the n-type source / drain component 244N and the p-type source / drain component 244P. For ease of illustration and description, the n-type source / drain component 244N and the p-type source / drain component 244P may be collectively referred to as the source / drain component 244, as Figure 8C shown.

[0035] Refer to Figure 1 and Figures 9A to 9B , method 100 includes block 118, where an interlayer dielectric (ILD) layer 248 is formed on the source / drain component 244. In some embodiments, a contact etch stop layer (CESL) 246 is also formed before forming the ILD layer 248. In some embodiments, the CESL 246 may include silicon nitride or aluminum nitride. In some implementations, the CESL 246 may be deposited using CVD or atomic layer deposition (ALD). Then, the ILD layer 248 is deposited over the CESL 246. In some embodiments, the ILD layer 248 includes a material such as tetraethyl orthosilicate (TEOS) oxide, undoped silicate glass, or doped silicon oxide such as borophosphosilicate glass (BPSG), fused silica glass (FSG), phosphosilicate glass (PSG), boron-doped silicon glass (BSG), and / or other suitable dielectric materials. The ILD layer 248 may be deposited using CVD, flowable CVD (FCVD), spin coating, or a suitable deposition technique. After depositing the ILD layer 248, the semiconductor device 200 may be planarized by a planarization process to remove the gate top hard mask layer 222 and expose the pseudo-gate stack 220. For example, the planarization process may include a chemical mechanical planarization (CMP) process. The exposure of the pseudo-gate stack 220 allows its removal.

[0036] Refer to Figure 1 and Figures 10A to 10B, method 100 includes block 120, in which a dummy gate stack 220 is removed to form a gate trench 250, and a plurality of channel layers 208 are released as channel members 2080. The removal of the dummy gate stack 220 may include one or more etching processes selective to the material of the dummy gate stack 220. For example, the removal of the dummy gate stack 220 may be implemented using selective wet etching, selective dry etching, or a combination thereof that is selective to the dummy gate stack 220. After forming the gate trench 250, a sacrificial layer 206 interleaved with the channel layer 208 in the channel region 212C is selectively removed. The selective removal of the sacrificial layer 206 releases the channel layer 208 to form the channel member 2080. Depending on the design, the channel member 2080 may take the form of a nanowire, a nanorod, a nanosheet, or other nanostructures. The selective removal of the sacrificial layer 206 forms spacings 252 between and around adjacent channel members 2080. The selective removal of the sacrificial layer 206 may be implemented by selective dry etching, selective wet etching, or other selective etching processes. Exemplary selective dry etching processes may include using one or more fluorine-based etchants, such as fluorine gas or hydrofluorocarbons. Exemplary selective wet etching processes may include APM etching (e.g., an ammonia hydroxide-hydrogen peroxide-water mixture). The germanium concentration difference between the outer layer of the source / drain component 244 and the sacrificial layer 206 creates an etch contrast, such that the source / drain component 244 can remain substantially intact during the selective removal of the sacrificial layer 206. It should be noted that, as Figure 10A and Figure 10B depicted, the topmost channel member 2080 may experience some etch loss due to being directly exposed in the gate trench 250. This causes a curvature profile to appear on the top surface at the center of the topmost channel member 2080 and exposes a portion of the bottom surface of the gate spacer 226.

[0037] Refer to Figure 1 and Figures 11A to 11B, method 100 includes block 122, in which a dielectric material layer 254 is deposited in the gate trench 250 and in and around the spacer 252 between the adjacent channel members 2080. As will be shown in further detail below, the dielectric material layer 254 is etched and formed into an inner spacer. Thus, the dielectric material layer 254 is also referred to as the inner spacer material layer 254. The inner spacer material layer 254 may include a dielectric material such as SiOC, SiOCN, SiCN, and / or other suitable materials. In various embodiments, at least the inner layer 226a of the gate spacer 226 and the inner spacer material layer 254 include different material compositions. In one example, the inner layer 226a of the gate spacer 226 includes silicon oxide, while each of the outer layer 226b of the gate spacer 226 and the inner spacer material layer 254 includes silicon nitride. In another example, the inner layer 226a of the gate spacer 226 includes silicon oxide, the outer layer 226b of the gate spacer 226 includes silicon nitride, and the inner spacer material layer 254 includes silicon oxycarbide. In some embodiments, the inner spacer material layer 254 is deposited in a cyclic deposition and etching (CDE) process. The CDE process may include multiple alternating deposition cycles and multiple etching cycles. In some examples, each deposition cycle is immediately followed by an etching cycle. In one example, each of the etching cycles includes using a fluorine-containing etchant such as sulfur hexafluoride (SF6) or nitrogen trifluoride (NF3). The etching cycles keep removing the dielectric material from the gate spacer 226, preventing the dielectric material from accumulating too fast and closing the gate trench 250. The etching cycles also allow the elongated spacer 252 to remain as a void between the adjacent channel members 2080. These voids are deliberately retained so that the etchant applied in a subsequent etching process can flow into these voids and facilitate partial removal of the inner spacer material layer 254 to form the inner spacer.

[0038] Reference Figure 1 and Figures 12A to 12C, Method 100 includes block 124, in which a central portion of the inner spacer material layer 254 is removed from the channel region 212C, while other portions located directly under the gate spacer 226 and adjacent to the source / drain components 244 are retained as the inner spacer 2540. In some embodiments, the etching process in block 124 includes a cyclic etching process that alternates between a surface treatment process and a selective etching process. In the cyclic process, the portions of the inner spacer material layer 254 exposed in the channel region 212C are repeatedly subjected to a surface treatment and a subsequent selective etching process to remove the treated surface portions. The cyclic process continues until the inner spacer material layer 254 is completely removed from the channel region 212C, with other portions located directly under the gate spacer 226 retained as the inner spacer 2540. In various embodiments, using the gate spacer 226 as a processing mask, the surface treatment (e.g., oxidation treatment or nitridation treatment) is performed through the gate trench 250, such as along Figure 12A shown in the cross-sectional view along the C-C’ line in Figure 12C , where the inner spacer 2540 is retained under the gate spacer 226. Still referring to Figure 12A and Figure 12B , the central portion of the inner spacer material layer 254 between the two opposite sidewalls of the gate spacer 226 is subjected to a surface treatment such that the material composition changes, resulting in an etching selectivity compared to other portions of the inner spacer material layer 254. Then, a selective etching process is applied in a cycle to remove the treated (e.g., oxidized or nitrided) surface portions of the inner spacer material layer 254, as the etching process is adjusted to be selective to the oxide or nitride and substantially does not etch the untreated portions. The remaining spacer (or void) 252 facilitates the etchant reaching the treated surface portions at different locations and improves the etching rate uniformity. The selective etching process may include wet etching, dry etching, reactive ion etching, or other suitable etching methods.

[0039] After removing the inner spacer material layer 254 from the channel region 212C, the channel member 2080 is released again. The spacer 252 expands between adjacent channel members 2080. As will be shown in further detail below, a high-k metal gate (HK MG) structure will be formed in the expanded spacer 252, adjacent to the inner spacer 2540. Thus, the inner spacer 2540 provides isolation between the metal gate structure and the epitaxial S / D component 238. The width of the expanded spacer 252 measured in the X direction may be greater than the width between the opposite sidewalls of the gate spacer 226. Therefore, the lower portion of the metal gate structure to be formed under the topmost channel member 2080 may be wider in the X direction than its upper portion between the opposite sidewalls of the gate spacer 226. In the depicted embodiment, as Figure 12A and Figure 12BAs shown, due to the etching process starting from the channel region 212C, the inner spacer 2540 has an inner sidewall facing the widened spacer 252 (the inner sidewall presents a concave profile that bends towards the source / drain component 244) and an outer sidewall that interfaces with the source / drain component 244 (the outer sidewall is substantially straight).

[0040] In some embodiments of the GAA fabrication process, the etching process for forming the inner spacer starts from the source / drain region 212SD, which results in the outer sidewall having a concave profile that bends towards the channel region 212C. In comparison, the curved inner sidewall and the substantially straight outer sidewall of the inner spacer 2540 as depicted herein represent one of the characteristic components of the resulting device through some exemplary fabrication processes proposed in the embodiments of the present disclosure. It should be noted that due to the curvature profile in the top surface of the topmost channel member 2080, a portion of the inner spacer material layer 254 located in the corner region of the curvature profile may remain directly below the gate spacer 226 without being removed. The remaining portion of the inner spacer material layer 254 vertically stacked between the topmost channel member 2080 and the gate spacer 226 is denoted as dielectric residue 254R, which may remain in the final structure. The dielectric residue 254R having the same material composition as the inner spacer 2540 as depicted herein represents another of the characteristic components of the resulting device through some exemplary fabrication processes proposed in the embodiments of the present disclosure.

[0041] Reference Figure 1 and Figures 13A to 13B , method 100 includes block 126, where a gate structure 260 is formed in the gate trench 250 to wrap the channel member 2080. Due to the high-K dielectric layer and the metal-containing gate electrode layer, the gate structure 260 is also referred to as a high-K metal gate (HK MG) structure, although other compositions are possible. As discussed above, due to the widening of the spacer 252, the lower portion of the gate structure 260 located below the topmost channel member 2080 can be wider when measured in the X direction than its upper portion between the opposing sidewalls of the gate spacer 226, as Figure 13A and Figure 13Bdepicted in. Optionally, the gate structure 260 may have a substantially uniform width in its upper and lower portions. In the described embodiment, the gate structure 260 includes an interface layer 262 that interfaces with the channel member 2080 and the substrate 202 in the channel region 212C, a high-k dielectric layer 264 above the interface layer 262, a work function layer 266 above the high-k dielectric layer 264 (including a p-type work function layer 266P in the PFET region and an n-type work function layer 266N in the NFET region), and a metal fill layer 268 surrounded by the work function layer 266 (including a metal fill layer 268P in the PFET region and a metal fill layer 268N in the NFET region). The interface layer 262 and the high-k dielectric layer 264 are collectively referred to as the gate dielectric layer. The work function layer 266 and the metal fill layer 268 are collectively referred to as the gate electrode layer.

[0042] The interface layer 262 may include a dielectric material such as silicon oxide, hafnium silicate, or silicon oxynitride. The interface layer may be formed by chemical oxidation, thermal oxidation, atomic layer deposition (ALD), chemical vapor deposition (CVD), and / or other suitable methods. The high-k dielectric layer 264 may include a high-k dielectric material such as hafnium oxide. Optionally, the gate dielectric layer may include other high-k dielectric materials such as titanium oxide (TiO2), hafnium zirconium oxide (HfZrO), tantalum oxide (Ta2O5), hafnium silicon oxide (HfSiO4), zirconium oxide (ZrO2), zirconium silicon oxide (ZrSiO2), lanthanum oxide (La2O3), aluminum oxide (Al2O3), zirconium oxide (ZrO), yttrium oxide (Y2O3), hafnium lanthanum oxide (HfLaO), lanthanum silicon oxide (LaSiO), aluminum silicon oxide (AlSiO), hafnium tantalum oxide (HfTaO), hafnium titanium oxide (HfTiO), combinations thereof, or other suitable materials. The high-k dielectric layer 264 may be formed by ALD, physical vapor deposition (PVD), CVD, oxidation, and / or other suitable methods.

[0043] The work function layer 266 may be a p-type or n-type work function layer depending on the type of device (PFET or NFET). The p-type work function layer 266P includes metals having a sufficiently large effective work function, selected from the group consisting of, but not limited to, titanium nitride (TiN), tantalum nitride (TaN), ruthenium (Ru), molybdenum (Mo), tungsten (W), platinum (Pt), or combinations thereof. The n-type work function layer 266N includes metals having a sufficiently low effective work function, selected from the group consisting of, but not limited to, titanium (Ti), aluminum (Al), tantalum carbide (TaC), tantalum carbonitride (TaCN), tantalum silicon nitride (TaSiN), titanium silicon nitride (TiSiN), or combinations thereof. Each of the metal fill layers 268N and 268P may include aluminum (Al), tungsten (W), cobalt (Co), and / or other suitable materials. In various embodiments, the gate electrode layer may be formed by ALD, PVD, CVD, electron beam evaporation, or other suitable processes.

[0044] Now refer to Figure 14A and Figure 14B . Figure 14A and Figure 14B illustrate an alternative embodiment of semiconductor device 200 at the end of the operation in block 126. As Figure 14A and Figure 14B shown, semiconductor device 200 has many aspects similar to the embodiments shown in Figure 13A and Figure 13B . One difference is that a buffer epitaxial layer 242 is deposited under the bottom of the source / drain component 244. Before forming the source / drain component 244, the buffer epitaxial layer 242 grows epitaxially from the top surface of the fin substrate 212B. For example, the epitaxial growth of the buffer epitaxial layer 242 can be implemented by VPE, ultra-high vacuum CVD (UHV-CVD), MBE, and / or other suitable epitaxial growth processes. In some embodiments, the buffer epitaxial layer 242 includes the same material as the substrate 202, such as silicon. In some alternative embodiments, the buffer epitaxial layer 242 includes a different semiconductor material other than silicon, such as SiGe, SiSn, or other suitable semiconductor materials. In some embodiments, the buffer epitaxial layer 242 does not contain dopants, for example, no intentional doping is implemented during the epitaxial growth process. By comparison, in one example, the substrate 202 is lightly doped and has a higher doping concentration than the buffer epitaxial layer 242. The buffer epitaxial layer 242 provides a high-resistance path from the S / D region to the semiconductor substrate, thereby suppressing leakage current in the semiconductor substrate.

[0045] Now refer to Figure 15A and Figure 15B . Figure 15A and Figure 15B illustrate an alternative embodiment of semiconductor device 200 at the end of the operation in block 126. As Figure 15A and Figure 15B shown, semiconductor device 200 has many aspects similar to the embodiments shown in Figure 13A and Figure 13B . One difference is that the inner spacer 2540 has a more rectangular shape, where both the inner sidewall and the outer sidewall are substantially straight. The straight inner sidewall is mainly due to different parameters applied to the cyclic etching process in block 124.

[0046] Now refer to Figure 16A and Figure 16B . Figure 16A and Figure 16B illustrate an alternative embodiment of semiconductor device 200 at the end of the operation in block 126. As Figure 16A and Figure 16BThe semiconductor device 200 shown in Figure 13A and Figure 13B has aspects similar to those of the embodiments shown therein. One difference is that the internal spacer 2540 has an inner sidewall and an outer sidewall, and the inner sidewall and the outer sidewall have a curvature profile that bends towards the source / drain component 244. Due to the curvature of the outer sidewall, a portion of the internal spacer 2540 is partially embedded in the sidewall of the source / drain component 244. The curvature of the outer sidewall is mainly due to the etching loss of the outer layer of the source / drain component 244 during the selective removal of the sacrificial layer 206 in the frame 120 due to limited etching contrast.

[0047] The semiconductor device 200 can undergo further processing to form various components and regions known in the art. For example, subsequent processing can form contact openings, contact metals, and various contact / via / wire and multi-layer interconnect components (e.g., metal layers and interlayer dielectrics) configured to connect the various components to form a functional circuit that can include one or more multi-gate devices on the substrate 202. In the progression of the example, the multi-layer interconnect can include vertical interconnects (such as vias or contacts) and horizontal interconnects (such as metal wires). The various interconnect components can employ various conductive materials including copper, tungsten, and / or silicides. In one example, a damascene and / or dual damascene process is used to form a copper-related multi-layer interconnect structure. Additionally, additional process steps can be implemented before, during, and after the method 100, and some of the process steps described above can be replaced or eliminated according to the various embodiments of the method 100.

[0048] Although not intended to be limiting, the embodiments of the present disclosure provide one or more of the following advantages. For example, the embodiments of the present disclosure provide a method for forming an internal spacer after forming the source / drain component, which effectively reduces crystal dislocations and other defects in the source / drain region of the GAA transistor. Additionally, the method for forming the internal spacer can be easily integrated into existing semiconductor manufacturing processes.

[0049] In an exemplary aspect, embodiments of the present disclosure relate to a method. The method includes: forming a stack including a plurality of channel layers interleaved with a plurality of sacrificial layers over a substrate; patterning the stack to form fin structures; forming a dummy gate stack over the channel regions of the fin structures; depositing gate spacers on sidewalls of the dummy gate stack; recessing source / drain regions of the fin structures to form source / drain trenches that expose sidewalls of the channel layers and sidewalls of the sacrificial layers; epitaxially growing a first epitaxial layer from the sidewalls of the channel layers and the sidewalls of the sacrificial layers; epitaxially growing a second epitaxial layer on the first epitaxial layer; removing the dummy gate stack; selectively removing the sacrificial layers in the channel regions to release the channel layers as channel members; depositing a dielectric material layer to wrap the channel members; removing the dielectric material layer from the channel regions, while a portion of the dielectric material layer located directly below the gate spacers remains as an inner spacer; and forming a metal gate structure to wrap the channel members, with the inner spacer being interposed between the metal gate structure and the first epitaxial layer. In some embodiments, the inner spacer has a first sidewall that interfaces with the first epitaxial layer and a second sidewall that interfaces with the metal gate structure, and the second sidewall of the inner spacer is curved towards the first epitaxial layer. In some embodiments, the first sidewall of the inner spacer is substantially straight. In some embodiments, the first sidewall of the inner spacer is curved towards the first epitaxial layer. In some embodiments, depositing the dielectric material layer includes a cyclic deposition and etching process. In some embodiments, removing the dielectric material layer includes a cyclic surface treatment and etching process. In some embodiments, voids remain between adjacent channel members after depositing the dielectric material layer. In some embodiments, each of the first epitaxial layer and the second epitaxial layer includes silicon germanium, and the germanium concentration expressed in atomic percentage is smaller in the first epitaxial layer than in the second epitaxial layer. In some embodiments, the first epitaxial layer includes a first sidewall that interfaces with the channel member and a second sidewall that interfaces with the second epitaxial layer, and the first sidewall and the second sidewall of the first epitaxial layer are substantially straight. In some embodiments, the method further includes: forming an epitaxial buffer layer between the substrate and the first epitaxial layer.

[0050] In another exemplary aspect, embodiments of the present disclosure relate to a method. The method includes: forming a structure including a plurality of channel members vertically stacked over a substrate; forming source / drain components adjacent to the channel members; after forming the source / drain components, depositing a dielectric material layer that wraps the channel members, with voids remaining between adjacent channel members after depositing the dielectric material layer; selectively removing a central portion of the dielectric material layer to release the channel members; and forming a metal gate structure that wraps the channel members. Side portions of the dielectric material layer are interposed between the metal gate structure and the source / drain components. In some embodiments, selectively removing the central portion of the dielectric material layer includes repeating steps of a processing step and a selective etching step until the channel members are released. In some embodiments, the processing step is an oxidation step or a nitridation step. In some embodiments, the side portions of the dielectric material layer include a first sidewall facing the source / drain components and a second sidewall facing the metal gate structure, and wherein the second sidewall of the side portions of the dielectric material layer is curved toward the source / drain components. In some embodiments, the first sidewall of the side portions of the dielectric material layer is substantially straight. In some embodiments, after selectively removing the central portion of the dielectric material layer, a portion of the dielectric material layer remains on the top surface of the topmost one of the channel members.

[0051] In yet another exemplary aspect, embodiments of the present disclosure relate to a semiconductor structure. The semiconductor structure includes: a plurality of nanostructures suspended over a substrate; a gate structure that wraps each of the plurality of nanostructures; gate spacers disposed on sidewalls of the gate structure; source / drain components adjacent to the nanostructures; and an internal spacer interposed between the gate structure and the source / drain components and extending between two adjacent nanostructures. The internal spacer includes a first sidewall facing the source / drain components and a second sidewall facing the gate structure, the first sidewall being straight and perpendicular, and the second sidewall being curved toward the source / drain components. In some embodiments, the gate structure includes a lower portion located below the topmost one of the nanostructures and an upper portion located above the topmost one of the nanostructures, and the lower portion is wider than the upper portion measured in the longitudinal direction of the nanostructures. In some embodiments, the source / drain components include a first epitaxial layer and a second epitaxial layer surrounded by the first epitaxial layer, the first epitaxial layer including a sidewall facing the gate structure, and the sidewall of the first epitaxial layer being straight and perpendicular. In some embodiments, the first epitaxial layer includes a germanium concentration lower than that of the second epitaxial layer.

[0052] Some embodiments of the present application provide a method of manufacturing a semiconductor structure, including: forming a stack including a plurality of channel layers interleaved with a plurality of sacrificial layers above a substrate; patterning the stack to form a fin structure; forming a dummy gate stack above a channel region of the fin structure; depositing gate spacers on sidewalls of the dummy gate stack; recessing source / drain regions of the fin structure to form source / drain trenches that expose sidewalls of the channel layers and sidewalls of the sacrificial layers; epitaxially growing a first epitaxial layer from the sidewalls of the channel layers and the sidewalls of the sacrificial layers; epitaxially growing a second epitaxial layer on the first epitaxial layer; removing the dummy gate stack; selectively removing the sacrificial layers in the channel region to release the channel layers as channel members; depositing a dielectric material layer wrapping the channel members; removing the dielectric material layer from the channel region, while a portion of the dielectric material layer directly under the gate spacers remains as an internal spacer; and forming a metal gate structure wrapping the channel members, with the internal spacer being between the metal gate structure and the first epitaxial layer.

[0053] In some embodiments, the internal spacer has a first sidewall interfacing with the first epitaxial layer and a second sidewall interfacing with the metal gate structure, and wherein the second sidewall of the internal spacer curves towards the first epitaxial layer. In some embodiments, the first sidewall of the internal spacer is substantially straight. In some embodiments, the first sidewall of the internal spacer curves towards the first epitaxial layer. In some embodiments, depositing the dielectric material layer includes a cyclic deposition and etching process. In some embodiments, removing the dielectric material layer includes a cyclic surface treatment and etching process. In some embodiments, voids remain between adjacent channel members after depositing the dielectric material layer. In some embodiments, each of the first epitaxial layer and the second epitaxial layer includes silicon germanium, and wherein the germanium concentration in atomic percentage is smaller in the first epitaxial layer than in the second epitaxial layer. In some embodiments, the first epitaxial layer has a first sidewall interfacing with the channel member and a second sidewall interfacing with the second epitaxial layer, and wherein the first sidewall and the second sidewall of the first epitaxial layer are substantially straight. In some embodiments, the method further includes: forming an epitaxial buffer layer between the substrate and the first epitaxial layer.

[0054] Some other embodiments of the present application provide a method of fabricating a semiconductor structure, including: forming a structure including a plurality of channel members vertically stacked over a substrate; forming source / drain components adjacent to the channel members; after forming the source / drain components, depositing a dielectric material layer that wraps the channel members, wherein voids remain between adjacent ones of the channel members after depositing the dielectric material layer; selectively removing a central portion of the dielectric material layer to release the channel members; and forming a metal gate structure that wraps the channel members, wherein side portions of the dielectric material layer are interposed between the metal gate structure and the source / drain components.

[0055] In some embodiments, selectively removing the central portion of the dielectric material layer includes repeating steps of a processing process and a selective etching process until the channel members are released. In some embodiments, the processing process is an oxidation process or a nitridation process. In some embodiments, the side portions of the dielectric material layer include a first sidewall facing the source / drain components and a second sidewall facing the metal gate structure, and wherein the second sidewall of the side portions of the dielectric material layer is curved toward the source / drain components. In some embodiments, the first sidewall of the side portions of the dielectric material layer is substantially straight. In some embodiments, after selectively removing the central portion of the dielectric material layer, a portion of the dielectric material layer remains on the top surface of the topmost one of the channel members.

[0056] Some further embodiments of the present application provide a semiconductor structure, including: a plurality of nanostructures suspended over a substrate; a gate structure that wraps each of the plurality of nanostructures; gate spacers disposed on sidewalls of the gate structure; source / drain components adjacent to the nanostructures; and internal spacers interposed between the gate structure and the source / drain components and extending between two adjacent ones of the nanostructures, wherein the internal spacers include a first sidewall facing the source / drain components and a second sidewall facing the gate structure, the first sidewall being straight and perpendicular, and the second sidewall being curved toward the source / drain components.

[0057] In some embodiments, the gate structure includes a lower portion positioned below the topmost one of the nanostructures and an upper portion positioned above the topmost one of the nanostructures, and the lower portion is wider than the upper portion measured in the longitudinal direction of the nanostructures. In some embodiments, the source / drain component includes a first epitaxial layer and a second epitaxial layer surrounded by the first epitaxial layer, the first epitaxial layer includes sidewalls facing the gate structure, and the sidewalls of the first epitaxial layer are straight and perpendicular. In some embodiments, the first epitaxial layer includes a germanium concentration lower than that of the second epitaxial layer.

[0058] The features of several embodiments are outlined above so that those of ordinary skill in the art can better understand various aspects of the embodiments of the present disclosure. Those of ordinary skill in the art should understand that they can readily use the embodiments of the present disclosure as a basis to design or modify other processes and structures for performing the same purposes and / or achieving the same advantages as the embodiments introduced herein. Those of ordinary skill in the art should also realize that such equivalent constructs do not depart from the spirit and scope of the embodiments of the present disclosure, and that various changes, substitutions, and alterations can be made herein without departing from the spirit and scope of the embodiments of the present disclosure.

Claims

1. A method of manufacturing a semiconductor structure, comprising: forming a stack including a plurality of channel layers interleaved with a plurality of sacrificial layers over a substrate; patterning the stack to form a fin structure; forming a dummy gate stack over a channel region of the fin structure; depositing gate spacers on sidewalls of the dummy gate stack; recessing source / drain regions of the fin structure to form source / drain trenches that expose sidewalls of the channel layers and sidewalls of the sacrificial layers; epitaxially growing a first epitaxial layer from the sidewalls of the channel layers and the sidewalls of the sacrificial layers; epitaxially growing a second epitaxial layer on the first epitaxial layer; removing the dummy gate stack; selectively removing the sacrificial layers in the channel region to release the channel layers as channel members; depositing a dielectric material layer that wraps the channel members; removing the dielectric material layer from the channel region, while a portion of the dielectric material layer located directly under the gate spacers remains as an internal spacer; and forming a metal gate structure that wraps the channel members, with the internal spacer being between the metal gate structure and the first epitaxial layer.

2. The method according to claim 1, wherein, The internal spacer has a first sidewall that interfaces with the first epitaxial layer and a second sidewall that interfaces with the metal gate structure, and wherein the second sidewall of the internal spacer is curved towards the first epitaxial layer.

3. The method according to claim 2, wherein The first sidewall of the internal spacer is substantially straight.

4. The method according to claim 2, wherein, The first sidewall of the internal spacer is curved towards the first epitaxial layer.

5. The method according to claim 1, wherein, Depositing the dielectric material layer includes a cyclic deposition and etching process.

6. The method according to claim 1, wherein Removing the dielectric material layer includes a cyclic surface treatment and etching process.

7. The method according to claim 1, wherein After depositing the dielectric material layer, voids remain between adjacent ones of the channel members.

8. The method according to claim 1, wherein, Each of the first epitaxial layer and the second epitaxial layer includes silicon germanium, and wherein the germanium concentration in atomic percentage is smaller in the first epitaxial layer than in the second epitaxial layer.

9. A method of manufacturing a semiconductor structure, comprising: forming a structure including a plurality of channel members vertically stacked over a substrate; forming source / drain components adjacent to the channel members; after forming the source / drain components, depositing a dielectric material layer that wraps the channel members, wherein voids remain between adjacent ones of the channel members after depositing the dielectric material layer; selectively removing a central portion of the dielectric material layer to release the channel members; and forming a metal gate structure that wraps the channel members, wherein side portions of the dielectric material layer are between the metal gate structure and the source / drain components.

10. A semiconductor structure, comprising: a plurality of nanostructures suspended over a substrate; a gate structure that wraps each of the plurality of nanostructures; gate spacers disposed on sidewalls of the gate structure; source / drain components adjacent to the nanostructures; and An internal spacer, which is disposed between the gate structure and the source / drain component and extends between two adjacent ones of the nanostructures, wherein the internal spacer includes a first sidewall facing the source / drain component and a second sidewall facing the gate structure, the first sidewall is straight and perpendicular, and the second sidewall is curved toward the source / drain component.

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