Semiconductor device and method of manufacturing the same

Abstract

A semiconductor device includes: first and second semiconductor patterns alternately stacked one by one on an upper surface of a substrate; a gate electrode on an uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern, the gate electrode extending in the first lateral direction; a first source / drain pattern and a second source / drain pattern spaced apart from each other in a second lateral direction intersecting the first lateral direction, the first semiconductor pattern and the second semiconductor pattern being between the first source / drain pattern and the second source / drain pattern; and a protection pattern between an uppermost semiconductor pattern of the first and second semiconductor patterns and the gate electrode. The protection pattern is directly on sidewalls of the first semiconductor pattern and the second semiconductor pattern in the first lateral direction.

Description

[0001] Cross - reference to related applications

[0002] This application claims priority based on and to Korean Patent Application No. 10 - 2024 - 0006808, filed with the Korean Intellectual Property Office on January 16, 2024, the entire disclosure of which is incorporated herein by reference. Technical field

[0003] The inventive concept relates to a semiconductor device and a method of manufacturing the semiconductor device. Background art

[0004] Semiconductor devices may include integrated circuits (ICs) that include not only metal - oxide - semiconductor field - effect transistors (MOSFETs) but also passive elements. Passive elements may include diodes. As the size and design rules of semiconductor devices are gradually reduced, the size reduction of MOSFETs and passive elements is also accelerating. As the sizes of MOSFETs and passive elements are reduced, the operating characteristics of semiconductor devices may deteriorate. Thus, various methods for forming semiconductor devices with excellent performance while overcoming the limitations caused by the high integration of semiconductor devices have been studied. Summary of the invention

[0005] The inventive concept provides a semiconductor device with improved electrical characteristics.

[0006] The inventive concept also provides a method of manufacturing a semiconductor device with improved electrical characteristics.

[0007] According to various aspects of the inventive concept, there is provided a semiconductor device including: a substrate including a first region and a second region adjacent to the first region, the first region having a first conductivity type and the second region having a second conductivity type different from the first conductivity type; a first semiconductor pattern and a second semiconductor pattern alternately stacked one by one on an upper surface of the substrate, the first semiconductor pattern including a material different from the second semiconductor pattern; a gate electrode on the uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern, the gate electrode extending in a first lateral direction; a first source / drain pattern and a second source / drain pattern spaced apart from each other in a second lateral direction intersecting the first lateral direction, the first semiconductor pattern and the second semiconductor pattern being between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern having the first conductivity type and the second source / drain pattern having the second conductivity type; and a protection pattern between the uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern and the gate electrode, the protection pattern including a dielectric material, wherein the protection pattern is directly on sidewalls of the first semiconductor pattern and the second semiconductor pattern in the first lateral direction.

[0008] According to various aspects of the inventive concept, a semiconductor device is provided, including: a lower wiring layer including a lower insulating layer and lower wirings in the lower insulating layer; a first semiconductor pattern and a second semiconductor pattern alternately stacked one by one on an upper surface of the lower wiring layer, the first semiconductor pattern including a material different from that of the second semiconductor pattern; a gate electrode on the uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern, the gate electrode extending in a first lateral direction; a first source / drain pattern and a second source / drain pattern spaced apart from each other in a second lateral direction intersecting the first lateral direction, the first semiconductor pattern and the second semiconductor pattern being between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern having a first conductivity type, and the second source / drain pattern having a second conductivity type different from the first conductivity type; a protection pattern between the uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern and the gate electrode, the protection pattern including a dielectric material; and a gate spacer on sidewalls of the gate electrode in the second lateral direction, wherein the protection pattern includes a first portion on the uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern and a second portion extending along an inner sidewall of the gate spacer in a vertical direction.

[0009] According to various aspects of the inventive concept, a semiconductor device is provided, including: a substrate including a first region and a second region adjacent to the first region, the first region having a first conductivity type, and the second region having a second conductivity type different from the first conductivity type; a first semiconductor pattern and a second semiconductor pattern alternately stacked one by one on an upper surface of the substrate, the first semiconductor pattern including a material different from that of the second semiconductor pattern; a gate electrode on the uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern, the gate electrode extending in a first lateral direction; a gate spacer on sidewalls of the gate electrode in a second lateral direction intersecting the first lateral direction; a first source / drain pattern and a second source / drain pattern spaced apart from each other in the second lateral direction, the first semiconductor pattern and the second semiconductor pattern being between the first source / drain pattern and the second source / drain pattern; a protection pattern between the uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern and the gate electrode, the protection pattern including a dielectric material; a gate capping pattern on an upper surface of the gate electrode; an interlayer insulating film on the gate capping pattern; and a metal layer on the interlayer insulating film, wherein the protection pattern is directly on sidewalls of the first semiconductor pattern and the second semiconductor pattern in the first lateral direction. BRIEF DESCRIPTION OF THE DRAWINGS

[0010] Example embodiments will be understood more clearly from the following detailed description in conjunction with the accompanying drawings, in which:

[0011] Figure 1 is a plan view of a semiconductor device according to some embodiments;

[0012] Figure 2 is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0013] Figure 3 is an enlarged view of region "M" according to some embodiments; Figure 2 of;

[0014] Figure 4 is a cross-sectional view taken along line I-I' according to some embodiments; Figure 3 of;

[0015] Figure 5A is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0016] Figure 5B is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0017] Figure 6 is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0018] Figure 7 is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0019] Figure 8A is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0020] Figure 8B is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0021] Figure 9 is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0022] Figure 10 is a cross-sectional view taken along line A-A' according to some embodiments; Figure 1 of;

[0023] Figure 11 is an enlarged view of region "N" according to some embodiments; Figure 10 of;

[0024] Figures 12A to 12I is a cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments; and

[0025] Figure 13A andFigure 13B is a cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments. DETAILED DESCRIPTION

[0026] Figure 1 is a plan view of a semiconductor device according to some embodiments. Figure 2 is according to some embodiments along Figure 1 sectional view taken along line A-A'.

[0027] Referring to Figure 1 and Figure 2 , the semiconductor device 1 may include a substrate 100.

[0028] The substrate 100 may include a semiconductor substrate including silicon, germanium, or silicon germanium. In some embodiments, the substrate 100 may include a compound semiconductor substrate. As an example, the substrate 100 may include a silicon substrate. As another example, the substrate 100 may include single-crystalline silicon, germanium, or silicon germanium.

[0029] When the substrate 100 includes single-crystalline silicon, germanium, or silicon germanium, the substrate 100 may have a (100) plane, a (110) plane, or a (111) plane as a main surface.

[0030] The active region AR may be defined by a trench (not shown) formed in the upper portion of the substrate 100. The active region AR may be provided as a plurality of. The active region AR may extend in the second lateral direction D2. In the active region AR, the substrate 100 may include a portion protruding in the vertical direction D3.

[0031] As used herein, a direction parallel to the upper surface of the substrate 100 may be defined as a first lateral direction D1, a direction parallel to the upper surface of the substrate 100 and intersecting the first lateral direction D1 may be defined as a second lateral direction D2, and a direction perpendicular to the upper surface of the substrate 100 may be defined as a vertical direction D3.

[0032] The active region AR may include a first region R1 and a second region R2 between a pair of isolation structures DB. The first region R1 and the second region R2 may be adjacent to each other in the second lateral direction D2. The second region R2 may be beside the first region R1.

[0033] In the first region R1, the substrate 100 may include impurities of a first conductivity type (e.g., n-type). In the second region R2, the substrate 100 may include impurities of a second conductivity type (e.g., p-type). For example, the first region R1 may have a first conductivity type, and the second region R2 may have a second conductivity type. The first conductivity type may be different from the second conductivity type.

[0034] The first region R1 and the second region R2 can form a PN junction. Therefore, the first region R1 and the second region R2 can be used as a diode.

[0035] In the active region AR, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be disposed on the substrate 100. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be alternately stacked one by one.

[0036] The first semiconductor patterns SP1 can be spaced apart from each other in the vertical direction D3. The second semiconductor patterns SP2 can be spaced apart from each other in the vertical direction D3.

[0037] The first semiconductor pattern SP1 can include one of silicon, germanium, or silicon-germanium, and the second semiconductor pattern SP2 can include the other of silicon, germanium, or silicon-germanium.

[0038] The second semiconductor pattern SP2 can include a material having an etching selectivity with respect to the first semiconductor pattern SP1. For example, the first semiconductor pattern SP1 can include silicon, and the second semiconductor pattern SP2 can include silicon-germanium. Each second semiconductor pattern SP2 can have a germanium (Ge) concentration of about 10 atomic percent (at%) to about 30 at%.

[0039] In the first region R1, the first source / drain pattern SD1 can be disposed on the substrate 100. The first recess RS1 can be formed in the upper portion of the substrate 100. The first recess RS1 can penetrate (i.e., extend through) the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The first source / drain pattern SD1 can be disposed within the first recess RS1. The first source / drain pattern SD1 can include impurities of a first conductivity type (e.g., n-type). For example, the first source / drain pattern SD1 can have a first conductivity type.

[0040] In the second region R2, the second source / drain pattern SD2 can be disposed on the substrate 100. The second recess RS2 can be formed in the upper portion of the substrate 100. The second recess RS2 can penetrate the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The second source / drain pattern SD2 can be disposed within the second recess RS2. The second source / drain pattern SD2 can include impurities of a second conductivity type (e.g., p-type). For example, the second source / drain pattern SD2 can have a second conductivity type.

[0041] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be adjacent to each other in the second lateral direction D2. The first semiconductor pattern SP1 and the second semiconductor pattern SP2 may be between the first source / drain pattern SD1 and the second source / drain pattern SD2. The stacked first semiconductor pattern SP1 and second semiconductor pattern SP2 may connect the first source / drain pattern SD1 and the second source / drain pattern SD2 to each other. As used herein, "element A is connected to element B" (or similar language) means that element A is physically and / or electrically connected to element B.

[0042] The first source / drain pattern SD1 may be on the sidewall and bottom surface of the first recess RS1 (e.g., may cover the sidewall and bottom surface of the first recess RS1). The second source / drain pattern SD2 may be on the sidewall and bottom surface of the second recess RS2 (e.g., may cover the sidewall and bottom surface of the second recess RS2).

[0043] The first source / drain pattern SD1 and the second source / drain pattern SD2 may be formed using a selective epitaxial growth (SEG) process.

[0044] In some embodiments, the upper surface of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be higher than the upper surface of the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0045] In other embodiments, the upper surface of at least one of the first source / drain pattern SD1 and the second source / drain pattern SD2 may be substantially at the same level as the upper surface of the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2 (e.g., coplanar with the upper surface of the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2).

[0046] The sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a non-uniform embossed shape. In other words, the sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may have a wavy profile. The sidewall of each of the first source / drain pattern SD1 and the second source / drain pattern SD2 may protrude (e.g., in the second lateral direction D2) toward each second semiconductor pattern SP2.

[0047] The gate electrode GE may be disposed to straddle the first semiconductor pattern SP1 and the second semiconductor pattern SP2 and may extend in a first lateral direction D1. The gate electrode GE may overlap the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in a vertical direction (i.e., the vertical direction D3). As used herein, "element A overlaps element B in direction X" (or similar language) means that there is at least one straight line that extends in direction X and intersects both element A and B.

[0048] The gate electrode GE may be on the upper surface of the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2.

[0049] The gate electrode GE may include a first metal pattern and a second metal pattern on the first metal pattern. The first metal pattern may include a work function metal. For example, the first metal pattern may include a metal nitride film. For example, the first metal pattern may include nitrogen (N) and at least one selected from the group consisting of titanium (Ti), tantalum (Ta), aluminum (Al), tungsten (W), and molybdenum (Mo). In addition, the first metal pattern may further include carbon (C). The first metal pattern may include a plurality of stacked work function metal films.

[0050] The second metal pattern may include a metal having a lower resistance than the first metal pattern. For example, the second metal pattern may include at least one metal selected from the group consisting of tungsten (W), aluminum (Al), titanium (Ti), and tantalum (Ta).

[0051] The protection pattern PTL may be (e.g., in the vertical direction D3) between the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2 and the gate electrode GE. The protection pattern PTL may be on at least a portion of the upper surface of the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2 (e.g., may cover at least a portion of the upper surface of the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2).

[0052] The protection pattern PTL may be spaced apart from the gate electrode GE, and a gate insulating film GI is between the protection pattern PTL and the gate electrode GE. Specifically, in Figure 2 the protection pattern PTL may be spaced apart from the gate electrode GE in the vertical direction D3, and a gate insulating film GI is between the protection pattern PTL and the gate electrode GE.

[0053] The protection pattern PTL may not be between the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2 and the gate spacer GS. That is, the protection pattern PTL may not overlap the gate spacer GS in the vertical direction D3.

[0054] The protective pattern PTL may include a low-k dielectric material. For example, the protective pattern PTL may include a silicon oxide film, a silicon oxynitride film, or a combination thereof.

[0055] A pair of gate spacers GS may be respectively on two (i.e., opposite) sidewalls of the gate electrode GE. The gate spacers GS may extend along the gate electrode GE in the first lateral direction D1.

[0056] The upper surface of the gate spacer GS may be at a level higher than the upper surface of the gate electrode GE. The upper surface of the gate spacer GS may be coplanar with the upper surface of the first interlayer insulating film 110. As used herein, the term "level" refers to the height or distance from the lower surface of the substrate 100 in the vertical direction D3.

[0057] In some embodiments, the gate spacer GS may include at least one of silicon carbonitride (SiCN), silicon oxynitride (SiCON), or silicon nitride (SiN). In other embodiments, the gate spacer GS may include a multilayer film including at least two of SiCN, SiCON, and SiN.

[0058] The gate capping pattern GP may be disposed on the gate electrode GE. The gate capping pattern GP may extend along the gate electrode GE in the first lateral direction D1.

[0059] The gate capping pattern GP may include a material having an etching selectivity with respect to the first interlayer insulating film 110 and the second interlayer insulating film 120. Specifically, the gate capping pattern GP may include at least one of silicon oxynitride (SiON), SiCN, SiCON, or SiN.

[0060] The gate insulating film GI may be between the gate electrode GE and the protective pattern PTL, and between the gate electrode GE and the gate spacer GS. The gate insulating film GI may be on the upper surface of the protective pattern PTL (e.g., may cover the upper surface of the protective pattern PTL). The gate insulating film GI may be on the side surface of the gate electrode GE (e.g., may cover the side surface of the gate electrode GE).

[0061] The first interlayer insulating film 110 may be disposed on the substrate 100. The first interlayer insulating film 110 may be on the gate spacers GS and the first source / drain pattern SD1 and the second source / drain pattern SD2 (e.g., may cover the gate spacers GS and the first source / drain pattern SD1 and the second source / drain pattern SD2).

[0062] The upper surface of the first interlayer insulating film 110 may form a substantially flat surface with the upper surface of the gate capping pattern GP and the upper surface of the gate spacer GS.

[0063] A second interlayer insulating film 120 on the gate capping pattern GP (e.g., covering the gate capping pattern GP) may be on the first interlayer insulating film 110. A third interlayer insulating film 130 may be disposed on the second interlayer insulating film 120. A fourth interlayer insulating film 140 may be disposed on the third interlayer insulating film 130. In some embodiments, each of the first interlayer insulating film 110 to the fourth interlayer insulating film 140 may include a silicon oxide film.

[0064] A pair of isolation structures DB may face each other in a second lateral direction D2, and a first source / drain pattern SD1 and a second source / drain pattern SD2 are between the pair of isolation structures DB. The isolation structures DB may extend parallel to the gate electrode GE in a first lateral direction D1.

[0065] The isolation structures DB may penetrate through the first interlayer insulating film 110 and the second interlayer insulating film 120 and extend into the substrate 100. The isolation structures DB may electrically isolate one active region AR and another adjacent active region AR.

[0066] A first active contact portion AC1 may penetrate through the first interlayer insulating film 110 and the second interlayer insulating film 120 and be electrically connected to the first source / drain pattern SD1. A second active contact portion AC2 may penetrate through the first interlayer insulating film 110 and the second interlayer insulating film 120 and be electrically connected to the second source / drain pattern SD2.

[0067] The first active contact portion AC1 and the second active contact portion AC2 may be respectively disposed on both sides of the gate electrode GE. In a view from above, each of the first active contact portion AC1 and the second active contact portion AC2 may have a bar shape extending in the first lateral direction D1.

[0068] The first active contact portion AC1 and the second active contact portion AC2 may be self-aligned contact portions. In other words, the first active contact portion AC1 and the second active contact portion AC2 may be formed in a self-aligned manner by using the gate capping pattern GP and the gate spacer GS. For example, the first active contact portion AC1 and the second active contact portion AC2 may be on at least a part of the sidewall of the gate spacer GS (e.g., may cover at least a part of the sidewall of the gate spacer GS).

[0069] Each of the first active contact portion AC1 and the second active contact portion AC2 may include a conductive pattern FM and a barrier pattern BM surrounding the conductive pattern FM. It should be understood that as used herein, "element A surrounds element B" (or similar language) means that element A is at least partially around element B, but does not necessarily mean that element A completely surrounds element B.

[0070] For example, the conductive pattern FM may include at least one metal among aluminum, copper, tungsten, molybdenum, or cobalt.

[0071] The barrier pattern BM may be on the sidewalls and bottom surface of the conductive pattern FM (e.g., may cover the sidewalls and bottom surface of the conductive pattern FM). The barrier pattern BM may include a metal film / metal nitride film.

[0072] The metal film may include at least one among titanium, tantalum, tungsten, nickel, cobalt, or platinum.

[0073] The metal nitride film may include at least one among a titanium nitride (TiN) film, a tantalum nitride (TaN) film, a tungsten nitride (WN) film, a nickel nitride (NiN) film, a cobalt nitride (CoN) film, or a platinum nitride (PtN) film.

[0074] The first metal-semiconductor compound layer SIC1 may be between the first active contact portion AC1 and the first source / drain pattern SD1. The second metal-semiconductor compound layer SIC2 may be between the second active contact portion AC2 and the second source / drain pattern SD2.

[0075] The first active contact portion AC1 may be electrically connected to the first source / drain pattern SD1 through the first metal-semiconductor compound layer SIC1. The second active contact portion AC2 may be electrically connected to the second source / drain pattern SD2 through the second metal-semiconductor compound layer SIC2.

[0076] For example, each of the first metal-semiconductor compound layer SIC1 and the second metal-semiconductor compound layer SIC2 may include at least one among titanium silicide, tantalum silicide, tungsten silicide, nickel silicide, or cobalt silicide.

[0077] The first metal layer M1 may be disposed in the third interlayer insulating film 130. For example, the first metal layer M1 may include a first wiring M1_I. The first wirings M1_I of the first metal layer M1 may extend parallel to each other in the second lateral direction D2.

[0078] The first metal layer M1 may further include first vias VI1. The first vias VI1 may be respectively disposed below the first wirings M1_I of the first metal layer M1. The first active contact portion AC1 and the second active contact portion AC2 may be electrically connected to the wirings of the first metal layer M1 through the first vias VI1. Although not shown, the gate electrode GE may be electrically connected to the first wiring M1_I of the first metal layer M1 through the first vias VI1.

[0079] A separate process may be used to form the first wiring M1_I of the first metal layer M1 and the first via VI1 thereunder. In other words, a single damascene process may be used to form each of the first wiring M1_I and the first via VI1 of the first metal layer M1. A semiconductor device 1 according to some embodiments may be formed using a process of 20 nanometers or less.

[0080] The second metal layer M2 may be disposed in the fourth interlayer insulating film 140. The second metal layer M2 may include a plurality of second wirings M2_I. Each second wiring M2_I of the second metal layer M2 may have a linear shape or a bar shape extending in the first lateral direction D1. In other words, the second wirings M2_I may extend parallel to each other in the first lateral direction D1.

[0081] The second metal layer M2 may further include second vias VI2 respectively disposed under the second wirings M2_I. The first wiring M1_I of the first metal layer M1 may be electrically connected to the second wiring M2_I of the second metal layer M2 through the second vias VI2. In some embodiments, a dual damascene process may be used to form the second wiring M2_I of the second metal layer M2 and the second vias VI2 thereunder together.

[0082] The first wiring M1_I of the first metal layer M1 and the second wiring M2_I of the second metal layer M2 may include the same conductive material as each other or different conductive materials from each other. For example, the first wiring M1_I of the first metal layer M1 and the second wiring M2_I of the second metal layer M2 may include at least one metal material selected from aluminum, copper, tungsten, molybdenum, ruthenium, and cobalt.

[0083] Although not shown, metal layers may be further stacked on the fourth interlayer insulating film 140.

[0084] The lower wiring layer 200 may be under the substrate 100. The lower wiring layer 200 may include a lower insulating layer 202 and lower wirings 204.

[0085] The lower insulating layer 202 may include a single layer or multiple layers. When the lower insulating layer 202 includes multiple layers, the multiple layers may include the same material or different materials.

[0086] The lower insulating layer 202 may include a low-k dielectric material. For example, the lower insulating layer 202 may include a silicon oxide film, a silicon nitride film, or a silicon oxynitride film. The lower insulating layer 202 may be on the lower surface of the substrate 100 (e.g., may cover the lower surface of the substrate 100).

[0087] The lower wirings 204 may be in the lower insulating layer 202. Although in Figure 2The lower middle wiring 204 is shown as extending in the second lateral direction D2, but the lower middle wiring 204 may extend in the first lateral direction D1. Although in Figure 2 the lower middle wiring 204 is shown as including only one layer, the lower middle wiring 204 may include multiple layers.

[0088] The lower middle wiring 204 may include at least one metal among aluminum, copper, tungsten, molybdenum, or cobalt.

[0089] In some embodiments, the lower middle wiring 204 may be electrically connected to the first wiring M1_I and / or the second wiring M2_I.

[0090] Figure 3 is according to some embodiments Figure 2 an enlarged view of the region M of. Figure 4 is a cross-sectional view taken along line I-I' of according to some embodiments Figure 3 of.

[0091] Referring to Figure 3 , the gate insulating film GI may include an interface film IL and a high-k dielectric film HK. The interface film IL may be directly on the top surface of the protection pattern PTL (e.g., may directly cover the top surface of the protection pattern PTL). For example, the interface film IL may be in contact with the protection pattern PTL. The interface film IL may be between the protection pattern PTL and the high-k dielectric film HK (e.g., in the vertical direction D3). For example, the high-k dielectric film HK may be spaced apart from the protection pattern PTL in the vertical direction D3, and the interface film IL is between the high-k dielectric film HK and the protection pattern PTL.

[0092] The high-k dielectric film HK may be between the interface film IL and the gate electrode GE (e.g., in the vertical direction D3). The high-k dielectric film HK may be directly on the surface of the gate electrode GE (e.g., may directly cover the surface of the gate electrode GE). For example, the high-k dielectric film HK may be in contact with the gate electrode GE. The high-k dielectric film HK may be directly on the top surface of the interface film IL (e.g., may directly cover the top surface of the interface film IL). The high-k dielectric film HK may extend along the sidewall of the gate electrode GE in the vertical direction D3.

[0093] On the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2, the high-k dielectric film HK may be spaced apart from the protection pattern PTL in the vertical direction D3.

[0094] The interface film IL may include a silicon oxide film or a silicon oxynitride film. The high-k dielectric film HK may include a high-k dielectric material having a dielectric constant higher than that of the silicon oxide film. In some embodiments, the high-k dielectric film HK may include at least one of the following: hafnium oxide, hafnium silicon oxide, hafnium zirconium oxide, hafnium tantalum oxide, lanthanum oxide, zirconium oxide, zirconium silicon oxide, tantalum oxide, titanium oxide, barium strontium titanium oxide, barium titanium oxide, strontium titanium oxide, lithium oxide, aluminum oxide, lead scandium tantalum oxide, or lead zinc niobate.

[0095] In some embodiments, the gate insulating film GI may include a ferroelectric material film. In other embodiments, the gate insulating film GI may include a plurality of ferroelectric material films spaced apart from each other. The gate insulating film GI may have a stacked film structure in which a plurality of ferroelectric material films and a plurality of paraelectric material films are alternately stacked.

[0096] Referring to Figure 4 , the protection pattern PTL may extend in the first lateral direction D1. The protection pattern PTL may extend along the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1, and may be directly on the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1 (e.g., may directly cover the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1). For example, the protection pattern PTL may be directly on the opposite sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1.

[0097] The interface film IL of the gate insulating film GI may extend in the first lateral direction D1. The interface film IL may extend along the sidewalls of the protection pattern PTL in the first lateral direction D1, and may be directly on the sidewalls of the protection pattern PTL in the first lateral direction D1 (e.g., may directly cover the sidewalls of the protection pattern PTL in the first lateral direction D1). For example, the interface film IL may be directly on the opposite sidewalls of the protection pattern PTL in the first lateral direction D1.

[0098] In some embodiments, the protection pattern PTL and the interface film IL may include the same material as each other. In this case, the boundary between the protection pattern PTL and the interface film IL may not be observed.

[0099] The high-k dielectric film HK of the gate insulating film GI may extend in the first lateral direction D1. The high-k dielectric film HK may extend along the sidewalls of the interface film IL in the first lateral direction D1, and may be directly on the sidewalls of the interface film IL in the first lateral direction D1 (e.g., may directly cover the sidewalls of the interface film IL in the first lateral direction D1). For example, the high-k dielectric film HK may be directly on the opposite sidewalls of the interface film IL in the first lateral direction D1.

[0100] On sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in a first lateral direction D1, the high-k dielectric film HK may be spaced apart from the protection pattern PTL in the first lateral direction D1 (e.g., the interface film IL is between the high-k dielectric film HK and the protection pattern PTL).

[0101] When the protection pattern PTL is omitted, sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1 may be exposed during manufacturing of the semiconductor device 1. In this case, the second semiconductor pattern SP2 may be removed by using a wet etching process, and a space from which the second semiconductor pattern SP2 is removed may be filled with a material of the gate electrode GE.

[0102] When the space from which the second semiconductor pattern SP2 is removed is filled with the material of the gate electrode GE, a distance between the gate electrode GE and the substrate 100 may be reduced. When the distance between the gate electrode GE and the substrate 100 is reduced, current leaking from the first region R1 and the second region R2 of the substrate 100 to the gate electrode GE may increase. In this case, a function of the diode performed by the first region R1 and the second region R2 may deteriorate. As a result, electrical characteristics and reliability of the semiconductor device 1 may be reduced.

[0103] According to the inventive concept, the semiconductor device 1 may include the first semiconductor pattern SP1 and the second semiconductor pattern SP2 that are alternately stacked one by one on the substrate 100 including the first region R1 and the second region R2. The gate electrode GE may be on the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The protection pattern PTL may be between the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2 and the gate electrode GE.

[0104] In addition, the protection pattern PTL may be on sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1 (e.g., may cover sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1). As a result, the second semiconductor pattern SP2 may not be removed during manufacturing of the semiconductor device 1. Accordingly, a distance between the gate electrode GE and the substrate 100 may increase, and thus, current leaking from the first region R1 and the second region R2 to the gate electrode GE may be reduced. For the above reasons, electrical characteristics and reliability of the semiconductor device 1 may be improved.

[0105] Figure 5A is a cross-sectional view taken along line A-A' of Figure 1 according to some embodiments. Figure 5B is a cross-sectional view taken along line A-A' of Figure 1Cross-sectional view taken along line A-A'. Except for those described below, the description of each component may be the same or similar to the description of each component given with reference to Figures 1 to 4 The description of each component given with reference to

[0106] With reference to Figure 5A and Figure 5B , the semiconductor device 2 may further include a third active contact portion AC3. One of the first active contact portion AC1 or the second active contact portion AC2 included in the semiconductor device 1 of Figure 2 may be omitted.

[0107] The third active contact portion AC3 may be in direct contact with the lower wiring 204. Alternatively, the third active contact portion AC3 may be electrically connected to the lower wiring 204 but not in direct contact with the lower wiring 204. The third active contact portion AC3 may pass through the lower insulating layer 202 and extend into the substrate 100 in the vertical direction D3. At least a portion of the third active contact portion AC3 may be surrounded by the substrate 100.

[0108] As Figure 5A shown, when the second active contact portion AC2 is omitted, the third active contact portion AC3 may extend into the second region R2 of the substrate 100 in the vertical direction D3. In this case, the third active contact portion AC3 may be electrically connected to the second region R2 of the substrate 100.

[0109] As Figure 5B shown, when the first active contact portion AC1 is omitted, the third active contact portion AC3 may extend into the first region R1 of the substrate 100 in the vertical direction D3. In this case, the third active contact portion AC3 may be electrically connected to the first region R1 of the substrate 100.

[0110] The third active contact portion AC3 may include a conductive pattern FM and a barrier pattern BM. The barrier pattern BM may be on the surface of the conductive pattern FM (e.g., may cover the surface of the conductive pattern FM). The conductive pattern FM and the barrier pattern BM may include materials the same as the materials of the conductive pattern FM and the barrier pattern BM described with reference to Figure 1 and Figure 2 .

[0111] When one of the first active contact portion AC1 and the second active contact portion AC2 is omitted and the third active contact portion AC3 is arranged, the degree of freedom in arranging the first wiring M1_I and the second wiring M2_I may increase. Therefore, the integration density of the semiconductor device 2 may increase.

[0112] Figure 6 is a cross-sectional view taken along Figure 1Cross-sectional view taken along line A-A'. Except for those described below, the description of each component may be the same or similar to the description of each component given with reference to Figures 1 to 4 Thus, repeated descriptions are briefly mentioned or excluded, and only the differences are described in detail.

[0113] With reference to Figure 6 , the semiconductor device 3 may further include a fourth active contact portion AC4 and a fifth active contact portion AC5. However, both the first active contact portion AC1 and the second active contact portion AC2 included in the semiconductor device 1 of Figure 2 may be omitted.

[0114] The fourth active contact portion AC4 and the fifth active contact portion AC5 may be directly connected to the lower wiring 204. Alternatively, the fourth active contact portion AC4 and the fifth active contact portion AC5 may be electrically connected to the lower wiring 204 but not in direct contact with the lower wiring 204. The fourth active contact portion AC4 and the fifth active contact portion AC5 may penetrate the lower insulating layer 202 and extend into the substrate 100 in the vertical direction D3. At least a portion of the fourth active contact portion AC4 and at least a portion of the fifth active contact portion AC5 may be surrounded by the substrate 100.

[0115] The fourth active contact portion AC4 may extend into the first region R1 of the substrate 100 in the vertical direction D3. The fourth active contact portion AC4 may be electrically connected to the first region R1 of the substrate 100.

[0116] The fifth active contact portion AC5 may extend into the second region R2 of the substrate 100 in the vertical direction D3. The fifth active contact portion AC5 may be electrically connected to the second region R2 of the substrate 100.

[0117] Each of the fourth active contact portion AC4 and the fifth active contact portion AC5 may include a conductive pattern FM and a barrier pattern BM. The barrier pattern BM may be on the surface of the conductive pattern FM (e.g., may cover the surface of the conductive pattern FM). The conductive pattern FM and the barrier pattern BM may include materials the same as those of the conductive pattern FM and the barrier pattern BM described with reference to Figure 1 and Figure 2 .

[0118] When the first active contact portion AC1 and the second active contact portion AC2 are omitted and the fourth active contact portion AC4 and the fifth active contact portion AC5 are arranged, the degree of freedom in arranging the first wiring M1_I and the second wiring M2_I may increase. Thus, the integration density of the semiconductor device 3 may increase.

[0119] Figure 7 is according to some embodiments along Figure 1Cross-sectional view taken along line A-A'. Except for those described below, the description of each component can be the same as or similar to the description of each component with reference to Figures 1 to 4 given. Therefore, repeated descriptions are briefly mentioned or excluded, and only the differences are described in detail.

[0120] With reference to Figure 7 , the semiconductor device 4 may include Figure 2 most of the components included in the semiconductor device 1 of Figure 2 . However, in the semiconductor device 4, the substrate 100 included in the semiconductor device 1 of

[0121] can be omitted. The space where the substrate 100 is omitted can be completely filled with the lower insulating layer 202. The lower insulating layer 202 may be in direct contact with the lowermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and the first source / drain pattern SD1 and the second source / drain pattern SD2.

[0122] Impurities of the first conductivity type in the first source / drain pattern SD1 may diffuse into the first semiconductor pattern SP1 and the second semiconductor pattern SP2. Impurities of the second conductivity type in the second source / drain pattern SD2 may diffuse into the first semiconductor pattern SP1 and the second semiconductor pattern SP2. As a result, a PN junction may be formed between the first source / drain pattern SD1 and the second source / drain pattern SD2. Therefore, the first source / drain pattern SD1 and the second source / drain pattern SD2 may constitute a diode.

[0123] Figure 8A is a cross-sectional view taken along line A-A' according to some embodiments of Figure 1 . Figure 8B is a cross-sectional view taken along line A-A' according to some embodiments of Figure 1 . Except for those described below, the description of each component can be the same as or similar to the description of each component with reference to Figure 7 given. Therefore, repeated descriptions are briefly mentioned or excluded, and only the differences are described in detail.

[0124] With reference to Figure 8A and Figure 8B , the semiconductor device 5 may include Figure 7 most of the components included in the semiconductor device 4 of Figure 7 . However, in the semiconductor device 5, either the first active contact portion AC1 or the second active contact portion AC2 included in the semiconductor device 4 of

[0125] can be omitted. The semiconductor device 5 may further include a sixth active contact portion AC6.

[0126] The sixth active contact portion AC6 can be directly connected to the lower wiring 204. Alternatively, the sixth active contact portion AC6 can be electrically connected to the lower wiring 204 but not in direct contact with the lower wiring 204. The sixth active contact portion AC6 can pass through the lower insulating layer 202 and extend in the vertical direction D3 into the first source / drain pattern SD1 or the second source / drain pattern SD2. At least a portion of the sixth active contact portion AC6 can be surrounded by the first source / drain pattern SD1 or the second source / drain pattern SD2.

[0127] As Figure 8A shown, when the first active contact portion AC1 is omitted, the sixth active contact portion AC6 can extend in the vertical direction D3 into the first source / drain pattern SD1. In this case, the sixth active contact portion AC6 can be electrically connected to the first source / drain pattern SD1.

[0128] As Figure 8B shown, when the second active contact portion AC2 is omitted, the sixth active contact portion AC6 can extend in the vertical direction D3 into the second source / drain pattern SD2. In this case, the sixth active contact portion AC6 can be electrically connected to the second source / drain pattern SD2.

[0129] The sixth active contact portion AC6 can include a conductive pattern FM and a barrier pattern BM. The barrier pattern BM can be on the surface of the conductive pattern FM (e.g., can cover the surface of the conductive pattern FM). The conductive pattern FM and the barrier pattern BM can include materials the same as those of the conductive pattern FM and the barrier pattern BM described with reference to Figure 1 and Figure 2 .

[0130] When one of the first active contact portion AC1 and the second active contact portion AC2 is omitted and the sixth active contact portion AC6 is arranged, the degree of freedom in arranging the first wiring M1_I and the second wiring M2_I can be increased. Accordingly, the integration density of the semiconductor device 5 can be increased.

[0131] Figure 9 is a cross-sectional view taken along line A-A' of Figure 1 according to some embodiments. Except for those described below, the description of each component can be the same as or similar to the description of each component given with reference to Figure 7 . Accordingly, repeated descriptions are briefly mentioned or excluded, and only the differences are described in detail.

[0132] The semiconductor device 6 can further include a seventh active contact portion AC7 and an eighth active contact portion AC8. However, both the first active contact portion AC1 and the second active contact portion AC2 included in the semiconductor device 4 of Figure 7 can be omitted.

[0133] The seventh active contact portion AC7 and the eighth active contact portion AC8 may be directly connected to the lower wiring 204. Alternatively, the seventh active contact portion AC7 and the eighth active contact portion AC8 may be electrically connected to the lower wiring 204 but not in direct contact with the lower wiring 204. The seventh active contact portion AC7 may pass through the lower insulating layer 202 and extend in the vertical direction D3 into the first source / drain pattern SD1. The eighth active contact portion AC8 may pass through the lower insulating layer 202 and extend in the vertical direction D3 into the second source / drain pattern SD2. At least a portion of the seventh active contact portion AC7 may be surrounded by the first source / drain pattern SD1. At least a portion of the eighth active contact portion AC8 may be surrounded by the second source / drain pattern SD2.

[0134] The seventh active contact portion AC7 may be electrically connected to the first source / drain pattern SD1. The eighth active contact portion AC8 may be electrically connected to the second source / drain pattern SD2.

[0135] Each of the seventh active contact portion AC7 and the eighth active contact portion AC8 may include a conductive pattern FM and a barrier pattern BM. The barrier pattern BM may be on the surface of the conductive pattern FM (e.g., may cover the surface of the conductive pattern FM). The conductive pattern FM and the barrier pattern BM may include materials the same as those of the conductive pattern FM and the barrier pattern BM described with reference to Figure 1 and Figure 2 description.

[0136] When the first active contact portions AC1 and AC2 are omitted and the seventh active contact portion AC7 and the eighth active contact portion AC8 are arranged, the degree of freedom in arranging the first wiring M1_I and the second wiring M2_I may be increased. Accordingly, the integration density of the semiconductor device 6 may be increased.

[0137] Figure 10 is a cross-sectional view taken along line A-A' of Figure 1 according to some embodiments. Figure 11 is an enlarged view of region N of Figure 10 according to some embodiments. Descriptions of each component may be the same as or similar to those of each component given with reference to Figures 1 to 4 except for those described below. Accordingly, repeated descriptions are briefly mentioned or excluded, and only the differences are described in detail.

[0138] With reference to Figure 10 and Figure 11 , the protection pattern PTL of the semiconductor device 7 may include a first portion PO1 and a second portion PO2 directly connected to the first portion PO1.

[0139] The first part PO1 of the protection pattern PTL may be a part that is in direct contact with the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The first part PO1 may have a first thickness T1. The first thickness T1 may be the thickness of the first part PO1 in the vertical direction D3. Similar to Figure 4 the semiconductor device 1, the first part PO1 may extend to the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1. The first part PO1 may be on the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1 (e.g., may cover the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1). For example, the first part PO1 may be on the opposite sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1.

[0140] The interface film IL of the gate insulating film GI may be on the upper surface of the first part PO1 and on the sidewalls of the first part PO1 in the first lateral direction D1 (e.g., may cover the upper surface of the first part PO1 and the sidewalls of the first part PO1 in the first lateral direction D1). For example, the interface film IL may be on the upper surface of the first part PO1 and may be on the opposite sidewalls of the first part PO1 in the first lateral direction D1.

[0141] The second part PO2 of the protection pattern PTL may be a part that extends from the first part PO1 along the inner sidewall of the gate spacer GS in the vertical direction D3. The second part PO2 of the protection pattern PTL may be directly on the sidewalls of the interface film IL and the high-k dielectric film HK in the second lateral direction D2 (e.g., may directly cover the sidewalls of the interface film IL and the high-k dielectric film HK in the second lateral direction D2). For example, the second part PO2 of the protection pattern PTL may be directly on the interface film IL and may be directly on the opposite sidewalls of the high-k dielectric film HK in the second lateral direction D2.

[0142] The high-k dielectric film HK may be spaced apart from the gate spacer GS in the second lateral direction D2, and the protection pattern PTL is between the high-k dielectric film HK and the gate spacer GS. Specifically, the high-k dielectric film HK may be spaced apart from the gate spacer GS in the second lateral direction D2, and the second part PO2 of the protection pattern PTL is between the high-k dielectric film HK and the gate spacer GS. For example, the high-k dielectric film HK may be directly on the inner sidewall of the second part PO2 of the protection pattern PTL.

[0143] The second part PO2 of the protection pattern PTL may have a second thickness T2. The second thickness T2 may be the thickness of the second part PO2 in the second lateral direction D2. The first thickness T1 may be greater than the second thickness T2. In other words, the second thickness T2 may be less than the first thickness T1.

[0144] The portion of the gate insulating film GI that is in direct contact with the first part PO1 of the protection pattern PTL may have a third thickness T3. The third thickness T3 may be less than each of the first thickness T1 and the second thickness T2. In other words, each of the first thickness T1 and the second thickness T2 may be greater than the third thickness T3.

[0145] According to the inventive concept, the protection pattern PTL may include a first part PO1 that is in direct contact with the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2, and a second part PO2 that extends from the first part PO1 along the inner sidewall of the gate spacer GS in the vertical direction D3. The first part PO1 may have a first thickness T1, and the second part PO2 may have a second thickness T2. The first thickness T1 may be greater than the second thickness T2. As a result, the distance between the gate electrode GE and the first semiconductor pattern SP1 and the second semiconductor pattern SP2 may increase. Accordingly, the current leaking from the first semiconductor pattern SP1 and the second semiconductor pattern SP2 to the gate electrode GE may decrease. For the above reasons, the electrical characteristics and reliability of the semiconductor device 7 may be improved.

[0146] Figures 12A to 12I is a cross-sectional view showing a method of manufacturing a semiconductor device according to some embodiments. Specifically, Figures 12A to 12I is a cross-sectional view taken along line A-A' of Figure 1 showing a method of manufacturing the semiconductor device 1 shown in Figure 2

[0147] Referring to Figure 1 and Figure 12A , a substrate 100 including an active region AR may be provided. In the active region AR, the substrate 100 may include a first region R1 and a second region R2.

[0148] The first region R1 of the substrate 100 may be doped with impurities of a first conductivity type, and the second region R2 of the substrate 100 may be doped with impurities of a second conductivity type. The first conductivity type may be different from the second conductivity type. For example, the first region R1 of the substrate 100 may have a first conductivity type, and the second region R2 of the substrate 100 may have a second conductivity type.

[0149] ​The first semiconductor layer SL1 and the second semiconductor layer SL2 can be alternately stacked one by one on the substrate 100. The first semiconductor layer SL1 can include one of silicon, germanium, or silicon-germanium, and the second semiconductor layer SL2 can include the other of silicon, germanium, or silicon-germanium.

[0150] The second semiconductor layer SL2 can include a material having an etching selectivity with respect to the first semiconductor layer SL1. For example, the first semiconductor layer SL1 can include silicon, and the second semiconductor layer SL2 can include silicon-germanium. Each second semiconductor layer SL2 can have a germanium (Ge) concentration of about 10 at% to about 30 at%.

[0151] The first semiconductor layer SL1 and the second semiconductor layer SL2 can be formed by using a chemical vapor deposition (CVD) process, a physical vapor deposition (PVD) process, an atomic layer deposition (ALD) process, and / or a combination thereof.

[0152] Although not shown, mask patterns can be formed on the active region AR of the substrate 100, respectively. The mask pattern can have a linear shape or a bar shape extending in the second lateral direction D2.

[0153] A trench (not shown) can be formed by performing a patterning process using the mask pattern as an etching mask. Due to the trench, the upper part of the substrate 100 can have a structure protruding in the vertical direction D3.

[0154] Refer to Figure 1 and Figure 12B , a sacrificial pattern PP can be formed on the substrate 100, and the sacrificial pattern PP intersects with the first semiconductor layer SL1 and the second semiconductor layer SL2. Each sacrificial pattern PP can be formed in a linear shape or a bar shape extending in the first lateral direction D1. The sacrificial pattern PP can be arranged in the second lateral direction D2. The sacrificial pattern PP can be formed on the uppermost semiconductor layer among the first semiconductor layer SL1 and the second semiconductor layer SL2.

[0155] Specifically, forming the sacrificial pattern PP can include: forming a sacrificial film on the entire surface of the substrate 100; forming a hard mask pattern MP on the sacrificial film; and patterning the sacrificial film by using the hard mask pattern MP as an etching mask. The sacrificial film can include polysilicon. Therefore, each sacrificial pattern PP can include polysilicon.

[0156] A pair of gate spacers GS can be formed on two (i.e., opposite) sidewalls of each sacrificial pattern PP. Forming the gate spacers GS can include: conformally forming a gate spacer film on the entire surface of the substrate 100; and anisotropically etching the gate spacer film. In some embodiments, the gate spacers GS can include a multi-layer film including at least two films.

[0157] Referring to Figure 1 、 Figure 12B and Figure 12C , first recesses RS1 and second recesses RS2 can be formed in the first semiconductor layer SL1 and the second semiconductor layer SL2. The first recesses RS1 can vertically overlap with the first region R1 of the substrate 100. The second recesses RS2 can vertically overlap with the second region R2 of the substrate 100. Due to the first recesses RS1, a part of the first region R1 of the substrate 100 can be removed. Due to the second recesses RS2, a part of the second region R2 of the substrate 100 can be removed.

[0158] Specifically, the first semiconductor layer SL1 and the second semiconductor layer SL2 can be etched by using the hard mask pattern MP and the gate spacer GS as an etching mask, and thus, the first recesses RS1 and the second recesses RS2 can be formed.

[0159] Forming the first recesses RS1 and the second recesses RS2 can further include performing a selective etching process on the exposed second semiconductor layer SL2. Due to the selective etching process, each second semiconductor layer SL2 can be recessed to form a recessed region IDE. Therefore, each of the first recesses RS1 and the second recesses RS2 can have an inner wall with a wavy shape.

[0160] During the formation of the first recesses RS1 and the second recesses RS2, the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be alternately stacked one by one between the first recesses RS1 and the second recesses RS2.

[0161] Referring to Figure 1 and Figure 12D , a first source / drain pattern SD1 can be formed in the first recesses RS1. Specifically, an SEG process can be performed by using the inner wall of the first recesses RS1 as a seed layer, and thus, the first source / drain pattern SD1 can be formed. The first source / drain pattern SD1 can be grown by using the first semiconductor pattern SP1, the second semiconductor pattern SP2, and the substrate 100 exposed by the first recesses RS1 as seeds.

[0162] In some embodiments, the SEG process can include a CVD process or a molecular beam epitaxy (MBE) process.

[0163] In some embodiments, during the formation of the first source / drain pattern SD1, impurities (e.g., phosphorus (P), arsenic (As), or antimony (Sb)) can be in-situ implanted into the first source / drain pattern SD1 such that the first source / drain pattern SD1 exhibits a first conductivity type. In other embodiments, after the first source / drain pattern SD1 is formed, impurities can be implanted into the first source / drain pattern SD1.

[0164] A second source / drain pattern SD2 can be formed within the second recess RS2. Specifically, the SEG process can be performed by using the inner sidewall of the second recess RS2 as a seed layer, and thus, the second source / drain pattern SD2 can be formed.

[0165] In some embodiments, during the formation of the second source / drain pattern SD2, impurities (e.g., boron (B), gallium (Ga), or indium (In)) can be in-situ implanted into the second source / drain pattern SD2 such that the second source / drain pattern SD2 exhibits a second conductivity type. In other embodiments, after the second source / drain pattern SD2 is formed, impurities can be implanted into the second source / drain pattern SD2.

[0166] Referring Figure 1 and Figure 12E , the first interlayer insulating film 110 can be formed to be on (e.g., cover) the first source / drain pattern SD1, the second source / drain pattern SD2, the hard mask pattern MP, and the gate spacer GS. In some embodiments, the first interlayer insulating film 110 can include a silicon oxide film.

[0167] The first interlayer insulating film 110 can be planarized such that the upper surface of the sacrificial pattern PP can be exposed. The planarization of the first interlayer insulating film 110 can be performed by using an etch-back process or a chemical mechanical polishing (CMP) process. During the planarization process, the hard mask pattern MP can be completely removed. As a result, the upper surface of the first interlayer insulating film 110 can form a flat surface with the upper surface of the sacrificial pattern PP and the upper surface of the gate spacer GS.

[0168] The exposed sacrificial pattern PP can be selectively removed. By removing the sacrificial pattern PP, an external region ORG exposing the first semiconductor pattern SP1 and the second semiconductor pattern SP2 can be formed. Removing the sacrificial pattern PP can include performing a wet etching process using an etchant to selectively etch polysilicon.

[0169] Referring Figure 1 and Figure 12F , the protection pattern PTL can be formed to be on the upper surface of the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2 (e.g., cover the upper surface of the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2). The protection pattern PTL can extend in the first lateral direction D1, as Figure 4 shown. As Figure 4As shown, the protection pattern PTL may be on the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1 (e.g., may cover the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1). The protection pattern PTL may completely cover the surfaces of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 that are exposed to the outside.

[0170] The protection pattern PTL may include a low-k dielectric material. For example, the protection pattern PTL may include a silicon oxide film.

[0171] According to the inventive concept, the protection pattern PTL may be on the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1 (e.g., may cover the sidewalls of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 in the first lateral direction D1). That is, the protection pattern PTL may completely cover the surfaces of the first semiconductor pattern SP1 and the second semiconductor pattern SP2 that are exposed to the outside. Thus, even when a wet etching process having an etching selectivity with respect to the second semiconductor pattern SP2 is performed later, the second semiconductor pattern SP2 may not be removed.

[0172] Referring to Figure 1 、 Figure 3 、 Figure 4 and Figure 12G , a gate insulating film GI may be formed on the protection pattern PTL. The gate insulating film GI may include an interfacial film IL and a high-k dielectric film HK. After the interfacial film IL is first formed, the high-k dielectric film HK may be formed.

[0173] The interfacial film IL may be on the protection pattern PTL (e.g., may cover the protection pattern PTL). Specifically, the interfacial film IL may directly cover the upper surface of the protection pattern PTL and the sidewalls of the protection pattern PTL in the first lateral direction D1 (e.g., may directly cover the upper surface of the protection pattern PTL and the sidewalls of the protection pattern PTL in the first lateral direction D1).

[0174] The high-k dielectric film HK may be formed on the interfacial film IL. The high-k dielectric film HK may directly cover the upper surface of the interfacial film IL and the sidewalls of the gate spacer GS (e.g., may directly cover the upper surface of the interfacial film IL and the sidewalls of the gate spacer GS).

[0175] Referring to Figure 1 and Figure 12H , a gate electrode GE may be formed on the gate insulating film GI. The gate electrode GE may be formed in the external region ORG. A part of the gate electrode GE may be removed, and thus, the height of the gate electrode GE may be reduced. A gate capping pattern GP may be formed on the recessed gate electrode GE.

[0176] Referring to Figure 1 and Figure 12I , a second interlayer insulating film 120 may be formed on the first interlayer insulating film 110. The second interlayer insulating film 120 may include a silicon oxide film.

[0177] The first active contact portion AC1 may be formed to penetrate through the second interlayer insulating film 120 and the first interlayer insulating film 110, and may be electrically connected to the first source / drain pattern SD1. The second active contact portion AC2 may be formed to penetrate through the second interlayer insulating film 120 and the first interlayer insulating film 110, and may be electrically connected to the second source / drain pattern SD2.

[0178] Forming the first active contact portion AC1 and the second active contact portion AC2 may include: forming a barrier pattern BM; and forming a conductive pattern FM on the barrier pattern BM. The barrier pattern BM may be formed conformally, and the barrier pattern BM may include a metal film / metal nitride film. The conductive pattern FM may include a low-resistance metal.

[0179] Before forming the first active contact portion AC1, a first metal semiconductor compound layer SIC1 may be formed on the first source / drain pattern SD1. Before forming the second active contact portion AC2, a second metal semiconductor compound layer SIC2 may be formed on the second source / drain pattern SD2.

[0180] A first metal semiconductor compound layer SIC1 may be formed between the first source / drain pattern SD1 and the first active contact portion AC1. A second metal semiconductor compound layer SIC2 may be formed between the second source / drain pattern SD2 and the second active contact portion AC2.

[0181] The isolation structures DB may each be formed to be spaced apart from the first source / drain pattern SD1 and the second source / drain pattern SD2 in a second lateral direction D2. A pair of isolation structures DB may be spaced apart from each other in the second lateral direction D2, with the first source / drain pattern SD1 and the second source / drain pattern SD2 therebetween. The isolation structures DB may extend from the second interlayer insulating film 120 through the first interlayer insulating film 110 into the substrate 100. The isolation structures DB may include an insulating material, for example, a silicon oxide film or a silicon nitride film.

[0182] A third interlayer insulating film 130 may be formed on the first active contact portion AC1, the second active contact portion AC2, and the isolation structures DB. A first metal layer M1 may be formed in the third interlayer insulating film 130. A fourth interlayer insulating film 140 may be formed on the third interlayer insulating film 130. A second metal layer M2 may be formed in the fourth interlayer insulating film 140.

[0183] Return to referenceFigure 1 And Figure 2 , a planarization process can be performed on the bottom surface 100b of the substrate 100 of Figure 12I . As a result, the thickness of the substrate 100 in the vertical direction D3 can be reduced.

[0184] Subsequently, a lower wiring layer 200 can be formed under the substrate 100. The lower wiring layer 200 can include a lower insulating layer 202 and lower wirings 204. The lower wiring layer 200 can be formed using a damascene process. As a result, a semiconductor device 1 as shown in Figure 2 can be manufactured.

[0185] Figure 13A And Figure 13B are cross-sectional views of a method for manufacturing a semiconductor device according to some embodiments. Specifically, Figure 13A And Figure 13B show a method for manufacturing a semiconductor device 7 as shown in Figure 10 And Figure 11 .

[0186] Referring to Figure 1 And Figure 13A , after performing the manufacturing method described with reference to Figures 12A to 12F , a deposition process can be performed, and thus, the thickness of the protection pattern PTL can be increased.

[0187] Referring to Figure 1 And Figure 13A together with Figure 11 , due to the deposition process, the protection pattern PTL can include a first portion PO1 and a second portion PO2. The first portion PO1 can be a portion that is in direct contact with the uppermost semiconductor pattern among the first semiconductor pattern SP1 and the second semiconductor pattern SP2. The second portion PO2 can be a portion that extends from the first portion PO1 along the inner surface of the gate spacer GS in the vertical direction D3. The first portion PO1 can have a first thickness T1. The second portion PO2 can have a second thickness T2. The first thickness T1 can be greater than the second thickness T2.

[0188] Referring to Figure 1 And Figure 13B , a gate insulating film GI can be formed on the protection pattern PTL.

[0189] Referring to Figure 1 And Figure 13B together with Figure 4 、 Figure 10 And Figure 11, the gate insulating film GI may include an interface film IL and a high-k dielectric film HK. The interface film IL may be on the upper surface of the first portion PO1 and on the sidewalls of the first portion PO1 in the first lateral direction D1 (e.g., may cover the upper surface of the first portion PO1 and the sidewalls of the first portion PO1 in the first lateral direction D1). For example, the interface film IL may be on the upper surface of the first portion PO1 and may be on the opposite sidewalls of the first portion PO1 in the first lateral direction D1.

[0190] The high-k dielectric film HK may be on the upper surface of the interface film IL (e.g., may cover the upper surface of the interface film IL). The high-k dielectric film HK may be on the inner sidewalls of the second portion PO2 of the protection pattern PTL (e.g., may cover the inner sidewalls of the second portion PO2 of the protection pattern PTL).

[0191] Subsequently, the manufacturing method described with reference to Figure 12H and Figure 12I may be fully executed. As a result, the semiconductor device 7 shown in Figure 10 and Figure 11 may be manufactured.

[0192] As used herein, the terms "comprise", "comprises", "comprising", "include", "includes", "including", "have", "has" and any other variations thereof indicate the presence of the stated features, steps, operations, elements, components and / or combinations, but do not preclude the presence or addition of one or more other features, steps, operations, elements, components and / or their combinations. In addition, it should be understood that although the terms "first", "second", etc. may be used herein to describe various elements, these elements should not be limited by these terms. Instead, these terms are only used to distinguish the elements from each other. For example, without departing from the scope of the present disclosure, a first element may be referred to as a second element, and similarly, a second element may be referred to as a first element.

[0193] Example embodiments are described herein with reference to the accompanying drawings. Many different forms and embodiments are possible without departing from the teachings of the present disclosure. Therefore, the present disclosure should not be construed as being limited to the example embodiments described herein.

[0194] Although the inventive concept has been specifically shown and described with reference to example embodiments thereof, it should be understood that various changes in form and detail may be made therein without departing from the scope of the appended claims.

Claims

1. A semiconductor device, comprising: A substrate including a first region and a second region adjacent to the first region, the first region having a first conductivity type, and the second region having a second conductivity type different from the first conductivity type; A first semiconductor pattern and a second semiconductor pattern stacked alternately on the upper surface of the substrate one by one, the first semiconductor pattern including a material different from the second semiconductor pattern; A gate electrode on the uppermost semiconductor pattern among the first semiconductor pattern and the second semiconductor pattern, the gate electrode extending in a first lateral direction; A first source / drain pattern and a second source / drain pattern spaced apart from each other in a second lateral direction intersecting the first lateral direction, the first semiconductor pattern and the second semiconductor pattern being between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern having the first conductivity type, and the second source / drain pattern having the second conductivity type; And A protection pattern between the uppermost semiconductor pattern among the first semiconductor pattern and the second semiconductor pattern and the gate electrode, the protection pattern including a dielectric material, Wherein the protection pattern is directly on the sidewalls of the first semiconductor pattern and the second semiconductor pattern in the first lateral direction.

2. The semiconductor device according to claim 1 further comprises: A gate insulating film between the gate electrode and the protection pattern, Wherein the gate insulating film is directly on the upper surface of the protection pattern and directly on the sidewalls of the protection pattern in the first lateral direction.

3. The semiconductor device according to claim 2, wherein, The gate insulating film includes an interface film in contact with the protection pattern and a high-k dielectric film in contact with the gate electrode, and Wherein the high-k dielectric film is spaced apart from the protection pattern in a vertical direction, and the interface film is between the high-k dielectric film and the protection pattern.

4. The semiconductor device according to claim 1, wherein, The protection pattern includes silicon oxide, silicon oxynitride, or a combination thereof.

5. The semiconductor device according to claim 1 further comprises: Gate spacers on the sidewalls of the gate electrode in the second lateral direction, Wherein the protection pattern does not overlap with the gate spacers in a vertical direction.

6. The semiconductor device according to claim 1, further comprising: A first active contact electrically connected to the first source / drain pattern and a second active contact electrically connected to the second source / drain pattern; And A lower wiring layer under the substrate, Wherein the lower wiring layer includes a lower insulating layer and lower wirings in the lower insulating layer.

7. The semiconductor device according to claim 6, wherein, The first active contact and the second active contact extend in a vertical direction, and Wherein the semiconductor device further comprises: a metal layer on the first active contact and the second active contact and electrically connected to the first active contact and the second active contact.

8. The semiconductor device according to claim 1, further comprising: A lower wiring layer under the substrate, the lower wiring layer including a lower insulating layer and lower wirings in the lower insulating layer; A first active contact electrically connected to the first source / drain pattern; And A second active contact portion is electrically connected to the lower wiring, and the second active contact portion extends vertically through the lower insulating layer and into the second region of the substrate.

9. The semiconductor device according to claim 1, further comprising: A lower wiring layer is disposed under the substrate, and the lower wiring layer includes a lower insulating layer and lower wiring in the lower insulating layer; A first active contact portion is electrically connected to the lower wiring, and the first active contact portion extends vertically through the lower insulating layer and into the first region of the substrate; And A second active contact portion is electrically connected to the lower wiring, and the second active contact portion extends vertically through the lower insulating layer and into the second region of the substrate.

10. A semiconductor device includes: A lower wiring layer including a lower insulating layer and lower wiring in the lower insulating layer; A first semiconductor pattern and a second semiconductor pattern are alternately stacked one by one on the upper surface of the lower wiring layer, and the first semiconductor pattern includes a material different from that of the second semiconductor pattern; A gate electrode is disposed on the uppermost semiconductor pattern among the first semiconductor pattern and the second semiconductor pattern, and the gate electrode extends in a first lateral direction; A first source / drain pattern and a second source / drain pattern are spaced apart from each other in a second lateral direction intersecting the first lateral direction, the first semiconductor pattern and the second semiconductor pattern are between the first source / drain pattern and the second source / drain pattern, the first source / drain pattern has a first conductivity type, and the second source / drain pattern has a second conductivity type different from the first conductivity type; A protection pattern is disposed between the uppermost semiconductor pattern among the first semiconductor pattern and the second semiconductor pattern and the gate electrode, and the protection pattern includes a dielectric material; And A gate spacer is disposed on a sidewall of the gate electrode in the second lateral direction, wherein the protection pattern includes a first portion on the uppermost semiconductor pattern among the first semiconductor pattern and the second semiconductor pattern, and a second portion extending vertically along an inner sidewall of the gate spacer.

11. The semiconductor device according to claim 10 further comprises: A gate insulating film is disposed between the gate electrode and the protection pattern, wherein the gate insulating film includes an interface film directly on the first portion of the protection pattern and a high-k dielectric film directly on an inner sidewall of the second portion of the protection pattern.

12. The semiconductor device according to claim 10 further comprises: A gate insulating film is disposed between the gate electrode and the protection pattern, wherein the gate insulating film is spaced apart from the gate spacer in the second lateral direction, and the second portion of the protection pattern is between the gate insulating film and the gate spacer.

13. The semiconductor device according to claim 10, wherein, The thickness of the first portion of the protection pattern is greater than the thickness of the second portion of the protection pattern.

14. The semiconductor device according to claim 10 further comprises: A gate insulating film is disposed between the gate electrode and the protection pattern, wherein a part of the gate insulating film contacts the first portion of the protection pattern, and Among them, the thickness of the part of the gate insulating film is less than each of the thickness of the first part of the protection pattern and the thickness of the second part of the protection pattern.

15. The semiconductor device according to claim 10, wherein, The lower insulating layer is in contact with the first source / drain pattern and the second source / drain pattern, and Among them, the semiconductor device further includes: a first active contact part, electrically connected to the lower wiring, and the first active contact part extends through the lower insulating layer in the vertical direction and extends into the first source / drain pattern.

16. The semiconductor device according to claim 15 further comprises: A second active contact part, electrically connected to the lower wiring, and the second active contact part extends through the lower insulating layer in the vertical direction and extends into the second source / drain pattern.

17. The semiconductor device according to claim 10, wherein The lower insulating layer is in contact with the first source / drain pattern and the second source / drain pattern, and Among them, the semiconductor device further includes: A first active contact part electrically connected to the first source / drain pattern and a second active contact part electrically connected to the second source / drain pattern, and the first active contact part and the second active contact part extend in the vertical direction; and A metal layer, on the first active contact part and the second active contact part, and electrically connected to the first active contact part and the second active contact part.

18. A semiconductor device, including: A substrate, including a first region and a second region beside the first region, the first region has a first conductivity type, and the second region has a second conductivity type different from the first conductivity type; A first semiconductor pattern and a second semiconductor pattern, alternately stacked one by one on the upper surface of the substrate, and the first semiconductor pattern includes a material different from the second semiconductor pattern; A gate electrode, on the uppermost semiconductor pattern among the first semiconductor pattern and the second semiconductor pattern, and the gate electrode extends in a first lateral direction; A gate spacer, on the sidewall of the gate electrode in a second lateral direction intersecting with the first lateral direction; A first source / drain pattern and a second source / drain pattern, spaced apart from each other in the second lateral direction, and the first semiconductor pattern and the second semiconductor pattern are between the first source / drain pattern and the second source / drain pattern; A protection pattern, between the uppermost semiconductor pattern among the first semiconductor pattern and the second semiconductor pattern and the gate electrode, and the protection pattern includes a dielectric material; A gate capping pattern, on the upper surface of the gate electrode; An interlayer insulating film, on the gate capping pattern; And A metal layer, on the interlayer insulating film, Among them, the protection pattern is directly on the sidewalls of the first semiconductor pattern and the second semiconductor pattern in the first lateral direction.

19. The semiconductor device according to claim 18 further comprises: A gate insulating film, between the protection pattern and the gate electrode, Among them, the gate insulating film is spaced apart from the gate spacer in the second lateral direction, and the protection pattern is between the gate insulating film and the gate spacer.

20. The semiconductor device according to claim 18, wherein, The protection pattern includes a first portion in contact with the uppermost semiconductor pattern of the first semiconductor pattern and the second semiconductor pattern, and a second portion extending from the first portion along the inner sidewall of the gate spacer in the vertical direction, and wherein the thickness of the first portion of the protection pattern is greater than the thickness of the second portion of the protection pattern.

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