Backside illuminated image sensor, preparation method thereof and electronic equipment

Abstract

The invention relates to a backside illuminated image sensor, a preparation method thereof and electronic equipment. The backside illuminated image sensor comprises a substrate, a grating, photodiodes and target isolation structures, wherein the photodiodes and the target isolation structures are located on the first surface of the substrate, are alternately arranged in the first direction parallel to the first surface and extend towards the substrate; the substrate internally comprises a plurality of trench isolation structures which extend into the substrate through the first surface and are arranged at intervals in the first direction; the trench isolation structures and the target isolation structures over the trench isolation structures are arranged in a one-to-one manner; the photodiode comprises a SiAs laminated layer and a SiAs cover layer which are arranged along a direction away from the substrate, and a SiP layer which penetrates through the SiAs laminated layer along a first direction and a direction towards the substrate; the target isolation structure comprises a protruding part higher than the top surface of the photodiode; the grating and the protruding parts are prepared in the same process step at the same period. Signal crosstalk of the BSI image sensor and unnecessary damage caused by IMP can be avoided, and photoelectric conversion efficiency can be improved.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technologies, and particularly to a back-illuminated image sensor, a preparation method thereof, and an electronic device. Background Art

[0002] An image sensor is a photoelectric conversion device widely used in many fields such as consumer electronics, security monitoring, automotive electronics, and machine vision. A back-illuminated (BSI) image sensor has advantages such as higher sensitivity, better wiring layout, and allowing high-speed recording, and is often applied to fields with high requirements for the pixel performance of the image sensor.

[0003] However, in the traditional front-end process of BSI, it is necessary to use high-energy ion implantation (IMP) to prepare a diode structure to form a pixel region, which causes damage to the substrate surface. Uneven ion implantation also causes signal crosstalk between different pixels, hindering the further improvement of the performance of the BSI image sensor. Summary of the Invention

[0004] Based on this, in view of the technical problems in the related art, it is necessary to provide a back-illuminated image sensor, a preparation method thereof, and an electronic device, which can at least avoid signal crosstalk of the BSI image sensor and unnecessary damage caused by IMP.

[0005] In a first aspect, the present application provides a back-illuminated image sensor, including a substrate, a grid, and photodiodes and target isolation structures that are alternately arranged along a first direction parallel to the first surface on the first surface of the substrate and extend toward the substrate;

[0006] The substrate includes a plurality of trench isolation structures that extend into the substrate through the first surface and are arranged at intervals along the first direction; the trench isolation structures are arranged in a one-to-one correspondence with the target isolation structures directly above them;

[0007] The photodiode includes a SiAs stack, a SiAs cover layer arranged in a direction away from the substrate, and a SiP layer that penetrates the SiAs stack along the first direction and toward the substrate;

[0008] The target isolation structure includes a protrusion whose top surface is higher than the top surface of the photodiode; the grid and the protrusion are prepared synchronously in the same process step.

[0009] In the back-illuminated image sensor in the above embodiments, the target isolation structure and the trench isolation structure are connected together along the direction towards the substrate, penetrate the pixel region, and form a fully isolated pixel structure with the photodiode, so that adjacent pixel structures are completely separated. When incident light enters the pixel structure, the propagation path is restricted to the internal photodiode. At the same time, the generated photo-generated electrons are intercepted to the greatest extent, effectively suppressing the adverse effect of the crosstalk effect on the image imaging clarity; moreover, the grating on the top surface of the target isolation structure is formed synchronously with the protrusion, which can increase the overall height of the grating, enhance the light converging effect, and reduce the risk of light entering adjacent pixel structures.

[0010] The photodiode is composed of a photosensitive layer including different doping elements. Among them, the SiP layer penetrates the SiAs stack in multiple directions, which can generate more light refraction after the incident light enters the photodiode, increase the optical path, increase the photon absorption distance, thereby improving the light absorption efficiency of the pixel structure and causing the quantum efficiency to increase.

[0011] In some embodiments, the SiAs stack includes a first SiAs layer and a second SiAs layer arranged at intervals along the direction away from the substrate;

[0012] In some embodiments, the SiP layer includes:

[0013] A first extension portion that penetrates the first SiAs layer along the direction towards the substrate;

[0014] A second extension portion located between the first SiAs layer and the second SiAs layer;

[0015] A third extension portion that penetrates the second SiAs layer along the direction towards the substrate and extends into the second extension portion along the direction towards the substrate;

[0016] A fourth extension portion located on the top surface of the second SiAs layer and extending along the first direction;

[0017] Among them, the top surface of the first extension portion is located inside the bottom surface of the second extension portion; the top surface of the third extension portion is located inside the bottom surface of the fourth extension portion.

[0018] In some embodiments, the size of the first extension portion in the first direction gradually decreases in the direction away from the substrate; the size of the third extension portion in the first direction gradually decreases in the direction towards the substrate.

[0019] In some embodiments, the first extension portion and the second extension portion are prepared synchronously in the same process step.

[0020] In some embodiments, the fourth extension portion and the SiAs capping layer are prepared synchronously in the same process step.

[0021] In some embodiments, the top surface of the photodiode is located within the bottom surface of the protruding portion.

[0022] In some embodiments, the back-illuminated image sensor further includes:

[0023] A filter, located between adjacent gratings and extending into the embedded protruding portion in the direction towards the substrate.

[0024] In a second aspect, the present application also provides a method for manufacturing a back-illuminated image sensor, including: providing a substrate, wherein the substrate includes a plurality of trench isolation structures extending into the substrate via a first surface and arranged at intervals in a first direction parallel to the first surface;

[0025] Forming, on the first surface, photodiodes and target isolation structures that are alternately arranged in the first direction and extend towards the substrate; the photodiodes include a SiAs stack layer, a SiAs capping layer arranged in a direction away from the substrate, and a SiP layer that penetrates the SiAs stack layer in the first direction and the direction towards the substrate; the target isolation structure includes a protruding portion with a top surface higher than the top surface of the photodiode; the grating and the protruding portion are prepared synchronously in the same process step.

[0026] In the above embodiments, by preparing a SiAs stack layer, a SiAs capping layer, and a SiP layer with a preset structure, a photodiode with different layer structures is formed, increasing the refraction of incident light, extending the optical path, achieving more effective photoelectric conversion, and improving the quantum efficiency. Subsequently, the process flow of forming the target isolation structure in one step and preparing the protruding portion of the grating synchronously can improve the process integration and efficiency, reduce costs, and ensure its structural integrity.

[0027] Compared with the traditional ion implantation process, preparing the photodiode structure on the top surface of the substrate can effectively avoid damage to the substrate caused by high-energy implanted ions, thereby reducing the number of defects in the photosensitive region and significantly reducing the recombination rate of photo-generated carriers.

[0028] In some embodiments, the SiAs stack layer includes a first SiAs layer and a second SiAs layer arranged at intervals in a direction away from the substrate;

[0029] The SiP layer includes:

[0030] A first extension portion that penetrates the first SiAs layer in the direction towards the substrate;

[0031] A second extension portion located between the first SiAs layer and the second SiAs layer;

[0032] A third extension portion that penetrates the second SiAs layer in the direction towards the substrate and extends into the second extension portion in the direction towards the substrate;

[0033] A fourth extension portion, located on the top surface of the second SiAs layer and extending along a first direction;

[0034] Wherein, the top surface of the first extension portion is within the bottom surface of the second extension portion; the top surface of the third extension portion is within the bottom surface of the fourth extension portion.

[0035] In some embodiments, the first extension portion and the second extension portion are prepared synchronously in the same process step.

[0036] In some embodiments, the fourth extension portion and the SiAs capping layer are prepared synchronously in the same process step.

[0037] In some embodiments, the dimension of the first extension portion along the first direction gradually decreases in a direction away from the substrate; the dimension of the third extension portion along the first direction gradually decreases in a direction towards the substrate.

[0038] In a third aspect, the present application further provides an electronic device, including: a back-illuminated image sensor as in any one of the above embodiments; or a back-illuminated image sensor prepared by the preparation method as in any one of the above embodiments.

[0039] In the above embodiments, by optimizing the quantum efficiency of the back-illuminated (BSI) image sensor and suppressing the dark current density, the imaging performance of the electronic device equipped with the sensor can be effectively improved, bringing higher sensitivity, a wider dynamic range, and a higher signal-to-noise ratio.

[0040] The back-illuminated image sensor, its preparation method, and the electronic device in the embodiments of the present application have the following unexpected technical effects:

[0041] Compared with the traditional high-energy ion implantation method, by using multiple epitaxial growth means to prepare a photodiode, the dark current generated due to substrate damage can be effectively reduced, and the image clarity can be effectively improved. By orderly overlapping the SiAs stack and the SiP layer, while optimizing the carrier transport path, the optical path of incident light in the photodiode can be increased, and the photoelectric conversion efficiency can be improved.

[0042] The target isolation structure and the trench isolation structure inside the substrate cooperate to ensure that the pixel structures are independent of each other, avoid the penetration of free electrons and the diffusion of light, and suppress the adverse effects of crosstalk on the image imaging clarity. At the same time, the protruding portion increases the height of the grating directly above, strengthens the light-gathering effect, reduces the probability of light entering adjacent pixel structures, and provides a solid guarantee for obtaining high-quality images. Description of the Drawings

[0043] To more clearly illustrate the technical solutions in the embodiments of the present application, the following will briefly introduce the accompanying drawings required for the description of the embodiments. Obviously, the accompanying drawings in the following description are only some embodiments of the present application. For those of ordinary skill in the art, without creative efforts, other accompanying drawings can also be obtained based on these drawings.

[0044] Figure 1 It is a flowchart of the preparation method provided in an embodiment;

[0045] Figure 2 It is a cross-sectional schematic diagram of the obtained structure of the substrate provided in step S20 of the preparation method provided in an embodiment;

[0046] Figure 3a It is a cross-sectional schematic diagram of the obtained structure after forming a trench isolation structure in step S302 of the preparation method provided in an embodiment;

[0047] Figure 3b For Figure 3a After forming a dielectric layer and an interlayer dielectric layer and performing a substrate thinning process, it is a cross-sectional schematic diagram of the obtained structure;

[0048] Figure 4 It is a cross-sectional schematic diagram of the obtained structure after forming a first SiAs layer in step S402 of the preparation method provided in an embodiment;

[0049] Figure 5 For Figure 4 After forming a first trench, it is a cross-sectional schematic diagram of the obtained structure;

[0050] Figure 6 For Figure 5 After forming a first SiP material layer, it is a cross-sectional schematic diagram of the obtained structure;

[0051] Figure 7 It is a cross-sectional schematic diagram of the obtained structure after forming a second SiAs layer in step S408 of the preparation method provided in an embodiment;

[0052] Figure 8 For Figure 7 After forming a second trench, it is a cross-sectional schematic diagram of the obtained structure;

[0053] Figure 9 For Figure 8 After forming a second SiP material layer, it is a cross-sectional schematic diagram of the obtained structure;

[0054] Figure 10 For Figure 9 After forming a SiAs capping layer, it is a cross-sectional schematic diagram of the obtained structure;

[0055] Figure 11Schematic cross-sectional view of the structure obtained after forming isolation trenches in step S420 of the manufacturing method provided in an embodiment;

[0056] Figure 12 is Figure 11 Schematic cross-sectional view of the structure obtained after forming an isolation material layer in;

[0057] Figure 13 Schematic cross-sectional view of the structure obtained after forming a first grid layer, a second grid layer, and a third grid layer in step S424 of the manufacturing method provided in an embodiment;

[0058] Figure 14 is Figure 13 Schematic cross-sectional view of the structure obtained after forming a groove in;

[0059] Figure 15 is Figure 14 Schematic cross-sectional view of the structure obtained after forming a filter.

[0060] Explanation of reference numerals:

[0061] 1. Initial substrate; 10. Substrate; 11. Dielectric layer; 12. Interlayer dielectric layer; 13. Oxide layer; 14. First grid layer; 15. Second grid layer; 16. Third grid layer; 20. Trench isolation structure; 30. SiAs stack; 31. First SiAs layer; 32. Second SiAs layer; 41. First trench; 42. Second trench; 43. Depression; 44. Isolation trench; 45. Groove; 50. SiP layer; 501. First SiP material layer; 502. Second SiP material layer; 51. First extension; 52. Second extension; 53. Third extension; 54. Fourth extension; 60. SiAs capping layer; 701. Silicon oxide layer; 70. Target isolation structure; 71. Isolation pillar; 72. Protrusion; 80. Grid. Detailed implementation manners

[0062] To facilitate understanding of the present application, the present application will be described more comprehensively below with reference to the relevant drawings. Preferred embodiments of the present application are shown in the drawings. However, the present application can be implemented in many different forms and is not limited to the embodiments described herein. On the contrary, these embodiments are provided to make the disclosure of the present application more thorough and comprehensive.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as commonly understood by those of ordinary skill in the technical field to which this application belongs. The terms used in the specification of this application herein are only for the purpose of describing specific embodiments and are not intended to limit the present application.

[0064] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected, or coupled to the other element or layer, or intervening elements or layers may be present. In contrast, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are only used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Thus, without departing from the teachings of this application, the first element, component, region, layer, doping type, or portion discussed below may be denoted as the second element, component, region, layer, or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for instance, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0065] Spatial relationship terms such as "under," "below," "beneath," "underneath," "above," "over," etc. are used herein to describe the relationship of one element or feature shown in the figures to other elements or features. It should be understood that, in addition to the orientation shown in the figures, spatial relationship terms also encompass different orientations of the device during use and operation. For example, if the device in the figures is flipped, an element or feature described as "under" or "beneath" or "underneath" another element or feature will be oriented "above" the other element or feature. Thus, the exemplary terms "under" and "beneath" can include both an upper and a lower orientation. Additionally, the device may include additional orientations (such as a 90-degree rotation or other orientations), and the spatial descriptors used herein are to be interpreted accordingly.

[0066] As used herein, the singular forms "a," "an," and "the" may also include the plural, unless the context clearly dictates otherwise. It should also be understood that when the terms "comprise" and / or "include" are used in this specification, the presence of the stated features, integers, steps, operations, elements, and / or components can be established, but one or more other features, integers, steps, operations, elements, components, and / or groups are not excluded from existence or addition. Also, as used herein, the term "and / or" includes any and all combinations of the associated listed items.

[0067] Embodiments of the invention are described herein with reference to cross-sectional views that are schematic illustrations of ideal embodiments (and intermediate structures) of the present application, so that variations in the shapes shown can be expected, for example, due to manufacturing techniques and / or tolerances. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but include shape deviations due to, for example, manufacturing techniques. For example, an implantation region shown as rectangular typically has rounded or curved features and / or an implantation concentration gradient at its edges, rather than a binary change from the implantation region to the non-implantation region. Similarly, a buried region formed by implantation can result in some implantation in the region between the buried region and the surface through which the implantation occurs. Thus, the regions shown in the figures are substantially schematic, and their shapes do not represent the actual shapes of the regions of the device and do not limit the scope of the present application.

[0068] In an embodiment of the present application, the substrate may include a first surface on the front side and a back side opposite to the front side, that is, a second surface. Ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction towards the substrate includes a second direction perpendicular to the first surface of the substrate. A first direction and a third direction that intersect each other (for example, are perpendicular to each other) are defined in the top and bottom directions of the substrate (that is, the plane where the substrate is located). For example, the arrangement direction of the target isolation structure is the first direction, and the plane where the substrate is located can be determined based on the first direction and the third direction. Among them, the first direction, the second direction, and the third direction can be perpendicular to each other in pairs. In an embodiment of the present application, the first direction is defined as the Y-axis direction, the second direction is defined as the Z-axis direction, and the third direction is defined as the X-axis direction.

[0069] Please refer to Figure 1 , the present application provides a method for manufacturing a back-illuminated image sensor, including: step S20 - step S40. The following is a specific description of the above steps with reference to the accompanying drawings:

[0070] Please refer to Figure 2 , step S20: Provide a substrate 10, and the substrate 10 includes a plurality of trench isolation structures 20 that extend into the substrate 10 via the first surface and are arranged at intervals along a first direction (OY direction) parallel to the first surface.

[0071] Exemplarily, the substrate 10 can be formed of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a substrate such as a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Or, for another example, the substrate can be a layered substrate including, for example, Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of the substrate should not limit the protection scope of the present disclosure.

[0072] In this embodiment, a P-type silicon wafer is used as the substrate 10.

[0073] Please refer to Figures 3a - 3b , in the extended step of step S20, it further includes:

[0074] Please refer to Figure 3a , step S302: In the front end of line (FEOL), an etching process and an epitaxial growth are used to form a shallow trench isolation (STI) structure in the initial substrate 1, denoted as the trench isolation structure 20.

[0075] Exemplarily, the cross-sectional shape of the trench isolation structure 20 in the OY direction can include a regular trapezoid, an inverted trapezoid, a rectangle, etc., or can also be a combination of shapes such as a regular trapezoid, an inverted trapezoid, a rectangle, etc. In the embodiment of the present application, the trench isolation structure only needs to be able to isolate electrons and light energy. In addition, in this embodiment, the distance between adjacent trenches is not specifically limited and can be set according to actual needs.

[0076] Among them, the material of the trench isolation structure 20 can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc., or a combination thereof.

[0077] Please refer to Figure 3b , step S304: Any deposition process can be used, but is not limited to, to form a dielectric layer 11 covering the trench isolation structure 20 on the initial substrate 1, and then form an interlayer dielectric layer 12 covering the dielectric layer 11, and then perform a thinning process on the above structure.

[0078] Exemplarily, at least one of a dry etching process, a wet etching process, a chemical mechanical polishing process, and a planarization process can be used to thin the initial substrate 1 on the side of the trench isolation structure 20 facing away from the interlayer dielectric layer 12 until the top surface 20a of the trench isolation structure 20 is exposed. At this time, the remaining initial substrate 1 is used to form the substrate 10.

[0079] Among them, the dielectric layer 11 can be a single layer or multiple layers. For example, the material of the dielectric layer 11 can include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbonitride, etc. or a combination thereof. Metal can be deposited after forming the dielectric layer 11 to form a metal wiring structure, and an interlayer dielectric layer 12 can be formed on this basis. The interlayer dielectric layer 12 can be a silicon oxide layer or other low dielectric material layer. Of course, this embodiment only shows one of the ways, as long as the reasonable formation of the metal wiring structure can be ensured.

[0080] Step S40: Form photodiodes and a target isolation structure 70 that are alternately arranged along the OY direction and extend toward the substrate 10 on the first surface. The photodiodes include a SiAs stack 30, a SiAs cap layer 60 arranged along the OZ direction, and a SiP layer 50 that penetrates the SiAs stack along the OY direction and the ZO direction; the target isolation structure 70 includes a protrusion 72 whose top surface is higher than the top surface of the photodiodes. The protrusion 72 and the grid 80 are prepared synchronously in the same process step.

[0081] In some embodiments, please refer to Figures 4 - 10 , step S40 further includes:

[0082] Please refer to Figure 4 , step S402: Epitaxially grow a first SiAs layer 31 on the first surface 10a of the substrate 10. Among them, the conductivity type of the first SiAs layer 31 is N-type, forming a homojunction PN junction with the P-type substrate 10.

[0083] Please refer to Figure 5 , step S404: Using a photolithography process, based on the patterned mask layer, form a plurality of first trenches 41 spaced along the OY direction in the first SiAs layer 31.

[0084] Specifically, the first trench 41 penetrates the first SiAs layer 31 along the ZO direction, and the width (the dimension along the OY direction) gradually increases in the ZO direction, and the cross-sectional shape on the zoy plane is a "right trapezoid".

[0085] Please refer to Figure 6 , step S406: Use epitaxial growth to form a first SiP material layer 501 that at least fills the first trenches 41.

[0086] In the above embodiment, due to the fact that the epitaxial growth rate of selective epitaxial growth is affected by the local geometry, the reaction gas is not transmitted as fully in a structure such as the first trench 41 as in the planar region. The first SiP material layer 501 presents a local depression in the first trench 41, and its top surface height is significantly lower than that of the adjacent planar region (the top surface of the first SiAs layer 31). Its depression depth is positively correlated with the trench depth-width ratio, and the edge presents a steep transition or a gentle slope.

[0087] Please refer to Figure 7 Step S408: Continuously epitaxially grow a second SiAs layer 32 on the top surface of the first SiP material layer 501.

[0088] In the above embodiments, the doping concentrations of arsenic (As) ions in the first SiAs layer 31 and the second SiAs layer 32 may be the same or different.

[0089] Please refer to Figure 8 Step S410: Form, by photolithography, a plurality of second trenches 42 in the second SiAs layer 32, which are arranged at intervals along the OY direction, penetrate the second SiAs layer 32 along the ZO direction, and extend to the first SiP material layer 501.

[0090] Specifically, the width (dimension along the OY direction) of the second trench 42 gradually decreases in the ZO direction, and the cross-sectional shape in the zoy plane is an "inverted trapezoid".

[0091] In the embodiments mentioned in the present application, the portion of the remaining first SiP material layer 501 that penetrates the first SiAs layer 31 along the ZO direction is denoted as the first extension portion 51; the portion located on the top surface of the first SiAs layer 31 and extending along the OY direction is denoted as the second extension portion 52.

[0092] Please refer to Figure 9 Step S412: Use epitaxial growth to form a second SiP material layer 502 that at least fills the second trenches 42.

[0093] Exemplarily, similar to the case of growing the first SiP material layer 501, the top surface of the second SiP material layer 502 that fills the second trenches 42 is lower than the top surface covering the second SiAs layer 32, forming a depression 43.

[0094] Please refer to Figure 10 Step S418: First grow at least one layer of SiAs material that fills the depression 43, and then use Chemical Mechanical Polish (CMP) to remove the SiAs material outside the depression 43 to form a SiAs cap layer 60. At this time, the portion of the remaining second SiP material layer 502 that penetrates the second SiAs layer 32 along the ZO direction is denoted as the third extension portion 53; the portion located on the top surface of the second SiAs layer 32 and extending along the OY direction is denoted as the fourth extension portion 54.

[0095] For example, the doping concentration of phosphorus (P) ions in the second SiP material layer 502 and the first SiP material layer 501 may be the same or different; the doping concentration of arsenic (As) ions in the SiAs cap layer 60 may be the same or different from the doping concentrations of the first SiAs layer 31 and the second SiAs layer 32. The first extension portion 51 and the third extension portion 53 fill the first trench 41 and the second trench 42 respectively, and thus have the same shape as the trench.

[0096] In the above embodiments, different doping elements (such as As and P) are introduced into a gradient refractive index distribution to enhance the reflection / refraction effect of light at the interlayer interface; the width (dimension along the OY direction) of the first extension portion 51 and the third extension portion 53 varies with the depth (dimension along the OZ direction), so that part of the incident light is reflected or refracted multiple times after being transmitted between layers to the side walls of the first extension portion 51 and the third extension portion 53, thereby extending the optical path of the light.

[0097] See also Figure 11 Step S420: after depositing an oxide layer 13 on the top surface of the SiAs cap layer 60 , etching to form an isolation trench 44 that penetrates the oxide layer 13 , the fourth extension portion 54 , the second SiAs layer 32 , the second extension portion 52 and the first SiAs layer 31 along the ZO direction.

[0098] The material of the oxide layer 13 is silicon oxide (SiO2). The width of the isolation trench 44 gradually decreases along the ZO direction to ensure the photosensitive area of the photodiode. At this time, the remaining second extension portion 52, the fourth extension portion 54 and the first extension portion 51, the third extension portion 53 are used together to form the SiP layer 50; the remaining first SiAs layer 31 and the second SiAs layer 32 are used together to form the SiAs stack 30.

[0099] See also Figure 12 Step S422: Spin coating a liquid dielectric formed by mixing a solvent with a silicon oxide (SiO 2 ) dielectric into the isolation trench 44 to form an isolation material layer whose top surface is not lower than the top surface of the oxide layer 13 .

[0100] In the above embodiment, the deposition method can better control the formation area of the oxide layer 13, and the spin coating method can avoid the existence of holes in the isolation material layer in the isolation trench 44 due to insufficient filling. Since the isolation material layer and the oxide layer 13 are made of the same material, have a continuous structure, and have synergistic functions, both of them play an isolation role and can be regarded as a single silicon oxide whole, which is recorded as silicon oxide layer 701.

[0101] See also Figure 13 , step S424: forming a first grid layer 14 , a second grid layer 15 , and a third grid layer 16 stacked along the OZ direction on the top surface of the silicon oxide layer 701 .

[0102] Among them, the materials of the first grating layer 14 include, but are not limited to, one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum pentoxide (Ta2O5), titanium dioxide (TiO2), or strontium titanate (SrTiO3), etc.; the material of the second grating layer 15 may include titanium nitride (TiN); the materials of the third grating layer 16 may include, but are not limited to, metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), copper (Cu), aluminum (Al), etc.

[0103] Here, in this embodiment, the first grating layer 14 is hafnium oxide (HfO2), the second grating layer 15 is titanium nitride (TiN); the third grating layer 16 is aluminum (Al).

[0104] Please refer to Figure 14 , step S426: Etch the first grating layer 14, the second grating layer 15, the third grating layer 16, and the silicon oxide layer 701 to obtain gratings 80 and grooves 45 arranged alternately along the OY direction; the grooves 45 extend into the silicon oxide layer 701 along the ZO direction, and the remaining silicon oxide layer 701 is used to form the target isolation structure 70, and the gratings 80 and the target isolation structure 70 are arranged one-to-one.

[0105] In the above embodiment, the target isolation structure 70 includes an isolation column 71 whose top surface is flush with the photodiode, and a protruding portion 72 whose top surface is higher than the top surface of the photodiode. The combination of the isolation column 71 and the trench isolation structure 20 isolates adjacent photodiodes from each other, thereby effectively preventing optical / electrical crosstalk and improving the imaging quality of the back-illuminated image sensor; the protruding portion 72 further increases the interception height of the grating 80 directly above, strengthening the light-gathering ability of the grating 80. In addition, the portion covering the top surface of the photodiode can serve as an etch stop layer when etching the groove 45 to prevent unnecessary damage to the underlying photodiode.

[0106] Among them, the structure of the back-illuminated image sensor obtained after the preparation method steps S20 - S40 can be referred to Figure 14 . Of course, for the convenience of understanding this application, Figure 14 only an example of the back-illuminated image sensor prepared by the preparation method in the embodiment of this application is given. There can be other suitable examples of the back-illuminated image sensor prepared by this preparation method, and this application does not limit them here.

[0107] In some embodiments, after step S40, it further includes: forming a filter in the groove 45.

[0108] Exemplarily, please refer to Figure 15, the filter includes but is not limited to a red filter, a yellow filter, a blue filter, etc., and three filters are arranged adjacent to each other to form a pixel group. The color filter maintains a high transmittance in a specific wavelength band. Among them, the red filter transmits red light waves, the yellow filter transmits yellow light waves, and the blue filter transmits blue light waves. In addition, the top of the filter is in a rounded arc shape, which is beneficial to the convergence of light. Other microlens structures can also be used to meet the light collection requirements, and the present application does not make specific limitations.

[0109] Please refer to Figure 14 , in some embodiments, the present application provides a back-illuminated image sensor, including a substrate 10, a grid 80, and photodiodes and target isolation structures 70 that are arranged alternately along the OY direction parallel to the first surface on the first surface of the substrate 10 and extend toward the substrate;

[0110] The substrate 10 includes a plurality of trench isolation structures 20 that extend into the substrate 10 through the first surface and are arranged at intervals along the OY direction; the trench isolation structures 20 are arranged one-to-one with the target isolation structures 70 directly above them;

[0111] The photodiode includes a SiAs stack 30 arranged along the ZO direction, a SiAs cover layer 60, and a SiP layer 50 that penetrates the SiAs stack 30 along the OY direction and the ZO direction;

[0112] The target isolation structure 70 includes a protrusion 72 that is higher than the top surface of the photodiode; the grid 80 is prepared synchronously with the protrusion 72 in the same process step.

[0113] Further, in some embodiments, the SiAs stack 30 includes a first SiAs layer 31 and a second SiAs layer 32 that are arranged at intervals in a direction away from the substrate;

[0114] The SiP layer 50 includes: a first extension 51 that penetrates the first SiAs layer 31 along the ZO direction; a second extension 52 that is located between the first SiAs layer 31 and the second SiAs layer 32; the top surface of the first extension 51 is within the bottom surface of the second extension 52; a third extension 53 that penetrates the second SiAs layer 32 along the ZO direction and extends into the second extension 52 in the ZO direction; a fourth extension 54 that is located on the top surface of the second SiAs layer 32 and extends along the OY direction; wherein, the top surface of the first extension 51 is within the bottom surface of the second extension 52; the top surface of the third extension 53 is within the bottom surface of the fourth extension 54.

[0115] In the above embodiments, the photosensitive materials doped with different elements, arsenic (As) and phosphorus (P), are arranged alternately to generate more photo-generated carriers. At the same time, optimizing the generation and separation processes of the carriers helps to maximize the conversion of incident light and reduce the carrier recombination phenomenon, thereby prolonging the carrier lifetime.

[0116] Further, please continue to refer to Figure 13 , in some embodiments, the size of the first extension portion 51 along the OY direction gradually decreases in the OZ direction; the size of the third extension portion 53 along the OY direction gradually decreases in the ZO direction.

[0117] In the above embodiments, the first extension portion 51 and the third extension portion 53 with a gradually changing width can introduce a plurality of inclined refraction surfaces in the photodiode, which helps to guide light in multiple directions, generate more light refraction / reflection, and increase the optical path to improve the photoelectric conversion efficiency.

[0118] In some embodiments, the first extension portion 51 and the second extension portion 52 are prepared synchronously in the same process step; the fourth extension portion 54 and the SiAs cover layer 60 are prepared synchronously in the same process step. Since the pixel layout of alternately arranging the SiAs stack 30 and the SiP layer 50 is relatively complex, the design of synchronous preparation in the same process step can significantly optimize the process integration degree and reduce the preparation complexity.

[0119] In some embodiments, the top surface of the photodiode is located within the bottom surface of the protruding portion 72;

[0120] The back-illuminated image sensor further includes:

[0121] A filter, located between adjacent gratings 80 and extending along the ZO direction to be embedded in the protruding portion 72.

[0122] In the above embodiments, the protruding portion 72 can avoid damaging the photodiode during the etching of the grating, ensuring the integrity and quality of the structure of the back-illuminated image sensor.

[0123] This application also provides an electronic device, including the back-illuminated image sensor prepared by the preparation method described in any one of the above embodiments; or the back-illuminated image sensor described in the above embodiments.

[0124] The back-illuminated image sensor, its preparation method, and the electronic device provided by this application have the following unexpected technical effects:

[0125] The photodiode is fabricated on the top surface of the substrate by using multiple epitaxial growth techniques, which can effectively avoid the unnecessary damage generated during the traditional high-energy ion implantation process, reduce the dark current caused by substrate damage, and thus improve the image clarity. In the photodiode, by alternately arranging photosensitive layers doped with different VA group elements (SiAs stack, SiP layer, and SiAs capping layer), a refractive index distribution difference is formed, which promotes multiple reflections of the incident light between the layers, extends the optical path, and significantly improves the photoelectric conversion efficiency.

[0126] In addition, the target isolation structure and the trench isolation structure in the substrate jointly construct an efficient all-physical isolation barrier, ensuring that the pixel structures are independent of each other, effectively preventing the penetration of free electrons and the diffusion of light, and suppressing the negative impact of the crosstalk effect on the image clarity. At the same time, the protrusion is used to increase the overall height of the grating directly above, thereby enhancing the light convergence effect and reducing the possibility of light entering the adjacent pixel structure, providing strong support for obtaining high-quality images.

[0127] In summary, by optimizing the manufacturing process and internal structure of the back-illuminated image sensor, the overall performance of the device can be significantly improved, laying a solid technical foundation for obtaining high-quality images.

[0128] The technical features of the above-described embodiments can be combined arbitrarily. For the sake of brevity of description, not all possible combinations of the technical features of the above-described embodiments are described. However, as long as there is no contradiction in the combination of these technical features, it should be considered as the scope described in this specification.

[0129] The above-described embodiments merely represent several implementation manners of the present application. Their descriptions are relatively specific and detailed, but they should not be construed as limiting the scope of the patent application. It should be noted that for those of ordinary skill in the art, without departing from the concept of the present application, several modifications and improvements can still be made, and these all belong to the protection scope of the present application. Therefore, the protection scope of the patent of the present application shall be subject to the appended claims.

Claims

1. A back-illuminated image sensor, characterized in that, It includes a substrate, a grid, and photodiodes and target isolation structures that are arranged alternately on the first surface of the substrate along a first direction parallel to the first surface and extend towards the substrate; The substrate includes a plurality of trench isolation structures that extend into the substrate through the first surface and are arranged at intervals along the first direction; the trench isolation structures are arranged in a one-to-one correspondence with the target isolation structures directly above them; The photodiode includes a SiAs stack, a SiAs cover layer arranged in a direction away from the substrate, and a SiP layer that penetrates the SiAs stack along the first direction and towards the substrate; The target isolation structure includes a protrusion whose top surface is higher than the top surface of the photodiode; The protrusion and the grid are prepared synchronously in the same process step.

2. The back-illuminated image sensor according to claim 1, wherein The SiAs stack includes a first SiAs layer and a second SiAs layer arranged at intervals in a direction away from the substrate; 3. The back-illuminated image sensor according to claim 2, wherein, The SiP layer includes: A first extension part that penetrates the first SiAs layer along a direction towards the substrate; A second extension part that is located between the first SiAs layer and the second SiAs layer; A third extension part that penetrates the second SiAs layer along a direction towards the substrate and extends into the second extension part along a direction towards the substrate; A fourth extension part that is located on the top surface of the second SiAs layer and extends along the first direction; Wherein, the top surface of the first extension part is located inside the bottom surface of the second extension part; the top surface of the third extension part is located inside the bottom surface of the fourth extension part.

4. The back-illuminated image sensor according to claim 3, wherein The dimension of the first extension part along the first direction gradually decreases in a direction away from the substrate; the dimension of the third extension part along the first direction gradually decreases in a direction towards the substrate.

5. The back-illuminated image sensor according to claim 3, wherein It includes at least one of the following features; The first extension part and the second extension part are prepared synchronously in the same process step; The fourth extension part and the SiAs cover layer are prepared synchronously in the same process step.

6. The back-illuminated image sensor according to claim 1, wherein The top surface of the photodiode is located inside the bottom surface of the protrusion; The back-illuminated image sensor further includes: A filter that is located between adjacent grids and extends towards the substrate to be embedded in the protrusion.

7. A method for manufacturing a back-illuminated image sensor, characterized in that, It includes: Provide a substrate, and the substrate includes a plurality of trench isolation structures that extend into the substrate through a first surface and are arranged at intervals along a first direction parallel to the first surface; Form photodiodes and target isolation structures that are arranged alternately along the first direction and extend towards the substrate on the first surface; The photodiode includes a SiAs stack, a SiAs cover layer arranged in a direction away from the substrate, and a SiP layer that penetrates the SiAs stack along the first direction and towards the substrate; the target isolation structure includes a protrusion whose top surface is higher than the top surface of the photodiode; The grid and the protrusion are prepared synchronously in the same process step.

8. The preparation method according to claim 7, characterized in that, The SiAs stack includes a first SiAs layer and a second SiAs layer arranged at intervals in a direction away from the substrate; The SiP layer includes: A first extension portion that penetrates through the first SiAs layer in a direction towards the substrate; A second extension portion that is located between the first SiAs layer and the second SiAs layer; A third extension portion that penetrates through the second SiAs layer in a direction towards the substrate and extends into the second extension portion in the direction towards the substrate; A fourth extension portion that is located on the top surface of the second SiAs layer and extends in the first direction; Wherein, the top surface of the first extension portion is within the bottom surface of the second extension portion; the top surface of the third extension portion is within the bottom surface of the fourth extension portion.

9. According to the preparation method described in claim 8, characterized in that, Comprising at least one of the following features; The first extension portion and the second extension portion are prepared synchronously in the same process step; The fourth extension portion and the SiAs capping layer are prepared synchronously in the same process step; The dimension of the first extension portion in the first direction gradually decreases in a direction away from the substrate; the dimension of the third extension portion in the first direction gradually decreases in a direction towards the substrate.

10. An electronic device, characterized in that, Comprising: A back-illuminated image sensor according to any one of claims 1-6; Or A back-illuminated image sensor prepared by the preparation method according to any one of claims 7-9.

Images