Back-illuminated image sensor, preparation method thereof, and electronic device

Abstract

The present application relates to a back-illuminated image sensor, a method for fabricating the same, and an electronic device. The device comprises a substrate, a grid, and photodiodes and a target isolation structure located on a first surface of the substrate and arranged alternately along a first direction parallel to the first surface and extending toward the substrate. The substrate comprises a plurality of trench isolation structures extending into the substrate through the first surface and arranged at intervals along the first direction. The trench isolation structures are arranged one-to-one with the target isolation structures directly above them. The photodiode comprises a SiAs stack arranged in a direction away from the substrate, a SiAs cap layer, and a SiP layer extending through the SiAs stack in the first direction and toward the substrate. The target isolation structure comprises a protrusion that is higher than the top surface of the photodiode. The grid and the protrusion are fabricated simultaneously in the same process step. This method can avoid signal crosstalk in the BSI image sensor and unnecessary damage caused by IMP (Inductively Coupled Plasma) while improving photoelectric conversion efficiency.

Description

Technical Field

[0001] The present application relates to the field of integrated circuit technology, and in particular to a back-illuminated image sensor, a preparation method thereof, and an electronic device. Background Art

[0002] Image sensors are photoelectric conversion devices widely used in consumer electronics, security monitoring, automotive electronics, machine vision, and other fields. Backside illuminated (BSI) image sensors offer advantages such as higher sensitivity, improved wiring layout, and high-speed recording, making them commonly used in applications requiring high pixel performance.

[0003] However, in traditional BSI front-end processes, high-energy ion implantation (IMP) is required to create the diode structure to form the pixel region, which can damage the substrate surface. Uneven ion implantation can also lead to signal crosstalk between different pixels, hindering further improvement in BSI image sensor performance. Summary of the Invention

[0004] Based on this, it is necessary to address the technical problems in related technologies and provide a back-illuminated image sensor and its preparation method and electronic equipment, which can at least avoid signal crosstalk of the BSI image sensor and unnecessary damage caused by IMP.

[0005] In a first aspect, the present application provides a back-illuminated image sensor, comprising a substrate, a grid, and photodiodes and a target isolation structure located on a first surface of the substrate and alternately arranged along a first direction parallel to the first surface and extending toward the substrate;

[0006] The substrate includes a plurality of trench isolation structures extending into the substrate through the first surface and spaced apart along a first direction; the trench isolation structures are arranged one-to-one with the target isolation structures directly above them;

[0007] The photodiode includes a SiAs stack arranged in a direction away from the substrate, a SiAs cap layer, and a SiP layer penetrating the SiAs stack in a first direction and a direction toward the substrate;

[0008] The target isolation structure includes a protrusion with a top surface higher than a top surface of the photodiode; the grid and the protrusion are prepared at the same time in the same process step.

[0009] In the back-illuminated image sensor described in the above embodiment, the target isolation structure and the trench isolation structure are connected together along the substrate, extending through the pixel region and forming a fully isolated pixel structure with the photodiode, completely isolating adjacent pixel structures. When incident light enters the pixel structure, its propagation path is confined to the internal photodiode, and the resulting photogenerated electrons are intercepted to the greatest extent possible, effectively suppressing the adverse effects of crosstalk on image clarity. Furthermore, the grille on the top surface of the target isolation structure is formed simultaneously with the protrusion, increasing its overall height, enhancing the light convergence effect, and reducing the risk of light entering adjacent pixel structures.

[0010] The photodiode is composed of an arrangement of photosensitive layers including different doping elements. Among them, the SiP layer penetrates the SiAs stack in multiple directions. After the incident light enters the photodiode, it can produce more light refraction, increase the optical path, and increase the photon absorption distance, thereby improving the light absorption efficiency of the pixel structure and improving the quantum efficiency.

[0011] In some embodiments, the SiAs stack includes a first SiAs layer and a second SiAs layer spaced apart and arranged in a direction away from the substrate;

[0012] In some embodiments, the SiP layer includes:

[0013] a first extension portion extending through the first SiAs layer in a direction toward the substrate;

[0014] a second extension portion, located between the first SiAs layer and the second SiAs layer;

[0015] a third extension portion, penetrating the second SiAs layer in a direction toward the substrate and extending into the second extension portion in a direction toward the substrate;

[0016] a fourth extension portion, located on the top surface of the second SiAs layer and extending along the first direction;

[0017] The top surface of the first extending portion is located inside the bottom surface of the second extending portion; and the top surface of the third extending portion is located inside the bottom surface of the fourth extending portion.

[0018] In some embodiments, a dimension of the first extension portion along the first direction gradually decreases in a direction away from the substrate; and a dimension of the third extension portion along the first direction gradually decreases in a direction toward the substrate.

[0019] In some embodiments, the first extension portion and the second extension portion are prepared simultaneously in the same process step.

[0020] In some embodiments, the fourth extension portion and the SiAs capping layer are prepared simultaneously in the same process step.

[0021] In some embodiments, a top surface of the photodiode is located within a bottom surface of the protrusion.

[0022] In some embodiments, the backside illuminated image sensor further comprises:

[0023] The filter is located between adjacent grids and extends toward the substrate to be embedded in the protrusion.

[0024] In a second aspect, the present application further provides a method for preparing a back-illuminated image sensor, comprising: providing a substrate, wherein the substrate includes a plurality of trench isolation structures extending into the substrate through a first surface and spaced apart along a first direction parallel to the first surface;

[0025] Photodiodes and a target isolation structure are formed on the first surface, which are alternately arranged along a first direction and extend toward the substrate. The photodiode includes a SiAs stack and a SiAs cap layer arranged in a direction away from the substrate, and a SiP layer that penetrates the SiAs stack along the first direction and toward the substrate. The target isolation structure includes a protrusion with a top surface higher than the top surface of the photodiode. The grid and the protrusion are prepared simultaneously in the same process step.

[0026] In the above-described embodiment, a pre-configured SiAs stack, SiAs cap layer, and SiP layer are fabricated to form a photodiode with a different layer structure. This increases the refraction of incident light, extends the optical path, achieves more efficient photoelectric conversion, and improves quantum efficiency. Subsequently, the targeted isolation structure is formed in a single process, and the protrusions are fabricated simultaneously with the grid. This process improves process integration and efficiency, reduces costs, and ensures structural integrity.

[0027] Compared with the traditional ion implantation process, preparing the photodiode structure on the top surface of the substrate can effectively avoid the damage to the substrate caused by high-energy implanted ions, thereby reducing the number of defects in the photosensitive area and significantly reducing the recombination rate of photogenerated carriers.

[0028] In some embodiments, the SiAs stack includes a first SiAs layer and a second SiAs layer spaced apart and arranged in a direction away from the substrate;

[0029] The SiP layer includes:

[0030] a first extension portion extending through the first SiAs layer in a direction toward the substrate;

[0031] a second extension portion, located between the first SiAs layer and the second SiAs layer;

[0032] a third extension portion, penetrating the second SiAs layer in a direction toward the substrate and extending into the second extension portion in a direction toward the substrate;

[0033] a fourth extension portion, located on the top surface of the second SiAs layer and extending along the first direction;

[0034] The top surface of the first extending portion is located inside the bottom surface of the second extending portion; and the top surface of the third extending portion is located inside the bottom surface of the fourth extending portion.

[0035] In some embodiments, the first extension portion and the second extension portion are prepared simultaneously in the same process step.

[0036] In some embodiments, the fourth extension portion and the SiAs capping layer are prepared simultaneously in the same process step.

[0037] In some embodiments, a dimension of the first extension portion along the first direction gradually decreases in a direction away from the substrate; and a dimension of the third extension portion along the first direction gradually decreases in a direction toward the substrate.

[0038] In a third aspect, the present application further provides an electronic device, comprising: a back-illuminated image sensor as in any one of the above embodiments; or a back-illuminated image sensor prepared by the preparation method as in any one of the above embodiments.

[0039] In the above embodiment, by optimizing the quantum efficiency of the backside-illuminated (BSI) image sensor and suppressing the dark current density, the imaging performance of the electronic device equipped with the sensor can be effectively improved, resulting in higher sensitivity, wider dynamic range, and higher signal-to-noise ratio.

[0040] The back-illuminated image sensor, its preparation method, and electronic device in the embodiments of the present application have the following unexpected technical effects:

[0041] Compared to traditional high-energy ion implantation methods, fabricating photodiodes through multiple epitaxial growth processes effectively reduces dark current caused by substrate damage, significantly improving image clarity. The orderly overlapping of SiAs and SiP layers optimizes carrier transport paths while increasing the optical path of incident light within the photodiode, thereby improving photoelectric conversion efficiency.

[0042] The target isolation structure works synergistically with the trench isolation structure within the substrate to ensure pixel isolation, preventing free electron penetration and light diffusion, and suppressing the negative impact of crosstalk on image clarity. Furthermore, the raised portion increases the height of the upper grille, enhancing light convergence and reducing the chance of light straying into adjacent pixel structures, providing a solid foundation for high-quality image capture. BRIEF DESCRIPTION OF THE DRAWINGS

[0043] In order to more clearly illustrate the technical solutions in the embodiments of the present application, the following briefly introduces the drawings required for use in the description of the embodiments. Obviously, the drawings described below are only some embodiments of the present application. For ordinary technicians in this field, other drawings can be obtained based on these drawings without any creative work.

[0044] Figure 1 is a flow chart of a preparation method provided in one embodiment;

[0045] Figure 2 1 is a schematic cross-sectional view of a structure obtained by providing a substrate in step S20 of a preparation method provided in an embodiment;

[0046] Figure 3a Schematic cross-sectional view of a structure obtained after forming a trench isolation structure in step S302 in a preparation method provided in one embodiment;

[0047] Figure 3b for Figure 3a A schematic cross-sectional view of the structure obtained after forming a dielectric layer and an interlayer dielectric layer and performing a substrate thinning process;

[0048] Figure 4 4 is a schematic cross-sectional view of a structure obtained after forming the first SiAs layer in step S402 of the preparation method provided in one embodiment;

[0049] Figure 5 for Figure 4 A schematic cross-sectional view of the structure obtained after the first trench is formed in FIG.

[0050] Figure 6 for Figure 5 A schematic cross-sectional view of the structure obtained after forming the first SiP material layer;

[0051] Figure 7 is a schematic cross-sectional view of a structure obtained after forming the second SiAs layer in step S408 of the preparation method provided in one embodiment;

[0052] Figure 8 for Figure 7 A schematic cross-sectional view of the structure obtained after forming the second trench;

[0053] Figure 9 for Figure 8 A schematic cross-sectional view of the structure obtained after forming the second SiP material layer;

[0054] Figure 10 for Figure 9 Schematic cross-sectional view of the structure obtained after the SiAs capping layer is formed;

[0055] Figure 11Schematic cross-sectional view of the structure obtained after forming the isolation trench in step S420 of the preparation method provided in one embodiment;

[0056] Figure 12 for Figure 11 A schematic cross-sectional view of the structure obtained after forming an isolation material layer;

[0057] Figure 13 Schematic cross-sectional view of the structure obtained after forming the first grid layer, the second grid layer, and the third grid layer in step S424 of the preparation method provided in one embodiment;

[0058] Figure 14 for Figure 13 A schematic cross-sectional view of the structure obtained after the groove is formed in the middle;

[0059] Figure 15 for Figure 14 Schematic cross-sectional view of the resulting structure after filter formation.

[0060] Description of reference numerals:

[0061] 1. Initial substrate; 10. Substrate; 11. Dielectric layer; 12. Interlayer dielectric layer; 13. Oxide layer; 14. First grid layer; 15. Second grid layer; 16. Third grid layer; 20. Trench isolation structure; 30. SiAs stack; 31. First SiAs layer; 32. Second SiAs layer; 41. First trench; 42. Second trench; 43. Recess; 44. Isolation trench; 45. Groove; 50. SiP layer; 501. First SiP material layer; 502. Second SiP material layer; 51. First extension; 52. Second extension; 53. Third extension; 54. Fourth extension; 60. SiAs cap layer; 701. Silicon oxide layer; 70. Target isolation structure; 71. Isolation column; 72. Protrusion; 80. Grid. DETAILED DESCRIPTION

[0062] To facilitate understanding of the present application, a more comprehensive description of the present application will be provided below with reference to the accompanying drawings. The drawings illustrate preferred embodiments of the present application. However, the present application may be implemented in many different forms and is not limited to the embodiments described herein. Rather, these embodiments are provided to provide a more thorough and comprehensive understanding of the present disclosure.

[0063] Unless otherwise defined, all technical and scientific terms used herein have the same meaning as those commonly understood by those skilled in the art to which this application pertains. The terms used herein in the specification of this application are for the purpose of describing specific embodiments only and are not intended to limit this application.

[0064] It should be understood that when an element or layer is referred to as being "on," "adjacent to," "connected to," or "coupled to" another element or layer, it can be directly on, adjacent to, connected to, or coupled to the other element or layer, or there can be intervening elements or layers. Conversely, when an element is referred to as being "directly on," "directly adjacent to," "directly connected to," or "directly coupled to" another element or layer, there are no intervening elements or layers. It should be understood that although the terms first, second, third, etc. may be used to describe various elements, components, regions, layers, doping types, and / or portions, these elements, components, regions, layers, doping types, and / or portions should not be limited by these terms. These terms are merely used to distinguish one element, component, region, layer, doping type, or portion from another element, component, region, layer, doping type, or portion. Therefore, without departing from the teachings of the present application, the first element, component, region, layer, doping type or portion discussed below may be represented as a second element, component, region, layer or portion; for example, the first doping type may be referred to as the second doping type, and similarly, the second doping type may be referred to as the first doping type; the first doping type and the second doping type are different doping types, for example, the first doping type may be P-type and the second doping type may be N-type, or the first doping type may be N-type and the second doping type may be P-type.

[0065] Spatially relative terms such as "under," "beneath," "below," "under," "above," "above," etc., may be used herein to describe the relationship of an element or feature shown in the figures to other elements or features. It should be understood that in addition to the orientations shown in the figures, spatially relative terms also include different orientations of the device in use and operation. For example, if the device in the drawings is turned over, the element or feature described as "under" or "beneath" or "beneath" the other elements will be oriented as "above" the other elements or features. Thus, the exemplary terms "under" and "under" may include both upper and lower orientations. In addition, the device may also include alternative orientations (e.g., rotated 90 degrees or other orientations), and the spatial descriptors used herein are interpreted accordingly.

[0066] As used herein, the singular forms "a," "an," and "the" may also include the plural forms, unless the context clearly indicates otherwise. It should also be understood that when the terms "comprising" and / or "including" are used in this specification, they may specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups. At the same time, when used herein, the term "and / or" includes any and all combinations of the relevant listed items.

[0067] Embodiments of the invention are described herein with reference to cross-sectional views which are schematic illustrations of idealized embodiments (and intermediate structures) of the present application, such that variations in the shapes shown due to, for example, manufacturing techniques and / or tolerances are anticipated. Accordingly, embodiments of the present application should not be limited to the specific shapes of the regions shown herein, but rather include deviations in shapes due to, for example, manufacturing techniques. For example, an implanted region shown as a rectangle typically has rounded or curved features and / or an implant concentration gradient at its edges, rather than a binary change from an implanted region to a non-implanted region. Similarly, a buried region formed by implantation may result in some implantation in the region between the buried region and the surface through which the implantation occurs. Accordingly, the regions shown in the figures are schematic in nature, their shapes do not represent the actual shape of the region of the device, and do not limit the scope of the present application.

[0068] In an embodiment of the present application, the substrate may include a first surface located on the front side, and a back side opposite to the front side, i.e., a second surface. Ignoring the flatness of the first surface and the second surface, a first direction parallel to the first surface is defined, and the direction toward the substrate includes a second direction perpendicular to the first surface of the substrate. A first direction and a third direction that intersect each other (e.g., perpendicular to each other) are defined in the top and bottom surface directions of the substrate (i.e., the plane where the substrate is located). For example, the arrangement direction of the target isolation structure is the first direction, and the plane where the substrate is located can be determined based on the first direction and the third direction. Among them, the first direction, the second direction, and the third direction can be perpendicular to each other in pairs. In an embodiment of the present application, the first direction is defined as the Y-axis direction, the second direction is defined as the Z-axis direction, and the third direction is defined as the X-axis direction.

[0069] See also Figure 1 The present application provides a method for preparing a back-illuminated image sensor, including steps S20 to S40. The above steps are described in detail below with reference to the accompanying drawings:

[0070] See also Figure 2 Step S20: providing a substrate 10, wherein the substrate 10 includes a plurality of trench isolation structures 20 extending into the substrate 10 through the first surface and arranged at intervals along a first direction (OY direction) parallel to the first surface.

[0071] For example, the substrate 10 can be made of a semiconductor material, an insulating material, a conductive material, or any combination thereof. The substrate can be a single-layer structure or a multi-layer structure. For example, the substrate can be a silicon (Si) substrate, a silicon germanium (SiGe) substrate, a silicon germanium carbon (SiGeC) substrate, a silicon carbide (SiC) substrate, a gallium arsenide (GaAs) substrate, an indium arsenide (InAs) substrate, an indium phosphide (InP) substrate, or other III / V semiconductor substrates or II / VI semiconductor substrates. Alternatively, for example, the substrate can be a layered substrate including Si / SiGe, Si / SiC, silicon on insulator (SOI), or silicon germanium on insulator. Therefore, the type of substrate should not limit the scope of protection of the present disclosure.

[0072] In this embodiment, a P-type silicon wafer is used as the substrate 10 .

[0073] See also Figure 3a-Figure 3b , in the extension step of step S20, further comprising:

[0074] See also Figure 3a Step S302 : In the front end of line (FEOL) process, a shallow trench isolation (STI) structure is formed in the initial substrate 1 by etching and epitaxial growth, which is recorded as a trench isolation structure 20 .

[0075] For example, the cross-sectional shape of the trench isolation structure 20 along the OY direction may include a regular trapezoid, an inverted trapezoid, a rectangle, or a combination thereof. In the present embodiment, the trench isolation structure only needs to be able to isolate electrons and light energy. Furthermore, the present embodiment does not impose any specific restrictions on the distance between adjacent trenches, which may be set according to actual needs.

[0076] The material of the trench isolation structure 20 may include but is not limited to silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or the like or a combination thereof.

[0077] See also Figure 3b Step S304: any deposition process may be used but is not limited to form a dielectric layer 11 covering the trench isolation structure 20 on the initial substrate 1, and then an interlayer dielectric layer 12 covering the dielectric layer 11 is formed, and then the above structure is subjected to a thinning process.

[0078] For example, at least one of a dry etching process, a wet etching process, a chemical mechanical polishing process, and a push-on process can be used to thin the initial substrate 1 located on the side of the trench isolation structure 20 facing away from the interlayer dielectric layer 12, so as to expose the top surface 20a of the trench isolation structure 20. At this time, the remaining initial substrate 1 is used to form the substrate 10.

[0079] The dielectric layer 11 may be a single layer or multiple layers. For example, the material of the dielectric layer 11 may include, but is not limited to, silicon oxide, silicon nitride, silicon oxynitride, silicon carbide nitride, or a combination thereof. After forming the dielectric layer 11, metal may be deposited to form a metal wiring structure, and on this basis, an interlayer dielectric layer 12 may be formed. The interlayer dielectric layer 12 may be a silicon oxide layer or other low-dielectric material layer. Of course, this embodiment represents only one method; any method will suffice as long as the metal wiring structure can be properly formed.

[0080] Step S40: Photodiodes and a target isolation structure 70 are formed on the first surface, which are alternately arranged along the OY direction and extend toward the substrate 10; the photodiode includes a SiAs stack 30 and a SiAs cap layer 60 arranged along the OZ direction, and a SiP layer 50 that penetrates the SiAs stack along the OY direction and the ZO direction; the target isolation structure 70 includes a protrusion 72 whose top surface is higher than the top surface of the photodiode; the protrusion 72 and the grid 80 are prepared at the same time in the same process step.

[0081] In some embodiments, see Figure 4-10 , step S40 further includes:

[0082] See also Figure 4 Step S402: epitaxially grow a first SiAs layer 31 on the first surface 10a of the substrate 10. The first SiAs layer 31 has an N-type conductivity and forms a homogeneous PN junction with the P-type substrate 10.

[0083] See also Figure 5 Step S404: using a photolithography process, based on the patterned mask layer, a plurality of first trenches 41 spaced apart along the OY direction are formed in the first SiAs layer 31 .

[0084] Specifically, the first trench 41 penetrates the first SiAs layer 31 along the ZO direction, and its width (dimension along the OY direction) gradually increases in the ZO direction, and its cross-sectional shape on the zoy plane is a “normal trapezoid”.

[0085] See also Figure 6 , step S406 : forming a first SiP material layer 501 that at least fills the first trench 41 by epitaxial growth.

[0086] In the above embodiment, since the epitaxial growth rate of the selective epitaxial growth is affected by the local geometric shape, the reaction gas is not transmitted as sufficiently in the structure such as the first trench 41 as in the planar area. The first SiP material layer 501 is locally recessed in the first trench 41, and its top surface height is significantly lower than that of the adjacent planar area (the top surface of the first SiAs layer 31). The depth of the recess is positively correlated with the aspect ratio of the trench, and the edge presents a steep transition or a gentle slope.

[0087] See also Figure 7 , step S408 : continuing to epitaxially grow a second SiAs layer 32 on the top surface of the first SiP material layer 501 .

[0088] In the above embodiment, the arsenic (As) ion doping concentrations in the first SiAs layer 31 and the second SiAs layer 32 may be the same or different.

[0089] See also Figure 8 Step S410 : forming a plurality of second trenches 42 in the second SiAs layer 32 by photolithography. The second trenches 42 are arranged at intervals along the OY direction, penetrate the second SiAs layer 32 along the ZO direction, and extend to the first SiP material layer 501 .

[0090] Specifically, the width (dimension along the OY direction) of the second groove 42 gradually decreases in the ZO direction, and the cross-sectional shape on the ZOy plane is an “inverted trapezoid”.

[0091] In the embodiment mentioned in this application, the portion of the remaining first SiP material layer 501 penetrating the first SiAs layer 31 along the ZO direction is recorded as the first extension portion 51; the portion located on the top surface of the first SiAs layer 31 and extending along the OY direction is recorded as the second extension portion 52.

[0092] See also Figure 9 Step S412 : forming a second SiP material layer 502 that at least fills the second trench 42 by epitaxial growth.

[0093] For example, similar to the case of growing the first SiP material layer 501 , the top surface of the second SiP material layer 502 filling the second trench 42 is lower than the top surface of the second SiAs layer 32 , forming a recess 43 .

[0094] See also Figure 10 Step S418: First, a layer of SiAs material is grown to at least fill the recess 43. Chemical mechanical polishing (CMP) is then used to remove the SiAs material outside the recess 43 to form a SiAs cap layer 60. At this point, the portion of the remaining second SiP material layer 502 that extends through the second SiAs layer 32 along the ZO direction is referred to as the third extension 53. The portion located on the top surface of the second SiAs layer 32 and extending along the OY direction is referred to as the fourth extension 54.

[0095] For example, the phosphorus (P) ion doping concentrations in the second SiP material layer 502 and the first SiP material layer 501 can be the same or different; the arsenic (As) ion doping concentration in the SiAs cap layer 60 can be the same or different from the doping concentrations in the first SiAs layer 31 and the second SiAs layer 32. The first extension 51 and the third extension 53 respectively fill the first trench 41 and the second trench 42, and therefore have the same shape as the trenches.

[0096] In the above embodiment, different doping elements (such as As and P) introduce a gradient refractive index distribution to enhance the reflection / refraction effect of light at the interface between layers; the width (dimension along the OY direction) of the first extension portion 51 and the third extension portion 53 varies with the depth (dimension along the OZ direction), so that part of the incident light is reflected or refracted multiple times after being transmitted between layers to the side walls of the first extension portion 51 and the third extension portion 53, thereby extending the optical path of the light.

[0097] See also Figure 11 Step S420: After depositing an oxide layer 13 on the top surface of the SiAs cap layer 60 , an isolation trench 44 is formed by etching along the ZO direction through the oxide layer 13 , the fourth extension 54 , the second SiAs layer 32 , the second extension 52 and the first SiAs layer 31 .

[0098] The oxide layer 13 is made of silicon oxide (SiO2). The width of the isolation trench 44 gradually decreases along the ZO direction to ensure the photosensitive area of ​​the photodiode. At this point, the remaining second extension 52, fourth extension 54, first extension 51, and third extension 53 together form the SiP layer 50; the remaining first SiAs layer 31 and second SiAs layer 32 together form the SiAs stack 30.

[0099] See also Figure 12 Step S422: Spin-coat a liquid dielectric formed by mixing a solvent with a silicon oxide (SiO 2 ) dielectric into the isolation trench 44 to form an isolation material layer whose top surface is not lower than the top surface of the oxide layer 13 .

[0100] In the above embodiment, the deposition method can effectively control the area where the oxide layer 13 is formed, while the spin coating method can avoid the presence of voids in the isolation material layer within the isolation trench 44 due to insufficient filling. Because the isolation material layer and the oxide layer 13 are made of the same material, have a continuous structure, and function synergistically, both performing the isolation function, they can be considered a single silicon oxide layer, denoted as silicon oxide layer 701.

[0101] See also Figure 13 Step S424 : forming a first grid layer 14 , a second grid layer 15 , and a third grid layer 16 stacked along the OZ direction on the top surface of the silicon oxide layer 701 .

[0102] Among them, the material of the first grid layer 14 includes but is not limited to one or more of aluminum oxide (Al2O3), hafnium oxide (HfO2), hafnium oxynitride (HfON), zirconium oxide (ZrO2), tantalum oxide (Ta2O5), titanium oxide (TiO2) or strontium titanium oxide (SrTiO3); the material of the second grid layer 15 may include titanium nitride (TiN); the material of the third grid layer 16 may include but is not limited to metal materials such as cobalt (Co), nickel (Ni), titanium (Ti), tungsten (W), copper (Cu), and aluminum (Al).

[0103] Here, in this embodiment, the first grid layer 14 is hafnium oxide (HfO 2 ), the second grid layer 15 is titanium nitride (TiN), and the third grid layer 16 is aluminum (Al).

[0104] See also Figure 14 Step S426: Etching the first grid layer 14, the second grid layer 15, the third grid layer 16, and the silicon oxide layer 701 to obtain grids 80 and grooves 45 arranged alternately along the OY direction; the grooves 45 extend into the silicon oxide layer 701 along the ZO direction, and the remaining silicon oxide layer 701 is used to form the target isolation structure 70. The grids 80 and the target isolation structure 70 are arranged one to one.

[0105] In the above embodiment, the target isolation structure 70 includes an isolation column 71 whose top surface is flush with the photodiode, and a protrusion 72 whose top surface is higher than the top surface of the photodiode. The combination of the isolation column 71 and the trench isolation structure 20 isolates adjacent photodiodes from each other, effectively preventing optical / electrical crosstalk and improving the imaging quality of the back-illuminated image sensor. The protrusion 72 further increases the interception height of the grid 80 directly above it, enhancing the light-gathering capability of the grid 80. In addition, the portion covering the top surface of the photodiode can serve as an etch stop layer when etching the groove 45, preventing unnecessary damage to the photodiode below.

[0106] The back-illuminated image sensor structure obtained after the preparation method steps S20-S40 can be referred to Figure 14 Of course, in order to facilitate the understanding of this application, Figure 14 The above is only one example of a back-illuminated image sensor prepared by the preparation method in the embodiment of the present application. There may be other suitable examples of back-illuminated image sensors prepared by the preparation method, and the present application does not limit them here.

[0107] In some embodiments, after step S40 , the method further includes forming a filter in the groove 45 .

[0108] For example, see Figure 15The color filters include but are not limited to red filters, yellow filters, and blue filters, and the three filters are arranged adjacent to form a pixel group. The color filters maintain high transmittance in a specific wavelength band, wherein the red filter transmits red light waves, the yellow filter transmits yellow light waves, and the blue filter transmits blue light waves. In addition, the top of the filter is a rounded arc shape, which is conducive to the convergence of light. Other microlens structures can also be used to meet the focusing requirements. This application does not impose specific restrictions.

[0109] See also Figure 14 In some embodiments, the present application provides a back-illuminated image sensor, comprising a substrate 10, a grid 80, and photodiodes and a target isolation structure 70 located on a first surface of the substrate 10 and alternately arranged along an OY direction parallel to the first surface and extending toward the substrate;

[0110] The substrate 10 includes a plurality of trench isolation structures 20 extending from the first surface into the substrate 10 and arranged at intervals along the OY direction; the trench isolation structures 20 are arranged one-to-one with the target isolation structures 70 directly above them;

[0111] The photodiode includes a SiAs stack 30 arranged along the ZO direction, a SiAs cap layer 60, and a SiP layer 50 penetrating the SiAs stack 30 along the OY direction and the ZO direction;

[0112] The target isolation structure 70 includes a protrusion 72 that is higher than the top surface of the photodiode; the grid 80 and the protrusion 72 are fabricated in the same process step.

[0113] Furthermore, in some embodiments, the SiAs stack 30 includes a first SiAs layer 31 and a second SiAs layer 32 that are spaced apart and arranged in a direction away from the substrate;

[0114] The SiP layer 50 includes: a first extension portion 51, which penetrates the first SiAs layer 31 along the ZO direction; a second extension portion 52, which is located between the first SiAs layer 31 and the second SiAs layer 32; the top surface of the first extension portion 51 is located within the bottom surface of the second extension portion 52; a third extension portion 53, which penetrates the second SiAs layer 32 along the ZO direction and extends into the second extension portion 52 in the ZO direction; a fourth extension portion 54, which is located on the top surface of the second SiAs layer 32 and extends along the OY direction; wherein the top surface of the first extension portion 51 is located within the bottom surface of the second extension portion 52; and the top surface of the third extension portion 53 is located within the bottom surface of the fourth extension portion 54.

[0115] In the above embodiment, the alternating arrangement of photosensitive materials doped with different elements of arsenic (As) and phosphorus (P) can generate more photogenerated carriers. At the same time, the generation and separation process of carriers is optimized, which helps to maximize the conversion of incident light and reduce carrier recombination, thereby extending the carrier lifetime.

[0116] For further information, please refer to Figure 13 In some embodiments, the size of the first extension portion 51 along the OY direction gradually decreases in the OZ direction; the size of the third extension portion 53 along the OY direction gradually decreases in the ZO direction.

[0117] In the above embodiment, the first extension portion 51 and the third extension portion 53 with a gradient width can introduce multiple inclined refractive surfaces in the photodiode, which helps to guide light in multiple directions, generate more light refraction / reflection, increase the optical path and improve the photoelectric conversion efficiency.

[0118] In some embodiments, the first extension 51 and the second extension 52 are fabricated simultaneously in the same process step; the fourth extension 54 and the SiAs cap layer 60 are also fabricated simultaneously in the same process step. Because the pixel layout with alternating SiAs stacks 30 and SiP layers 50 is relatively complex, fabricating them simultaneously in the same process step can significantly optimize process integration and reduce fabrication complexity.

[0119] In some embodiments, the top surface of the photodiode is located within the bottom surface of the protrusion 72;

[0120] Backside illuminated image sensors also include:

[0121] The filter is located between adjacent grids 80 and extends along the ZO direction to be embedded in the protrusion 72 .

[0122] In the above embodiment, the protrusion 72 can prevent damage to the photodiode during the etching process of the grid, thereby ensuring the integrity and quality of the back-illuminated image sensor structure.

[0123] The present application also provides an electronic device, comprising a back-illuminated image sensor prepared by the preparation method described in any one of the above embodiments; or the back-illuminated image sensor described in the above embodiments.

[0124] The back-illuminated image sensor, its preparation method, and electronic device provided by this application have the following unexpected technical effects:

[0125] The use of multiple epitaxial growth technology on the top surface of the substrate to prepare photodiodes can effectively avoid unnecessary damage caused by traditional high-energy ion implantation, reduce dark current caused by substrate damage, and thus improve image clarity; in the photodiode, by alternating the arrangement of photosensitive layers doped with different VA group elements (SiAs stack, SiP layer and SiAs cap layer), a difference in refractive index distribution is formed, which promotes multiple reflections of incident light between layers, extends the optical path, and significantly improves the photoelectric conversion efficiency.

[0126] Furthermore, the target isolation structure and the trench isolation structure within the substrate together form a highly effective, fully physical isolation barrier, ensuring pixel structures are independent of each other, effectively preventing free electron penetration and light diffusion, and suppressing the negative impact of crosstalk on image clarity. Furthermore, the use of protrusions to increase the overall height of the upper grille enhances light convergence and reduces the possibility of light entering adjacent pixel structures, providing strong support for obtaining high-quality images.

[0127] In summary, by optimizing the preparation process and internal structure of back-illuminated image sensors, the overall performance of the device can be significantly improved, laying a solid technical foundation for the acquisition of high-quality images.

[0128] The technical features of the above-mentioned embodiments can be combined arbitrarily. In order to make the description concise, not all possible combinations of the technical features of the above-mentioned embodiments are described. However, as long as there is no contradiction in the combination of these technical features, they should be considered to be within the scope of this specification.

[0129] The above-described embodiments merely represent several implementation methods of the present application. While the descriptions are relatively specific and detailed, they should not be construed as limiting the scope of the patent application. It should be noted that a person of ordinary skill in the art may make various modifications and improvements without departing from the spirit of the present application, and these modifications and improvements fall within the scope of protection of the present application. Therefore, the scope of protection of the present patent application shall be determined by the appended claims.

Claims

1. A back-illuminated image sensor, characterized in that: The device comprises a substrate, a grid, and a photodiode and a target isolation structure located on a first surface of the substrate and alternately arranged along a first direction parallel to the first surface and extending toward the substrate; The substrate includes a plurality of trench isolation structures extending into the substrate through the first surface and spaced apart along the first direction; the trench isolation structures are arranged one-to-one with the target isolation structures directly above them; The photodiode includes a SiAs stack arranged in a direction away from the substrate, a SiAs cap layer, and a SiP layer penetrating the SiAs stack along the first direction and towards the substrate; The target isolation structure includes a protrusion having a top surface higher than a top surface of the photodiode; The protrusion and the grille are prepared at the same time in the same process step.

2. The back-illuminated image sensor according to claim 1, wherein: The SiAs stack includes a first SiAs layer and a second SiAs layer that are spaced apart and arranged in a direction away from the substrate.

3. The back-illuminated image sensor according to claim 2, wherein: The SiP layer includes: a first extension portion, extending through the first SiAs layer in a direction toward the substrate; a second extension portion, located between the first SiAs layer and the second SiAs layer; a third extension portion, penetrating the second SiAs layer in a direction toward the substrate and extending into the second extension portion in a direction toward the substrate; a fourth extension portion, located on a top surface of the second SiAs layer and extending along the first direction; The top surface of the first extension portion is located inside the bottom surface of the second extension portion; and the top surface of the third extension portion is located inside the bottom surface of the fourth extension portion.

4. The back-illuminated image sensor according to claim 3, wherein: The dimension of the first extension portion along the first direction gradually decreases in a direction away from the substrate; the dimension of the third extension portion along the first direction gradually decreases in a direction toward the substrate.

5. The back-illuminated image sensor according to claim 3, wherein: Includes at least one of the following features; The first extension portion and the second extension portion are prepared at the same time in the same process step; The fourth extension portion and the SiAs cap layer are prepared at the same time in the same process step.

6. The back-illuminated image sensor according to claim 1, wherein: The top surface of the photodiode is located within the bottom surface of the protrusion; Backside illuminated image sensors also include: The filter is located between adjacent grids and extends in a direction toward the substrate until it is embedded in the protrusion.

7. A method for preparing a back-illuminated image sensor, characterized in that: include: Providing a substrate, wherein the substrate includes a plurality of trench isolation structures extending into the substrate through a first surface and arranged at intervals along a first direction parallel to the first surface; forming photodiodes and target isolation structures on the first surface, which are alternately arranged along the first direction and extend toward the substrate; The photodiode includes a SiAs stack arranged in a direction away from the substrate, a SiAs cap layer, and a SiP layer penetrating the SiAs stack in the first direction and in a direction toward the substrate; the target isolation structure includes a protrusion with a top surface higher than a top surface of the photodiode; The grid and the protrusion are prepared at the same time in the same process step.

8. The preparation method according to claim 7, characterized in that The SiAs stack comprises a first SiAs layer and a second SiAs layer which are spaced apart in a direction away from the substrate; The SiP layer includes: a first extension portion, extending through the first SiAs layer in a direction toward the substrate; a second extension portion, located between the first SiAs layer and the second SiAs layer; a third extension portion, penetrating the second SiAs layer in a direction toward the substrate and extending into the second extension portion in a direction toward the substrate; a fourth extension portion, located on a top surface of the second SiAs layer and extending along the first direction; The top surface of the first extension portion is located inside the bottom surface of the second extension portion; and the top surface of the third extension portion is located inside the bottom surface of the fourth extension portion.

9. The preparation method according to claim 8, characterized in that Includes at least one of the following features; The first extension portion and the second extension portion are prepared at the same time in the same process step; The fourth extension portion and the SiAs cap layer are prepared at the same time in the same process step; The dimension of the first extension portion along the first direction gradually decreases in a direction away from the substrate; the dimension of the third extension portion along the first direction gradually decreases in a direction toward the substrate.

10. An electronic device, characterized in that: include: The back-illuminated image sensor according to any one of claims 1 to 6; or A back-illuminated image sensor prepared by the preparation method according to any one of claims 7 to 9.

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