Preparation method of doped polycrystalline silicon, silicon wafer and application of silicon wafer

Abstract

The invention discloses a preparation method of doped polycrystalline silicon, a silicon wafer and application of the silicon wafer, and the preparation method comprises the following steps: sequentially preparing a doped source layer and an amorphous silicon layer by adopting a PECVD (Plasma Enhanced Chemical Vapor Deposition) method, and repeating the preparation steps of the doped source layer and the amorphous silicon layer to form a doped amorphous silicon composite film layer formed by stacking the doped source layer and the amorphous silicon layer. According to the preparation method, the doped amorphous silicon composite film layer which is formed by stacking the doped source layer and the amorphous silicon layer and is good in inter-chip uniformity and high in doping concentration is prepared firstly, and then the doped polycrystalline silicon which is good in inter-chip uniformity and high in doping concentration can be obtained after annealing treatment. The obtained silicon wafer can be widely used for preparing a TOPCon battery, an IBC battery or a TBC battery, and the preparation method also has the advantages of short process time, convenience in operation, small damage to a tunneling layer, good inter-wafer uniformity, high doping concentration, convenience in mass production and the like, and is high in use value and good in application prospect.

Description

Technical Field

[0001] The present invention belongs to the technical field of solar cell preparation, and relates to a preparation method of doped polysilicon, a silicon wafer and their applications. Background Art

[0002] In the production process of Poly Passivated solar cells (such as TOPcon cells), in order to achieve an efficient passivation contact structure, it is usually necessary to prepare boron-doped polysilicon (p-poly-Si) or phosphorus-doped polysilicon (n-poly-Si) on the silicon substrate, which are respectively used for hole selective contact and electron selective contact, thereby facilitating the improvement of the electron and hole separation efficiency, which can not only reduce the metal contact recombination current, but also increase the open circuit voltage and short circuit current of the battery, and ultimately contribute to the improvement of the battery conversion efficiency.

[0003] Taking boron-doped polysilicon (p-poly-Si) as an example, the existing preparation methods mainly include the LPCVD method and the PECVD method. Among them, the existing process for preparing p-poly-Si based on the LPCVD method has problems such as long process time and slow poly film formation speed. Moreover, during the boron diffusion process, there are also deficiencies such as relatively high crystallinity of the poly grown by LPCVD and defects such as relatively large damage to the tunneling layer caused thereby. In addition, in the process of preparing boron-doped polysilicon (p-poly-Si) by the traditional PECVD method, due to the easy decomposition property of the boron source, problems such as poor uniformity of P-poly silicon and low doping concentration at the furnace tail are likely to occur, and high-frequency phenomena are also likely to occur, ultimately resulting in poor deposition effect of P-poly silicon. Further, researchers have proposed a new method for depositing P-poly silicon, which improves the traditional gas inlet mode. By accompanying the gas compensation of B2H6 during the deposition process, the uniform distribution of B2H6 gas at the furnace mouth and the furnace tail can be achieved, ultimately improving the deposition uniformity and avoiding high-frequency phenomena. However, in the above-mentioned method for depositing P-poly silicon proposed based on the PECVD method, there are still the following defects: (a) greatly affected by the inherent properties of the boron source, there are still problems such as poor uniformity between the prepared P-poly wafers; (b) the thickness of the prepared intrinsic poly silicon is relatively thin, resulting in that boron doping easily damages the tunneling oxide layer and causes internal diffusion, easily causing damage to the tunneling oxide layer, increasing the substrate recombination loss, which is not conducive to improving the efficiency of the battery. At the same time, due to the relatively thin thickness of the intrinsic poly silicon, it is also difficult to improve the insulation performance of the graphite boat, resulting in problems such as the need to replace the graphite boat or frequently clean the graphite boat during the deposition process, which is difficult to improve the production efficiency, and even difficult to achieve mass production, and is not conducive to improving the utilization rate of production capacity: (c) large raw material consumption, easily causing too high production costs, and it is difficult to effectively increase the boron doping concentration, or more B2H6 needs to be used, resulting in a low doping concentration, which is not only not conducive to improving the efficiency of the battery. Therefore, how to obtain a preparation method of doped polysilicon with short process time, convenient operation, small damage to the tunneling layer, good uniformity between wafers, high doping concentration and easy mass production has an important role in promoting the wide use of solar cells. Summary of the Invention

[0004] The technical problem to be solved by the present invention is to overcome the deficiencies of the prior art and provide a preparation method of doped polysilicon with short process time, convenient operation, small damage to the tunneling layer, good uniformity between wafers, high doping concentration and easy mass production. The present invention also provides a silicon wafer and its application.

[0005] To solve the above technical problems, the present invention adopts the following technical solutions:

[0006] A preparation method of doped polysilicon, the preparation method comprising: sequentially preparing a doped source layer and an amorphous silicon layer by PECVD method, and repeating the preparation steps of the doped source layer and the amorphous silicon layer to form a doped amorphous silicon composite film layer stacked by the doped source layer and the amorphous silicon layer.

[0007] For the above preparation method of doped polysilicon, further improved, the preparation steps of the doped source layer and the amorphous silicon layer are repeated 3 to 30 times; before each preparation of the doped source layer and the amorphous silicon layer, it further includes: performing a vacuum pumping treatment on the equipment.

[0008] For the above preparation method of doped polysilicon, further improved, the preparation steps of the doped source layer and the amorphous silicon layer are repeated 8 to 20 times.

[0009] For the above preparation method of doped polysilicon, further improved, the doping source used in the preparation process of the doped source layer is a boron source or a phosphorus source, and the carrier gas is H2 and / or Ar; the boron source includes at least one of borane, boron trifluoride, and trimethylboron; the phosphorus source includes at least one of phosphine, trimethylphosphine, and silane phosphide; the process parameters used in the preparation process of the doped source layer are: the flow rate of the doping source is 1000 sccm to 5000 sccm, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 10 s to 100 s.

[0010] For the above preparation method of doped polysilicon, further improved, the silicon source used in the preparation process of the amorphous silicon layer is silane, and the carrier gas is H2 and / or Ar; the process parameters used in the preparation process of the amorphous silicon layer are: the flow rate of silane is 2000 sccm to 3500 sccm, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the pressure is 400 Pa to 460 Pa, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 30 s to 120 s.

[0011] For the above method for preparing doped polysilicon, further improved, a doped amorphous silicon composite film layer is prepared on an intrinsic silicon layer; the thickness of the intrinsic silicon layer is 50 nm to 250 nm; the intrinsic silicon layer is prepared by PECVD; the process parameters used in the preparation process of the intrinsic silicon layer are: the silicon source is silane, the flow rate of silane is 2000 sccm to 3500 sccm, the carrier gas is H2 and / or Ar, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the pressure is 200 Pa to 460 Pa, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 600 s to 3000 s.

[0012] For the above method for preparing doped polysilicon, further improved, an intrinsic silicon layer is prepared on a tunneling oxide layer; the tunneling oxide layer is prepared by PECVD; the process parameters used in the preparation process of the tunneling oxide layer are: the reaction gas is nitrous oxide, the flow rate of nitrous oxide is 8000 sccm to 15000 sccm, the pressure is 100 Pa to 180 Pa, the power is 10000 W to 18000 W, the duty cycle is 1 / 100 to 1 / 240, 40 kHz to 100 kHz, and the time is 80 s to 180 s.

[0013] For the above method for preparing doped polysilicon, further improved, after the doped amorphous silicon composite film layer is prepared, the following treatment is further included: a silicon oxide layer is prepared on the doped amorphous silicon composite film layer by PECVD; the reaction gases used in the preparation process of the silicon oxide layer are silane and nitrous oxide.

[0014] For the above method for preparing doped polysilicon, further improved, after the silicon oxide layer is prepared, the following treatment is further included: annealing the doped amorphous silicon composite film layer with a silicon oxide layer on the surface to obtain doped polysilicon.

[0015] As a general technical concept, the present invention further provides a silicon wafer, on the surface of which doped polysilicon is deposited; the doped polysilicon is prepared by the above preparation method.

[0016] As a general technical concept, the present invention further provides an application of the above silicon wafer, and the silicon wafer is used to prepare a TOPCon cell, an IBC cell or a TBC cell.

[0017] Compared with the prior art, the advantages of the present invention are:

[0018] (1) In view of the deficiencies in the existing preparation methods, such as poor inter-chip uniformity and low doping concentration, the present invention creatively proposes a method for preparing doped polysilicon. The PECVD method is used to sequentially prepare a doping source layer and an amorphous silicon layer, and the preparation steps of the doping source layer and the amorphous silicon layer are repeated to form a doped amorphous silicon composite film layer stacked by the doping source layer and the amorphous silicon layer. Thus, a doped amorphous silicon layer with good inter-chip uniformity and high doping concentration is prepared. After annealing treatment, a doped polysilicon with good inter-chip uniformity and high doping concentration can be obtained. Compared with the conventional deposition process, in the present invention, by using the PECVD method to prepare a doped amorphous silicon composite film layer stacked by the doping source layer and the amorphous silicon layer, the following advantages are achieved: (a) By preparing the doping source layer and the amorphous silicon layer multiple times, not only can the tunneling oxide layer be better protected by the amorphous silicon layer, with less damage to the tunneling oxide layer. On the one hand, it can reduce the recombination loss of the substrate, which is beneficial to improving the electrical performance of the battery. On the other hand, it can also improve the insulation performance of the graphite boat, which is beneficial to increasing the service life (number of uses) of the graphite boat. Moreover, under the blocking effect of the amorphous silicon layer, it is also beneficial to increase the shallow surface layer concentration and obtain a higher doping concentration; (b) By controlling the number of cycles, the adverse effects that the doping source may bring can be eliminated to the greatest extent, which is more conducive to adjusting the doping concentration. Thus, the doping uniformity can be improved, facilitating industrial production.

[0019] (2) In the present invention, a doped amorphous silicon composite film layer is prepared on the intrinsic silicon layer, where the thickness of the intrinsic silicon layer ≥ 100 nm. As a high-thickness protective layer, the intrinsic silicon layer, in conjunction with the amorphous silicon layer, can better protect the tunneling oxide layer and can more significantly improve the insulation of the graphite boat, solving the problem that the graphite boat needs to be taken offline for cleaning under the premise of fewer uses in the traditional deposition process. Description of the Drawings

[0020] To make the objectives, technical solutions, and advantages of the embodiments of the present invention clearer, the technical solutions in the embodiments of the present invention will be clearly and completely described below with reference to the drawings in the embodiments of the present invention.

[0021] Figure 1 It is the process flow chart of the preparation of doped polysilicon in Embodiment 1 of the present invention.

[0022] Figure 2 It is the diagram showing the influence of different cycle numbers on the insulation of the graphite boat in Embodiment 1 of the present invention.

[0023] Figure 3 It is the diagram showing the influence of different cycle numbers on the insulation of the graphite boat in Comparative Example 1.

[0024] Figure 4This is the graph of the change in boron doping concentration in the doped polysilicon prepared in Example 1 and Comparative Example 1 of the present invention.

[0025] Figure 5 This is the graph of the influence of different cycle numbers on the boron doping concentration in the doped polysilicon in Example 2 of the present invention. Detailed implementation manners

[0026] The present invention will be further described below in conjunction with the accompanying drawings of the specification and specific preferred embodiments, but the protection scope of the present invention is not limited thereby. Obviously, the described embodiments are only a part of the embodiments of the present invention, rather than all embodiments. All other embodiments obtained by those of ordinary skill in the art based on the embodiments of the present invention without creative efforts shall fall within the protection scope of the present invention.

[0027] The "range" disclosed in the present invention can be defined in the form of a lower limit and an upper limit. A given range is defined by selecting a lower limit and an upper limit, and the selected lower limit and upper limit define the boundary of a specific range. The range defined in this way can include or not include the end values. Any one of the end values can be independently included or not included, and can be combined arbitrarily, that is, any lower limit can be combined with any upper limit to form a range. For example, if ranges of 60 to 120 and 80 to 110 are listed for a specific parameter, ranges of 60 to 110 and 80 to 120 are also contemplated. In addition, if the minimum range values of 1 and 2 are listed, and if the maximum range values of 3, 4, and 5 are also listed, the following ranges are all contemplated: 1 to 3, 1 to 4, 1 to 5, 2 to 3, 2 to 4, and 2 to 5. In the present invention, unless otherwise specified, the numerical range "a to b" represents an abbreviated representation of any real number combination between a and b, where a and b are both real numbers. For example, the numerical range "0 to 5" means that all real numbers between "0 to 5" have been fully listed herein, and "0 to 5" is only an abbreviated representation of these numerical combinations.

[0028] In the present invention, the terms "a plurality of", "a variety of", etc., unless otherwise specified, refer to a quantity greater than 2 or equal to 2. For example, "one or more" means one or greater than or equal to two.

[0029] If there is no special description, all embodiments and optional embodiments of the present invention can be combined with each other to form a new technical solution.

[0030] References to "embodiments" in this specification mean that the particular features, structures, or characteristics described in connection with the embodiments can be included in at least one embodiment or implementation of the present invention. The phrase may not necessarily refer to the same embodiment at every occurrence in the specification, nor is it an independent or alternative embodiment mutually exclusive with other embodiments. Those skilled in the art will explicitly and implicitly understand that the embodiments described herein can be combined with other embodiments. Similar understanding applies to "implementations" referred to in this specification.

[0031] Those skilled in the art will understand that in the methods of each embodiment or implementation, the written order of each step does not mean a strict execution order that constitutes any limitation on the implementation process, and the detailed execution order of each step should be determined by its function and possible internal logic. Without special instructions, all steps of the present invention can be carried out sequentially or randomly, preferably sequentially. For example, the method includes steps (a) and (b), which means that the method may include steps (a) and (b) carried out sequentially, or may also include steps (b) and (a) carried out sequentially. For example, it is mentioned that the method may further include step (c), which means that step (c) can be added to the method in any order. For example, the method may include steps (a), (b), and (c), or may also include steps (a), (c), and (b), or may include steps (c), (a), and (b), etc.

[0032] In the present invention, unless otherwise specified, A (such as B) means that B is a non-limiting example of A, and it can be understood that A is not limited to B.

[0033] In the present invention, "optionally", "optional", "option" mean that it can be either present or absent, that is, it refers to any one of two alternative options of "present" or "absent". If "optional" appears multiple times in a technical solution, unless otherwise specified and there are no contradictions or mutual restrictions, each "optional" is independent of each other.

[0034] In a first aspect, aiming at the deficiencies such as poor inter-chip uniformity and low doping concentration in the existing preparation methods, the present invention creatively proposes a preparation method of doped polysilicon. The doped source layer and the amorphous silicon layer are sequentially prepared by the PECVD method, and the preparation steps of the doped source layer and the amorphous silicon layer are repeated to form a doped amorphous silicon composite film layer stacked by the doped source layer and the amorphous silicon layer. In the present invention, by cyclically preparing the doped source layer and the amorphous silicon layer, a doped amorphous silicon layer with good inter-chip uniformity and high doping concentration can be prepared. After annealing treatment, the doped amorphous silicon layer can obtain doped polysilicon with good inter-chip uniformity and high doping concentration. Compared with the conventional deposition process, the present invention has the following advantages in preparing a doped amorphous silicon composite film layer stacked by the doped source layer and the amorphous silicon layer by the PECVD method: (a) By preparing the doped source layer and the amorphous silicon layer multiple times, not only can the tunneling oxide layer be better protected by the amorphous silicon layer, and the damage to the tunneling oxide layer is smaller. On the one hand, it can reduce the recombination loss of the substrate, which is beneficial to improving the electrical performance of the battery. On the other hand, it can also improve the insulation performance of the graphite boat, which is beneficial to increasing the service life (number of uses) of the graphite boat. Moreover, under the blocking effect of the amorphous silicon layer, it is also beneficial to increase the concentration of the shallow surface layer, and a higher doping concentration can be obtained; (b) By controlling the number of cycles, the adverse effects that the doped source may bring can be eliminated to the greatest extent, so as to be more conducive to adjusting the doping concentration. Thereby, the doping uniformity can be improved, which is convenient for industrial production.

[0035] In some embodiments, the preparation steps of the doped source layer and the amorphous silicon layer are repeated 3 to 30 times. As an example, the number of repetitions of the preparation steps of the doped source layer and the amorphous silicon layer can be 3 times, 5 times, 7 times, 9 times, 11 times, 13 times, 15 times, 16 times, 18 times, 20 times, 23 times, 24 times, 26 times, 27 times, 28 times, 29 times, 30 times, or can also be within the range formed by any two of the above point values as the end values. Preferably, the preparation steps of the doped source layer and the amorphous silicon layer are repeated 8 to 20 times.

[0036] In some embodiments, before each preparation of the doped source layer and the amorphous silicon layer, it further includes: performing a vacuum pumping treatment on the equipment, specifically pumping to a low pressure.

[0037] In some embodiments, the doped source used in the preparation process of the doped source layer is a boron source or a phosphorus source, and the carrier gas is H2 and / or Ar.

[0038] In some embodiments, the boron source includes at least one of borane, boron trifluoride, and trimethylboron.

[0039] In some embodiments, the phosphorus source includes at least one of phosphine, trimethylphosphine, and silane phosphide.

[0040] In some embodiments, the process parameters used in the preparation of the doped source layer are as follows: the flow rate of the doped source is 1000 sccm to 5000 sccm, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 10 s to 100 s.

[0041] In some embodiments, the silicon source used in the preparation of the amorphous silicon layer is silane, and the carrier gas is H2 and / or Ar.

[0042] In some embodiments, the process parameters used in the preparation of the amorphous silicon layer are as follows: the flow rate of silane is 2000 sccm to 3500 sccm, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the pressure is 400 Pa to 460 Pa, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 30 s to 120 s.

[0043] In some embodiments, a doped amorphous silicon composite film layer is prepared on the intrinsic silicon layer.

[0044] In some embodiments, the thickness of the intrinsic silicon layer is 50 nm to 250 nm.

[0045] In some embodiments, the intrinsic silicon layer is prepared by PECVD method.

[0046] In some embodiments, the process parameters used in the preparation of the intrinsic silicon layer are as follows: the silicon source is silane, the flow rate of silane is 2000 sccm to 3500 sccm, the carrier gas is H2 and / or Ar, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the pressure is 200 Pa to 460 Pa, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 600 s to 3000 s.

[0047] In some embodiments, an intrinsic silicon layer is prepared on the tunneling oxide layer.

[0048] In some embodiments, the tunneling oxide layer is prepared by PECVD method.

[0049] In some embodiments, the process parameters used in the preparation of the tunneling oxide layer are as follows: the reaction gas is nitrous oxide, the flow rate of nitrous oxide is 8000 sccm to 15000 sccm, the pressure is 100 Pa to 180 Pa, the power is 10000 W to 18000 W, the duty cycle is 1 / 100 to 1 / 240, 40 kHz to 100 kHz, and the time is 80 s to 180 s.

[0050] In some embodiments, after preparing the doped amorphous silicon composite film layer, the following treatment is further included: preparing a silicon oxide layer on the doped amorphous silicon composite film layer by PECVD method.

[0051] In some embodiments, the reaction gases used in the preparation process of the silicon oxide layer are silane and nitrous oxide.

[0052] In some embodiments, after preparing the silicon oxide layer, the following treatment is further included: annealing the doped amorphous silicon composite film layer with a silicon oxide layer prepared on its surface to obtain doped polycrystalline silicon.

[0053] In a second aspect, the present invention also provides a silicon wafer, on the surface of which doped polycrystalline silicon is deposited, and the doped polycrystalline silicon is obtained by the preparation method of the first aspect.

[0054] In a third aspect, the present invention also provides an application of the silicon wafer of the second aspect, and the silicon wafer is used to prepare a TOPCon cell, an IBC cell or a TBC cell.

[0055] In the following embodiments of the present invention, unless otherwise specified, the materials and instruments used are commercially available, the equipment used is conventional equipment, and the obtained data are the average values of more than three repeated experiments.

[0056] Example 1

[0057] A preparation method of doped polycrystalline silicon, specifically, boron-doped polycrystalline silicon is prepared by PECVD deposition using boron trifluoride as a doping source, and its preparation process diagram is as Figure 1 shown, including the following steps:

[0058] (a) The surface of the silicon wafer is polished with KOH solution to form a polished surface on the silicon wafer surface.

[0059] (b) The treated silicon wafer is placed in a graphite boat, and the boat is loaded into the furnace tube of the PECVD equipment.

[0060] (c) The furnace tube is heated to 480 °C, held for 600 s, evacuated to a low pressure, and kept at a constant temperature for 600 s to provide a constant temperature and stable pressure for subsequent deposition.

[0061] (d) 12000 sccm of nitrous oxide is introduced into the furnace tube for constant pressure of 150 Pa. After constant pressure, 100 s of discharge deposition is carried out, the power is 12000 W, the pulse on / off is 2 ms / 240 ms (i.e., the duty cycle is 1 / 120), and the power supply frequency is 40 kHz. During this process, a tunneling oxide layer is formed, specifically, a silicon oxide layer is deposited on the silicon wafer.

[0062] (e) After the deposition of the tunneling oxide layer is completed, the furnace tube is evacuated to a low pressure (1 - 5 Pa).

[0063] (f) Introduce 2500 sccm of SiH4 and 12000 sccm of H2 into the furnace tube, maintain a constant pressure of 400 Pa, then perform Plasma discharge for 1600 s with a power of 7200 W, a pulse on / off of 6 ms / 60 ms (i.e., a duty cycle of 1 / 10), and a power supply frequency of 40 kHz. During this process, an intrinsic silicon layer is formed, specifically, an intrinsic silicon layer with a thickness of 100 nm is deposited on the silicon oxide layer, which is a high-thickness film layer.

[0064] (g) After the deposition of the intrinsic silicon layer is completed, evacuate the furnace tube to a low pressure (1 - 5 Pa).

[0065] (h) Introduce 2000 sccm of BF3 gas and 12000 sccm of H2 into the furnace tube for Plasma discharge for 30 s with a power of 6000 W, a pulse on / off of 6 ms / 60 ms (i.e., a duty cycle of 1 / 10), and a power supply frequency of 40 kHz. During this process, a boron-doped source layer is formed, specifically, a boron-doped source layer is deposited on the intrinsic silicon layer with a thickness of 100 nm.

[0066] (i) After the deposition of the boron-doped source layer is completed, evacuate the furnace tube to a low pressure (1 - 5 Pa).

[0067] (j) After the deposition of the boron-doped source layer is completed, maintain a constant pressure, introduce 2500 sccm of SiH4 and 12000 sccm of H2, maintain a constant pressure of 400 Pa, then perform Plasma discharge for 100 s with a power of 7200 W, a pulse on / off of 6 ms / 60 ms (i.e., a duty cycle of 1 / 10), and a power supply frequency of 40 kHz. During this process, an amorphous silicon layer is formed, specifically, an amorphous silicon layer is deposited on the boron-doped source layer.

[0068] (k) After the deposition of the amorphous silicon layer is completed, evacuate the furnace tube to a low pressure (1 - 5 Pa).

[0069] (l) On this basis, use the process from (h) to (k) for a cyclic process, cycle 10 times, that is, repeat the preparation steps of the boron-doped source layer and the amorphous silicon layer 10 times, and deposit a doped amorphous silicon composite film layer stacked by the doped source layer and the amorphous silicon layer on the intrinsic silicon layer with a thickness of 100 nm.

[0070] (m) After the deposition of the doped amorphous silicon composite film layer is completed, evacuate the furnace tube to a low pressure (1 - 5 Pa).

[0071] (n) Introduce silane and nitrous oxide into the furnace tube, maintain a constant pressure of 400 Pa, then perform Plasma discharge to deposit a silicon oxide layer on the doped amorphous silicon composite film layer as a mask layer.

[0072] (o) After the deposition is completed, the silicon wafer is sent into an annealing furnace for annealing treatment to convert amorphous silicon into polycrystalline silicon, and at the same time, boron atoms are effectively activated in the polycrystalline silicon to obtain doped polycrystalline silicon.

[0073] After testing, in this embodiment, the effective doping concentration of boron element in the prepared doped polycrystalline silicon is 7E+19 atoms / cm 3 , and the non-uniformity between wafers is 5%; after being used 10 times, the resistance value of the graphite boat is still as high as more than 25 MΩ (as Figure 2 shown).

[0074] The silicon wafer with doped polycrystalline silicon deposited on its surface prepared in the above embodiment can be used to prepare TOPCon cells, or can be used to prepare IBC cells and TBC cells.

[0075] Comparative Example 1

[0076] A method for preparing doped polycrystalline silicon, except that the preparation method of the boron-doped amorphous silicon layer is different from that of Example 2, and other conditions are the same, including the following steps:

[0077] (a) The surface of the silicon wafer is polished with KOH to form a polished surface on the silicon wafer surface.

[0078] (b) The processed silicon wafer is placed in a graphite boat, and the boat is loaded into the furnace tube of the PECVD equipment.

[0079] (c) The furnace tube is heated to 480 °C, held for 600 s to evacuate to a low pressure, and kept at a constant temperature for 600 s to provide a constant temperature and stable pressure for deposition.

[0080] (d) 12000 sccm of nitrous oxide is introduced for a constant pressure of 150 Pa. After the constant pressure, a 100-s discharge deposition is carried out, the power is 12000 W, the pulse on / off is 2 ms / 240 ms (i.e., the duty cycle is 1 / 120), and the power supply frequency is 40 kHz. During this process, a tunneling oxide layer is formed.

[0081] (e) After the deposition is completed, evacuation is carried out.

[0082] (f) 2500 sccm of SiH4, 12000 sccm of H2, and 800 sccm of BF3 are introduced into the furnace tube, the pressure is kept constant at 400 Pa, and then Plasma discharge is carried out for 1600 s, the power is 7200 W, the pulse on / off is 6 ms / 60 ms (i.e., the duty cycle is 1 / 10), and the power supply frequency is 40 kHz. A boron-doped amorphous silicon layer is deposited on the tunneling oxide layer.

[0083] (g) Silane and nitrous oxide are introduced into the furnace tube, and the pressure is kept constant at 400 Pa. Then, Plasma discharge is carried out to deposit a silicon oxide layer on the boron-doped amorphous silicon layer as a mask layer.

[0084] (h) After the deposition is completed, the silicon wafer is sent into an annealing process for annealing treatment to transform the amorphous silicon into polycrystalline silicon, and at the same time, the boron atoms are effectively activated in the polycrystalline silicon to obtain doped polycrystalline silicon.

[0085] After testing, in Comparative Example 1, the doping concentration of boron element in the prepared doped polycrystalline silicon is 5E+19 atoms / cm 3 , and the non-uniformity between wafers is 8%; after being used 10 times, the resistance value of the graphite boat is 0 (as Figure 3 shown).

[0086] Figure 4 This is a graph showing the change of boron doping concentration in the doped polycrystalline silicon prepared in Example 1 and Comparative Example 1 of the present invention. From Figure 4 it can be seen that in Comparative Example 1, a significant boron damage tunneling layer phenomenon occurs at a junction depth of 110 nm, and a large amount of boron diffuses inward to the silicon substrate; while in Example 1, at a junction depth of 130 nm, the damage to the tunneling layer is small and the inward diffusion amount is low, which can protect the interface passivation effect of the tunneling layer.

[0087] Example 2

[0088] Investigate the influence of different cycle numbers on the interface doping concentration. Except for the different cycle numbers, other conditions are the same as those in Example 2.

[0089] Figure 5 This is a graph showing the influence of different cycle number conditions on the boron doping concentration in the doped polycrystalline silicon in Example 2 of the present invention. Figure 5 In it, cycle3, cycle6, cycle9, cycle15 represent 3 times, 6 times, 9 times, and 15 times of cycling in sequence. From Figure 5 it can be seen that by changing the cycle number, the adjustment of the overall thickness and boron doping concentration of the amorphous silicon layer can be achieved, and both the thickness and concentration of the amorphous silicon layer increase with the increase of the cycle number; in addition, in the preparation method of the present invention, the cyclic deposition preparation method simplifies the process adjustment difficulty.

[0090] Example 3

[0091] Investigate the influence of different thicknesses of the intrinsic silicon layer on the insulation of the graphite boat. Except for the different intrinsic silicon layers, other conditions are the same as those in Example 2.

[0092] As can be seen from Table 1, when the graphite boat is used 10 times without the base intrinsic layer, the resistance value is only 1.4 MΩ. As the thickness of the base intrinsic layer increases, the number of times the graphite boat can be used also increases. In particular, when the thickness of the intrinsic layer increases to 100 nm and the graphite boat is used 30 times, the resistance value of the graphite boat can remain at ∞, approaching infinity, which belongs to an insulating state.

[0093] Table 1 Resistance values of the graphite boat corresponding to doped polysilicon prepared under different thickness conditions of the intrinsic silicon layer

[0094] Thickness of intrinsic silicon layer (nm) Resistance value of graphite boat (MΩ) Remarks 0 1.4 The graphite boat is used 10 times 50 26 The graphite boat is used 15 times 100 ∞ The graphite boat is used 15 times 150 ∞ The graphite boat is used 30 times 200 ∞ The graphite boat is used 30 times 300 ∞ The graphite boat is used 30 times

[0095] As can be seen from the above results, compared with the conventional deposition process, in the method for preparing doped polysilicon of the present invention, the PECVD method is used to sequentially prepare the doped source layer and the amorphous silicon layer, and the preparation steps of the doped source layer and the amorphous silicon layer are repeated, so as to form a doped amorphous silicon composite film layer with good inter-chip uniformity and high doping concentration, which is stacked by the doped source layer and the amorphous silicon layer. After the doped amorphous silicon layer is annealed, doped polysilicon with good inter-chip uniformity and high doping concentration can be obtained, which has the following advantages: (a) By preparing the doped source layer and the amorphous silicon layer multiple times, not only can the tunneling oxide layer be better protected by the amorphous silicon layer, and the damage to the tunneling oxide layer is smaller. On the one hand, the recombination loss of the substrate can be reduced, which is beneficial to improving the electrical performance of the battery. On the other hand, the insulation performance of the graphite boat can also be improved, which is beneficial to increasing the service life (number of uses) of the graphite boat. Moreover, under the blocking effect of the amorphous silicon layer, it is also beneficial to increase the concentration of the shallow surface layer, and a higher doping concentration can be obtained; (b) By controlling the number of cycles, the adverse effects that the doped source may bring can be eliminated to the greatest extent, so as to more effectively adjust the doping concentration, thereby improving the doping uniformity and facilitating industrial production. At the same time, in the present invention, the thickness of the intrinsic silicon layer is optimized, so that under the combined action of the intrinsic silicon layer and the amorphous silicon layer, the tunneling oxide layer can be better protected, and the insulation of the graphite boat can be more significantly improved, solving the problem that the graphite boat needs to be taken offline for cleaning under the premise of fewer use times in the traditional deposition process. The method for preparing doped polysilicon of the present invention has the advantages of short process time, convenient operation, small damage to the tunneling layer, good inter-chip uniformity, high doping concentration, and easy mass production. When doped polysilicon is deposited on the silicon wafer surface by the method of the present invention, the obtained silicon wafer can be widely used in the preparation of TOPCon batteries, IBC batteries or TBC batteries, with high use value and good application prospects.

[0096] The above embodiments are only the preferred embodiments of the present invention, and the protection scope of the present invention is not limited to the above embodiments. All technical solutions falling within the idea of the present invention belong to the protection scope of the present invention. It should be noted that for those of ordinary skill in the art, improvements and refinements made without departing from the principle of the present invention should also be regarded as within the protection scope of the present invention.

Claims

1. A preparation method of doped polysilicon, characterized in that, The preparation method includes: sequentially preparing a doped source layer and an amorphous silicon layer by PECVD method, and repeating the preparation steps of the doped source layer and the amorphous silicon layer to form a doped amorphous silicon composite film layer stacked by the doped source layer and the amorphous silicon layer.

2. The preparation method of doped polysilicon according to claim 1, characterized in that, The preparation steps of the doped source layer and the amorphous silicon layer are repeated 3 to 30 times; before each preparation of the doped source layer and the amorphous silicon layer, it further includes: performing a vacuum pumping treatment on the equipment.

3. The preparation method of the doped polysilicon according to claim 2, characterized in that, The preparation steps of the doped source layer and the amorphous silicon layer are repeated 8 to 20 times.

4. The preparation method of the doped polysilicon according to claim 3, wherein, In the preparation process of the doped source layer, the doped source used is a boron source or a phosphorus source, and the carrier gas is H2 and / or Ar; the boron source includes at least one of borane, boron trifluoride, and trimethylboron; the phosphorus source includes at least one of phosphine, trimethylphosphine, and silane phosphide; the process parameters used in the preparation process of the doped source layer are: the flow rate of the doped source is 1000 sccm to 5000 sccm, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 10 s to 100 s.

5. The preparation method of the doped polysilicon according to claim 4, wherein, In the preparation process of the amorphous silicon layer, the silicon source used is silane, and the carrier gas is H2 and / or Ar; the process parameters used in the preparation process of the amorphous silicon layer are: the flow rate of silane is 2000 sccm to 3500 sccm, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the pressure is 400 Pa to 460 Pa, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 30 s to 120 s.

6. The preparation method of doped polysilicon according to any one of claims 1 to 5, characterized in that, The doped amorphous silicon composite film layer is prepared on the intrinsic silicon layer; the thickness of the intrinsic silicon layer is 50 nm to 250 nm; the intrinsic silicon layer is prepared by PECVD method; the process parameters used in the preparation process of the intrinsic silicon layer are: the silicon source is silane, the flow rate of silane is 2000 sccm to 3500 sccm, the carrier gas is H2 and / or Ar, the flow rate of the carrier gas is 8000 sccm to 15000 sccm, the pressure is 200 Pa to 460 Pa, the power is 5000 W to 15000 W, the duty cycle is 1 / 8 to 1 / 20, the power supply frequency is 40 kHz to 100 kHz, and the time is 600 s to 3000 s.

7. The preparation method of the doped polysilicon according to claim 6, characterized in that, The intrinsic silicon layer is prepared on the tunneling oxide layer; the tunneling oxide layer is prepared by PECVD method; the process parameters used in the preparation process of the tunneling oxide layer are: the reaction gas is nitrous oxide, the flow rate of nitrous oxide is 8000 sccm to 15000 sccm, the pressure is 100 Pa to 180 Pa, the power is 10000 W to 18000 W, the duty cycle is 1 / 100 to 1 / 240, 40 kHz to 100 kHz, and the time is 80 s to 180 s.

8. The preparation method of the doped polysilicon according to any one of claims 1 to 5, characterized in that, After the doped amorphous silicon composite film layer is prepared, the following treatment is further included: a silicon oxide layer is prepared on the doped amorphous silicon composite film layer by PECVD method; the reaction gases used in the preparation process of the silicon oxide layer are silane and nitrous oxide; After the silicon oxide layer is prepared, the following treatment is further included: annealing the doped amorphous silicon composite film layer with a silicon oxide layer prepared on its surface to obtain doped polysilicon.

9. A silicon wafer, characterized in that, The surface of the silicon wafer is deposited with doped polysilicon; the doped polysilicon is prepared by the preparation method according to any one of claims 1 to 8.

10. An application of the silicon wafer as described in claim 9, characterized in that, The silicon wafer is used to prepare a TOPCon cell, an IBC cell or a TBC cell.

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