Debris management for memory systems

Abstract

Aspects of the present disclosure configure system components, such as a memory subsystem controller, to provide media fragment management. The controller receives, from a host, a file-based optimization (FBO) entry including a plurality of logical block addresses (LBAs) associated with a file. The controller accesses a page table that associates the plurality of LBAs with respective physical addresses of a set of memory components and determines a first number of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs. The controller calculates a regression level of the file based on the first number of read operations relative to a second number of LBAs included in the plurality of LBAs.

Description

[0001] Priority Application

[0002] This application claims the benefit of priority of U.S. Application No. 18 / 383,761, filed Oct. 25, 2023, which claims the benefit of priority of Indian Patent Application No. 202241072538, filed Dec. 15, 2022, the entire contents of all applications are incorporated herein by reference. Technical Field

[0003] Embodiments of the present disclosure generally relate to memory subsystems, and more particularly, to providing adaptive media management for memory components such as memory dies. Background Art

[0004] A memory subsystem may be a storage system such as a solid state drive (SSD) and may include one or more memory components that store data. For example, the memory components may be non-volatile memory components and volatile memory components. Generally, a host system may utilize the memory subsystem to store data on and retrieve data from the memory components. Brief Description of the Drawings

[0005] The present disclosure will be more fully understood from the detailed description given below and from the accompanying drawings of various embodiments of the disclosure.

[0006] Figure 1 is a block diagram illustrating an example computing environment that includes a memory subsystem in accordance with some embodiments of the present disclosure.

[0007] Figure 2 is a block diagram of an example media operation manager in accordance with some embodiments of the present disclosure.

[0008] Figure 3 is a block diagram of an example page table in accordance with some embodiments of the present disclosure.

[0009] Figure 4 is a block diagram of a set of example channels for multiple memory dies in accordance with some embodiments of the present disclosure.

[0010] Figure 5A and 5B is a flowchart of an example method for managing data fragmentation in accordance with some embodiments of the present disclosure.

[0011] Figure 6 is a block diagram illustrating a pictorial representation of a machine in the form of a computer system within which a set of instructions may be executed to cause the machine to perform any one or more of the methodologies discussed herein. Detailed Description

[0012] Aspects of the present disclosure configure system components, such as a memory subsystem controller, to perform different memory management operations (e.g., defragmentation operations) on different groups of memory components (e.g., memory dies) based on the respective regression levels (fragmentation levels) of files corresponding to data stored in the memory components. The memory subsystem controller may receive file-based optimization (FBO) entries from a host that identify logical block addresses (LBAs) of one or more files. Using the FBO entries, the memory subsystem controller may determine the regression level of a file based on calculating the number of read operations needed to retrieve data from the memory components corresponding to the one or more files. The regression level may be communicated back to the host to determine whether one or more defragmentation operations need to be performed. For example, if the regression level exceeds a threshold regression level, the host may instruct the memory subsystem controller to defragment the data by copying as much data as possible into fewer memory blocks to reduce the number of read operations needed to read the LBAs of the one or more files. If the regression level does not exceed the threshold regression level, the memory subsystem controller may perform other types of defragmentation operations to improve the efficiency of reading data from the corresponding physical block addresses. By dynamically customizing different media management operations (e.g., defragmentation operations) based on the regression levels of data corresponding to one or more files, the overall efficiency of operating the memory subsystem is improved.

[0013] The memory subsystem may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices and memory modules are described below in connection with Figure 1 Generally, a host system may utilize a memory subsystem that includes one or more memory components, such as memory devices (e.g., memory dies) that store data. The host system may send access requests (e.g., write commands, read commands) to the memory subsystem, such as to store data at the memory subsystem and to read data from the memory subsystem. Data (or a data set) specified by the host is hereinafter referred to as “host data,” “application data,” or “user data.”

[0014] A memory subsystem may initiate media management operations (e.g., write operations) on host data stored on a memory device. For example, as part of a garbage collection management operation, the firmware of the memory subsystem may rewrite previously written host data from a location on the memory device to a new location. The rewritten data (e.g., initiated by the firmware) is hereinafter referred to as “garbage collection data”. “User data” may include host data and garbage collection data. “System data” hereinafter refers to data created and / or maintained by the memory subsystem for performing operations in response to host requests and for media management. Examples of system data include, but are not limited to, system tables (e.g., logical to physical address mapping tables), data from logging, scratchpad data, etc.

[0015] Many different media management operations may be performed on the memory device. For example, media management operations may include different scan rates, different scan frequencies, different wear leveling, different read disturbance management, different near error error correction (ECC), different defragmentation operations, and / or different dynamic data refreshes. Wear leveling ensures that all blocks in a memory component approach their defined erase cycle budget at the same time, rather than some blocks approaching the erase cycle budget earlier. Read disturbance management counts all read operations on a memory component. If a certain threshold is reached, then the surrounding area is refreshed. Near error ECC refreshes all data read by an application that exceeds a configured error threshold. As a background operation, dynamic data refresh scans and reads all data and identifies the error status of all blocks. If a certain error threshold per block or ECC unit is exceeded during this scan read, then a refresh operation is triggered.

[0016] The memory device may be a non-volatile memory device. A non-volatile memory device is an encapsulation of one or more dies (or chips). Each die may include one or more planes. For some types of non-volatile memory devices (e.g., NAND devices), each plane includes a set of physical blocks. For some memory devices, a block is the smallest area that can be erased. Each block includes a set of pages. Each page includes a set of memory cells that store data bits. The memory device may be a raw memory device (e.g., NAND), which is externally managed by an external controller, for example. The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller for memory management within the same memory device encapsulation.

[0017] There are challenges in efficiently managing a typical memory device or performing media management operations on a typical memory device. Specifically, a typical memory system receives data from a host associated with various LBAs and stores the data in free memory blocks at physical memory locations. Generally, the host does not notify the memory system which data set corresponds to which set of files. That is, the memory subsystem generally does not know which of the stored data corresponds to an individual file. Also, the host generally does not know how the data is arranged in the memory subsystem and specifically, does not know which physical memory addresses map to the LBAs of one or more files. Due to the lack of communication between the memory subsystem and the host, the data stored in the memory subsystem may remain severely fragmented (distributed across multiple memory dies and blocks), which results in a large number of read operations being required to read a set of LBAs corresponding to an individual file. This severely degrades the efficiency and speed of reading data from the memory subsystem.

[0018] For example, the host cannot issue an instruction to the memory device to improve the performance regression for defragmentation or reduce the regression level of certain LBAs because the host does not know the current regression level of the LBAs. Also, the memory device does not know which set of data stored in the memory device is critical to the performance of the host, which prevents the memory controller from providing the performance regression level of this data to the host. Without a handshake regarding the regression level and LBA information of individual files between the host and the memory system, the host cannot instruct the memory system to execute an optimization program to improve the regression level. This may result in the data remaining severely fragmented and the read performance of the memory system not being optimal or less than ideal. Current memory systems do not provide a solution that solves the necessary handshake for data fragmentation or regression level.

[0019] Aspects of the present disclosure address the above and other deficiencies by providing a memory controller that can perform different memory management operations (e.g., defragmentation operations) on different groups of memory components (e.g., memory dies) based on the respective regression levels (fragmentation levels) of files corresponding to the data stored in the memory components. Specifically, the memory controller can receive FBO entries from the host that identify the LBAs of individual files or file sets. Using the FBO entries, the memory controller can determine the regression level of an individual file, for example, by calculating the number of read operations required to retrieve data from the memory relative to the maximum number of read operations that may need to be performed. The regression level can be communicated back to the host to determine whether one or more defragmentation operations need to be performed.

[0020] In some cases, if the regression level exceeds a threshold regression level, then the host may instruct the memory subsystem controller to defragment the data by copying as much data as possible to new memory blocks to reduce the number of read operations that need to be performed to read one or more files' LBAs. In some cases, if the regression level does not exceed the threshold regression level, then the memory controller may perform other types of defragmentation operations to improve the efficiency of reading data from the corresponding physical block addresses, such as by rearranging how physical addresses corresponding to an LBA are concurrently read from the same memory channel corresponding to a set of memory dies. By dynamically customizing different media management operations (e.g., defragmentation operations) based on the regression level of data corresponding to one or more files, the overall efficiency of operating the memory subsystem is improved, which increases the efficiency of operating the memory system.

[0021] For some embodiments, a memory subsystem (e.g., a memory subsystem controller) may receive from a host an FBO entry that includes a plurality of LBAs associated with a file. The memory subsystem controller accesses a page table that associates the plurality of LBAs with corresponding physical addresses of the set of memory components and determines a first number of read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs. The memory subsystem controller calculates a regression level of the file based on the first number of read operations relative to a second number of LBAs included in the plurality of LBAs.

[0022] In some instances, the memory subsystem controller determines the first number of read operations by determining whether adjacent pairs of the plurality of LBAs stored in a table are associated with non-adjacent corresponding physical addresses. In some instances, the memory subsystem controller identifies a plurality of adjacent pairs of the plurality of LBAs stored in the table (each of which is associated with a corresponding set of non-adjacent corresponding physical addresses) and calculates a first number based on the number of the identified plurality of adjacent pairs. In some instances, the memory subsystem controller determines a maximum number of read operations that need to be performed to read data associated with the plurality of LBAs. The second number may correspond to the maximum number. In some instances, the regression level is calculated as a ratio of the first number of read operations to the maximum number of read operations.

[0023] In some instances, the memory subsystem controller transmits the regression level to the host in response to receiving the FBO entry. In some instances, the memory subsystem controller (or the host) compares the regression level of the file with a threshold regression level and performs (or is instructed by the host to perform) one or more data defragmentation operations based on comparing the regression level of the file with the threshold regression level. In some instances, one or more data defragmentation operations are performed in response to (the host or the memory subsystem controller) determining that the regression level of the file exceeds the threshold regression level.

[0024] In some instances, one or more data defragmentation operations include modifying the read order of physical addresses of the set of memory components associated with the plurality of LBAs. In some instances, the memory subsystem controller modifies the read order by identifying a first set of physical addresses associated with a first set of the plurality of LBAs of the same channel corresponding to the set of memory components as a second set of physical addresses associated with a second set of the plurality of LBAs, the first set of physical addresses corresponding to a first chip enable on the same channel and the second set of physical addresses corresponding to a second chip enable. The memory subsystem controller interlaces reading the second set of physical addresses with transferring data to be read from the first set of physical addresses to a processing device based on the second chip enable indicating the same channel of the set of memory components.

[0025] In some instances, the memory subsystem controller reads data from the first set of physical addresses based on a first chip enable indicating the same channel of the set of memory components. After reading data from the first set of physical addresses and while the data is being transferred from the set of memory components to a processing device, the memory subsystem controller reads data from the second set of physical addresses based on a second chip enable indicating the same channel of the set of memory components. In some instances, the last LBA in the first set of the plurality of LBAs is not adjacent to the first LBA in the second set of the plurality of LBAs.

[0026] In some instances, the memory subsystem controller determines a storage type associated with one or more of the physical addresses. The memory subsystem controller transmits a first regression indicator to a host in response to determining that the storage type associated with one or more physical addresses is a first type based on comparing a regression level of a file with a threshold regression level and transmits a second regression indicator to the host in response to determining that the storage type associated with one or more physical addresses is a second type based on comparing the regression level of the file with the threshold regression level. In some instances, the first type includes single-level cell (SLC) storage or triple-level cell (TLC) storage and the second type includes quad-level cell (QLC) storage. In some instances, the second regression indicator represents the regression level and the first regression indicator represents a regression below the regression level.

[0027] In some instances, one or more data defragmentation operations include copying data associated with non-adjacent physical addresses among physical addresses associated with multiple logical block addresses (LBAs) to a new virtual block or superblock. In some instances, the memory subsystem controller determines that the number of free virtual blocks caused by copying data into the new virtual block has decreased below a threshold and delays copying the data until the number of free virtual blocks exceeds the threshold. In some instances, the memory subsystem controller determines that less than all of the new virtual blocks are filled with the copied data of the multiple LBAs. In response to determining that less than all of the new virtual blocks are filled with the copied data of the multiple LBAs, the memory subsystem controller adds other data associated with different LBAs to the remainder of the new virtual block. The other data may include data collected during garbage collection and / or data from another frame buffer object (FBO) entry.

[0028] Although various embodiments are described herein as being implemented with respect to a memory subsystem (e.g., a controller of a memory subsystem), some or all portions of the embodiments may be implemented with respect to a host system (e.g., a software application or operating system of a host system).

[0029] Figure 1 An example computing environment 100 including a memory subsystem 110 is illustrated in accordance with some instances of the present disclosure. The memory subsystem 110 may include media, such as memory components 112A through 112N (hereinafter also referred to as "memory devices"). The memory components 112A through 112N may be volatile memory devices, non-volatile memory devices, or a combination thereof. The memory components 112A through 112N may be implemented by individual dies such that a first memory component 112A may be implemented by a first memory die (or a first set of memory dies) and a second memory component 112N may be implemented by a second memory die (or a second set of memory dies).

[0030] In some embodiments, the memory subsystem 110 is a storage system. The memory subsystem 110 may be a storage device, a memory module, or a hybrid of a storage device and a memory module. Examples of storage devices include solid state drives (SSDs), flash drives, universal serial bus (USB) flash drives, embedded multimedia card (eMMC) drives, universal flash storage (UFS) drives, and hard disk drives (HDDs). Examples of memory modules include dual in-line memory modules (DIMMs), small DIMMs (SO-DIMMs), and non-volatile dual in-line memory modules (NVDIMMs).

[0031] The computing environment 100 may include a host system 120 coupled to the memory system. The memory system may include one or more memory subsystems 110. In some embodiments, the host system 120 is coupled to different types of memory subsystems 110.Figure 1 An example of a host system 120 coupled to a memory subsystem 110 is described. For example, the host system 120 uses the memory subsystem 110 to write data to and read data from the memory subsystem 110. As used herein, "coupled to" generally refers to a connection between components, which can be an indirect communication connection or a direct communication connection (e.g., without an intermediary component), whether wired or wireless, including connections such as electrical connections, optical connections, magnetic connections, etc.

[0032] The host system 120 can be, for example, a desktop computer, a laptop computer, a network server, a mobile device, an embedded computer (e.g., an embedded computer included in a vehicle, an industrial device, or a networked commercial device), or such a computing device that includes a memory and a processing device. The host system 120 can include or be coupled to the memory subsystem 110 such that the host system 120 can read data from or write data to the memory subsystem 110. The host system 120 can be coupled to the memory subsystem 110 via a physical host interface. Examples of the physical host interface include, but are not limited to, a Serial Advanced Technology Attachment (SATA) interface, a Peripheral Component Interconnect Express (PCIe) interface, a Universal Serial Bus (USB) interface, a Fibre Channel interface, a Serial Attached SCSI (SAS) interface, etc. The physical host interface can be used to transfer data between the host system 120 and the memory subsystem 110. When the memory subsystem 110 is coupled to the host system 120 via a PCIe interface, the host system 120 can further utilize the Non-Volatile Memory Express (NVMe) interface to access the memory components 112A to 112N. The physical host interface can provide an interface for transferring control, address, data, and other signals between the memory subsystem 110 and the host system 120.

[0033] Memory components 112A to 112N may include any combination of different types of non-volatile memory components and / or volatile memory components. Examples of non-volatile memory components include NAND-type flash memory. Each of memory components 112A to 112N may include one or more memory cell arrays, such as single-level cells (SLCs) or multi-level cells (MLCs) (e.g., TLCs or QLCs). In some embodiments, a particular memory component 112 may include both an SLC portion and an MLC portion of memory cells. Each of the memory cells may store one or more data bits (e.g., blocks) used by host system 120. Although non-volatile memory components such as NAND-type flash memory are described, memory components 112A to 112N may be based on any other type of memory, such as volatile memory. In some embodiments, memory components 112A to 112N may be, but are not limited to, random access memory (RAM), read-only memory (ROM), dynamic random access memory (DRAM), synchronous dynamic random access memory (SDRAM), phase change memory (PCM), magnetoresistive random access memory (MRAM), "NOR" flash memory, electrically erasable programmable read-only memory (EEPROM), and cross-point arrays of non-volatile memory cells. Cross-point arrays of non-volatile memory cells may perform bit storage based on changes in bulk resistance in conjunction with a stackable cross-grid data access array. Additionally, compared to many flash-based memories, cross-point non-volatile memory may perform in-place write operations, where non-volatile memory cells may be programmed without first erasing the non-volatile memory cells. Additionally, the memory cells of memory components 112A to 112N may be grouped into memory pages or blocks, which may refer to the units of memory components 112 for storing data. In some instances, the memory cells of memory components 112A to 112N may be grouped into a set of different regions or virtual blocks (VBs) of equal or unequal size for storing data for corresponding applications. In such cases, each application may store data in an associated region of the set of different regions.

[0034] Memory subsystem controller 115 may communicate with memory components 112A to 112N to perform operations such as reading data, writing data, or erasing data at memory components 112A to 112N and other such operations. Memory subsystem controller 115 may communicate with memory components 112A to 112N to perform various memory management operations, such as different scan rates, different scan frequencies, different wear leveling, different read disturbance management, different near error ECC operations, different defragmentation operations, and / or different dynamic data refreshing.

[0035] The memory subsystem controller 115 may include hardware such as one or more integrated circuits and / or discrete components, buffer memory, or a combination thereof. The memory subsystem controller 115 may be a microcontroller, dedicated logic circuitry (e.g., a field programmable gate array (FPGA), an application specific integrated circuit (ASIC), etc.), or another suitable processor. The memory subsystem controller 115 may include a processor (processing device) 117 configured to execute instructions stored in local memory 119. In the illustrated example, the local memory 119 of the memory subsystem controller 115 includes an embedded memory configured to store instructions for performing various processes, operations, logic flows, and routines for controlling the operation of the memory subsystem 110, including handling communication between the memory subsystem 110 and the host system 120. In some embodiments, the local memory 119 may include memory registers for storing memory pointers, fetched data, etc. The local memory 119 may also include read only memory (ROM) for storing microcode. Although the Figure 1 illustrated example memory subsystem 110 has been described as including a memory subsystem controller 115, in another embodiment of the present disclosure, the memory subsystem 110 may not include a memory subsystem controller 115 and may instead rely on external control (e.g., provided by an external host or by a processor 117 or controller separate from the memory subsystem 110).

[0036] Generally, the memory subsystem controller 115 may receive commands or operations from the host system 120 and may convert the commands or operations into instructions or appropriate commands to achieve the desired access to the memory components 112A to 112N. In some instances, the commands or operations received from the host system 120 may specify a regression level and / or a regression threshold for the memory components 112A to 112N. In some instances, the memory subsystem controller 115 may provide or transmit to the host system 120 a command or operation specifying a regression level and / or a regression threshold for a set of LBAs associated with FBO entries stored in the memory components 112A to 112N.

[0037] The memory subsystem controller 115 may be responsible for other memory management operations such as wear leveling operations, garbage collection operations, error detection and error correction code (ECC) operations, encryption operations, cache operations, and address translation. The memory subsystem controller 115 may further include host interface circuitry for communicating with the host system 120 via a physical host interface. The host interface circuitry may convert commands received from the host system 120 into command instructions to access the memory components 112A to 112N and may convert responses associated with the memory components 112A to 112N into information for the host system 120.

[0038] The memory subsystem 110 may also include additional circuitry or components not shown. In some embodiments, the memory subsystem 110 may include a cache or buffer (e.g., DRAM or other temporary storage location or device) and address circuitry (e.g., row decoder and column decoder) that may receive an address from the memory subsystem controller 115 and decode the address to access the memory components 112A through 112N.

[0039] The memory device may be a raw memory device (e.g., NAND) that is managed externally, for example, by an external controller (e.g., the memory subsystem controller 115). The memory device may be a managed memory device (e.g., managed NAND), which is a raw memory device combined with a local embedded controller (e.g., local media controller) for memory management within the same memory device package. Any of the memory components 112A through 112N may include a media controller (e.g., media controllers 113A and 113N) to manage the memory cells of the memory component (e.g., perform one or more memory management operations), communicate with the memory subsystem controller 115, and execute memory requests (e.g., read or write) received from the memory subsystem controller 115.

[0040] The memory subsystem controller 115 may include a media operations manager 122. The media operations manager 122 may be configured to selectively and adaptively perform different memory management operations (e.g., defragmentation operations) on the memory components 112A through 112N based on the regression level of the FBO entries associated with the respective memory components 112A through 112N. For example, the media operations manager 122 may receive FBO entries from the host system 120 that identify the LBA of an individual file or collection of files. Using the FBO entries, the memory subsystem controller 115 may determine the regression level of the individual file, for example, by calculating the number of read operations required to retrieve data from the memory relative to the maximum number of read operations that may need to be performed. The regression level may be communicated back to the host system 120 to determine whether one or more defragmentation operations need to be performed. In some cases, the defragmentation operation is selectively performed based on the type of memory in which the data for storing the FBO entries is stored. That is, if the data is stored in a TLC or SLC memory type, the regression level may be communicated back to the host as a level lower than the actual regression level to prevent the defragmentation operation from being performed. If the data is stored in a QLC memory type, the regression level may be communicated back to the host as the actual regression level to cause the defragmentation operation to be performed.

[0041] In some instances, the memory subsystem controller 115 compares the regression level of the FBO entry with a regression level threshold. The memory subsystem controller 115 may determine that the regression level exceeds the threshold. Based on whether the regression level exceeds the threshold, the memory subsystem controller 115 may perform one or more data defragmentation operations. The data defragmentation operation may include rearranging the physical addresses that map the logical block addresses (LBAs) of the FBO entry read from one or more of the memory components 112A to 112N. The data defragmentation operation may include copying the data of the FBO entry distributed across a number of virtual blocks (VBs) on the memory components 112A to 112N into fewer VBs or a single VB to reduce the number of read operations required to read the data corresponding to the FBO entry. In some cases, if the number of available free VBs is below a threshold number, the data is only copied into a new VB. If the number of available free VBs is not below the threshold number, the memory subsystem controller 115 may delay copying the data into a new VB until the number of available free VBs exceeds the threshold number.

[0042] Depending on the embodiment, the media operation manager 122 may include logic (e.g., a set of transient or non-transient machine instructions, such as firmware) or one or more components that cause the media operation manager 122 to perform the operations described herein. The media operation manager 122 may include a tangible or non-tangible unit capable of performing the operations described herein. Additional details regarding the operations of the media operation manager 122 are described below.

[0043] Figure 2 is a block diagram of an example media operation manager 200 according to some embodiments of the present disclosure. As illustrated, the media operation manager 122 includes a regression calculation module 220, a page table 230, and a defragmentation operation module 240. For some embodiments, the components or arrangements (e.g., fewer or more components) of the media operation manager 122 may be different from Figure 2 those illustrated.

[0044] The media operation manager 200 receives FBO entries from the host system 120 that list multiple LBAs of individual files. In response to receiving the FBO entries, the regression calculation module 220 accesses the page table 230 to identify a list of physical addresses that map to each respective LBA in the FBO entries. The regression calculation module 220 calculates the regression level of the FBO entry by analyzing the arrangement of the identified physical addresses. That is, the regression calculation module 220 calculates the total number of read operations required to read data from all the identified physical addresses relative to the maximum amount of read operations that need to be performed.

[0045] Specifically, the regression calculation module 220 may determine the worst - case scenario for the fragmentation of data corresponding to an FBO entry. This may occur when each LBA of the FBO is associated with a physical address (e.g., a page) in a different VB. That is, the data of the FBO entry may be stored across a certain number of VBs corresponding to the number of LBAs in the FBO. In such a worst - case scenario, the memory subsystem controller 115 may need to perform the maximum number of read operations corresponding to the number of LBAs in the FBO to obtain all the data of the FBO entry. For example, if an FBO entry contains 10 LBAs, the worst - case scenario for reading the data corresponding to the FBO entry is to perform up to 10 reads to access 10 different VBs from memory components 112A to 112N.

[0046] The regression calculation module 220 may calculate the actual total number of read operations required to read the data corresponding to an FBO entry by determining how many VBs are used to store the data corresponding to the FBO entry. In some cases, the regression calculation module 220 may traverse the list of identified physical addresses corresponding to multiple LBAs. In response to determining that a first LBA corresponds to a first physical address that is not adjacent to a second physical address corresponding to a second LBA that is sequentially adjacent to the first LBA, the regression calculation module 220 may increment a counter representing the number of reads. This may be because reading non - adjacent physical addresses may require additional reads. In this way, the regression calculation module 220 identifies pairs of adjacent LBAs in the page table 230 that correspond to an FBO entry (which corresponds to non - adjacent physical addresses). The regression calculation module 220 calculates the number of read operations required to read the data corresponding to the FBO entry (e.g., a first quantity) based on the number of the identified multiple adjacent pairs. The regression calculation module 220 may calculate the regression level of the FBO as the ratio of the first number of read operations to the maximum number of read operations and may provide this regression level back to the host system 120.

[0047] Figure 3 is a block diagram of an example page table 300 according to some embodiments of the present disclosure. The regression calculation module 220 may communicate with the page table 230 to obtain the page table 300 corresponding to the FBO entry received from the host system 120. The page table 300 may include a list of LBAs 310 corresponding to the FBO entry and their corresponding physical addresses 320. The regression calculation module 220 may determine that a first LBA1 312 is adjacent to a second LBA2 314. The regression calculation module 220 may determine that a first physical address (PA1) 322 corresponding to the first LBA1 312 is adjacent to a second physical address (PA2) 324 corresponding to the second LBA2 314. In such a case, the regression calculation module 220 determines that the same read operation may be performed to obtain the data of the first LBA1 312 and the second LBA2 314.

[0048] The regression calculation module 220 can determine that the third LBA4 316 is adjacent to the fourth LBA5 318. The regression calculation module 220 can determine that the third physical address (PA8) 326 corresponding to the third LBA 4 316 is not adjacent to the fourth physical address PA10 328 corresponding to the fourth LBA5 318. In such cases, the regression calculation module 220 determines that two read operations need to be performed to obtain the data of the third LBA4 316 and the fourth LBA5 318. In response, the regression calculation module 220 updates or increments the counter for the number of read operations required to obtain the data of the FBO entry. After fully traversing or processing the LBA 310 of the FBO entry, the regression calculation module 220 uses the current value of the counter as the first number of reads required to read the data corresponding to the FBO entry. The regression calculation module 220 calculates the regression level of the FBO entry based on the first number of read operations required to read the data corresponding to the FBO entry and the worst-case scenario maximum number. The regression calculation module 220 can return this regression level to the host system 120.

[0049] In some cases, the regression calculation module 220 provides the regression level to the defragmentation operation module 240. The defragmentation operation module 240 can compare the regression level with a regression level threshold (which can be provided by the host system 120). The defragmentation operation module 240 can perform one or more defragmentation operations based on the current regression level of the data corresponding to the FBO entry. In some cases, the defragmentation operation module 240 performs one or more data defragmentation operations in response to determining that the regression level of the file exceeds the threshold regression level.

[0050] For example, as one of the defragmentation operations, the defragmentation operation module 240 can modify the read order of the physical addresses of the set of memory components associated with multiple LBAs. Specifically, the defragmentation operation module 240 identifies a first set of physical addresses associated with a first set of multiple LBAs in the same channel corresponding to the set of memory components 112A to 112N as a second set of physical addresses associated with a second set of multiple LBAs, the first set of physical addresses corresponding to a first chip enable on the same channel and the second set of physical addresses corresponding to a second chip enable. The defragmentation operation module 240 interleaves reading the second set of physical addresses based on the second chip enable indicating the same channel of the set of memory components 112A to 112N with transferring the data to be read from the first set of physical addresses to the memory subsystem controller 115.

[0051] In some cases, the defragmentation operation module 240 reads data from a first set of physical addresses from the same channel of the set of memory components 112A to 112N based on a first die enable. After reading data from the first set of physical addresses and when the data is transferred from the set of memory components to the memory subsystem controller 115, the defragmentation operation module 240 reads data from a second set of physical addresses from the same channel of the set of memory components 112A to 112N based on a second die enable. The last LBA in the first set of the plurality of LBAs may not be adjacent to the first LBA in the second set of the plurality of LBAs.

[0052] Figure 4 is a block diagram 400 of a set of example channels for multiple memory dies according to some embodiments of the present disclosure. Figure 4 Each memory die shown therein may correspond to a different one of the set of memory components 112A to 112N. In some instances, the defragmentation operation module 240 may perform virtual defragmentation on data associated with FBO entries by controlling the order in which physical addresses corresponding to the LBA are read from the memory components 112A to 112N. Thus, the defragmentation operation module 240 may read data from the third physical address 326 after reading data from the first physical address 322, rather than reading the second physical address 324 corresponding to the second LBA 314 after reading the data corresponding to the first physical address 322. This may be performed if the defragmentation operation module 240 determines that the third physical address 326 is on the same channel as the first physical address 322 and on a different one of the memory components 112A to 112N. That is, the defragmentation operation module 240 may determine that the third physical address 326 is on the same channel as the first physical address 322 rather than on the same channel as the second physical address 324. In such cases, the defragmentation operation module 240 may interleave reading data from the third physical address 326 with reading data from the first physical address 322.

[0053] Specifically, the defragmentation operation module 240 may determine that the third physical address 326 corresponding to the third LBA 316 is not adjacent to the fourth physical address 328 corresponding to the fourth LBA 318. Additionally, the defragmentation operation module 240 may determine that the third physical address 326 and the fourth physical address 328 correspond to different ones of the memory components 112A to 112N of the same channel. Specifically, the defragmentation operation module 240 may determine that the third physical address 326 corresponds to the first die enable 412 of the first memory component 112A and the fourth physical address 328 corresponds to the second die enable 414 of the second memory component 112N. The defragmentation operation module 240 may also determine that the first and second memory components 112A and 112N are on the same channel 410 of the memory subsystem.

[0054] In such cases, the defragmentation operation module 240 may interleave reading data from the third physical address 326 with reading data from the fourth physical address 328. This can reduce the amount of time required to retrieve and read data from the same channel 410. That is, the defragmentation operation module 240 may instruct the first memory component 112A (using the first chip enable 412) to read data corresponding to the third physical address 326. After reading data from the third physical address 326 and when the data is transferred to the memory subsystem controller 115, the memory subsystem controller 115 instructs the same channel 410 to read data corresponding to the fourth physical address 328 from the second memory component 112N (using the second chip enable 414). In this way, the memory subsystem controller 115 does not have to wait for the transfer of data corresponding to the third physical address 326 to complete before initiating the transfer of data corresponding to the fourth physical address 328, which reduces the total latency experienced by the memory subsystem controller 115.

[0055] The defragmentation operation module 240 may perform a similar operation to interleave data read from the second channel 420 that includes memory components 112C and 112D (not shown) corresponding to other chip enables 422 and 424. This reduces the total latency experienced by the memory subsystem controller 115 that performs virtual defragmentation on the data.

[0056] In some instances, the defragmentation operation module 240 (or the host system 120) may determine that the regression level of the FBO entry exceeds a regression level threshold. The defragmentation operation module 240 may determine or receive instructions from the host system 120 to actively defragment the data corresponding to the FBO entry. To do so, the defragmentation operation module 240 may determine how many free VBs are currently available. The defragmentation operation module 240 may determine that the number of available free VBs exceeds a threshold. The defragmentation operation module 240 may calculate how many VBs are needed to defragment or store all the data corresponding to the FBO entry. The defragmentation operation module 240 may decrement the number of required VBs from the currently available number of free VBs. The defragmentation operation module 240 may determine whether the decremented number still exceeds the threshold. If the decremented number still exceeds the threshold, then the defragmentation operation module 240 may copy all the data corresponding to the FBO entry into the free VBs and update the page table 300. In some cases, the defragmentation operation module 240 may calculate the minimum LBA start and maximum length of the FBO entry to determine the number of VBs required to store the data corresponding to the FBO entry.

[0057] If the decremented number no longer exceeds the threshold, then the defragmentation operation module 240 may delay copying the data into the free VBs until the number of free VBs minus the number of VBs required to store the data corresponding to the FBO entry exceeds the threshold.

[0058] In some instances, the defragmentation operation module 240 determines that a single VB is larger than the available data corresponding to an FBO entry. That is, the FBO entry contains LBAs that can fit into several VBs, but at least one of the VBs still has available free space. For example, the FBO entry may contain 100 LBAs and each VB may store 30 pages. In such cases, the FBO entry may be divided into four VBs, but the fourth VB will have 10 pages remaining blank. Instead of filling the blank pages with dummy data, the defragmentation operation module 240 may fill the remaining space in the VB with data corresponding to different FBO entries, system data, and / or data in the VBs in the garbage collection. In some cases, the defragmentation operation module 240 may close partially blank VBs by filling the blank space with dummy data after a threshold time period to avoid locking the memory system.

[0059] Figure 5A and 5B are flowcharts of example methods 500 and 501 for managing data fragmentation in accordance with some embodiments of the present disclosure. Methods 500 and 501 may be executed by processing logic, which may include hardware (e.g., a processing device, circuitry, dedicated logic, programmable logic, microcode, hardware of a device, an integrated circuit, etc.), software (e.g., instructions running or executing on a processing device), or a combination thereof. In some embodiments, methods 500 and 501 are executed by Figure 1 the media operation manager 122. Although the processes are shown in a particular sequence or order, the order of the processes may be modified unless otherwise specified. Thus, the illustrated embodiments should be understood only as examples. The illustrated processes may be executed in a different order and some processes may be executed in parallel. Additionally, one or more processes may be omitted in various embodiments. Thus, not all processes are required in every embodiment. Other process flows are possible.

[0060] Now refer to Figure 5A, method (or process) 500 begins with operation 505, where the media operation manager 122 (e.g., the memory subsystem controller 115) of the memory subsystem (e.g., memory subsystem 110) receives from the host system 120 an FBO entry that includes a plurality of LBAs associated with a file. Next, in operation 510, the memory subsystem controller 115 accesses a page table that associates the plurality of LBAs with corresponding physical addresses of a set of memory components 112A through 112N, and in operation 515, the memory subsystem controller 115 determines the number of first read operations that need to be performed to read data from the physical addresses of the set of memory components associated with the plurality of LBAs. Thereafter, in operation 520, the memory subsystem controller 115 calculates a regression level of the file based on the number of first read operations relative to a second number of LBAs included in the plurality of LBAs.

[0061] Now refer to Figure 5B , method (or process) 501 begins with operation 530, where the media operation manager 122 (e.g., the memory subsystem controller 115) of the memory subsystem (e.g., memory subsystem 110) compares the regression level with a threshold. Next, in operation 540, the memory subsystem controller 115 determines that the regression level exceeds the threshold, and in operation 550, the memory subsystem controller 115 performs one or more data defragmentation operations to defragment or virtually defragment the data corresponding to the FBO entry.

[0062] Figure 6 Describes an example machine in the form of a computer system 600 within which a set of instructions can be executed to cause the machine to perform any one or more of the methodologies discussed herein. In some embodiments, the computer system 600 can correspond to a host system (e.g., Figure 1 host system 120), which includes, is coupled to, or utilizes a memory subsystem (e.g., Figure 1 memory subsystem 110) or can be used to execute the operations of a controller (e.g., execute an operating system to perform operations corresponding to Figure 1 media operation manager 122). In alternative embodiments, the machine can be connected (e.g., networked) to other machines in a local area network (LAN), intranet, extranet, and / or the Internet. The machine can operate as a server or client machine in a client-server network environment, as a peer machine in a peer-to-peer (or distributed) network environment, or as a server or client machine in a cloud computing infrastructure or environment.

[0063] The machine can be a personal computer (PC), a tablet PC, a set-top box (STB), a personal digital assistant (PDA), a cellular phone, a network device, a server, a network router, a network switch, a network bridge, or any machine capable of executing a set of instructions (sequentially or otherwise) that specify actions to be taken by the machine. Additionally, while a single machine is illustrated, the term "machine" shall also be taken to include any collection of machines that individually or jointly execute a set (or multiple sets) of instructions to perform any one or more of the methodologies discussed herein.

[0064] Example computer system 600 includes a processing device 602, a main memory 604 (e.g., read-only memory (ROM), flash memory, dynamic random access memory (DRAM) (such as synchronous DRAM (SDRAM) or Rambus DRAM (RDRAM), etc.), static memory 606 (e.g., flash memory, static random access memory (SRAM)), etc.), and a data storage system 618, which communicate with each other via a bus 630.

[0065] The processing device 602 represents one or more general-purpose processing devices, such as a microprocessor, a central processing unit, or the like. More specifically, the processing device 602 can be a complex instruction set computing (CISC) microprocessor, a reduced instruction set computing (RISC) microprocessor, a very long instruction word (VLIW) microprocessor, a processor implementing other instruction sets, or multiple processors implementing a combination of instruction sets. The processing device 602 can also be one or more special-purpose processing devices, such as an application-specific integrated circuit (ASIC), a field-programmable gate array (FPGA), a digital signal processor (DSP), a network processor, or the like. The processing device 602 is configured to execute instructions 626 for performing the operations and steps discussed herein. The computer system 600 can further include a network interface device 608 to communicate via a network 620.

[0066] The data storage system 618 can include a machine-readable storage medium 624 (also referred to as a computer-readable medium) on which is stored one or more sets of instructions 626 or software embodying any one or more of the methodologies or functions described herein. The instructions 626 can also reside, completely or at least partially, within the main memory 604 and / or within the processing device 602 during execution by the computer system 600, and the main memory 604 and the processing device 602 also constitute machine-readable storage media. The machine-readable storage medium 624, the data storage system 618, and / or the main memory 604 can correspond to Figure 1 the memory subsystem 110.

[0067] In one embodiment, the instructions 626 implement corresponding to Figure 1The functionality of media operation manager 122. Although the machine-readable storage medium 624 is shown as a single medium in the example embodiments, the term "machine-readable storage medium" should be regarded as including a single medium or multiple media that store one or more sets of instructions. The term "machine-readable storage medium" should also be regarded as including any medium that is capable of storing or encoding a set of instructions for execution by a machine and causing the machine to perform any one or more of the methodologies of the present disclosure. Thus, the term "machine-readable storage medium" should be regarded as including, but not limited to, solid-state memories, optical media, and magnetic media.

[0068] Some portions of the foregoing detailed description have been presented in terms of algorithms and symbolic representations of operations on data bits within a computer memory. These algorithmic descriptions and representations are the means used by those skilled in the data processing arts to most effectively convey the substance of their work to others skilled in the art. An algorithm is here, and generally, conceived as a self-consistent sequence of operations leading to a desired result. The operations are those requiring physical manipulation of physical quantities. Usually, though not necessarily, these quantities take the form of electrical or magnetic signals capable of being stored, combined, compared, and otherwise manipulated. It has proven convenient at times, principally for reasons of generality, to refer to these signals as bits, values, elements, symbols, characters, terms, numbers, or the like.

[0069] However, it should be borne in mind that all of these and similar terms are to be associated with the appropriate physical quantities and are merely convenient labels applied to these quantities. The present disclosure may relate to the actions and processes of a computer system or similar electronic computing device that manipulates and transforms data represented as physical (electronic) quantities within the registers and memories of the computer system into other data similarly represented as physical quantities within the memories or registers or other such information storage systems of the computer system.

[0070] The present disclosure also relates to an apparatus for performing the operations herein. This apparatus may be specially constructed for the intended purpose or it may comprise a general-purpose computer selectively activated or reconfigured by a computer program stored in a computer. Such a computer program may be stored in a computer-readable storage medium, such as, but not limited to, any type of disk including floppy disks, optical disks, CD-ROMs, and magneto-optical disks; read-only memory (ROM); random access memory (RAM); erasable programmable read-only memory (EPROM); EEPROM; magnetic or optical cards; or any type of media suitable for storing electronic instructions, each coupled to a computer system bus.

[0071] The algorithms and displays presented herein are not inherently related to any particular computer or other device. Various general-purpose systems may be used in conjunction with programs in accordance with the teachings herein, or it may prove convenient to construct more specialized devices to perform the methods. The structure of many of these systems will appear as described above in the description. Additionally, the present disclosure is not described with reference to any particular programming language. It will be understood that a variety of programming languages may be used to implement the teachings of the present disclosure as described herein.

[0072] The present disclosure may be provided as a computer program product or software, which may include a machine-readable medium having instructions stored thereon that may be used to program a computer system (or other electronic device) to perform a process in accordance with the present disclosure. The machine-readable medium includes any mechanism for storing information in a form readable by a machine (e.g., a computer). In some embodiments, the machine-readable (e.g., computer-readable) medium includes a machine-readable (e.g., computer-readable) storage medium, such as a read-only memory (ROM), random access memory (RAM), magnetic disk storage media, optical storage media, flash memory components, and the like.

[0073] In the foregoing specification, embodiments of the present disclosure have been described with reference to specific example embodiments of the present disclosure. It will be understood that various modifications may be made to the present disclosure without departing from the broader spirit and scope of the embodiments of the present disclosure set forth in the appended claims. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims

1. A system, comprising: A set of memory components of a memory subsystem; And A processing device operably coupled to the set of memory components, the processing device being configured to perform operations including: Receiving from a host a file-based optimization (FBO) entry including a plurality of logical block addresses (LBAs) associated with a file; Accessing a page table that associates the plurality of LBAs with corresponding physical addresses of the set of memory components; Determining a first number of read operations required to read data from the physical addresses of the set of memory components associated with the plurality of LBAs; And Calculating a regression level of the file based on the first number of read operations relative to a second number of LBAs included in the plurality of LBAs.

2. The system according to claim 1, wherein the operation for determining the first number of read operations includes: Determining whether adjacent pairs of the plurality of LBAs stored in the page table are associated with non-adjacent corresponding physical addresses, and calculating the first number of read operations based on determining that the adjacent pairs are associated with the non-adjacent corresponding physical addresses.

3. The system according to claim 1, the operations including: Identifying a plurality of adjacent pairs of the plurality of LBAs stored in the table, each associated with a corresponding set of non-adjacent corresponding physical addresses; And Calculating the first number of read operations according to the number of the identified plurality of adjacent pairs.

4. The system according to claim 1, the operations including: Determining a maximum number of read operations required to read data associated with the plurality of LBAs, wherein the second number of LBAs corresponds to the maximum number of read operations.

5. The system according to claim 4, wherein the regression level is calculated as a ratio of the first number of read operations to the maximum number of read operations.

6. The system according to claim 1, the operations including: Transmitting the regression level to the host in response to receiving the FBO entry.

7. The system according to claim 1, the operations including: Comparing the regression level of the file with a threshold regression level; And Performing one or more data defragmentation operations based on comparing the regression level of the file with the threshold regression level.

8. The system according to claim 7, wherein the one or more data defragmentation operations are performed in response to determining that the regression level of the file exceeds the threshold regression level.

9. The system according to claim 7, wherein the one or more data defragmentation operations include modifying a read order of the physical addresses of the set of memory components associated with the plurality of LBAs.

10. The system according to claim 9, wherein modifying the read order includes: Identifying a first set of physical addresses associated with a first set of the plurality of LBAs corresponding to the same channel of the set of memory components as a second set of physical addresses associated with a second set of the plurality of LBAs, the first set of physical addresses corresponding to a first chip enable on the same channel and the second set of physical addresses corresponding to a second chip enable; and Based on the second chip enable, enabling the same channel of the set of memory components to interleave reading the second set of physical addresses with transferring data read from the first set of physical addresses to the processing device.

11. The system according to claim 10, wherein the operation comprises: Based on the first chip enable, reading the data from the first set of physical addresses of the same channel of the set of memory components; and After reading the data from the first set of physical addresses and when the data is transferred from the set of memory components to the processing device, based on the second chip enable, reading data from the second set of physical addresses of the same channel of the set of memory components.

12. The system according to claim 10, wherein the last LBA in the first set of the plurality of LBAs is not adjacent to the first LBA in the second set of the plurality of LBAs.

13. The system according to claim 7, wherein the operation comprises: Determining a storage type associated with one or more of the physical addresses; Based on comparing the regression level of the file with the threshold regression level, transmitting a first regression indicator to the host in response to determining that the storage type associated with the one or more physical addresses is a first type; and Based on comparing the regression level of the file with the threshold regression level, transmitting a second regression indicator to the host in response to determining that the storage type associated with the one or more physical addresses is a second type.

14. The system according to claim 13, wherein the first type includes single-level cell (SLC) storage or triple-level cell (TLC) storage, and wherein the second type includes quad-level cell (QLC) storage.

15. The system according to claim 14, wherein the second regression indicator represents the regression level and the first regression indicator represents a regression lower than the regression level.

16. The system according to claim 7, wherein the one or more data defragmentation operations include copying data associated with non-adjacent physical addresses among the physical addresses associated with the plurality of LBAs to a new virtual block.

17. The system according to claim 16, wherein the operation comprises: Determining that the number of free virtual blocks caused by copying the data into the new virtual block is reduced below a threshold; and Delaying copying the data until the number of free virtual blocks exceeds the threshold.

18. The system according to claim 16, wherein the operation comprises: Determining that less than all of the new virtual blocks are filled with the copied data of the plurality of LBAs; and In response to determining that less than all of the new virtual blocks are filled with the copied data of the plurality of LBAs, placing other data associated with different LBAs into the remaining portion of the new virtual block.

19. A method, comprising: Receiving, from a host, a file-based optimization (FBO) entry including a plurality of logical block addresses (LBAs) associated with a file; Access a page table that associates the plurality of LBAs with corresponding physical addresses of a set of memory components; Determine a first number of read operations required to read data from the physical addresses of the set of memory components associated with the plurality of LBAs; And Calculate a regression level of the file based on the first number of read operations relative to a second number of LBAs included in the plurality of LBAs.

20. A non-transitory computer-readable storage medium comprising instructions that, when executed by a processing device, cause the processing device to perform operations including the following: Receive, from a host, a file-based optimization (FBO) entry including a plurality of logical block addresses (LBAs) associated with a file; Access a page table that associates the plurality of LBAs with corresponding physical addresses of a set of memory components; Determine a first number of read operations required to read data from the physical addresses of the set of memory components associated with the plurality of LBAs; And Calculate a regression level of the file based on the first number of read operations relative to a second number of LBAs included in the plurality of LBAs.

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