Stacked CMOS device with two dielectric materials in gate cut-out

Abstract

A complementary field effect transistor (CFET) device is formed on a semiconductor substrate. The CFET device has a first transistor underlying a second transistor. The filled gate cut is directly adjacent a sidewall of the gate of the CFET device. The first dielectric material in the gate cut is adjacent to the first transistor. A second dielectric material in the gate cut is adjacent to the second transistor. The two dielectric materials in the gate cut-out are selected to improve the electrical performance of each of the NFETs and PFETs in the CFET device. When the first transistor is a PFET, the first dielectric material may apply a compressive stress to the channel of the first transistor to improve the electrical performance of the PFET. When the second transistor is an NFET, the second dielectric material applies a tensile stress to the NFET to improve NFET performance.

Description

BACKGROUND OF THE DISCLOSURE

[0001] The present disclosure generally relates to nanosheet transistors. The present disclosure particularly relates to a CFET formed with two dielectric materials in a gate notch between two adjacent complementary field effect transistor (CFET) devices.

[0002] As semiconductor industry technology continues to scale down according to Moore's law and as the industry looks to go beyond the 5nm technology node, significant challenges have emerged. As the demand for reducing the size of transistor devices increases, nanosheet field effect transistors (FETs) help to achieve reduced device footprint while maintaining device performance. A nanosheet FET device includes one or more portions of a semiconductor channel material layer having a vertical thickness substantially less than its width. A typical nanosheet FET includes a plurality of stacked nanosheets extending between a pair of source / drain epitaxial regions. The nanosheet FET device can be a gate-all-around device where the gate surrounds the channel of the nanosheet FET device.

[0003] Compared to current FinFET technology, the gate-all-around (GAA) nanosheet metal oxide semiconductor field effect transistor (MOSFET) structure has been considered an excellent candidate for achieving improved power performance and area scaling. Specifically, due to the wide effective channel width (Weff), nanosheet-based semiconductor structures such as GAA nanosheet MOSFETs provide high drive current while maintaining short channel control.

[0004] A complementary field effect transistor (CFET) consists of two stacked complementary FETs, where the stacked complementary FETs include a vertically stacked p-type FET (PFET) and an n-type FET (NFET). The CFET device provides a further evolution of the gate-all-around (GAA) nanosheet transistor. The CFET device stacks both the n-type device and the p-type device on top of each other, rather than stacking n-type devices on top of other n-type devices or p-type devices on top of other p-type devices as in conventional vertically stacked GAA nanosheet transistors. The CFET stacked transistors provide a scaling path by stacking the NFET and PFET on top of each other, thus providing an area benefit. In combination with appropriate interconnects, the CFET approach can effectively halve the inverter footprint, double the area density, and further push the limits of Moore's law.

[0005] However, CFET devices give rise to unique device mobility issues related to the stacked NFETs and PFETs in the CFET device because the layers of the nanosheets forming the CFET grow epitaxially from a semiconductor substrate or wafer, where the crystal orientation serves as the semiconductor substrate. A typical nanosheet structure places the (100) crystal plane of the nanosheet parallel to the substrate, as opposed to the (110)-oriented channel in a FinFET. The (100) planes of the two transistors using the CFET alter the absolute and relative mobilities of electrons and holes in the transistor channels. In a CFET device with NFETs and PFETs, a Si wafer with a channel in the (100) crystal plane can be used to form the nanosheets to provide the highest electron mobility for the n-type transistors (NFETs), while the p-type transistors (PFETs) face challenges in hole mobility required for optimal PFET performance due to the (100) crystal plane orientation of the channel material. Summary of the Invention

[0006] The following presents an overview to provide a basic understanding of one or more embodiments of the present disclosure. This overview is not intended to identify key or critical elements or to delineate any scope of particular embodiments or any scope of the claims. Its sole purpose is to present concepts in a simplified form as a prelude to the more detailed description that is presented later.

[0007] Aspects of the disclosed invention relate to a semiconductor device structure of a complementary field effect transistor (CFET) device on a semiconductor substrate, where the CFET device has a first transistor under a second transistor. The first transistor and the second transistor create a stacked pair of transistors composed of NFETs and PFETs, forming the CFET device. A filled gate cut is directly adjacent and contiguous to the gate of the CFET device. Aspects of the present invention disclose that the gate cut is filled with a first dielectric material under a second dielectric material, where the first dielectric material is adjacent to the first transistor and the second dielectric material is adjacent to the second transistor. The two dielectric materials in the gate cut are selected to improve the electrical performance of each of the n-type FET (NFET) and p-type FET (PFET) in the CFET device. In a CFET device, neither the bottom source / drain nor the top source / drain tank generates sufficient strain on the channels of the stacked NFETs or the stacked PFETs to produce sufficient electron or hole mobility for optimizing FET performance. Accordingly, aspects of the present invention disclose a CFET device with a new structure that uses a filled gate cut directly adjacent to the CFET device, which enhances hole mobility in the PFET channel by applying compressive stress to the PFET channel and improves electron mobility in the NFET channel by applying tensile stress, thereby improving NFET performance.

[0008] Embodiments of the present invention provide a first dielectric material in a gate notch, which applies one of compressive stress or tensile stress to the channel of a first transistor. When the first transistor is an NFET, the first dielectric material applies tensile stress to the channel of the first transistor, and then a second dielectric material is selected to apply compressive stress to the channel of a second transistor, where the second transistor is a PFET in a CFET device. Aspects of the present invention also disclose that when the first transistor is a PFET, the first dielectric material in the gate notch applies a compressive stressor to the channel of the first transistor to improve the electrical performance of the PFET by increasing hole mobility. When the first transistor is a PFET, the second transistor is an NFET, and the second dielectric material in the gate notch applies tensile stress to the channel of the NFET to increase the electron mobility in the channel of the NFET. Increasing the electron mobility in the NFET channel can improve the electrical performance of the NFET.

[0009] Aspects of the present invention disclose that a gate notch is filled with a first dielectric material and a second dielectric material, which are located between the gates of at least two adjacent complementary field effect transistor devices in two adjacent cells, where the first and second dielectric materials are selected to apply appropriate stress to improve the electrical performance of the PFET and NFET in each adjacent CFET device.

[0010] Aspects of the present invention disclose a method of forming a complementary field effect transistor (CFET) device. The method includes epitaxially growing a stack of nanosheets on a semiconductor substrate, and selectively etching portions of the stack of nanosheets and the top of the semiconductor substrate. The method includes forming shallow trench isolation (STI) in the semiconductor substrate adjacent to the remaining portion of the nanosheet stack. The method includes forming at least two stacked gate-all-around field effect transistors separated by an intermediate dielectric isolation material on the semiconductor substrate, where at least a first transistor is below the intermediate dielectric isolation material and at least a second transistor is above the intermediate dielectric isolation material. The method includes performing a gate notch through a portion between an adjacent first transistor and an adjacent second transistor through each gate. The gate notch extends through the shallow trench isolation structure adjacent to the first transistor and the top of the semiconductor substrate. The method includes filling the gate notch with a first dielectric material, and recessing the first dielectric material, where if the first transistor is a PFET, the first dielectric material is selected to generate compressive stress, or if the first transistor is an NFET, the first dielectric material is selected to provide tensile stress. The method includes depositing a second dielectric material, where the second dielectric material is selected to apply tensile stress when the second transistor is an NFET, or compressive stress when the second transistor is a PFET. The method includes performing planarization to remove an excess or excessive portion of the second dielectric material.

[0011] Aspects of the present invention disclose a semiconductor structure having a plurality of complementary field-effect transistor (CFET) device units, where each CFET device has a first transistor under a second transistor. The semiconductor structure includes a first dielectric material that adjoins a portion of each channel of the first transistor in the first CFET device in the first unit and adjoins a portion of each channel of the first transistor in the second CFET device in the second unit of the CFET device. The first unit of the CFET device is adjacent to the second unit of the CFET device. The first dielectric material has fixed charges of a first polarity. The semiconductor structure includes a second dielectric material that adjoins a portion of each channel of the second transistor in the first CFET device of the first unit of the CFET device and adjoins a portion of each channel of the second transistor in the second CFET device of the second unit of the CFET device. The second dielectric material has fixed charges of a second polarity. The second dielectric material adjoining the second transistor is located on the first dielectric material adjoining the first transistor. The first dielectric material and the second dielectric material with fixed polarities are selected to improve the electrical performance of the NFETs and PFETs in each of the first CFET device and the second CFET device. BRIEF DESCRIPTION OF THE DRAWINGS

[0012] The above and other aspects, features, and advantages of various embodiments of the present invention will become more apparent from the following description in conjunction with the accompanying drawings.

[0013] Figure 1 A cross-sectional view of a semiconductor structure after forming a nanosheet stack on a semiconductor substrate according to an embodiment of the present invention is shown.

[0014] Figure 2 A cross-sectional view of a semiconductor structure after patterning a nanosheet stack and forming shallow trench isolation (STI) according to an embodiment of the present invention is shown.

[0015] Figure 3 A top view of a semiconductor structure after forming a stacked field-effect transistor (FET) with adjacent CFET devices having active regions and gates in three units according to an embodiment of the present invention is shown.

[0016] Figure 3A After forming a stacked FET with adjacent CFET devices having bottom and top source / drains and gates in a unit according to an embodiment of the present invention, Figure 3 A cross-sectional view of the shown semiconductor structure in the X-X direction is shown.

[0017] Figure 3BShows, according to an embodiment of the present invention, after forming stacked FETs with bottom and top S / Ds and gates in adjacent CFET devices, Figure 3 A cross-sectional view of the semiconductor structure shown in the Y-Y direction.

[0018] Figure 4 Shows, after forming a notch in each gate according to an embodiment of the present invention, Figure 3 A top view of the semiconductor structure.

[0019] Figure 4A Depicts, after forming a notch in each gate according to an embodiment of the present invention, Figure 4 A cross-sectional view of the semiconductor structure depicted in the X-X direction.

[0020] Figure 4B Depicts, after forming a notch in each of the gates according to an embodiment of the present invention, Figure 4 A cross-sectional view of the semiconductor structure in the Y-Y direction depicted.

[0021] Figure 5A Shows a cross-sectional view of the semiconductor structure in the X-X direction after depositing a first dielectric material according to an embodiment of the present invention.

[0022] Figure 5B Shows a cross-sectional view of the semiconductor structure in the Y-Y direction after depositing a first dielectric material according to an embodiment of the present invention.

[0023] Figure 6A Shows a cross-sectional view of the semiconductor structure in the X-X direction after performing chemical mechanical polishing (CMP) and removing a portion of the first dielectric material in each gate notch according to an embodiment of the present invention.

[0024] Figure 6B Shows a cross-sectional view of the semiconductor structure in the Y-Y direction after performing CMP and removing portions of the first dielectric material in each gate notch according to an embodiment of the present invention.

[0025] Figure 7A Shows a cross-sectional view of the semiconductor structure in the X-X direction after depositing a second dielectric material and performing CMP according to an embodiment of the present invention.

[0026] Figure 7B Shows a cross-sectional view of the semiconductor structure in the Y-Y direction after depositing a second dielectric material and performing CMP according to an embodiment of the present invention.

[0027] Figure 8AShows a cross-sectional view in the X-X direction of a semiconductor structure after depositing a front-side interlayer dielectric (ILD), forming front-side contacts with front-side interconnect layers, bonding a carrier wafer, removing a semiconductor substrate, depositing a back-side ILD, forming back-side contacts to bottom S / D, and forming back-side interconnect layers, according to an embodiment of the present invention.

[0028] Figure 8B Shows a cross-sectional view in the Y-Y direction of a semiconductor structure after depositing a front-side interlayer dielectric (ILD), forming front-side contacts with front-side interconnect layers, bonding a carrier wafer, removing a semiconductor substrate, depositing a back-side ILD, forming back-side contacts to bottom S / D, and forming back-side interconnect layers, according to an embodiment of the present invention.

[0029] Figure 9 Shows a cross-sectional view of a semiconductor structure through and parallel to a gate after etching a nanosheet stack to form STI and gate structures, according to an embodiment of the present invention.

[0030] Figure 10 Shows, according to an embodiment of the present invention, after forming a cut that bisects each active region and a cut in the gate between the remaining portion of the channel material and the active region Figure 10 top view of the semiconductor structure.

[0031] Figure 10A Describes, according to an embodiment of the present invention, after forming cuts in the active regions and in the gate between the remaining portions of the channel material Figure 10 cross-sectional view in the X-X direction of the semiconductor structure described in.

[0032] Figure 10B Depicts, according to an embodiment of the present invention, after forming cuts in each active region and in the gate between the remaining portions of the channel material Figure 10 cross-sectional view in the Y-Y direction of the semiconductor structure depicted in.

[0033] Figure 11A Shows, according to an embodiment of the present invention, after depositing a first dielectric material in the cuts, performing chemical mechanical polishing (CMP), and removing the top of the first dielectric material in each cut Figure 10 cross-sectional view along the X-X direction of the semiconductor structure shown.

[0034] Figure 11B Shows, according to an embodiment of the present invention, after depositing a first dielectric material, performing CMP, and removing the top of the first dielectric material in each cut Figure 10 cross-sectional view in the Y-Y direction of the semiconductor structure shown.

[0035] Figure 12AShows a cross-sectional view in the X-X direction of a semiconductor structure after depositing a second dielectric material and performing CMP according to an embodiment of the present invention.

[0036] Figure 12B Shows a cross-sectional view in the Y-Y direction of a semiconductor structure after depositing a second dielectric material and performing CMP according to an embodiment of the present invention.

[0037] Figure 13A Shows a cross-sectional view in the X-X direction of a semiconductor structure after depositing a front-side interlayer dielectric (ILD), forming a front-side contact with a front-side interconnect layer, carrier wafer bonding, semiconductor substrate removal, depositing a back-side ILD, forming a back-side contact to the bottom S / D, and forming a back-side interconnect layer according to an embodiment of the present invention.

[0038] Figure 13B Shows a cross-sectional view in the Y-Y direction of a semiconductor structure after depositing a front-side interlayer dielectric (ILD), forming a front-side contact with a front-side interconnect layer, carrier wafer bonding, semiconductor substrate removal, depositing a back-side ILD, forming a back-side contact to the bottom S / D, and forming a back-side interconnect layer according to an embodiment of the present invention. Detailed Description

[0039] Embodiments of the present invention recognize that, in following Moore's Law, many technological advancements have been made in the semiconductor industry to produce even smaller transistors, fit more transistors in the same area, and at the same time reduce the power consumption of these evolving transistors and the resulting semiconductor devices. For the development of transistors with reduced dimensions, semiconductor technology has evolved from planar transistor designs to three-dimensional FinFET designs, and three-dimensional FinFET designs have further evolved to gate-all-around transistor designs. Embodiments of the present invention recognize that 3D stacked complementary metal-oxide-semiconductor (CMOS) devices and CFET (complementary field-effect transistor) devices will be key to continuing to extend Moore's Law.

[0040] Embodiments of the present invention recognize that complementary field-effect transistors (CFETs) provide a further development of gate-all-around (GAA) nanosheet transistors by stacking NFETs and PFETs in the same CFET device. Embodiments of the present invention recognize that a CFET approach using vertically stacked GAA NFETs and GAA PFETs formed from nanosheets of epitaxially formed semiconductor materials can provide significant area advantages compared to conventional planar and fin FET devices. Specifically, embodiments of the present invention recognize that using a back-end interconnect CFET device provides more routing options for stacked FETs with less congestion in the middle-of-line (MOL) and back-end-of-line (BEOL) interconnect layers. However, embodiments of the present invention recognize that for a CFET formed using stacked NFETs and PFETs formed from semiconductor nanosheets and back-end interconnects, neither the bottom S / D epitaxial layer nor the top S / D epitaxial layer can generate sufficient strain in the channel, and thus, due to the lack of channel strain resulting in low electron or hole mobility, the performance of the stacked FETs in the CFET device is a problem. Strain is the deformation or displacement of a material caused by an applied stress, where stress is the force applied to the material divided by the cross-sectional area of the material.

[0041] Embodiments of the present invention provide a semiconductor structure and a method for the semiconductor structure that provide optimal channel strain for channels in NFETs and PFETs stacked in adjacent CFET devices. Embodiments of the present invention disclose forming a gate notch between adjacent CFET devices. The gate notch extends from the top surface of the gate of the complementary field-effect transistor device through a shallow isolation trench into the top portion of the semiconductor substrate beneath the complementary field-effect transistor device. The gate notch is filled with two dielectric materials, where one dielectric material is capable of providing appropriate stress to the channel of the NFET and the second dielectric material provides appropriate stress to the channel of the PFET. One of the dielectric materials in the gate notch is selected to provide compressive stress to the PFET channel adjacent to the gate notch, and the second dielectric material in the gate notch is adjacent to the NFET channel. The second dielectric material is selected to provide tensile stress to the NFET channel.

[0042] More specifically, embodiments of the present invention provide a first dielectric material in a bottom portion of a gate notch of a first FET adjacent to a stacked FET, and provide a second dielectric material on the first dielectric material in a gate of a second transistor of the stacked FET adjacent to an adjacent CFET device. If the first transistor is a PFET, a first dielectric material having a composition that can provide compressive stress to the first transistor is selected, or if the first transistor is an NFET, a first dielectric material having a composition that provides tensile stress to the first transistor is selected. Similarly, embodiments of the present invention provide a second dielectric material in a gate notch between adjacent CFET devices, which can provide compressive stress to a second device formed as a PFET, or provide tensile stress to a second device formed as an NFET.

[0043] In this way, embodiments of the present invention can provide improved or optimal performance of PFETs and NFETs in CFET devices. Compressive stress is applied to the channel of the PFET in the CFET device, where the dielectric material is used to fill the gate directly adjacent to the PFET, which improves the hole mobility of the PFET. Similarly, tensile stress is applied to the NFET channel in the CFET device having a tensile stress generating dielectric material in the gate notch adjacent to the NFET, which improves the electron mobility of the NFET and thereby improves the electrical performance of the NFET in the CFET device.

[0044] In another aspect, embodiments of the present invention improve the packaging density of CFET devices, semiconductor structures, and methods of forming semiconductor structures with reduced cell sizes for CFET devices by removing a portion of the gate extension between adjacent CFET devices in adjacent cells. The semiconductor structure allows for a closer inter-cell spacing or pitch between adjacent cells of the CFET device while still providing robust inter-cell electrical isolation. Embodiments of the present invention provide a gate notch that simultaneously bisects the remaining portion of the nanosheet channel of the transistor in the CFET devices in two adjacent cells. In this way, a gate extension portion adjacent to the gate notch is not formed, allowing for a closer spacing of adjacent CFET devices around the gate notch. The gate notch is filled with two dielectric materials to improve the electrostatics in the transistor channel region not covered by the gate structure.

[0045] By removing a portion of the gate extension on the facing sidewalls of adjacent CFET devices, a semiconductor structure of CFET devices is produced that provides a more compact cell-to-cell pitch. The adjacent CFET devices are located in cells of adjacent CFET devices. The gate extension typically adds approximately ten nanometers to one side of each CFET device. Removing a portion of the gate extension from the sidewalls of two adjacent CFET devices significantly reduces the pitch between the sidewalls of the two CFET devices (the CFET-to-CFET distance of the exposed channels of the two CFET devices is reduced by approximately twenty nanometers, but is not limited to this pitch reduction).

[0046] A semiconductor structure and a method of forming the same are provided where there is no gate extension between two adjacent CFET devices in adjacent cells of CFET devices, and the method significantly reduces the footprint of the adjacent CFET devices and the footprint of multiple cells of CFET devices without gate extensions.

[0047] In addition, aspects of the present invention provide two dielectric materials in a gate notch adjacent to the exposed portions of the channels of two transistors in adjacent CFET devices, without a portion of the gate extension. Two different dielectric materials are used to fill the gate notch, where each dielectric material is selected to have a fixed charge to improve electrostatics in the transistor channel type (e.g., NFET or PFET), and the dielectric materials in the gate notch are adjacent.

[0048] Using the semiconductor structure and the method of forming the same, the electrical performance of NFETs and PFETs in CFET devices in the region without gate extensions can be improved. By filling the gate notches adjacent to portions of the channels of each of the top and bottom transistors in adjacent CFET devices without a portion of the gate extension with a dielectric material having a fixed charge, the dielectric material having a fixed charge improves the performance of each specific type of transistor. More specifically, aspects of the present invention disclose using a dielectric material having a fixed positive charge in the bottom portion of the gate notch directly adjacent to the exposed surface of the channel of the bottom transistor when the bottom transistor is a PFET. The positively charged dielectric material is adjacent to two bottom PFET transistors on two opposite sides of the gate notch. Similarly, if the bottom transistor is an NFET, the bottom dielectric material adjacent to the exposed portions of the channels of two CFET devices directly adjacent to the gate notch is selected to have a negative fixed charge.

[0049] The top dielectric material in the gate notch is located on the bottom dielectric material in the gate notch. The top dielectric material in the gate notch directly adjoins the exposed portions of the channels of the top two transistors of the CFET device in the two cells directly adjacent to the gate notch. The channel portion exposed by the gate notch adjacent to the top transistor does not contact the gate, and thus, as described above, the electrical performance is degraded. For example, when the top transistor is an NFET, a negatively charged dielectric material can be selected for the top dielectric to improve the electrical performance of the two NFET transistors adjacent to the top dielectric material. When the bottom transistor is an NFET, the polarity or fixed negative charge of the top dielectric material improves the electrical performance in the two adjacent transistors.

[0050] When the top transistor in the CFET device adjacent to the gate notch in the adjacent cell is an NFET, the bottom transistor is a PFET. In this case, the bottom dielectric material adjacent to the bottom transistor (i.e., the PFET) has a different fixed charge, and the fixed charge has a polarity that improves the electrical performance of the PFET in the CFET device. The bottom dielectric material adjacent to the PFET channel provides a fixed positive charge to the exposed edge of the channel of the bottom transistor.

[0051] Alternatively, when the top transistor in the CFET device of the adjacent cell is a PFET, the dielectric material adjacent to the exposed edge of the channel of the top transistor can have a positive fixed charge to improve the electrical performance of the PFET. When the top transistor is a PFET, the bottom transistor adjacent to the gate notch will be an NFET, and in this case, the exposed edge of the channel of the NFET adjacent to the bottom dielectric material in the gate notch has a negative fixed charge.

[0052] Embodiments of the present invention provide a first dielectric material having a fixed positive charge in a gate notch adjacent to an exposed portion of a channel of a PFET in a CFET device, wherein the exposed portion of the channel of the PFET abuts a gate notch between adjacent CFET cells, and provide a second dielectric material having a fixed negative charge in a gate notch adjacent to an exposed channel of an NFET in a CFET device of an adjacent cell of the CFET device. Using this method of forming CFET devices in adjacent cells, wherein the exposed channels of the NFET and PFET contact a dielectric material having an appropriate fixed charge, improves the electrical performance of the NFET and PFET devices in the region without gate extensions, while also providing a reduction in the space between CFET devices in adjacent cells.

[0053] Some embodiments will be described in more detail with reference to the accompanying drawings, in which embodiments of the present disclosure have been shown. However, the present disclosure can be implemented in various ways and should not be construed as limited to the embodiments disclosed herein.

[0054] It should be understood that aspects of the present invention will be described in accordance with a given illustrative architecture; however, within the scope of aspects of the present invention, other architectures, substrate materials, process features, and steps may be varied.

[0055] It should also be understood that when an element such as a layer, region, or substrate is referred to as being “on” or “above” another element, it can be directly on the other element or intervening elements may also be present. In contrast, when an element is referred to as being “directly on” or “directly above” another element, no intervening elements are present. It will also be understood that when an element is referred to as being “connected” or “coupled” to another element, it can be directly connected or coupled to the other element, or intervening elements may be present. In contrast, when an element is referred to as being “directly connected” or “directly coupled” to another element, no intervening elements are present.

[0056] The methods described herein can be used to fabricate integrated circuit chips, also referred to as semiconductor chips. The manufacturer may distribute the resulting integrated circuit chips in raw wafer form (i.e., as a single wafer having multiple unpackaged chips), as a bare die, or in a packaged form. In the latter case, the chip is mounted in a single chip package (e.g., a plastic carrier having leads that are fixed to a motherboard or other higher level carrier) or a multi-chip package (e.g., a ceramic carrier having either or both surface interconnections or buried interconnections). In any case, the chip is then integrated with other chips, discrete circuit elements, and / or other signal processing devices, as part of (a) an intermediate product such as a motherboard or (b) a final product. The final product can be any product that includes an integrated circuit chip, ranging from toys and other low-end applications to advanced computer products having a display, keyboard, or other input device, and a central processor.

[0057] References in the specification to “one embodiment” or “an embodiment” and other variations thereof mean that the particular features, structures, characteristics, etc. described in connection with the embodiment are included in at least one embodiment. Thus, the appearances of the phrases “in one embodiment” or “in an embodiment” and other variations thereof in various places throughout the specification are not necessarily all referring to the same embodiment.

[0058] The terms used herein are for the purpose of describing particular embodiments only and are not intended to limit the exemplary embodiments. As used herein, the singular forms “a,” “an,” and “the” are intended to include the plural forms as well, unless the context clearly indicates otherwise. It will also be understood that the terms “comprises,” “comprising,” and / or “having,” when used herein, specify the presence of the stated features, integers, steps, operations, elements, and / or components, but do not preclude the presence or addition of one or more other features, integers, steps, operations, elements, components, and / or groups thereof.

[0059] For ease of description, spatial relative terms such as "below", "beneath", "lower", "above", "upper", etc. may be used herein to describe the relationship of one element or feature to another element or feature, as shown in the figures. It should be understood that the spatial relative terms are intended to encompass different orientations of the device in use or operation in addition to the orientation shown in the figures. For example, if the device in the figures is flipped, an element described as "below" or "beneath" another element or feature will be oriented "above" the other element or feature. Thus, the term "below" can include both an upper and a lower orientation. The device may be otherwise oriented (rotated 90 degrees or in other directions), and the spatial relative descriptions used herein can be interpreted accordingly. In addition, it should be understood that when a layer is referred to as being "between" two layers, it can be the only layer between the two layers, or there can also be one or more intermediate layers.

[0060] It should be understood that although terms such as first, second, etc. may be used herein to describe various elements, these elements should not be limited by these terms. These terms are only used to distinguish one element from another. Thus, without departing from the scope of this concept, the first element discussed below may be referred to as the second element.

[0061] Detailed embodiments of the claimed structures and methods are disclosed herein. The method steps described below do not form a complete process flow for fabricating an integrated circuit on a semiconductor chip. The embodiments of the present invention can be practiced in conjunction with integrated circuit manufacturing techniques for semiconductor chips and devices currently used in this technology, and only include as many of the commonly practiced process steps as are necessary to understand the described embodiments. The drawings represent cross-sectional portions of a semiconductor chip or substrate (e.g., a semiconductor wafer during fabrication), and are not drawn to scale, but are drawn to illustrate the features of the described embodiments. The specific structural and functional details disclosed herein should not be construed as limiting, but only as a representative basis for teaching those skilled in the art to employ the methods and structures of the present disclosure in various ways. In the description, details of well-known features and techniques may be omitted to avoid unnecessarily obscuring the presented embodiments.

[0062] The deposition processes for the metallic material and the sacrificial material include, for example, chemical vapor deposition (CVD), physical vapor deposition (PVD), atomic layer deposition (ALD), molecular layer deposition (MLD), high density plasma (HDP) deposition, or gas cluster ion beam (GCIB) deposition. Variations of the CVD process include, but are not limited to, atmospheric pressure CVD (APCVD), low pressure CVD (LPCVD), plasma enhanced CVD (PECVD), and metalorganic CVD (MOCVD), and combinations thereof may also be used. In an alternative embodiment using ALD, the chemical precursors react with the surface of the material one at a time to deposit a thin film on the surface. In an alternative embodiment using gas cluster ion beam (GCIB) deposition, a high-pressure gas is allowed to expand in a vacuum and then condenses into clusters. The clusters can be ionized and directed onto the surface, providing highly anisotropic deposition.

[0063] The selective etching used herein includes, but is not limited to, patterning using lithography, extreme ultraviolet (EUV) lithography process, or any other known semiconductor patterning process, followed by one or more etching processes. Various materials are referred to herein as "removed" or "etched", and etching generally refers to performing one or more processes that remove one or more materials while leaving other protected areas of the materials masked during the lithography process unaffected. Some examples of etching processes include, but are not limited to, processes such as dry etching processes using reactive ion etching (RIE) or ion beam etching (IBE), wet chemical etching processes, or combinations of these etching processes. Dry etching can be performed using a plasma. Ion milling, ion beam etching (IBE), sputter etching, or reactive ion etching (RIE) bombards the wafer with high-energy ions of an inert gas, and the high-energy ions of the inert gas approach the wafer from substantially one direction. Therefore, these processes are anisotropic or directional etching processes.

[0064] The terms "epitaxial growth and / or deposition" and "epitaxial growth and / or deposition" refer to growing a semiconductor material on a deposition surface of a semiconductor material, wherein the grown semiconductor material has the same crystal characteristics as the semiconductor material of the deposition surface. In epitaxial deposition techniques, the chemical reactants provided by the source gas are controlled and the system parameters are set such that the deposited atoms reach the deposition surface of the semiconductor substrate with sufficient energy to move around on the surface and orient themselves to the crystal arrangement of the atoms of the deposition surface. Therefore, the epitaxial semiconductor material has the same crystal characteristics as the deposition surface on which the epitaxial semiconductor material is formed. Examples of various epitaxial growth techniques include, for example, rapid thermal chemical vapor deposition (RTCVD), low energy plasma deposition (LEPD), ultra-high vacuum chemical vapor deposition (UHVCVD), low pressure chemical vapor deposition (LPCVD), atmospheric pressure chemical vapor deposition (APCVD), and molecular beam epitaxy (MBE).

[0065] As is known to those skilled in the art, doping of semiconductor materials (e.g., in channels, source / drain, substrates, etc.) is the intentional introduction of impurities into an intrinsic semiconductor to modulate the electrical, optical, and structural properties of the intrinsic semiconductor. As used herein, "p-type" refers to the addition of impurities to an intrinsic semiconductor, which creates a deficiency of valence electrons. In silicon-containing semiconductors, examples of p-type dopants, i.e., impurities, include but are not limited to: boron, aluminum, gallium, and indium. As used herein, "n-type" refers to the addition of impurities to an intrinsic semiconductor that contribute free electrons. In a silicon-containing substrate, examples of n-type dopants, i.e., impurities, include but are not limited to antimony, arsenic, and phosphorus.

[0066] It should also be understood that material compounds will be described in terms of the listed elements, such as SiGe. These compounds include different proportions of elements within the compound, e.g., SiGe includes SixGe1-x, where x is less than 1, etc. Additionally, other elements may be included in the compound and still function in accordance with this principle. Compounds with additional elements will be referred to herein as alloys.

[0067] As is known to those skilled in the art, the damascene process for forming circuit lines and / or contacts typically includes various steps of patterning vias and trenches in a dielectric material (e.g., interlayer dielectric), filling the vias and trenches with a metal layer, and planarizing the metal using a chemical mechanical process (e.g., chemical mechanical polishing (CMP)) to remove excess or excessive metal.

[0068] Now refer to the accompanying drawings. The drawings provide a schematic cross-sectional view of a semiconductor device in an intermediate stage of manufacture according to one or more embodiments of the present invention. The device provides a schematic representation of the device of the present invention and should not be considered exact or a limitation on the scale of the device elements.

[0069] Figure 1 A cross-sectional view of a semiconductor structure 100 after forming a stack of nanosheets on a semiconductor substrate 21 according to an embodiment of the present invention is shown. As depicted, Figure 1 The semiconductor structure 100 includes a semiconductor substrate 21, a sacrificial layer 4, a sacrificial layer 14, and alternating layers of channel material 12 and sacrificial material 10, and is formed using known semiconductor processes for nanosheet stacking.

[0070] The semiconductor substrate 21 can be, for example, a bulk substrate, which can be made of any one of several known semiconductor materials, such as silicon, germanium, silicon-germanium alloys, and compound (e.g., III-V and II-VI) semiconductor materials. Non-limiting examples of compound semiconductor materials include gallium arsenide, indium arsenide, indium phosphide, or indium gallium arsenide. Generally, the semiconductor substrate 21 can be approximately but not limited to several hundred micrometers thick. In various embodiments, the semiconductor substrate 21 is a wafer or a part of a wafer. In some embodiments, the semiconductor substrate 21 is composed of a semiconductor material including one or more of doped, undoped, or containing doped regions, undoped regions, stress regions, or defect-rich regions. In some examples, the semiconductor substrate 21 can include one or more other devices or transistors (not depicted). In one embodiment, the semiconductor substrate 21 is one of the layered semiconductor substrates, such as a semiconductor-on-insulator substrate (SOI), a germanium-on-insulator (GeOI), or a silicon-replacement insulator (SRI). Figure 1 The nanosheet stack described in Figure 1 also includes alternating layers of sacrificial semiconductor material and semiconductor channel material, and as is known to those skilled in the art, Figure 1 the nanosheet stack described in Figure 1 can include more or fewer semiconductor channel material layers and sacrificial material layers.

[0071] The channel material 12 is composed of a semiconductor material. As previously mentioned, the channel material 12 can be grown or deposited epitaxially using one of the known processes such as UHVCVD, RTCVD, LEPVD, MBE or another similar semiconductor material growth process. In various embodiments, the channel material 12 is a silicon material. In other embodiments, the channel material 12 is composed of any Group-IV semiconductor material or compound (e.g., III-V or II-VI) semiconductor material. In various embodiments, the channel material 12 is intrinsic or undoped. In some cases, the channel material 12 can be doped using known doping methods. The channel material 12 has different etching sensitivities and / or etching rates from the semiconductor substrate 21, the sacrificial layer 4, the sacrificial layer 14, and the sacrificial material 10.

[0072] The sacrificial layer 4 and the sacrificial layer 14 are composed of epitaxially grown semiconductor materials. For example, the sacrificial layer 4 and the sacrificial layer 14 can be formed using one of RTCVD, LEPD, LEPVD, MBE, or another known epitaxial growth process. In various embodiments, the sacrificial layer 4 and the sacrificial layer 14 are composed of silicon and germanium (SiGe). For example, the sacrificial layer 4 and the sacrificial layer 14 can be composed of SiGe having approximately sixty atomic percent germanium, but are not limited to these percentages. The composition of the sacrificial layer 4 and the sacrificial layer 14 provides an etching sensitivity different from that of the sacrificial material 10, the channel material 12, and the semiconductor substrate 21. In some embodiments, the sacrificial layer 4 and the sacrificial layer 14 are composed of the same material. For example, the sacrificial layer 4 and the sacrificial layer 14 are composed of different materials.

[0073] The sacrificial material 10 is composed of a semiconductor material that can be deposited or grown using one of known epitaxial processes (such as RTCVD, LEPVD, etc.). In various embodiments, the sacrificial material 10 is composed of SiGe. For example, the sacrificial material 10 can have a germanium concentration of less than 50 atomic percent or a germanium concentration ranging from approximately 20 atomic percent to approximately 40 atomic percent, but is not limited to these materials and percentages. The sacrificial material 10 has an etching sensitivity different from that of the sacrificial layer 4 and the sacrificial layer 14, and the sacrificial material 10 also has an etching sensitivity different from that of the material of the semiconductor substrate 21.

[0074] In various embodiments, the nanosheet stack includes a bottom layer of the sacrificial layer 4 on the semiconductor substrate 21, which is covered by the sacrificial material 10. As depicted, the nanosheet stack further includes a channel material layer 12 located on the sacrificial material 10. As Figure 1 shown, a second sacrificial material layer 10 is on the channel material 12, and a third sacrificial material layer 10 is on the channel material 12. In Figure 1 which, the third sacrificial material layer 10 is located on the second channel material layer 12 and under the layer of the sacrificial layer 14. The portion of the nanosheet layer stack composed of the bottom three sacrificial material layers 10 and the bottom channel material layer 12 is labeled as the nanosheet layer stack portion 101. In the subsequent figures. The nanosheet stack portion 101 forms the FET 201.

[0075] In Figure 1 which, the sacrificial material layer 10 is located on the sacrificial layer 14, and more than two channel material layers 12 are located above the sacrificial material 10 on the sacrificial layer 14. Another sacrificial material layer 10 is located between the two channel material layers 12. As Figure 1 shown, in some cases, a top dielectric layer or hard mask (not shown) can cover Figure 1 the top layer of the channel material 12 in Figure 1As shown, the top two layers of sacrificial material 10 and the top two layers of channel material 12 are labeled as the nanosheet stack portion 103. In subsequent figures, the nanosheet stack portion 103 can form the FET 203.

[0076] Figure 2 FIG. 4 shows a cross-sectional view of a semiconductor structure 200 after patterning a nanosheet stack and forming the STI 20 according to an embodiment of the present invention. As described, Figure 2 including Figure 1 elements, wherein a portion of the STI 20 is formed under the removed portion of the nanosheet stack. Using known lithography and etching processes (e.g., RIE), a portion of the nanosheet layer stack composed of the sacrificial layer 4, the sacrificial material 10, the channel material 10, and the sacrificial layer 14 is selectively removed, and also the top portion of the semiconductor substrate 21 under the removed portion of the nanosheet layer stack is removed. Using known deposition processes, the STI 20 is formed in the semiconductor substrate 21 adjacent to each remaining portion of the nanosheet stack portion 101. Each STI 20 abuts and is located below the remaining portion of the sacrificial layer 4, as Figure 2 shown. In different embodiments, the horizontal width of each STI 20 is 30 to 100 nm. In some cases, the width of the STI 20 can be greater than or less than 30 to 100 nm.

[0077] Figure 3 FIG. 14 shows, according to an embodiment of the present invention, after forming the CFETs 41, 42, and 43 and Figure 3A the CFETs 50, 42, and 63 as shown in Figure 3B , top views 300 of the semiconductor structures 300A and 300B. As shown, Figure 3 including a top view of the cells 1, 2, 3, the active region 30, and the gate 36. The dashed lines indicate the cell lower boundary between the cells 1 and 2 and the cell upper boundary between the cells 2 and 3, Figure 3 also including subsequent Figure 3A , 3B , 4A, 4B, 5A, 5B, 6A, 6B, 7A, 7B, 8A, and 8B, the identifications of the cross-sections X-X and Y-Y of the cross-sections A and B. The cross-section X-X, as shown, is parallel and passes through one of the active regions 30, that is, the longitudinal direction of the gate 36. Therefore, Figure 3A , 4A , 5A, 6A, 7A, and 8A are cross-sections X-X perpendicular to each gate 36, as shown by the position of the cross-section X-X. The cross-section Y-Y is parallel to the longitudinal direction of the gate 36 and passes through one of the gates 36. As described later, Figure 3B , 4BEach of 5B, 6B, 7B, and 8B depicts a cross-section Y-Y parallel to and passing through one of the gates 36.

[0078] In various embodiments, the gate 36 is an alternative metal gate structure (e.g., including a high-k gate dielectric layer, a gate electrode, inner spacers, gate spacers, associated liners, and Figure 3 any other alternative metal gate elements not depicted in

[0079] Figure 3A FIG. shows a cross-sectional view of the semiconductor structure 300A in the Figure 3 X-X direction shown, after forming CFET 41, CFET 42, CFET 43, CFET 50, CFET 63 in the inner interlayer 33 of cells 1, 2, and 3 according to an embodiment of the present invention. As shown, Figure 3A includes cell 2, which has an ILD 37, ILD 39, gate 36, gate spacer 35, channel material 12, inner spacer 33, dielectric isolation material 31, top S / D 34, bottom S / D 32, FET 201, FET 203 in each of CFET 41, CFET 42, and CFET 43 on the bottom layer of the dielectric isolation material 31 above the semiconductor substrate 21. As is known to those skilled in the art, a cell can be composed of more than one or multiple CFET devices.

[0080] Each of the three FETs 203 is above one of the three FETs 201, where each pair of vertically stacked FET 201 and FET 203 forms one of CFET 41, CFET 42, and CFET 43 in cell 2, as Figure 3A shown. In Figure 3A each of the nanosheet stack portions 101 and nanosheet stack portions 103 shown in Figure 2 forms FET 201 and FET 203 respectively to create CFET 41, CFET 42, and CFET 43 in cell 2.

[0081] FET 201 and FET 203 are formed using known semiconductor processes for nanosheet FET formation of GAAFETs with alternative metal gates. CFET 41, CFET 42, and CFET 43 are formed using known methods for forming stacked nanosheet FETs with a GAA structure. As Figure 3A shown, the three bottom FETs of each of CFET 41, CFET 42, and CFET 43 are labeled as FET 201. Each FET 201 can use the nanosheet stack portion 101 (in Figure 1 and Figure 2is formed on the underlying layer of the dielectric isolation material 31. Each FET 201 is formed from the remaining portion of a nanosheet stack portion 101 that includes the bottom two layers including the channel material 12 as depicted in Figure 3A , a bottom S / D 32, a gate 36 with a gate spacer 35, and a portion of an internal spacer 33. Each FET 201 is located on the dielectric isolation material 31, and the top surface of the bottom S / D 32 is covered by an ILD 39. As depicted in Figure 3A , the sidewalls of the channel material 10 of the FET 201 are surrounded by the bottom S / D 32.

[0082] As depicted in Figure 3A , each FET 203 can be formed on the dielectric isolation material 31 above the FET 201 using a nanosheet stack portion 103 ( Figure 1 and Figure 2 as depicted). As depicted in Figure 3A , each FET 203 includes a portion of the top two layers of channel material 12, a top S / D 34, a gate 36 with a gate spacer 35, and an internal spacer 33. Each FET 203 resides on the dielectric isolation material 31 (e.g., an intermediate isolation layer) on the FET 201. Each top S / D 34 is covered by an ILD 37. As depicted in Figure 3A , the sidewalls of the channel material 10 of the FET 203 are surrounded by the top S / D 34.

[0083] The method of forming the semiconductor structure 300A from the semiconductor structure 200 is a known method of forming stacked GAAFETs from nanosheet stacks and includes using the nanosheet stack portion 101 and the nanosheet stack portion 103 depicted in Figure 2 to form the FET 201 and the FET 203, respectively.

[0084] In various embodiments, the steps of converting the nanosheet stack portion 101 depicted in Figure 2 into the FET 201 and converting the nanosheet stack portion 103 depicted in Figure 2 into the FET 203 are discussed below. As is known to those skilled in the art, in some cases, the order and process of the steps discussed below can be different in other examples of the method of forming the semiconductor structure 300A.

[0085] For example, using a known dummy formation process, a dummy gate (not shown) with a hard mask can be formed on the top layer of the channel material 12 of the nanosheet stack portion 101 ( Figure 2 as shown) and around the nanosheet stack portion 101 and the nanosheet stack portion 103 ( Figure 2 the nanosheet stacks 101 and 103 are shown).

[0086] For example, wet or dry lateral etching processes such as dry etching with gaseous HCl can be used to selectively remove Figure 2 the sacrificial layer 4 and the sacrificial layer 14 shown in. A conformal deposition process such as ALD can deposit a dielectric isolation material 31 in the grooves left by removing the sacrificial layer 4 and the sacrificial layer 14. The portion of the dielectric isolation material 31 on the semiconductor substrate 21 can be the bottom dielectric isolation (BDI) of the FET 201, and the dielectric isolation material 31 above the FET 201 can be the middle isolation layer (MDI) separating the FET 201 and the FET 203. The dielectric isolation material 31 can be composed of any suitable dielectric material, such as any dielectric material, such as silicon nitride (SiN), silicon boron carbon nitride (SiBCN), silicon oxynitride carbon nitride (SiOCN), aluminum oxide (AlOx), and can include a single layer or can include multiple dielectric material layers. The dielectric isolation material 31 can have a thickness ranging from about 3 nm to about 15 nm. An anisotropic etching process such as RIE removes the exposed horizontal portions of the dielectric isolation material 31.

[0087] In various embodiments, by Figure 2 depressing the outer edges of the sacrificial material 10 depicted in (e.g., using one or more known lateral etching processes), and then conformally depositing a dielectric material such as silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOC, low-k dielectric, or any combination of these materials for the inner spacer 33, the inner spacer 33 is formed. An anisotropic etching process removes the exposed horizontal portions of the inner spacer 33.

[0088] In various embodiments, the bottom S / D 32 can be epitaxially grown from the exposed portions of the channel material 10 in the nanosheet stack portion 101 ( Figure 2 depicted in). As described, the bottom S / D 32 surrounds the vertical portion of the FET 201 on the bottom dielectric isolation material 31, and the bottom S / D 32 can surround the inner spacer 33 in the FET 201 and the exposed sidewalls of the underlying layer of the channel material 12. During the epitaxial growth of the bottom S / D 32, Figure 2 the sidewalls of the nanosheet stack portion 103 shown in can be protected by the sacrificial layer, or in other cases, any epitaxial growth on the sidewalls of the nanosheet stack portion 103 can be removed, for example, by a dry etching process. In some embodiments, after the bottom S / D 32 is grown, a dry or wet etching process depresses the bottom S / D 32 to a level approximately flush with the bottom surface of the middle dielectric isolation material layer 31, and in other cases, the top surface of the S / D 32 is exactly above the top surface of the second channel material layer 12.

[0089] In some embodiments, the bottom S / D 32 is doped. For example, the bottom S / D 32 is doped with boron, phosphorus, or another semiconductor doping material. The dopant used will depend on the type of FET 201 being formed (e.g., whether a PFET or an NFET is desired for FET 201). In various embodiments of the present invention, one or both of the later-formed bottom S / D 32 and top S / D 34 can be in-situ doped by adding one or more dopant species to the epitaxial source / drain material.

[0090] In some examples, a combination of dry and wet etching and a recessing step on the bottom S / D 32 can recess the bottom S / D 32 to a level where, for example, the top surface of the S / D 32 can be flush with any part of the dielectric isolation material 31 above the FET 201.

[0091] The ILD 39 can be deposited, for example, by ALD, CVD, PVD, etc. on the exposed top surface of the bottom S / D 32. The ILD 39 can be composed of any dielectric material used in nanosheet semiconductor devices (e.g., SiN, SiBCN, SiO2, etc.). As described, the ILD 39 is located on the top S / D 32 between two facing portions of the dielectric isolation material 31 in the FET 201. CMP can planarize the ILD 39 and, for example, recess it by RIE to a level approximately flush with the dielectric isolation material 31 on the FET 201.

[0092] In various embodiments, the top S / D 34 grows epitaxially around Figure 2 the sidewalls of the channel material 12 in the nanosheet stack portion 103 shown in. As Figure 3A shown, the top S / D 34 surrounds portions of the two upper channel materials 12 and the internal spacer 33 in the FET 203. In some cases, the top S / D 34 can be doped, for example, with an n-type dopant or a p-type dopant. As Figure 3A shown, the top S / D 34 is located on the ILD 39 and, in some embodiments, the top surface of the top S / D 34 can be equal to or higher than the top surface of the uppermost layer of the channel material 12. The ILD 37 can be deposited on the top S / D 34.

[0093] Known processes can be used to form the gate 36, to remove the dummy gate and form a metal replacement gate for the gate 36 with the gate spacer 35. In various embodiments, using known replacement metal gate processes, the gate 36 can be formed (e.g., depositing a gate dielectric, depositing a gate metal, conformally depositing a dielectric spacer material, and performing RIE to remove the horizontal portions of the spacer material). As previously described, the gate 36 can be a metal replacement gate with a high-k gate dielectric layer. After forming the gate 36 with the gate spacer 35, CMP can planarize the top surface of the semiconductor structure 300A.

[0094] In various embodiments, each of the FETs 201 and 203 is a PFET or an NFET. As Figure 3A and 3B shown, the FETs 201 and 203 are gate-all-around FETs, and the combination of one of the FETs 203 stacked on one of the FETs 201 each forms one of the CFETs 41, 42, and 43. In various embodiments, each of the CFETs 41, 42, and 43 is composed of two different complementary types of FETs 201 and 203 (e.g., the FET 201 is a PFET and the FET 203 is an NFET, or the FET 201 is an NFET and the FET 203 is a PFET). In an embodiment, each of the CFETs 41, 42, and 43 is a stacked CMOS device with FETs of the same type (e.g., both the FETs 201 and 203 are PFETs). Although only two FETs (i.e., stacking the FETs 201 and 203 in Figure 3A ), in other examples, more than two FETs can be stacked to form the CFETs 41, 42, and 43 (e.g., the CFET 41 can have two NFETs and two PFETs).

[0095] Figure 3B A cross-sectional view of the semiconductor structure 300B in the Y-Y direction after forming the CFETs 50, 42, and 63 in the cells 1, 2, and 3, respectively, is shown in Figure 3 as described. Figure 3BIncludes three FETs 201, each FET being under the dielectric isolation material 31 and under one FET 203, wherein each pair of stacked FETs 201 and FET 203 forms one of the CFET 50, CFET 42, and CFET 6 on the bottom layer of the dielectric isolation material 31 and adjacent to the STI 20 in the semiconductor substrate 21. The CFET 50, CFET 42, and CFET 63 are formed by the process discussed in detail above with reference to Figure 3A As shown, each STI 20 is covered by a portion of the gate 36 and is located in the semiconductor substrate 21 between two of the CFET 50, CFET 42, and CFET 63.

[0096] Figure 4 Describes a top view 400 of a semiconductor structure after forming a gate cutout that exposes a portion of the semiconductor substrate 21 according to an embodiment of the present invention. As shown, Figure 4A and 4B of. As shown, Figure 4 Includes Figure 3 of the elements, wherein each gate cutout is located in each cell boundary and each gate cutout exposes a portion of the semiconductor substrate 21. Figure 4 Depicts two gate cutouts that expose two portions of the semiconductor substrate 21. These two gate cutouts are perpendicular to each gate 36 and parallel to the cross-section X-X indicated in Figure 4 and these two gate cutouts are parallel to the active region 30 depicted in Figure 4 .

[0097] Figure 4A Depicts a cross-sectional view of the semiconductor substrate 400A of cell 2 in the X-X direction after forming a gate cutout (not depicted in Figure 4A ) according to an embodiment of the present invention. As depicted, Figure 4 Includes Figure 4A of the elements. Figure 3A Figure 4A Shows the semiconductor substrate 21, dielectric isolation material 31, CFET 41, CFET 42, and CFET 43 in cell 2 having FET 201 and FET 203, gate 36, inner spacer 33, gate spacer 35, channel material 12, top S / D 34 under ILD 37, and bottom S / D 32 under ILD 39. Due to the position of the cross-section X-X as shown in Figure 4 , the gate cutout is not shown in Figure 4A .

[0098] Figure 4B Depicts a cross-sectional view of the semiconductor structure 400B in the Y-Y direction after forming two gate cutouts in the gate 36 according to an embodiment of the present invention. As shown,Figure 4B including CFET 50, CFET 42, and CFET 63, where a first gate cut is located between CFET 50 in unit 1 and CFET 42 in unit 2, and a second gate cut is located between CFET 42 in unit 2 and CFET 63 in unit 3. In Figure 4B , a first portion of gate 36 is removed by the leftmost gate cut located between CFET 50 and CFET 42, and a second portion of gate 36 removed by the rightmost gate cut is located between CFET 42 and CFET 63. In Figure 4A , each gate cut extends downward through a portion of gate 36, through one of the STIs 20, and into the top of semiconductor substrate 21.

[0099] The gate cuts occur after gate 36 is formed (i.e., after gate 36 is formed as a replacement metal gate). In various embodiments, the gate cut trenches are formed by conventional lithography and etching processes. The width of the gate cut should leave a sufficient amount of gate 36 to prevent degradation of the electrical performance of each stacked FET formed by nanosheet stack portion 101 and nanosheet stack portion 103. For example, the horizontal distance from the sidewall of the gate cut to the sidewall of each channel material 10 should be in the range of at least 10 nm to 15 nm, but is not limited to this range. The width of the gate cut depends at least in part on the horizontal spacing between adjacent FETs 201 and 203. Generally, the denser or more tightly packed the density of adjacent FETs 201 and 203, the thinner the gate cut. In other words, as the CFET density increases, the width of the gate cut decreases. A typical width of the gate cut between adjacent CFETs can be 10 nm to 50 nm, but is not limited to this width as the width depends at least in part on the spacing between adjacent CFETs (e.g., CFET 50, CFET 42, and CFET 63).

[0100] As Figure 4B shown, the depth of the two gate cuts extends beyond the STI 20 and into the semiconductor substrate 21. For example, the gate cuts can be flush with the surface of the semiconductor substrate 21 or can extend 100 nm below the surface of the semiconductor substrate 21, but is not limited to these depths. In other embodiments, the depth of the gate cut should be from the top surface of the semiconductor structure 400B to at least the top surface of the dielectric isolation material 31 on the semiconductor substrate 21. In some cases, the depth of the gate cut can further extend into the semiconductor substrate 21. For example, after depositing a dielectric material into the gate cut, a deeper gate cut into the semiconductor substrate 21 can provide further stress advantages, as Figures 6A to 8BThis occurs during the subsequent process steps described herein. In various embodiments, the gate cuts appear above the STI 20 and pass through the gates 36 of the STI, and are located between each adjacent CFET device. As described, the gate cuts leave a portion of the gate 36 around the sidewalls of the channel material 12 in each of the FET 201 and FET 203.

[0101] Figure 5A FIG. shows a cross-sectional view of the semiconductor structure 500A in the X-X direction after the deposition of the first dielectric stress material 51 according to an embodiment of the present invention. As described, Figure 5A comprising Figure 4A the elements and the first dielectric stress material 51. The first dielectric stress material layer 51 is deposited on the semiconductor structure 500A using one or more known deposition processes, such as but not limited to ALD, CVD, PVD, MLD, or spin coating techniques, followed by a planarization process, such as CMP. As Figure 5A in the cross-section Figure X-X shown, the first dielectric stress material 51 is on the top surfaces of the ILD layer 37, the gates 36, and the gate spacers 35.

[0102] The specific dielectric material selected for the first dielectric stress source material 51 can be determined based on the type of FET (e.g., PFET or NFET) formed for the FET 201. As is known to those skilled in the art, some dielectric materials are capable of applying lateral stress on the sidewalls of adjacent materials. For example, when the dielectric stress source material 51 is deposited in the gate cut ( Figure 5A not shown) between two adjacent FET 201s, the dielectric material 51 can be selected to provide either compressive stress or tensile stress on the channel material 12 of the FET 201. In various embodiments, the first dielectric stress material 51 can include one or more layers. For example, the first dielectric stress material 51 can be composed of any dielectric material, such as silicon oxide, silicon oxynitride, silicon nitride, SiBCN, SiOC, another low-k dielectric material, or any combination of these materials.

[0103] Figure 5B FIG. shows a cross-sectional view of the semiconductor structure 500B in the Y-Y direction after the deposition of the first dielectric stress material 51 according to an embodiment of the present invention. As described, Figure 5B comprising Figure 4B the elements and the first dielectric stress material 51. Using the previously described with respect to Figure 5AOne or more of the deposition processes discussed deposit a first dielectric stress material 51 over and around the exposed surfaces on top of the gate 36, the STI 20, and the semiconductor substrate 21. As described, the first dielectric stress source material 51 covers the top surface of the gate 36 and fills the leftmost gate notch in the gate 36 between the CFET 50 and the CFET 42, as well as the rightmost gate notch between the CFET 42 and the CFET 63. As Figure 5B shown, the leftmost gate notch separates cell 1 from cell 2, thus separating the CFET in cell 1 (e.g., CFET 50) from the CFET in cell 2 (e.g., CFET 42). Similarly, the rightmost gate notch separates the CFET device in cell 2 (e.g., CFET 42) from the CFET in cell 3 (e.g., CFET 63). Figure 5B The first dielectric stress source material 51 in fills the gate notches shown, and the first dielectric stress source material 51 abuts the sidewalls of each of the FET 201 and the FET 203 (e.g., directly abuts the gate 36 of each of the FET 201 and the FET 203) and covers the top surface of the gate 36.

[0104] Figure 6A FIG. shows a cross-sectional view of the semiconductor structure 600A in the X-X direction after performing CMP in each gate notch and recessing the first dielectric stress material 51. As described, Figure 6A including the elements without the first dielectric stress material 51 Figure 5A CMP planarizes the top surface of the semiconductor structure 600A and removes the first dielectric stress material 51 from the top surface of the semiconductor structure 600A. In Figure 6A the recessing of the first dielectric stress source material 51 in each gate notch is not shown. In the semiconductor structure 600A, the top surfaces of the gate 36 and the gate spacer 35 are exposed.

[0105] Figure 6B FIG. shows a cross-sectional view of the semiconductor structure 600B in the Y-Y direction after performing CMP in each gate notch and recessing the first dielectric material 51. As described, FIG. 600B includes elements without the first dielectric stress material 51 on the top surface of the gate 36 and without the first dielectric stress material 51 on top in each gate notch adjacent to the FET 203 Figure 5B of.

[0106] In various embodiments, CMP removes portions of the first dielectric stress material 51 on the gate 36. After CMP, a top portion of the first dielectric stress material 51 in each gate notch is removed using one or more known wet or dry etching processes, such as but not limited to RIE. As depicted and previously discussed, two gate notches are on either side of the CFET 42 in the cell 2. After recessing the first dielectric stress source material 51 in the two gate notches, a top surface of the first dielectric stress source material 51 is flush with a portion of a sidewall of the dielectric isolation material 31 between the FETs 201 and 203. As described, the remaining portion of the first dielectric stress material 51 abuts each of two adjacent FETs 201. In various embodiments, a top surface of the remaining first dielectric stress source material 51 is at least flush with or above a top layer of the channel material 12 in the FET 201. However, in other cases, a remaining amount of the first dielectric stress source material 51 after recessing extends approximately to a height of a top surface of an intermediate layer of the dielectric isolation material 31 such that the first dielectric material 51 applies stress to the channel material 12 through sidewalls of the gate 36 in the FET 201.

[0107] In various embodiments, when the FET 201 is a PFET, the dielectric material selected for the first dielectric material 51 creates compressive stress on the channel material 12 through the gate 36 of the FET 201 and thus improves electrical performance of the FET 201 (e.g., improves hole mobility in the channel of the FET 201 as a PFET). In other embodiments, in the case where the FET 201 is an NFET, the first dielectric stress material 51 is selected to create tensile stress on the FET 201. The tensile stress applied to the channel material 12 in the FET 201 improves electron mobility in the channel of the FET 201 as an NFET.

[0108] Figure 7A A cross-sectional view in the X-X direction of a semiconductor structure 700A after depositing the second dielectric stress material 73 and performing CMP is shown according to an embodiment of the present invention. As shown, Figure 7A including Figure 6A elements in the cell 2 are not shown in cross-section X-X for the second dielectric stress material 73 and the first dielectric stress material 51. After CMP, the second dielectric stress material 73 is removed from a top surface of the semiconductor structure 700A, and top surfaces of the gate 36 and the gate spacer 35 are exposed.

[0109] The second dielectric stress source material 73 can be determined based on the type of FET formed for the FET 203 (e.g., a dielectric material that creates compressive stress for a PFET or a material that creates tensile stress on an NFET) Figure 7AThe specific dielectric material selected (not shown in the figure). The second dielectric stress source material 73 can be deposited using one or more of the processes discussed for the first dielectric stress source material 51 in the description of Figure 5A .

[0110] Figure 7B FIG. shows a cross-sectional view in the Y-Y direction of the semiconductor structure 700B after depositing the second dielectric stress material 73 and performing CMP according to an embodiment of the present invention. As described, Figure 7B including Figure 6B components, but a portion of the second dielectric stress material 73 is above the first dielectric stress material 51 in the gate notch. For example, Figure 7B shows the second dielectric stress source material 73, the first dielectric material 51, the gate 36, the gate spacer 35, the internal spacer 33, the channel material 12, the bottom S / D 32, the top S / D 34, the dielectric isolation material 31, the FET 201, and the FET 203 for forming the CFET 50, the CFET 42, and the CFET 63. As depicted, the second dielectric stress source material 73 fills the leftmost gate notch between the FET 203 in unit 1 and the FET 203 in unit 2, and fills the rightmost gate notch between the FET 203 in unit 2 and the FET 203 in unit 3.

[0111] As described above, one or more of the processes and materials discussed for the first dielectric stress source material 51 in the description of Figure 5A can be used to deposit the second dielectric stress source material 73. The specific dielectric material selected for the second dielectric stress source material 73 can be determined based on the type of FET formed for the FET 203 (e.g., PFET or NFET). In an embodiment where the FET 203 is a PFET, the second dielectric stress source material 73 is selected using a dielectric material composition and / or material that generates compressive stress on the channel material 12 of the FET 203. Similarly, when the FET 203 is an NFET, the second dielectric material 73 is selected to provide tensile stress on the channel material 12 of the FET 203.

[0112] As Figure 7B shown, after CMP, the top surface of the second dielectric stress material 73 is flush with the top surface of the gate 36. Figure 7BThe bottom surface of the second dielectric stress material 73 therein is located on the top surface of the first dielectric stress material 51, and the second dielectric stress material 71 is located between two adjacent FETs 203. In various embodiments, the bottom surface of the second dielectric stress material 73 is flush or approximately flush with the dielectric isolation material 31. In various embodiments, the second dielectric stress material 73 abuts or directly contacts the sidewalls of the gate 36 of each of the two adjacent FETs 203. As described, each of the two adjacent FETs 203 is separated by the top portion of the gate cutout filled with the second dielectric stress material 73, and the portion of the gate 36 that contacts the second dielectric stress material 73 can be the portion where the gate 36 is in direct contact with the sidewalls of the two layers of channel material 12 in the FET 203.

[0113] As previously described, when the FET 203 is a PFET, the material selected for the second dielectric stress material 73 creates a compressive stress on the upper portion of the filled gate cutout surrounding the FET 203 and on the portion of the gate 36 adjacent to the FET 203. The second dielectric stress source material 73 creates a compressive stress on the gate 36 and the adjacent channel material 12 in the FET 203. For example, when the FET 203 is a PFET, the second dielectric stress material 73 is a material such as, but not limited to, a nitride that creates a compressive stress on the channel material 12. As previously described, the compressive stress on the channel material 12 of the PFET creates a higher hole mobility in the channel material 12 and can improve the electrical performance of the PFET.

[0114] However, in other examples, when the FET 203 is an NFET, the material selected for the second dielectric stress material 73 creates a tensile stress on the portion of the gate 36 surrounding the upper portion of the filled gate cutout adjacent to the FET 203. In this case, the second dielectric stress source material 73 creates a tensile stress on the adjacent channel material 12 in the FET 203, where the tensile stress increases the electron mobility of the NFET (i.e., the FET 203).

[0115] As described above, each of FET 201 and FET 203 can be an NFET or a PFET in the NFET / PFET pair of a CFET device. For example, when FET 201 is a PFET in one of CFETs 41, 42, or 43, then FET 203 is a PFET (i.e., FET 203 is a FET of a complementary type to FET 201 below FET 203). In various embodiments, when FET 203 is a PFET, the second dielectric stress source material 73 is selected to apply compressive stress on the channel material 12 in FET 203, and then, FET 201 is an NFET. As described above, when FET 201 is an NFET, the first dielectric stress material 51 applies tensile stress on the channel material 12 in FET 201 to improve the NFET electrical performance, and the second dielectric stress material 73 applies compressive stress to improve the PFET electrical performance.

[0116] In an embodiment, in a stacked complementary metal oxide semiconductor (CMOS) device, when both FET 203 and FET 201 are PFETs or both are NFETs, only the first dielectric stress raw material 51 is deposited to provide appropriate stress (e.g., compressive stress if both FET 201 and FET 203 are PFETs in a stacked CMOS device).

[0117] Figure 8A A cross-sectional view of a semiconductor structure 800A along the X-X direction through cell 2 is shown after depositing ILD 87, forming top contacts 82, 84, gate contact 88 ( Figure 8A not shown in the figure), forming a front interconnect layer 80, performing a carrier wafer bonding, removing the semiconductor substrate 21, depositing a back ILD 83, forming a back contact 86, and forming a back interconnect layer 90. As shown, Figure 8A including Figure 7AAll elements of ILD 87, top contact 82, top contact 84, top interconnect layer 80, ILD 83, bottom contact 86, and bottom interconnect layer 90, e.g., semiconductor structure 800A, depict CFET41 and CFET 42, which include bottom S / D 32 under top S / D 34, where top contact 82 is connected to top interconnect layer 80, the top S / D 34 between CFET 42 and CFET 43 is connected to top interconnect layer 80, and bottom contact 86 under the bottom S / D 32 between CFET 42 and CFET 43 is connected to bottom interconnect layer 90. Top contact 82 passes through a portion of ILD 87 and ILD 37 to contact the top S / D 34 between two adjacent FETs 203 in CFET 41 and CFET 42. Top contact 84 passes through ILD87, ILD 37, top S / D 32, and ILD 39 to connect to the bottom S / D 34 between two adjacent FETs 201 in CFET 42 and CFET 43. As shown, each of CFET 41, CFET 42, and CFET 43 resides in cell 2.

[0118] Semiconductor structure 800A can be formed from semiconductor structure 700A using known back - end - of - line contact formation processes and interconnect layer formation processes. For example, ILD 87 can be deposited on the top surface of gate 36 and gate spacer 35, followed by the formation of top contact 82, top contact 84, and gate contact 88 ( Figure 8A not shown in). Top interconnect layer 80 can be formed on ILD87 and top contact 82 and top contact 84.

[0119] Using known semiconductor processes, a carrier wafer can be bonded to top interconnect layer 80, and the wafer is flipped so that the semiconductor substrate 21 can be removed (e.g., by wafer grinding and / or wet etching processes) to expose the underlying dielectric isolation material 31. ILD 83 can be deposited on dielectric isolation material 31. For example, back contact 86 can be formed using known damascene processes. Bottom interconnect layer 90 can be formed on ILD 83 and back contact 86.

[0120] Figure 8B A cross - sectional view of semiconductor structure 800B in the Y - Y direction after depositing ILD 87, forming top contact 82 and top contact 84 ( Figure 8B not shown in), forming gate contact 88, forming front - side interconnect layer 80, performing carrier wafer bonding, removing semiconductor substrate 21, depositing back - side ILD 83, forming back - side contact 86, and forming back - side interconnect layer 90 is shown. As shown, Figure 8B including Figure 7BAll components of, and ILD 87, gate contacts 88, top interconnect layer 80, ILD 83, and bottom interconnect layer 90, semiconductor structure 800B can be formed using the process described above with respect to Figure 8A . In addition, Figure 8B includes arrows A and B, which represent the directions of stress applied by the first dielectric stress material 51 and the second dielectric stress material 73.

[0121] The gate contacts 88 connect each gate 36 to the top interconnect layer 80 through the ILD 87, Figure 8B shows three gate contacts 88, where each gate contact 88 connects the gate 36 on the CFET 50 in cell 1, one of the CFET 42 in cell 2, and the CFET 6 in cell 3 to the top interconnect layer 80. As depicted, Figure 8B depicts two filled gate cuts, where the first gate cut is between cell 1 and cell 2 (i.e., the gate cut between the CFET 50 and the CFET 42), and the second gate cut is between cell 2 and cell 3 (i.e., the gate cut between the CFET 42 and the CFET 63). The bottom of each gate is filled with the first dielectric stress material 51 under the second dielectric stress material 73. The ILD87 covers the top surface of the second dielectric stress material 72.

[0122] In various embodiments, when the FET 201 is a PFET, the dielectric material selected for the first dielectric material 51 generates a compressive stress through the gate 36 of the FET 201 as shown by arrow A on the channel material 12. Thus, the first dielectric stress source material 51 improves the electrical performance of the FET 201 by increasing the hole mobility in the channel of the FET 201 (i.e., the PFET). As Figure 8B shown, when the FET 201 is a PFET, the FET 203 is an NFET, and the second dielectric stress source material 73 generates a tensile stress to increase the electron mobility of the channel of the NFET. The tensile stress is depicted by arrow B on the channel material 12 of the FET 203.

[0123] In other embodiments, when the FET 201 is an NFET and the FET 203 is a PFET, the first dielectric stress material 51 is selected to generate a tensile stress on the FET 201 ( Figure 8B not shown), and the second dielectric stress material 73 generates a compressive stress. The tensile stress applied by the first dielectric stress source material 51 to the channel material 12 in the FET 201 improves the electron mobility in the channel of the NFET of the FET 201, while the compressive stress improves the hole mobility to improve the electrical performance of the FET 203 (PFET).

[0124] In various embodiments, a semiconductor structure 800B having two different dielectric materials filling each gate notch between two adjacent CFET devices (e.g., the gate notch between CFET41 and CFET 42) provides optimized or improved electrical performance for each of the NFET and PFET in the CFET device by selecting one dielectric material between adjacent PFETs to provide a compressive force on the PFET channel and selecting a second dielectric material between adjacent NFETs to provide a tensile force on the NFET channel. As described, when FET 203 is a PFET, the semiconductor structure 800B having arrow A in FET 203, and when FET 201 is an NFET, the semiconductor structure 800B having arrow B in FET 201 includes a second dielectric stress source material 73 that generates a tensile stress on the channel material 12 of FET203 (e.g., NFET), and a second dielectric material 73 that generates a compressive stress indicated by arrow A on the channel material 12 of FET 203 (e.g., PFET). As a result, the electron mobility in FET 201 (e.g., NFET) and the hole mobility in FET 203 (e.g., PFET) are increased by the additional tensile stress on the channel material 12 provided respectively by the second dielectric stress source material 73 in the upper part of the gate notch and the first dielectric material 51 in the lower part of the gate notch, thereby enhancing the electrical performance of FET 201 and FET 203. This novel semiconductor structure 800B improves the electrical performance of the CFET device by introducing a preferred type of stress into the PFET channel and NFET channel in the CFET device.

[0125] Figure 9 A cross-sectional view of a semiconductor structure in a direction through and parallel to gate 136 after etching a nanosheet stack to form STI 120 and gate 136, according to an embodiment of the present invention, is shown later in Figure 10 the Y-Y direction shown in. Using the nanosheet stack process discussed with respect to Figure 2 and the known semiconductor processes discussed in detail with respect to Figure 3A the nanosheet stack is etched to form two remaining portions of the nanosheet stack, and a gate 136 is formed around the remaining portions of the nanosheet stack. In various embodiments, gate 136 is an alternative metal gate structure having a low-k gate dielectric. Gate 136 can be formed from a dummy gate in steps discussed in detail with reference to Figure 3A In one embodiment, gate 136 is formed directly on the remaining portions of the nanosheet stack without forming a dummy gate.

[0126] Figure 9 the two remaining nanosheet portions shown in Figure 2The three remaining portions of the nanosheet stack shown in have substantially the same coverage area. It is important to note that Figure 9 two remaining portions of the nanosheet stack shown in will be separated to form Figure 12B four CFET devices in. Thus, compared with the coverage area of the three CFET devices shown in Figure 7B the semiconductor structure 1200B can provide a reduction of about 30% in the coverage area size of the three CFET devices.

[0127] As described, Figure 9 including the STI 120 in the semiconductor substrate 21, the dielectric material 31 between the portions of the semiconductor substrate 21 and in the middle layer of the channel material 12, the gate 136, and parentheses indicating the remaining portions of the nanosheet stack (i.e., the channel material 12) that will form the NFET and PFET of the CFET devices after subsequent processes. The remaining portions of the nanosheet layer stack are labeled as the nanosheet portion 301 below the nanosheet portion 303. After subsequent process steps, the nanosheet portions 301 and 303 will each become four transistors (four upper transistors 303 and four lower transistors 301) of four CFET devices (e.g., the CFET 131, CFET 142, CFET 153, and CFET 164 described later in Figure 10B ).

[0128] Figure 10 shows a top view 1000 of the semiconductor structure after forming the gate 136 between the gate cut that bisects each layer of the channel material 12 and the remaining portion of the channel material 12 according to an embodiment of the present invention. As shown, Figure 9 includes the gate 136, unit 1, unit 2, unit 3, unit 4, the unit boundaries identified by the dashed lines, the active regions 30, where each active region 30 is bisected by a gate cut that exposes a portion of the semiconductor substrate 21, and a third gate cut that occurs between two active regions 30 also exposes a portion of the semiconductor substrate 21. As is known to those skilled in the art, the active regions 30 determine the position of the remaining portions of the nanosheet layer stack composed of the channel material 12 with the dielectric material 31 and the portion of the gate 136 ( Figure 10 not shown in). Figure 10 ).

[0129] Figure 10A Depicts a cross-sectional view of the semiconductor structure 1000A along the X-X direction after forming the gate cut in the portion of the channel material 12 (not depicted in this view) and in the portion of the gate 136 between two adjacent units (not depicted) according to an embodiment of the present invention. As depicted, Figure 10AILD 139, which includes the semiconductor substrate 21 and the remaining part of the channel material layer 12, separates the bottom S / D 132 from the top S / D 134, ILD 137, the gate 136 with gate spacers 135, and the internal spacers 133. Moreover, Figure 10A CFETs 141, 142, and 143 of cell 2 are shown. As previously described, the gate 136 can be a gate structure replacing a metal gate. In Figure 10A the gate cut that bisects the channel material 12 through the top of the gate 136 and between the channel materials 12 extending downward into the semiconductor substrate 21 is not depicted.

[0130] Figure 10B A cross-sectional view in the Y - Y direction of the semiconductor structure 1000B after forming gate cuts in each remaining part of the channel material 12 and in a part of the gate 136 between the remaining parts of the channel material 12 in CFET 142 and CFET 153 according to an embodiment of the present invention is shown. As depicted, Figure 10B includes Figure 9 elements, where three gate cuts remove parts of the semiconductor structure 900. Two outer gate cuts remove the central part of the channel material 12, the dielectric material 31, the gate 136 located above the central part of the channel material 12, and the semiconductor substrate 21 located below the central part of the channel material 12. The middle gate cut removes the part of the gate 136 located Figure 9 between the remaining parts of the channel material 12 as shown, a part of the middle STI 120 located below a part of the gate 136, and a part of the semiconductor substrate 21 located below the removed part of the STI 120. The gate cuts remove parts of the semiconductor structure 1000B to form trenches extending into parts of the semiconductor substrate 21 between cell 1 and cell 2, cell 2 and cell 3, and cell 4, as depicted.

[0131] After removing the part of the semiconductor structure 900 with gate cuts, four cells of the CFET device are formed. As shown, cell 1 includes at least CFET 131, cell 2 includes at least CFET 142, cell 3 includes at least CFET 153, and cell 4 includes at least CFET 164. As previously described, a cell generally includes multiple CFET devices.

[0132] In Figure 10B each transistor is formed by the top of the remaining channel material 12 ( Figure 9 the nanosheet part 303 marked in Figure 9The nanosheet part 301) marked in [Chinese] constitutes. A pair of transistors formed by the nanosheet parts 303 and 301 stacked on top of each other forms one of CFET 131, CFET 142, CFET 153, and CFET 164. As Figure 10B shown, the sidewalls of the channel material 12 in CFET 131 and CFET 142 that are directly adjacent or adjacent to the remaining part of the gate cut are exposed (for example, a part of the facing sidewalls of the CFET devices in adjacent cells 1 and 2 is exposed by one of the gate cuts). Similarly, a part of the sidewalls of the devices in adjacent cells 3 and 4 is exposed by the rightmost gate cut. Figure 10B The central gate cut in [Chinese] removes the central part of the gate 136 located between memory cell 2 and memory cell 3, as well as part of the STI 120 and the semiconductor substrate 21. After the gate cut is completed, CFET 131 in memory cell 1, CFET 142 in memory cell 2, CFET 153 in memory cell 3, and CFET 164 in memory cell 4 are formed. Each of CFET 131, 142, 153, and 164 includes transistor 303 on transistor 301. Hereinafter, the nanosheet part 301 and the nanosheet part 303 will be referred to as transistor 301 and transistor 303, respectively. In various embodiments, each pair of transistor 301 and transistor 303 directly above and below each other forms a CFET device. As is known to those skilled in the art, transistor 301 and transistor 303 in each CFET device (e.g., CFET 131, 142, 153, and 164) are a pair of complementary transistors (i.e., NFET and PFET).

[0133] Figure 11A shows a cross-sectional view of the semiconductor structure 1100A in the X-X direction after depositing a first dielectric material (not shown) in the gate cut (not shown), performing chemical mechanical polishing (CMP), and removing a part of the first dielectric material in each cut. As depicted, Figure 11A includes Figure 10A elements.

[0134] Figure 11B shows a cross-sectional view of the semiconductor structure 1100B in the Y-Y direction after depositing the first dielectric material 211, performing CMP, and removing the top of the first dielectric material 211 in each gate cut. As depicted, Figure 11B includes Figure 10B elements, where a part of the first dielectric material 211 remains in the lower part of each gate cut. The semiconductor structure 1100B can be used previously regarding Figure 5A , 6Aformed by the semiconductor processes discussed in detail with FIGS. 6A and 6B. As depicted, the top surface of the first dielectric material 211 is approximately equal to or horizontal with a portion of the top dielectric material 31 layer (e.g., between transistor 301 and transistor 303).

[0135] The first dielectric material 211 abuts the exposed sidewalls of transistor 301 in units 1, 2, 3, and 4, while filling the bottom portion of the middle gate cut in gate 136 between units 2 and 3. The first dielectric material 211 also abuts the upper semiconductor substrate 21 in each gate cut and abuts a portion of the STI 120 in the middle gate cut.

[0136] The first dielectric material 211 is selected to have a fixed charge having a polarity that enhances the electrical performance of each of the transistors 301. Since the exposed edges of the channel material 12 in the transistors 301 do not directly contact a portion of the gate 136, the electrostatics of this region of the transistors 301 is not as good as that of the region of the transistors 201 that contacts the gate 136. To improve the electrostatics of this region, the first dielectric material 211 having a fixed charge is selected, which will improve the electrostatics of the transistors 301. For example, when the transistor 301 is a PFET, the first dielectric material 211 is selected to provide a positive fixed charge (e.g., SiN), such that the first dielectric material 211 effectively increases the Vt (voltage) of the cut edges of the transistor 301 (e.g., the exposed edges of the channel material 12). Thus, the first dielectric material 211 having a fixed positive charge improves the electrostatics of the transistors 301. Similarly, when the transistor 301 is an NFET, the first dielectric material 211 is selected to have a negative variation (e.g., SiN, Al2O3), such that the first dielectric material 211 increases the Vt near the exposed edges of the transistor 301 (NFET), thereby improving the electrostatics of the region of the transistor 301.

[0137] Figure 12A A cross-sectional view of a semiconductor structure in the X-X direction after depositing a second dielectric material and performing CMP according to an embodiment of the present invention is shown. As depicted, Figure 12A including Figure 11A elements. Figure 12A The first dielectric material 211 and the second dielectric material 233 are not depicted in

[0138] Figure 12B A cross-sectional view of a semiconductor structure 1200B in the Y-Y direction after depositing a second dielectric material 233 and performing CMP according to an embodiment of the present invention is shown. As depicted, Figure 12B including Figure 11BThe elements and a second dielectric material 233 on the first dielectric material 211 in each of the gate cuts. In various embodiments, the bottom surface of the second dielectric material 233 on the first dielectric material 211 is substantially flush with the upper dielectric material layer 31, and the second dielectric material 233 abuts the exposed sidewalls of the transistors 303. The second dielectric material 233 contacts the exposed portions of the sidewalls of the channel material 12 and portions of the gates 136 in the transistors 303 in a portion of the CFET 131 and CFET 142 (e.g., in adjacent cells 1 and 2) and a portion of the CFET 153 and CFET 164 (e.g., in adjacent cells 3 and 4).

[0139] The second dielectric material 233 is selected to have a fixed charge with a polarity that enhances the electrical performance of each of the transistors 303. Since the exposed edges of the channel material 12 in the transistors 303 do not directly contact a portion of the gate 136, the electrostatics of this region of the transistors 303 is not as good as that of the region of the transistor 201 that contacts the gate 136. To improve the electrostatics of this region of each transistor 303, the second dielectric material 233 with a fixed charge is selected, which will improve the electrostatics of the transistors 303.

[0140] For example, when the transistor 303 is an NFET, the second dielectric material 233 is selected to have a negative variation (e.g., Al2O3), such that the second dielectric material 233 increases the Vt near the exposed edges of the transistor 303 (NFET), thereby improving the electrostatics of the region of the transistor 303.

[0141] Similarly, when the transistor 303 is a PFET, the second dielectric material 233 is selected to provide a positive fixed charge (e.g., SiN), such that the second dielectric material 233 effectively increases the Vt (voltage) at the notch edges of the transistor 303 (e.g., the exposed edges of the channel material 12). In this way, the second dielectric material 233 with a fixed positive charge improves the electrostatics of the transistor 303 (PFET).

[0142] In addition, in Figure 12B more CFET devices can be formed in a coverage area that is substantially the same as the coverage area in which the CFET devices were previously formed in Figure 7B (in Figure 12B four CFET devices are formed in a region that is substantially the same as the region in which the three CFET devices shown in Figure 7B are shown). By bisecting the leftmost remaining portion of the nanosheet stack shown in Figure 9 (i.e., bisecting a portion of each layer of the channel material 12), the CFET 131 in cell 1 and the CFET 142 in cell 2 are formed, and by bisecting Figure 9The rightmost remaining portion of the nanosheet stack shown in forms CFET 153 in unit 3 and CFET 164 in unit 4, Figure 12B The area required for the four CFETs is less than the area used by four conventionally formed CFET devices.

[0143] Figure 13A A cross-sectional view in the X-X direction of semiconductor structure 1300B is shown after depositing the front-side ILD 187, forming the front-side contacts 182 and 184 that connect the top S / D 134 and the bottom S / D 134 to the front-side interconnect layer 180, carrier wafer bonding, removing the semiconductor substrate 21, depositing the back-side ILD 183, forming the back-side contact 186 to the bottom S / D 132, and forming the back-side interconnect layer 190. Using the known BEOL semiconductor process as previously discussed with respect to Figure 8A Semiconductor structure 1300A is formed. As shown, Figure 13A Includes Figure 12A The elements of and the front-side contacts 182 and 184, the front-side ILD 187, the front-side interconnect layer 180, the back-side contact 186, and the back-side ILD 183.

[0144] Figure 13B A cross-sectional view in the Y-Y direction of semiconductor structure 1300B is shown after depositing the front-side ILD 187, forming the gate contact 188 with the front-side interconnect layer 180, carrier wafer bonding, removing the semiconductor substrate 21, depositing the back-side ILD 183, and forming the back-side interconnect layer 190. As shown, Figure 13B Includes Figure 12B The elements of and the gate contact 188, the front-side ILD 187, the front-side interconnect layer 180, the back-side ILD 183, and the back-side interconnect layer 190.

[0145] As discussed in detail previously, by removing the gate extensions between adjacent cells of a CFET device and depositing a dielectric material having a fixed charge in a gate cut portion that is directly adjacent to an exposed portion of the channel material 12 in each transistor (i.e., each of transistors 301 and 303 in each CFET device), the semiconductor structure 1300B provides a more densely packaged CFET device than a conventionally formed CFET device, the dielectric material improving the electrostatics of regions of the channel material 12 that do not directly contact the gate 136 in each of transistors 301 and 303. A first dielectric material 211 adjacent to transistor 301 is selected to provide one of a negative charge to an exposed edge of the channel material 12 in each transistor 301, or a positive charge to the exposed edge of the channel material 12 depending on the type of transistor 301 (i.e., a negative charge dielectric material for an NFET and a positive charge dielectric for a PFET). Similarly, a second dielectric material 233 is selected to improve Figure 13B the electrical performance of transistors 303 in CFETs 131, 142, 153, and 164

[0146] The description of the various embodiments of the invention has been presented for purposes of illustration, but is not intended to be exhaustive or limited to the disclosed embodiments. Many modifications and variations will be apparent to those of ordinary skill in the art without departing from the scope of the invention. The terms used herein were chosen to best explain the principles of the embodiments, the practical application, or the improvement of technologies found in the marketplace, or to enable other ordinary skilled artisans in the art to understand the embodiments disclosed herein.

Claims

1. A semiconductor structure, comprising: A complementary field-effect transistor device, the complementary field-effect transistor device having a first transistor below a second transistor, and A gate notch, the gate notch being directly adjacent to and contiguous with the gate of the complementary field-effect transistor device, wherein the gate notch is filled with a first dielectric material below a second dielectric material.

2. The semiconductor structure according to claim 1, wherein the first dielectric material applies stress to one or more channels of the first transistor, the stress being selected from the group consisting of compressive stress and tensile stress.

3. The semiconductor structure according to claim 2, wherein the first dielectric material applies the tensile stress to the one or more channels of the first transistor, and the first transistor is an n-type field-effect transistor NFET.

4. The semiconductor structure according to claim 2, wherein the first dielectric material applies the compressive stress to the one or more channels of the first transistor, and the first transistor is a p-type field-effect transistor PFET.

5. The semiconductor structure according to claim 1, wherein the first transistor is an NFET, the second transistor is a PFET, and the second dielectric material applies compressive stress to one or more channels of the second transistor.

6. The semiconductor structure according to claim 1, wherein the first transistor is a PFET, the second transistor is an NFET, and the second dielectric material applies tensile stress to the one or more channels of the second transistor.

7. The semiconductor structure according to claim 1, wherein the gate notch extends from the top surface of the gate of the complementary field-effect transistor device into a portion of the semiconductor substrate below the complementary field-effect transistor device.

8. The semiconductor structure according to claim 1, wherein the gate notch is contiguous with the sidewall of the gate of the complementary field-effect transistor device, and wherein the first dielectric material below the second dielectric material is adjacent to the first transistor.

9. The semiconductor structure according to claim 2, wherein the gate of the complementary field-effect transistor device directly contacts each of the one or more channels of the first transistor and the second transistor.

10. The semiconductor structure according to claim 2, wherein the bottom portion of the gate of the complementary field-effect transistor device is between the one or more channels of the first transistor and the first dielectric material, and wherein the top portion of the gate of the complementary field-effect transistor device is between the one or more channels of the second transistor and the second dielectric material.

11. The semiconductor device structure according to claim 1, wherein the first transistor is electrically isolated from the second transistor by at least one layer of intermediate dielectric isolation material.

12. The semiconductor structure according to claim 1, further comprising: A first top contact, the first top contact connecting the top surface of the source / drain of the first transistor to a plurality of front-side interconnect layers; A second top contact that connects the top surface of the source / drain of the second transistor to the plurality of front-side interconnect layers; and a gate contact that connects the bottom surface of the source / drain of the second transistor to a plurality of back-side interconnect layers.

13. The semiconductor structure according to claim 1, wherein both the first transistor and the second transistor are gate-all-around transistors, and wherein each channel layer of the first transistor and the second transistor is a stacked layer of nanosheets.

14. A semiconductor structure, comprising: a plurality of cells of complementary field-effect transistor (CFET) devices, wherein each of the CFET devices has a top transistor below a bottom transistor, a first dielectric material adjacent to portions of each channel of the top transistors of a first CFET device in a first cell of the CFET devices and adjacent to portions of each channel of the top transistors of a second CFET device in a second cell of the CFET devices adjacent to the first cell, wherein the first dielectric material has fixed charges with a first polarity; and a second dielectric material adjacent to portions of each channel of the bottom transistors of the first CFET device in the first cell of the CFET devices and adjacent to portions of each channel of the bottom transistors of the second CFET device in the second cell of the CFET devices, wherein the second dielectric material has the fixed charges with a second polarity.

15. A method of forming a complementary field-effect transistor (CFET) device, the method comprising: epitaxially growing a stacked layer of nanosheets on a semiconductor substrate; selectively etching the stacked layer of nanosheets and a top portion of the semiconductor substrate; forming shallow trench isolation (STI) adjacent to the remaining portion of the stacked layer of nanosheets in the semiconductor substrate; forming at least two stacked gate-all-around field-effect transistors separated by an intermediate dielectric isolation material on the semiconductor substrate, wherein more than one first transistor is below the intermediate dielectric isolation material and more than one second transistor is above the intermediate dielectric isolation material; performing a gate cut that passes through portions of each gate between the more than one first transistor and the more than one second transistor, wherein the gate cut passes through the STI adjacent to the more than one first transistor and the top portion of the semiconductor substrate; filling the gate cut with a first dielectric material; recessing the first dielectric material; depositing a second dielectric material; and performing planarization.

16. The method according to claim 15, further comprising: forming top contacts and a plurality of top interconnect layers; forming back contacts for the complementary field-effect transistor devices; and forming a plurality of bottom interconnect layers connected to bottom contacts.

17. The method according to claim 15, wherein forming the at least two stacked gate-all-around field-effect transistors separated by the intermediate dielectric isolation material on the semiconductor substrate further comprises: Form a dummy gate over each shallow trench isolation and over and around portions of the remaining portion of the nanosheet stack; Remove two layers of a first sacrificial material in the remaining portion of the nanosheet stack; Conformally deposit a dielectric isolation material at the location of the first sacrificial dielectric material and around the dummy gate, Remove the horizontal portions of the dielectric isolation material to form a bottom dielectric isolation on the semiconductor substrate, an intermediate dielectric isolation in an intermediate region of the nanosheet stack, and a gate spacer around the dummy gate; Selectively remove portions of the remaining portion of the nanosheet stack that are between the dummy gates; Laterally etch outer edges of a second sacrificial material of the two sacrificial materials; Form an inner spacer adjacent to the remaining portion of the second sacrificial material; Epitaxially grow a bottom source / drain adjacent to a bottom portion of the remaining portion of the nanosheet stack; Recess the bottom source / drain; Deposit a dielectric material on the bottom source / drain; Epitaxially grow a top source / drain adjacent to a top portion of the remaining portion of the nanosheet stack; And Perform planarization.

18. The method according to claim 15, wherein the first dielectric material generates compressive stress on a first transistor of the at least two stacked gate-all-around field effect transistors, and the more than one first transistor is a PFET.

19. The method according to claim 15, wherein the second dielectric material generates tensile stress on a second transistor of the at least two stacked gate-all-around field effect transistors, and the second transistor is an NFET.

20. The method according to claim 15, wherein the PFET of the at least two stacked gate-around field effect transistors is adjacent to a dielectric material that generates compressive stress on a plurality of channels of the PFET, and the NFET of the at least two stacked gate-around field effect transistors is adjacent to the second dielectric material that generates tensile stress on the plurality of channels of the NFET.

21. A computer program comprising program code adapted to perform the method steps of any one of claims 15 to 20 when the program is run on a computer.

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